技术领域Technical Field
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same.
背景技术Background technique
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It is composed of multiple storage cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.
在DRAM等半导体结构中栅电极采用多层导电材料组成，例如多晶硅和金属材料。而为了降低制程工艺过程中的热预算，需要先对多晶硅进行掺杂，然后再形成位于多晶硅上的金属材料层。但是，多晶硅中的掺杂离子易扩散至金属材料层中，从而导致包括所述栅电极的所述晶体管中反型层厚度的增加，影响所述晶体管的性能，降低了半导体结构的良率。In semiconductor structures such as DRAM, the gate electrode is composed of multiple layers of conductive materials, such as polysilicon and metal materials. In order to reduce the thermal budget during the process, the polysilicon needs to be doped first, and then a metal material layer is formed on the polysilicon. However, the doped ions in the polysilicon are easily diffused into the metal material layer, thereby increasing the thickness of the inversion layer in the transistor including the gate electrode, affecting the performance of the transistor and reducing the yield of the semiconductor structure.
因此，如何减少栅电极等导电结构中的掺杂离子向外部扩散，从而改善半导体结构的性能，是当前亟待解决的技术问题。Therefore, how to reduce the diffusion of doped ions in conductive structures such as gate electrodes to the outside, thereby improving the performance of semiconductor structures, is a technical problem that needs to be solved urgently.
发明内容Summary of the invention
本公开一些实施例提供的半导体结构及其形成方法，用于减少导电结构中的掺杂离子向外部扩散，从而改善半导体结构的性能。Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to reduce the diffusion of doped ions in a conductive structure to the outside, thereby improving the performance of the semiconductor structure.
根据一些实施例，本公开提供了一种半导体结构的形成方法，包括如下步骤：According to some embodiments, the present disclosure provides a method for forming a semiconductor structure, comprising the following steps:
提供衬底；providing a substrate;
于所述衬底上形成第一导电层，所述第一导电层包括第一掺杂区、以及位于所述第一掺杂区上方的第二掺杂区，所述第一掺杂区包括第一掺杂元素，所述第二掺杂区包括第二掺杂元素，且所述第二掺杂区的致密度大于所述第一掺杂区的致密度；Forming a first conductive layer on the substrate, the first conductive layer comprising a first doping region and a second doping region located above the first doping region, the first doping region comprising a first doping element, the second doping region comprising a second doping element, and the density of the second doping region being greater than the density of the first doping region;
于所述第一导电层上方形成第二导电层，以形成包括所述第一导电层和所述第二导电层的第一导电结构。A second conductive layer is formed over the first conductive layer to form a first conductive structure including the first conductive layer and the second conductive layer.
在一些实施例中，于所述衬底上形成第一导电层的具体步骤包括：In some embodiments, the specific steps of forming the first conductive layer on the substrate include:
沉积第一材料于所述衬底的表面，形成初始第一导电层；Depositing a first material on the surface of the substrate to form an initial first conductive layer;
注入所述第一掺杂元素和所述第二掺杂元素至所述初始第一导电层，形成包括所述第一掺杂区和所述第二掺杂区的所述第一导电层。The first doping element and the second doping element are implanted into the initial first conductive layer to form the first conductive layer including the first doping region and the second doping region.
在一些实施例中，注入所述第一掺杂元素和所述第二掺杂元素至所述初始第一导电层之前，还包括如下步骤：In some embodiments, before the first doping element and the second doping element are implanted into the initial first conductive layer, the following steps are further included:
沉积第二材料于所述初始第一导电层表面，形成覆盖所述初始第一导电层的保护层。A second material is deposited on the surface of the initial first conductive layer to form a protective layer covering the initial first conductive layer.
在一些实施例中，形成包括所述第一掺杂区和所述第二掺杂区的所述第一导电层的具体步骤包括：In some embodiments, the specific steps of forming the first conductive layer including the first doping region and the second doping region include:
注入所述第一掺杂元素至全部的所述初始第一导电层，形成初始第一掺杂区；Implanting the first doping element into the entire initial first conductive layer to form an initial first doping region;
注入所述第二掺杂元素至所述初始第一掺杂区的顶部，形成所述第二掺杂区，位于所述第二掺杂区下方的所述初始第一掺杂区作为所述第一掺杂区。The second doping element is implanted into the top of the initial first doping region to form the second doping region, and the initial first doping region located below the second doping region serves as the first doping region.
在一些实施例中，所述第二掺杂区至少覆盖所述第一掺杂区的整个顶面，且所述第二掺杂区的厚度小于所述第一掺杂区的厚度。In some embodiments, the second doping region at least covers the entire top surface of the first doping region, and a thickness of the second doping region is less than a thickness of the first doping region.
在一些实施例中，所述第一导电层的材料为多晶硅材料，所述第二导电层的材料为金属材料，所述第一掺杂元素为第Ⅲ主族或者第Ⅴ主族的元素，所述第二掺杂元素为氮元素。In some embodiments, the material of the first conductive layer is polysilicon material, the material of the second conductive layer is metal material, the first doping element is an element of Group III or Group V, and the second doping element is nitrogen.
在一些实施例中，所述第二掺杂元素在所述第二掺杂区中的掺杂浓度为1×1017个/cm3～1×1019个/cm3。In some embodiments, the doping concentration of the second doping element in the second doping region is 1×1017 elements/cm3 to 1×1019 elements/cm3 .
在一些实施例中，于所述第一导电层上方形成第二导电层的具体步骤包括：In some embodiments, the specific steps of forming the second conductive layer above the first conductive layer include:
于所述第一导电层的顶面形成第一阻挡层；forming a first barrier layer on a top surface of the first conductive layer;
于所述第一阻挡层的顶面形成所述第二导电层，所述第一阻挡层电连接所述第一导电层和所述第二导电层。The second conductive layer is formed on the top surface of the first barrier layer, and the first barrier layer electrically connects the first conductive layer and the second conductive layer.
在一些实施例中，所述第一阻挡层的材料为氮化钛、氮化硅钛中的任一种或者两者的组合。In some embodiments, the material of the first barrier layer is any one of titanium nitride and titanium silicon nitride, or a combination of the two.
在一些实施例中，所述衬底包括存储区域、以及位于所述存储区域外部的外围区域；于所述衬底上形成第一导电层的具体步骤包括：In some embodiments, the substrate includes a storage area and a peripheral area outside the storage area; the specific steps of forming a first conductive layer on the substrate include:
沉积第一材料于所述衬底的表面，于所述外围区域形成初始第一导电层、并同时于所述存储区域形成初始第三导电层；Depositing a first material on the surface of the substrate to form an initial first conductive layer in the peripheral region and simultaneously forming an initial third conductive layer in the storage region;
注入所述第一掺杂元素至全部的所述初始第一导电层和全部的所述初始接触层，于所述外围区域形成初始第一掺杂区、并于所述存储区域形成第三导电层；Implanting the first doping element into all of the initial first conductive layer and all of the initial contact layer to form an initial first doping region in the peripheral region and a third conductive layer in the storage region;
注入所述第二掺杂元素至所述初始第一掺杂区的顶部，形成所述第二掺杂区，位于所述第二掺杂区下方的所述初始第一掺杂区作为所述第一掺杂区。The second doping element is implanted into the top of the initial first doping region to form the second doping region, and the initial first doping region located below the second doping region serves as the first doping region.
在一些实施例中，于所述第一导电层上方形成第二导电层的具体步骤包括：In some embodiments, the specific steps of forming the second conductive layer above the first conductive layer include:
于所述第一导电层上方形成所述第二导电层、并同时于所述存储区域的所述第三导电层上方形成第四导电层，以形成包括所述第一导电层和所述第二导电层的所述第一导电结构、并形成包括所述第三导电层和所述第四导电层的第二导电结构。The second conductive layer is formed above the first conductive layer, and a fourth conductive layer is simultaneously formed above the third conductive layer of the storage area to form the first conductive structure including the first conductive layer and the second conductive layer, and to form a second conductive structure including the third conductive layer and the fourth conductive layer.
在一些实施例中，所述衬底包括存储区域、以及位于所述存储区域外部的外围区域；于所述衬底上的所述外围区域形成所述第一导电层之后，还包括如下步骤：In some embodiments, the substrate includes a storage area and a peripheral area outside the storage area; after forming the first conductive layer in the peripheral area on the substrate, the following steps are further included:
于所述存储区域形成第二导电结构，所述第二导电结构包括第三导电层、以及位于所述第三导电层上方的第四导电层。A second conductive structure is formed in the storage area, wherein the second conductive structure includes a third conductive layer and a fourth conductive layer located above the third conductive layer.
根据另一些实施例，本公开还提供了一种半导体结构，包括：According to some other embodiments, the present disclosure further provides a semiconductor structure, including:
衬底；substrate;
第一导电结构，位于所述衬底上，包括第一导电层、以及位于所述第一导电层上方的第二导电层，所述第一导电层中包括第一掺杂区、以及位于所述第一掺杂区上方的第二掺杂区，所述第一掺杂区包括第一掺杂元素，所述第二掺杂区包括第二掺杂元素，且所述第二掺杂区的致密度大于所述第一掺杂区的致密度。A first conductive structure is located on the substrate, and includes a first conductive layer and a second conductive layer located above the first conductive layer. The first conductive layer includes a first doping region and a second doping region located above the first doping region. The first doping region includes a first doping element, the second doping region includes a second doping element, and the density of the second doping region is greater than the density of the first doping region.
在一些实施例中，所述第二掺杂区至少覆盖所述第一掺杂区的整个顶面，且所述第二掺杂区的厚度小于所述第一掺杂区的厚度。In some embodiments, the second doping region at least covers the entire top surface of the first doping region, and a thickness of the second doping region is less than a thickness of the first doping region.
在一些实施例中，所述第一导电层的材料为多晶硅材料，所述第二导电层的材料为金属材料，所述第一掺杂元素为第Ⅲ主族或者第Ⅴ主族的元素，所述第二掺杂元素为氮元素。In some embodiments, the material of the first conductive layer is polysilicon material, the material of the second conductive layer is metal material, the first doping element is an element of Group III or Group V, and the second doping element is nitrogen.
在一些实施例中，所述第一导电结构还包括：In some embodiments, the first conductive structure further includes:
第一阻挡层，位于所述第一导电层和所述第二导电层之间，且电连接所述第一导电层和所述第二导电层。The first barrier layer is located between the first conductive layer and the second conductive layer, and electrically connects the first conductive layer and the second conductive layer.
在一些实施例中，所述第一阻挡层的材料为氮化钛、氮化硅钛中的任一种或者两者的组合。In some embodiments, the material of the first barrier layer is any one of titanium nitride and titanium silicon nitride, or a combination of the two.
在一些实施例中，所述第二掺杂区还包括所述第一掺杂元素；In some embodiments, the second doping region further includes the first doping element;
所述第二掺杂区中所述第一掺杂元素的掺杂浓度小于或者等于所述第一掺杂区中所述第一掺杂元素的掺杂浓度。A doping concentration of the first doping element in the second doping region is less than or equal to a doping concentration of the first doping element in the first doping region.
在一些实施例中，所述第二掺杂元素在所述第二掺杂区中的掺杂浓度为1×1017个/cm3～1×1019个/cm3。In some embodiments, the doping concentration of the second doping element in the second doping region is 1×1017 elements/cm3 to 1×1019 elements/cm3 .
在一些实施例中，所述衬底包括存储区域、以及位于所述存储区域外部的外围区域，所述导电结构位于所述外围区域；所述半导体结构还包括：In some embodiments, the substrate includes a storage area and a peripheral area outside the storage area, and the conductive structure is located in the peripheral area; the semiconductor structure further includes:
第二导电结构，位于所述存储区域，所述第二导电结构包括第三导电层、以及位于所述第三导电层上方的第四导电层，所述第三导电层的材料与所述第一掺杂区的材料相同，且所述第四导电层的材料与所述第二导电层的材料相同。A second conductive structure is located in the storage area, and the second conductive structure includes a third conductive layer and a fourth conductive layer located above the third conductive layer, the material of the third conductive layer is the same as the material of the first doping area, and the material of the fourth conductive layer is the same as the material of the second conductive layer.
在一些实施例中，所述第一导电结构为栅电极，所述第二导电结构为位线。In some embodiments, the first conductive structure is a gate electrode, and the second conductive structure is a bit line.
本公开一些实施例提供的半导体结构及其形成方法，通过在第一导电层中形成第一掺杂区、以及位于所述第一掺杂区上方的第二掺杂区，所述第二掺杂区中的第二掺杂元素使得所述第二掺杂区的致密度增大，即使得所述第二掺杂区的致密度大于所述第一掺杂区的致密度，从而能够通过所述第二掺杂区阻挡所述第一掺杂区中的第一掺杂元素向所述第二导电层扩散，确保了所述第一导电结构性能的稳定，改善了所述半导体结构的性能。Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. A first doping region and a second doping region located above the first doping region are formed in a first conductive layer. The second doping element in the second doping region increases the density of the second doping region, i.e., the density of the second doping region is greater than that of the first doping region. The second doping region can thereby block the first doping element in the first doping region from diffusing into the second conductive layer, thereby ensuring the stability of the performance of the first conductive structure and improving the performance of the semiconductor structure.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
附图1是本公开具体实施方式中半导体结构的形成方法流程图；FIG. 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;
附图2-附图9是本公开具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。2 to 9 are schematic cross-sectional views of the main processes in forming a semiconductor structure according to a specific embodiment of the present disclosure.
具体实施方式Detailed ways
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。The specific implementation of the semiconductor structure and the method for forming the same provided by the present disclosure will be described in detail below with reference to the accompanying drawings.
本具体实施方式提供了一种半导体结构的形成方法，附图1是本公开具体实施方式中半导体结构的形成方法流程图，附图2-附图9是本公开具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。如图1-图9所示，所述半导体结构的形成方法，包括如下步骤：This specific embodiment provides a method for forming a semiconductor structure. FIG1 is a flow chart of the method for forming a semiconductor structure in the specific embodiment of the present disclosure. FIG2-FIG9 are schematic cross-sectional views of the main processes in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. As shown in FIG1-FIG9, the method for forming a semiconductor structure includes the following steps:
步骤S11，提供衬底20；Step S11, providing a substrate 20;
步骤S12，于所述衬底20上形成第一导电层，所述第一导电层包括第一掺杂区60、以及位于所述第一掺杂区60上方的第二掺杂区61，所述第一掺杂区60包括第一掺杂元素，所述第二掺杂区61包括第二掺杂元素，且所述第二掺杂区61的致密度大于所述第一掺杂区60的致密度，如图6所示；Step S12, forming a first conductive layer on the substrate 20, wherein the first conductive layer includes a first doping region 60 and a second doping region 61 located above the first doping region 60, wherein the first doping region 60 includes a first doping element, and the second doping region 61 includes a second doping element, and the density of the second doping region 61 is greater than that of the first doping region 60, as shown in FIG6;
步骤S13，于所述第一导电层上方形成第二导电层71，以形成包括所述第一导电层和所述第二导电层71的第一导电结构，如图7所示。Step S13 , forming a second conductive layer 71 on the first conductive layer to form a first conductive structure including the first conductive layer and the second conductive layer 71 , as shown in FIG. 7 .
本具体实施方式中所述的半导体结构可以是但不限于DRAM，以下以所述半导体结构为DRAM为例进行说明。所述20为硅衬底为例进行说明。在其他实施例中，所述衬底20还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底20的顶面用于形成器件结构，所述衬底20的底面是指与所述衬底20的顶面相对的表面。The semiconductor structure described in this specific embodiment can be, but is not limited to, a DRAM. The semiconductor structure is described below by taking the DRAM as an example. The 20 is described by taking a silicon substrate as an example. In other embodiments, the substrate 20 can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The top surface of the substrate 20 is used to form a device structure, and the bottom surface of the substrate 20 refers to the surface opposite to the top surface of the substrate 20.
在一些实施例中，于所述衬底20上形成第一导电层的具体步骤包括：In some embodiments, the specific steps of forming the first conductive layer on the substrate 20 include:
沉积第一材料于所述衬底20的表面，形成初始第一导电层22，如图2所示；Depositing a first material on the surface of the substrate 20 to form an initial first conductive layer 22, as shown in FIG. 2 ;
注入所述第一掺杂元素和所述第二掺杂元素至所述初始第一导电层22，形成包括所述第一掺杂区60和所述第二掺杂区61的所述第一导电层。The first doping element and the second doping element are implanted into the initial first conductive layer 22 to form the first conductive layer including the first doping region 60 and the second doping region 61 .
在一些实施例中，注入所述第一掺杂元素和所述第二掺杂元素至所述初始第一导电层22之前，还包括如下步骤：In some embodiments, before the first doping element and the second doping element are implanted into the initial first conductive layer 22, the following steps are further included:
沉积第二材料于所述初始第一导电层22表面，形成覆盖所述初始第一导电层22的保护层30，如图3所示。A second material is deposited on the surface of the initial first conductive layer 22 to form a protective layer 30 covering the initial first conductive layer 22 , as shown in FIG. 3 .
在一些实施例中，形成包括所述第一掺杂区50和所述第二掺杂区51的所述第一导电层的具体步骤包括：In some embodiments, the specific steps of forming the first conductive layer including the first doping region 50 and the second doping region 51 include:
注入所述第一掺杂元素至全部的所述初始第一导电层22，形成初始第一掺杂区50，如图5所示；Implanting the first doping element into the entire initial first conductive layer 22 to form an initial first doping region 50, as shown in FIG. 5;
注入所述第二掺杂元素至所述初始第一掺杂区50的顶部，形成所述第二掺杂区61，位于所述第二掺杂区61下方的所述初始第一掺杂区50作为所述第一掺杂区60，如图6所示。The second doping element is implanted into the top of the initial first doping region 50 to form the second doping region 61 , and the initial first doping region 50 below the second doping region 61 serves as the first doping region 60 , as shown in FIG. 6 .
以下以所述第一导电结构为栅电极、所述第一掺杂元素为硼元素、所述第二掺杂元素为氮元素、所述第一材料为多晶硅材料为例进行说明。具体来说，在沉积所述第一材料之前，可以先采用原位水汽生成(ISSG)或者沉积工艺(例如原子层沉积工艺)形成覆盖于所述衬底20的顶面的介质层21，如图2所示。所述介质层21后续作为晶体管中栅电极与沟道之间的栅极介质层。之后，可以采用沉积多晶硅材料于所述介质层21的表面，形成覆盖所述介质层21背离所述衬底20的表面的所述初始第一导电层22，如图2所示。为了避免沉积的所述初始第一导电层22的顶面因暴露于环境中而受到损伤(例如被环境中的氧气氧化)，沉积所述初始第一导电层22之后，还可以沉积所述保护层30于所述初始第一导电层22的表面，如图3所示，通过所述保护层30隔绝所述初始第一导电层22与外部环境。在一示例中，所述保护层30的材料可以为氧化物材料(例如二氧化硅)。之后，形成图案化的光阻层40于所述保护层30的表面，如图4所示。沿所述光阻层40中的图案刻蚀所述初始第一导电层22，形成图案化的所述初始第一导电层22，即形成栅电极图案。接着，可以采用等离子体注入等元素掺杂方法注入所述第一掺杂元素至整个所述初始第一导电层22内，形成所述初始第一掺杂区50，如图5所示。此时，所述第一掺杂元素在整个所述初始第一掺杂区50中均匀分布。之后，再次采用等离子体注入等元素掺杂方式注入所述第二掺杂元素至所述初始第一掺杂区50的顶部，形成包括所述第一掺杂元素和所述第二掺杂元素的所述第二掺杂区51，残留于所述第二掺杂区61下方的所述初始第一掺杂区50作为所述第一掺杂区60，如图6所示。本具体实施方式中，可以通过调整注入所述第二掺杂元素时的注入参数(例如离子注入能量等参数)，使得所述第二掺杂元素仅注入至所述初始第一掺杂区50的顶部。之后，对包括所述第一掺杂区60和所述第二掺杂区61的所述第一导电层进行退火处理，以修复所述第一导电层内部的晶格缺陷。The following is an example in which the first conductive structure is a gate electrode, the first doping element is a boron element, the second doping element is a nitrogen element, and the first material is a polysilicon material. Specifically, before depositing the first material, an in-situ water vapor generation (ISSG) or a deposition process (such as an atomic layer deposition process) can be used to form a dielectric layer 21 covering the top surface of the substrate 20, as shown in FIG2. The dielectric layer 21 is subsequently used as a gate dielectric layer between the gate electrode and the channel in the transistor. Afterwards, a polysilicon material can be deposited on the surface of the dielectric layer 21 to form the initial first conductive layer 22 covering the surface of the dielectric layer 21 away from the substrate 20, as shown in FIG2. In order to prevent the top surface of the deposited initial first conductive layer 22 from being damaged due to exposure to the environment (for example, being oxidized by oxygen in the environment), after depositing the initial first conductive layer 22, the protective layer 30 can also be deposited on the surface of the initial first conductive layer 22, as shown in FIG3, and the initial first conductive layer 22 is isolated from the external environment by the protective layer 30. In one example, the material of the protective layer 30 can be an oxide material (such as silicon dioxide). Afterwards, a patterned photoresist layer 40 is formed on the surface of the protective layer 30, as shown in FIG4. The initial first conductive layer 22 is etched along the pattern in the photoresist layer 40 to form a patterned initial first conductive layer 22, that is, a gate electrode pattern is formed. Next, the first doping element can be implanted into the entire initial first conductive layer 22 by an element doping method such as plasma implantation to form the initial first doping region 50, as shown in FIG5. At this time, the first doping element is uniformly distributed throughout the initial first doping region 50. Afterwards, the second doping element is implanted into the top of the initial first doping region 50 by an element doping method such as plasma implantation again to form the second doping region 51 including the first doping element and the second doping element, and the initial first doping region 50 remaining below the second doping region 61 is used as the first doping region 60, as shown in FIG6. In this specific embodiment, the second doping element can be implanted only into the top of the initial first doping region 50 by adjusting the implantation parameters (such as ion implantation energy and other parameters) when the second doping element is implanted. Afterwards, the first conductive layer including the first doping region 60 and the second doping region 61 is annealed to repair lattice defects inside the first conductive layer.
所述第一掺杂元素用于增大所述第一材料的导电性能，所述第二掺杂元素用于增大所述第一材料的致密度。本具体实施方式中的所述第二掺杂区61仅位于所述第一掺杂区50的顶部，使得致密度较大的所述第二掺杂区61既能够阻挡所述第一掺杂区50中的所述第一掺杂元素向外部扩散(例如阻挡所述第一掺杂区50中的所述第一掺杂元素向所述第二导电层71扩散)，又能避免造成所述第一导电层内阻的增大。The first doping element is used to increase the conductivity of the first material, and the second doping element is used to increase the density of the first material. The second doping region 61 in this specific embodiment is only located on the top of the first doping region 50, so that the second doping region 61 with a higher density can not only block the first doping element in the first doping region 50 from diffusing to the outside (for example, blocking the first doping element in the first doping region 50 from diffusing to the second conductive layer 71), but also avoid increasing the internal resistance of the first conductive layer.
本具体实施方式是以所述第一掺杂元素在所述第一掺杂区60中的掺杂浓度与在所述第二掺杂区61中的掺杂浓度相等为例进行说明的。在其他实施例中，本领域技术人员人员也可以使得所述第二掺杂区61中所述第一掺杂元素的掺杂浓度小于所述第一掺杂区60中的所述第一掺杂元素的掺杂浓度，从而避免所述第二掺杂区61中的所述第一掺杂元素向所述第一导电层外部扩散(例如避免所述第二掺杂区61中的所述第一掺杂元素向所述第二导电层71扩散)。This specific embodiment is described by taking the doping concentration of the first doping element in the first doping region 60 as being equal to the doping concentration in the second doping region 61. In other embodiments, those skilled in the art may also make the doping concentration of the first doping element in the second doping region 61 less than the doping concentration of the first doping element in the first doping region 60, thereby preventing the first doping element in the second doping region 61 from diffusing to the outside of the first conductive layer (for example, preventing the first doping element in the second doping region 61 from diffusing to the second conductive layer 71).
为了更好的避免所述第一掺杂区60中的所述第一掺杂元素向所述第一导电层外部扩散，在一些实施例中，所述第二掺杂区61至少覆盖所述第一掺杂区60的整个顶面，且所述第二掺杂区61的厚度小于所述第一掺杂区60的厚度。其中，所述第二掺杂区61的厚度是指所述第二掺杂区61在沿垂直于所述衬底20的顶面的方向上的厚度，所述第一掺杂区60的厚度是指所述第一掺杂区60在沿垂直于所述衬底20的顶面的方向上的厚度。In order to better prevent the first doping element in the first doping region 60 from diffusing to the outside of the first conductive layer, in some embodiments, the second doping region 61 at least covers the entire top surface of the first doping region 60, and the thickness of the second doping region 61 is less than the thickness of the first doping region 60. The thickness of the second doping region 61 refers to the thickness of the second doping region 61 in a direction perpendicular to the top surface of the substrate 20, and the thickness of the first doping region 60 refers to the thickness of the first doping region 60 in a direction perpendicular to the top surface of the substrate 20.
在一些实施例中，所述第一导电层的材料为多晶硅材料，所述第二导电层71的材料为金属材料，所述第一掺杂元素为第Ⅲ主族或者第Ⅴ主族的元素，所述第二掺杂元素为氮元素。在一示例中，所述第一导电结构为PMOS晶体管中的栅电极，所述第一掺杂元素为硼元素，所述第二掺杂元素为氮元素，所述第二导电层71的材料可以为但不限于金属钨。当所述第一导电结构为晶体管时，通过在所述第一导电层中设置所述第一掺杂区60、以及位于所述第一掺杂区60上方且致密度大于所述第一掺杂区60的所述第二掺杂区61，能够阻挡所述第一掺杂区60中的所述第一掺杂元素向所述第二导电层71，从而能够降低所述晶体管中反型层的厚度，极大的改善了所述晶体管的电性能。In some embodiments, the material of the first conductive layer is polysilicon material, the material of the second conductive layer 71 is metal material, the first doping element is an element of the III main group or the V main group, and the second doping element is nitrogen. In one example, the first conductive structure is a gate electrode in a PMOS transistor, the first doping element is boron, the second doping element is nitrogen, and the material of the second conductive layer 71 may be but is not limited to metal tungsten. When the first conductive structure is a transistor, by providing the first doping region 60 in the first conductive layer, and the second doping region 61 located above the first doping region 60 and having a greater density than the first doping region 60, the first doping element in the first doping region 60 can be blocked from moving toward the second conductive layer 71, thereby reducing the thickness of the inversion layer in the transistor, greatly improving the electrical performance of the transistor.
所述第二掺杂元素在所述第二掺杂区61中的掺杂浓度不宜过小，否则不能有效的阻挡所述第一掺杂元素向所述第一导电层外部扩散；所述第二掺杂元素在所述第二掺杂区61中的掺杂浓度也不宜过大，否则会导致所述第一导电层内阻的增大。在一些实施例中，所述第二掺杂元素在所述第二掺杂区中的掺杂浓度为1×1017个/cm3～1×1019个/cm3，以在有效的阻挡所述第一掺杂元素向所述第一导电层外部扩散的同时，避免所述第一导电层内阻的增大。The doping concentration of the second doping element in the second doping region 61 should not be too small, otherwise it cannot effectively block the first doping element from diffusing to the outside of the first conductive layer; the doping concentration of the second doping element in the second doping region 61 should not be too large, otherwise it will lead to an increase in the internal resistance of the first conductive layer. In some embodiments, the doping concentration of the second doping element in the second doping region is 1×1017 cells/cm3 to 1×1019 cells/cm3 , so as to effectively block the first doping element from diffusing to the outside of the first conductive layer and avoid an increase in the internal resistance of the first conductive layer.
在一些实施例中，于所述第一导电层上方形成第二导电层71的具体步骤包括：In some embodiments, the specific steps of forming the second conductive layer 71 above the first conductive layer include:
于所述第一导电层的顶面形成第一阻挡层70；forming a first barrier layer 70 on the top surface of the first conductive layer;
于所述第一阻挡层70的顶面形成所述第二导电层71，所述第一阻挡层70电连接所述第一导电层和所述第二导电层71。The second conductive layer 71 is formed on the top surface of the first barrier layer 70 , and the first barrier layer 70 electrically connects the first conductive layer and the second conductive layer 71 .
在一些实施例中，所述第一阻挡层70的材料为氮化钛、氮化硅钛中的任一种或者两者的组合。In some embodiments, the material of the first barrier layer 70 is any one of titanium nitride and titanium silicon nitride, or a combination of the two.
具体来说，通过在所述第一导电层和所述第二导电层71之间设置所述第一阻挡层70，一方面，能够阻挡所述第二导电层71中的导电粒子向所述第一导电层扩散(例如当所述第二导电层71的材料为金属材料时，所述第一阻挡层70能够阻挡所述第二导电层71中的金属离子向所述第一导电层扩散)；另一方面，还能够进一步阻挡所述第一导电层中的所述第一掺杂元素向所述第二导电层71扩散。所述第一阻挡层70这两方面的阻挡作用，都有助于提高所述半导体结构的电性能。Specifically, by providing the first barrier layer 70 between the first conductive layer and the second conductive layer 71, on the one hand, the conductive particles in the second conductive layer 71 can be blocked from diffusing into the first conductive layer (for example, when the material of the second conductive layer 71 is a metal material, the first barrier layer 70 can block the metal ions in the second conductive layer 71 from diffusing into the first conductive layer); on the other hand, the first doping element in the first conductive layer can be further blocked from diffusing into the second conductive layer 71. Both of these blocking effects of the first barrier layer 70 are helpful to improve the electrical performance of the semiconductor structure.
在一些实施例中，所述衬底20包括存储区域、以及位于所述存储区域外部的外围区域；于所述衬底20上形成第一导电层的具体步骤包括：In some embodiments, the substrate 20 includes a storage area and a peripheral area outside the storage area; the specific steps of forming the first conductive layer on the substrate 20 include:
沉积第一材料于所述衬底20的表面，于所述外围区域形成初始第一导电层22、并同时于所述存储区域形成初始第三导电层；Depositing a first material on the surface of the substrate 20 to form an initial first conductive layer 22 in the peripheral region and simultaneously forming an initial third conductive layer in the storage region;
注入所述第一掺杂元素至全部的所述初始第一导电层22和全部的所述初始接触层，于所述外围区域形成初始第一掺杂区50(参见图5)、并于所述存储区域形成第三导电层82(参见图8)；Implanting the first doping element into the entirety of the initial first conductive layer 22 and the entirety of the initial contact layer to form an initial first doping region 50 in the peripheral region (see FIG. 5 ) and to form a third conductive layer 82 in the storage region (see FIG. 8 );
注入所述第二掺杂元素至所述初始第一掺杂区50的顶部，形成所述第二掺杂区61，位于所述第二掺杂区61下方的所述初始第一掺杂区50作为所述第一掺杂区60。The second doping element is implanted into the top of the initial first doping region 50 to form the second doping region 61 , and the initial first doping region 50 below the second doping region 61 serves as the first doping region 60 .
在一些实施例中，于所述第一导电层上方形成第二导电层71的具体步骤包括：In some embodiments, the specific steps of forming the second conductive layer 71 above the first conductive layer include:
于所述第一导电层上方形成所述第二导电层71、并同时于所述存储区域的所述第三导电层82上方形成第四导电层84，以形成包括所述第一导电层和所述第二导电层71的所述第一导电结构、并形成包括所述第三导电层82和所述第四导电层84的第二导电结构。The second conductive layer 71 is formed above the first conductive layer, and the fourth conductive layer 84 is simultaneously formed above the third conductive layer 82 of the storage area to form the first conductive structure including the first conductive layer and the second conductive layer 71, and to form the second conductive structure including the third conductive layer 82 and the fourth conductive layer 84.
以下以所述半导体结构为DRAM为例进行说明。举例来说，所述衬底20包括所述存储区域和所述外围区域，所述存储区域包括呈阵列排布的多个有源区80、以及用于隔离相邻所述有源区80的第一隔离结构81，如图8所示。所述外围区域包括外围沟道区91、以及用于隔离相邻所述沟道区91的第二隔离结构90，如图9所示。沉积所述第一材料于所述衬底20的所述存储区域和所述外围区域，同时形成位于所述外围区域的所述初始第一导电层22和位于所述存储区域的所述初始第三导电层。之后，同时向所述初始第一导电层22和所述初始第三导电层掺杂所述第一掺杂元素，以同时形成所述初始第一掺杂区50和所述第三导电层82。通过同步形成所述初始第一掺杂区50和所述第三导电层82，可以简化所述半导体结构的制造工艺，提高所述半导体结构的制造效率。之后，仅向所述外围区域的所述初始第一掺杂区50的顶部注入所述第二掺杂元素，以于所述外围区域形成包括所述第一掺杂区60和所述第二掺杂区61的所述第一导电层。之后，可以于所述第一导电层上形成所述第一阻挡层70、并同步于所述第三导电层82上形成第二阻挡层83，并于所述第一阻挡层70上形成所述第二导电层71、并同步于所述第二阻挡层83上形成所述第四导电层84，如图8和图9所示。采用上述方法形成的所述第一导电结构和所述第二导电结构，既能够使得所述第一导电结构中所述第一导电层内的所述第一掺杂元素向所述第二导电层71扩散，又不影响所述存储区域内所述第二导电结构的性能，例如不会导致所述第二导电结构内部接触电阻的增大，还能够进一步简化所述半导体结构的制程工艺。The following description is made by taking the semiconductor structure as a DRAM as an example. For example, the substrate 20 includes the storage area and the peripheral area, and the storage area includes a plurality of active areas 80 arranged in an array, and a first isolation structure 81 for isolating adjacent active areas 80, as shown in FIG8 . The peripheral area includes a peripheral channel area 91, and a second isolation structure 90 for isolating adjacent channel areas 91, as shown in FIG9 . The first material is deposited on the storage area and the peripheral area of the substrate 20, and the initial first conductive layer 22 located in the peripheral area and the initial third conductive layer located in the storage area are formed at the same time. Afterwards, the initial first conductive layer 22 and the initial third conductive layer are doped with the first doping element at the same time to simultaneously form the initial first doping area 50 and the third conductive layer 82. By simultaneously forming the initial first doping area 50 and the third conductive layer 82, the manufacturing process of the semiconductor structure can be simplified and the manufacturing efficiency of the semiconductor structure can be improved. Afterwards, the second doping element is only implanted into the top of the initial first doping region 50 in the peripheral region to form the first conductive layer including the first doping region 60 and the second doping region 61 in the peripheral region. Afterwards, the first barrier layer 70 can be formed on the first conductive layer, and the second barrier layer 83 can be formed on the third conductive layer 82 simultaneously, and the second conductive layer 71 can be formed on the first barrier layer 70, and the fourth conductive layer 84 can be formed on the second barrier layer 83 simultaneously, as shown in FIG8 and FIG9. The first conductive structure and the second conductive structure formed by the above method can make the first doping element in the first conductive layer of the first conductive structure diffuse to the second conductive layer 71, and do not affect the performance of the second conductive structure in the storage region, for example, it will not cause the increase of the internal contact resistance of the second conductive structure, and can further simplify the process technology of the semiconductor structure.
在另一些实施例中，所述衬底包括存储区域、以及位于所述存储区域外部的外围区域；于所述衬底20上的所述外围区域形成所述第一导电层之后，还包括如下步骤：In some other embodiments, the substrate includes a storage area and a peripheral area outside the storage area; after the first conductive layer is formed in the peripheral area on the substrate 20, the following steps are further included:
于所述存储区域形成第二导电结构，所述第二导电结构包括第三导电层82、以及位于所述第三导电层82上方的第四导电层84。A second conductive structure is formed in the storage region, wherein the second conductive structure includes a third conductive layer 82 and a fourth conductive layer 84 located above the third conductive layer 82 .
以下仍以所述半导体结构为DRAM为例进行说明。举例来说，所述衬底20包括所述存储区域和所述外围区域，所述存储区域包括呈阵列排布的多个有源区80、以及用于隔离相邻所述有源区80的第一隔离结构81，如图8所示。所述外围区域包括外围沟道区91、以及用于隔离相邻所述沟道区91的第二隔离结构90，如图9所示。在所述外围区域形成所述第一导电层之后，再于所述存储区域形成包括所述第三导电层82、所述第二阻挡层83和所述第四导电层84的所述第二导电结构。之后，再于所述外围区域形成位于所述第一导电层上的所述第一阻挡层70和所述第二导电层71。采用这种方式，可以灵活调整所述存储区域中的所述第三导电层82的材料、掺杂元素的种类、掺杂浓度、以及所述第二阻挡层83的材料，使得所述外围区域中所述第一导电结构的形成工艺与所述存储区域中所述第二导电结构的形成工艺互不影响，从而有助于进一步改善所述半导体结构的性能。The semiconductor structure is still described below as a DRAM. For example, the substrate 20 includes the storage area and the peripheral area, and the storage area includes a plurality of active areas 80 arranged in an array, and a first isolation structure 81 for isolating adjacent active areas 80, as shown in FIG8 . The peripheral area includes a peripheral channel area 91, and a second isolation structure 90 for isolating adjacent channel areas 91, as shown in FIG9 . After the first conductive layer is formed in the peripheral area, the second conductive structure including the third conductive layer 82, the second barrier layer 83 and the fourth conductive layer 84 is formed in the storage area. After that, the first barrier layer 70 and the second conductive layer 71 located on the first conductive layer are formed in the peripheral area. In this way, the material of the third conductive layer 82 in the storage area, the type of doping elements, the doping concentration, and the material of the second barrier layer 83 can be flexibly adjusted, so that the formation process of the first conductive structure in the peripheral area and the formation process of the second conductive structure in the storage area do not affect each other, thereby helping to further improve the performance of the semiconductor structure.
本具体实施方式还提供了一种半导体结构。本具体实施方式提供的半导体结构可以采用如图1-图9所示的半导体结构的形成方法形成。本具体实施方式提供的半导体结构的示意图可以参见图7-图9。如图7-图9所示，所述半导体结构，包括：This specific embodiment also provides a semiconductor structure. The semiconductor structure provided in this specific embodiment can be formed by using the method for forming a semiconductor structure as shown in Figures 1 to 9. The schematic diagrams of the semiconductor structure provided in this specific embodiment can be seen in Figures 7 to 9. As shown in Figures 7 to 9, the semiconductor structure includes:
衬底20；Substrate 20;
第一导电结构，位于所述衬底20上，包括第一导电层、以及位于所述第一导电层上方的第二导电层71，所述第一导电层中包括第一掺杂区60、以及位于所述第一掺杂区60上方的第二掺杂区61，所述第一掺杂区60包括第一掺杂元素，所述第二掺杂区61包括第二掺杂元素，且所述第二掺杂区62的致密度大于所述第一掺杂区61的致密度。The first conductive structure is located on the substrate 20, and includes a first conductive layer and a second conductive layer 71 located above the first conductive layer. The first conductive layer includes a first doping region 60 and a second doping region 61 located above the first doping region 60. The first doping region 60 includes a first doping element, the second doping region 61 includes a second doping element, and the density of the second doping region 62 is greater than the density of the first doping region 61.
具体来说，所述第一掺杂元素用于增大所述第一材料的导电性能，所述第二掺杂元素用于增大所述第一材料的致密度。通过在所述第一导电层中的所述第一掺杂区60的上方设置所述第二掺杂区61，且使得所述第二掺杂区61的致密度大于所述第一掺杂区60的致密度，使得能够通过所述第二掺杂区61阻挡所述第一掺杂区中的所述第一掺杂元素向所述第二导电层71扩散，从而确保了所述第一导电层的导电性能，改善了所述半导体结构的性能。Specifically, the first doping element is used to increase the conductivity of the first material, and the second doping element is used to increase the density of the first material. By arranging the second doping region 61 above the first doping region 60 in the first conductive layer, and making the density of the second doping region 61 greater than the density of the first doping region 60, the first doping element in the first doping region can be blocked from diffusing to the second conductive layer 71 through the second doping region 61, thereby ensuring the conductivity of the first conductive layer and improving the performance of the semiconductor structure.
为了更好的避免所述第一掺杂区60中的所述第一掺杂元素向所述第一导电层外部扩散，在一些实施例中，所述第二掺杂区61至少覆盖所述第一掺杂区60的整个顶面，且所述第二掺杂区61的厚度小于所述第一掺杂区60的厚度。本具体实施方式中的所述第二掺杂区61仅位于所述第一掺杂区50的顶部，使得致密度较大的所述第二掺杂区61既能够阻挡所述第一掺杂区50中的所述第一掺杂元素向外部扩散(例如阻挡所述第一掺杂区50中的所述第一掺杂元素向所述第二导电层71扩散)，又能避免造成所述第一导电层内阻的增大。In order to better prevent the first doping element in the first doping region 60 from diffusing to the outside of the first conductive layer, in some embodiments, the second doping region 61 at least covers the entire top surface of the first doping region 60, and the thickness of the second doping region 61 is less than the thickness of the first doping region 60. The second doping region 61 in this specific embodiment is only located on the top of the first doping region 50, so that the second doping region 61 with a higher density can not only block the first doping element in the first doping region 50 from diffusing to the outside (for example, block the first doping element in the first doping region 50 from diffusing to the second conductive layer 71), but also avoid increasing the internal resistance of the first conductive layer.
在一些实施例中，所述第一导电层的材料为多晶硅材料，所述第二导电层71的材料为金属材料，所述第一掺杂元素为第Ⅲ主族或者第Ⅴ主族的元素，所述第二掺杂元素为氮元素。In some embodiments, the material of the first conductive layer is polysilicon material, the material of the second conductive layer 71 is metal material, the first doping element is an element of Group III or Group V, and the second doping element is nitrogen.
在一些实施例中，所述第一导电结构还包括：In some embodiments, the first conductive structure further includes:
第一阻挡层70，位于所述第一导电层和所述第二导电层71之间，且电连接所述第一导电层和所述第二导电层71。The first barrier layer 70 is located between the first conductive layer and the second conductive layer 71 , and electrically connects the first conductive layer and the second conductive layer 71 .
在一些实施例中，所述第一阻挡层70的材料为氮化钛、氮化硅钛中的任一种或者两者的组合。In some embodiments, the material of the first barrier layer 70 is any one of titanium nitride and titanium silicon nitride, or a combination of the two.
在一些实施例中，所述第二掺杂区61还包括所述第一掺杂元素；In some embodiments, the second doping region 61 further includes the first doping element;
所述第二掺杂区61中所述第一掺杂元素的掺杂浓度小于或者等于所述第一掺杂区60中所述第一掺杂元素的掺杂浓度。The doping concentration of the first doping element in the second doping region 61 is less than or equal to the doping concentration of the first doping element in the first doping region 60 .
在一示例中，所述第二掺杂区61中所述第一掺杂元素的掺杂浓度等于所述第一掺杂区60中所述第一掺杂元素的掺杂浓度，从而可以进一步简化所述半导体结构的制造工艺。在另一示例中，所述第二掺杂区61中所述第一掺杂元素的掺杂浓度小于所述第一掺杂区60中所述第一掺杂元素的掺杂浓度，从而可以进一步避免所述第二掺杂区61中的所述第一掺杂元素向所述第二导电层71扩散。In one example, the doping concentration of the first doping element in the second doping region 61 is equal to the doping concentration of the first doping element in the first doping region 60, thereby further simplifying the manufacturing process of the semiconductor structure. In another example, the doping concentration of the first doping element in the second doping region 61 is less than the doping concentration of the first doping element in the first doping region 60, thereby further preventing the first doping element in the second doping region 61 from diffusing into the second conductive layer 71.
所述第二掺杂元素在所述第二掺杂区61中的掺杂浓度不宜过小，否则不能有效的阻挡所述第一掺杂元素向所述第一导电层外部扩散；所述第二掺杂元素在所述第二掺杂区61中的掺杂浓度也不宜过大，否则会导致所述第一导电层内阻的增大。在一些实施例中，所述第二掺杂元素在所述第二掺杂区61中的掺杂浓度为1×1017个/cm3～1×1019个/cm3，以在有效的阻挡所述第一掺杂元素向所述第一导电层外部扩散的同时，避免所述第一导电层内阻的增大。The doping concentration of the second doping element in the second doping region 61 should not be too small, otherwise it cannot effectively block the first doping element from diffusing to the outside of the first conductive layer; the doping concentration of the second doping element in the second doping region 61 should not be too large, otherwise it will lead to an increase in the internal resistance of the first conductive layer. In some embodiments, the doping concentration of the second doping element in the second doping region 61 is 1×1017 cells/cm3 to 1×1019 cells/cm3 , so as to effectively block the first doping element from diffusing to the outside of the first conductive layer and avoid an increase in the internal resistance of the first conductive layer.
在一些实施例中，所述衬底20包括存储区域、以及位于所述存储区域外部的外围区域，所述导电结构位于所述外围区域；所述半导体结构还包括：In some embodiments, the substrate 20 includes a storage area and a peripheral area outside the storage area, and the conductive structure is located in the peripheral area; the semiconductor structure further includes:
第二导电结构，位于所述存储区域，所述第二导电结构包括第三导电层82、以及位于所述第三导电层82上方的第四导电层84，所述第三导电层82的材料与所述第一掺杂区60的材料相同，且所述第四导电层84的材料与所述第二导电层71的材料相同。The second conductive structure is located in the storage area, and the second conductive structure includes a third conductive layer 82 and a fourth conductive layer 84 located above the third conductive layer 82, the material of the third conductive layer 82 is the same as the material of the first doping area 60, and the material of the fourth conductive layer 84 is the same as the material of the second conductive layer 71.
在一示例中，所述存储区域中的所述第二导电结构中的所述第三导电层82可以与所述外围区域中的所述第一导电结构中的所述第一掺杂区60同步形成，且所述存储区域中的所述第二导电结构中的所述第四导电层84可以与所述外围区域中的所述第一导电结构中的所述第二导电层71同步形成，以进一步简化所述半导体结构的制造工艺。在另一示例中，所述存储区域中的所述第二导电结构与所述外围区域中的所述第一导电结构分开形成，从而可以灵活调整所述第一导电结构和所述第二导电结构的材料及结构，有助于进一步改善所述半导体结构的性能。In one example, the third conductive layer 82 in the second conductive structure in the storage area can be formed synchronously with the first doped region 60 in the first conductive structure in the peripheral area, and the fourth conductive layer 84 in the second conductive structure in the storage area can be formed synchronously with the second conductive layer 71 in the first conductive structure in the peripheral area, so as to further simplify the manufacturing process of the semiconductor structure. In another example, the second conductive structure in the storage area is formed separately from the first conductive structure in the peripheral area, so that the materials and structures of the first conductive structure and the second conductive structure can be flexibly adjusted, which helps to further improve the performance of the semiconductor structure.
在一些实施例中，所述第一导电结构为栅电极，所述第二导电结构为位线。即所述第一导电结构为位于所述外围区域的所述栅电极，即外围栅电极，所述第二导电结构为位于所述存储区域的所述位线。In some embodiments, the first conductive structure is a gate electrode, and the second conductive structure is a bit line. That is, the first conductive structure is the gate electrode located in the peripheral region, that is, the peripheral gate electrode, and the second conductive structure is the bit line located in the storage region.
本具体实施方式一些实施例提供的半导体结构及其形成方法，通过在第一导电层中形成第一掺杂区、以及位于所述第一掺杂区上方的第二掺杂区，所述第二掺杂区中的第二掺杂元素使得所述第二掺杂区的致密度增大，即使得所述第二掺杂区的致密度大于所述第一掺杂区的致密度，从而能够通过所述第二掺杂区阻挡所述第一掺杂区中的第一掺杂元素向所述第二导电层扩散，确保了所述第一导电结构性能的稳定，改善了所述半导体结构的性能。Some embodiments of the present specific implementation manner provide a semiconductor structure and a method for forming the same. By forming a first doping region in a first conductive layer and a second doping region located above the first doping region, the second doping element in the second doping region increases the density of the second doping region, i.e., the density of the second doping region is greater than that of the first doping region. Thus, the first doping element in the first doping region can be blocked from diffusing into the second conductive layer through the second doping region, thereby ensuring the stability of the performance of the first conductive structure and improving the performance of the semiconductor structure.
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。The above is only a preferred embodiment of the present disclosure. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.
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