Disclosure of Invention
Based on the above, the application provides a transistor testing method and a memory monitoring method, which can comprehensively detect whether a transistor to be tested has a defect or not, and prevent a chip containing the defect transistor from flowing out, so that the product yield is improved.
According to some embodiments, an aspect of the present application provides a transistor testing method, including:
Applying a working voltage to a grid electrode of a transistor to be tested, grounding a source electrode of the transistor to be tested, and obtaining a first current-voltage characteristic curve according to a change relation between a first test voltage applied to a drain electrode of the transistor to be tested and a first test current under the action of the first test voltage;
Continuously applying the working voltage to the grid electrode, grounding the drain electrode, and obtaining a second current-voltage characteristic curve according to the change relation between the second test voltage applied to the source electrode and the second test current under the action of the second test voltage;
And comparing the first current-voltage characteristic curve with the second current-voltage characteristic curve to obtain a difference degree, and judging that the transistor to be tested is abnormal when the difference degree exceeds a preset threshold value.
In some embodiments, the first test voltage comprises a plurality of first sub-voltages that dynamically vary, and the first test current comprises a plurality of first sub-currents that correspond one-to-one to the plurality of first sub-voltages; the second test voltage comprises a plurality of second sub-voltages which dynamically change, and the second test current comprises a plurality of second sub-currents which are in one-to-one correspondence with the plurality of second sub-voltages;
the comparing the first current-voltage characteristic curve and the second current-voltage characteristic curve to obtain a difference degree comprises the following steps:
Determining a first sampling point and a second sampling point from the first current-voltage characteristic curve and the second current-voltage characteristic curve respectively; the first sub-voltage corresponding to the first sampling point and the second sub-voltage corresponding to the second sampling point have the same voltage value;
The difference between the first sub-current corresponding to the first sampling point and the second sub-current corresponding to the second sampling point is taken as the degree of difference.
In some embodiments, the preset threshold comprises an order of magnitude of current.
In some embodiments, when the difference exceeds a preset threshold, determining that the transistor under test is abnormal includes:
And if the difference exceeds a preset threshold and the first current-voltage characteristic curve is positioned below the second current-voltage characteristic curve, judging that the source electrode is abnormal.
In some embodiments, when the difference exceeds a preset threshold, determining that the transistor under test is abnormal includes:
and if the difference exceeds a preset threshold and the second current-voltage characteristic curve is positioned below the first current-voltage characteristic curve, judging that the drain electrode is abnormal.
In some embodiments, the voltage values of the first sub-voltage corresponding to the first sampling point and the second sub-voltage corresponding to the second sampling point are in a range of 0.8v to 1.5v.
In some embodiments, the first sub-voltage corresponding to the first sampling point and the second sub-voltage corresponding to the second sampling point have the same voltage value as the operating voltage.
In some embodiments, the transistor under test is located on a substrate; the substrate comprises a first type well region and two second type doped regions embedded in the first type well region and arranged at intervals; the source electrode is in contact with one of the second-type doped regions and the drain electrode is in contact with the other of the second-type doped regions;
The grounding the source electrode of the transistor to be tested comprises the following steps: accessing the first type well region to a reference voltage;
the grounding the drain electrode comprises: and continuing to access the first type well region to the reference voltage.
In some embodiments, the accessing the first type well region to a reference voltage includes: grounding the first type well region;
The continuing to access the first type well region to the reference voltage includes: and continuing to grounded the first type well region.
According to some embodiments, another aspect of the present application provides a memory monitoring method for monitoring a memory including a plurality of transistors; the memory monitoring method comprises the following steps:
Selecting a transistor to be tested from a plurality of transistors; the transistor under test is tested using the transistor test method described in some of the embodiments above.
The transistor testing method and the memory monitoring method provided by the application have the following unexpected advantages:
In the embodiment of the application, working voltage is firstly applied to the grid electrode of the transistor to be tested, and the source electrode of the transistor to be tested is grounded, so that a first current-voltage characteristic curve can be obtained according to the change relation between the first test voltage applied to the drain electrode of the transistor to be tested and the first test current under the action of the first test voltage; and then, continuously applying working voltage to the grid electrode and grounding the drain electrode, so that a second current-voltage characteristic curve can be obtained according to the change relation between the second test voltage applied to the source electrode and the second test current under the action of the second test voltage. Obtaining the difference between the first current-voltage characteristic curve and the second current-voltage characteristic curve by comparing the two curves; when the difference exceeds a preset threshold, the drain electrode or the source electrode of the transistor to be tested is abnormal, and the transistor to be tested is judged to be abnormal. By adopting the embodiment of the application, whether the drain electrode is abnormal or the source electrode is abnormal can be found in time, so that whether the transistor to be tested has a defect or not can be comprehensively detected, the chip containing the defective transistor is prevented from flowing out, and the product yield is improved. The method has the advantages of simple steps, easy realization and high test efficiency, and can be conveniently applied to the chip production and manufacturing process.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," it can be directly on the other element or layer or intervening elements or layers may be present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, test voltages and/or sections, these elements, components, regions, layers, test voltages and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, test voltage or section from another element, component, region, layer, test voltage or section. Thus, a first element, component, region, layer, test voltage or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first test voltage may be referred to as a second test voltage, and similarly, the second test voltage may be referred to as a first test voltage; the first test voltage and the second test voltage are different test voltages.
Spatial relationship terms, such as "located on," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "on" would then be oriented "under" the other elements or features. Thus, the exemplary term "located on" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
At present, on-line transistor electrical measurement cannot comprehensively detect whether a transistor to be detected has a defect, so that the defect transistor flows out easily to influence the product yield.
In some examples, for example, a static random access memory (Static Random Access Memory, abbreviated as SRAM), if any transistor in each memory Cell (SRAM Cell) is electrically abnormal, there is a failure risk in writing or reading the SRAM, which easily results in a reduction in the yield of products. Therefore, in the existing chip production and manufacturing process, in order to monitor the electrical characteristics of each transistor in the SRAM, test patterns with the same size are usually designed on the periphery of the chip, which is compatible with the chip production process, and whether the electrical characteristics of the transistors meet the requirements is judged by on-line WAT monitoring data.
However, in the conventional electrical measurement of the on-line transistor, an operating voltage is usually applied only to the Drain (Drain) terminal of the transistor, and a voltage of 0V is applied to the Source (Source) terminal, so that the electrical parameter measured by the method cannot accurately determine whether the Drain terminal and the Source terminal of the transistor are abnormal. For example, if Silicon damage (Silicon damage) has occurred on the Drain terminal of the transistor, the Drain terminal of the transistor will be in a high-resistance state, resulting in failure of the SRAM when writing or reading, but it is difficult to find an abnormality only by WAT monitoring data.
However, if a wafer test (Chip Probing) is performed on the Chip, although defects in the Chip manufacturing process can be detected more comprehensively and completely, the Chip is required to complete the whole process manufacturing flow, and the whole wafer test process is completed, so that a large amount of resources are input, which is time-consuming and labor-consuming.
In view of the above-mentioned shortcomings in the related art, the present application provides a transistor testing method and a memory monitoring method, which can be used for detecting whether a transistor has a defect. The details of which will be elucidated in the following examples.
In one aspect, the present application provides a transistor testing method according to some embodiments. It will be appreciated that the transistors referred to in the embodiments of the present application may include PMOS transistors and NMOS transistors, but are not limited thereto.
Referring to fig. 1, in some embodiments, the transistor testing method may specifically include the following steps:
s100: and applying a working voltage to the grid electrode of the transistor to be tested, grounding the source electrode of the transistor to be tested, and obtaining a first current-voltage characteristic curve according to the change relation between the first test voltage applied to the drain electrode of the transistor to be tested and the first test current under the action of the first test voltage.
S200: and continuously applying working voltage to the grid electrode, grounding the drain electrode, and obtaining a second current-voltage characteristic curve according to the change relation between the second test voltage applied to the source electrode and the second test current under the action of the second test voltage.
S300: and comparing the first current-voltage characteristic curve with the second current-voltage characteristic curve to obtain a difference degree, and judging that the transistor to be tested is abnormal when the difference degree exceeds a preset threshold value.
In the transistor testing method provided in the above embodiment, a working voltage is applied to a gate of a transistor to be tested, and a source of the transistor to be tested is grounded, so that a first current-voltage characteristic curve can be obtained according to a change relationship between a first test voltage applied to a drain of the transistor to be tested and a first test current under the action of the first test voltage; and then, continuously applying working voltage to the grid electrode and grounding the drain electrode, so that a second current-voltage characteristic curve can be obtained according to the change relation between the second test voltage applied to the source electrode and the second test current under the action of the second test voltage. Obtaining the difference between the first current-voltage characteristic curve and the second current-voltage characteristic curve by comparing the two curves; when the difference exceeds a preset threshold, the drain electrode or the source electrode of the transistor to be tested is abnormal, and the transistor to be tested is judged to be abnormal.
By adopting the transistor testing method, whether the drain electrode is abnormal or the source electrode is abnormal can be found timely, so that whether the transistor to be tested has a defect or not can be comprehensively detected, the chip containing the defective transistor is prevented from flowing out, and the product yield is improved. In addition, the transistor testing method is simple in steps, easy to realize, high in testing efficiency and convenient to apply to the chip production and manufacturing process.
As an example, the first test voltage may include a plurality of first sub-voltages that dynamically vary, and the first test current may include a plurality of first sub-currents that one-to-one correspond to the plurality of first sub-voltages. Correspondingly, the second test voltage may include a plurality of second sub-voltages that dynamically vary, and the second test current may include a plurality of second sub-currents that correspond one-to-one to the plurality of second sub-voltages.
Referring to fig. 2, in some embodiments, the step of comparing the first current-voltage characteristic curve and the second current-voltage characteristic curve to obtain the difference in step S300 may specifically include the following steps:
S310: determining a first sampling point and a second sampling point from the first current-voltage characteristic curve and the second current-voltage characteristic curve respectively; the first sub-voltage corresponding to the first sampling point and the second sub-voltage corresponding to the second sampling point have the same voltage value.
S320: the difference between the first sub-current corresponding to the first sampling point and the second sub-current corresponding to the second sampling point is taken as the degree of difference.
It should be understood that, although the steps in the flowcharts of fig. 1 to 2 are sequentially shown as indicated by arrows, the steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1-2 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the steps or stages in other steps or other steps.
In order to more clearly illustrate the transistor testing method in some of the above embodiments, some embodiments of the present application are understood below with reference to fig. 3 to 6.
As an example, as shown in fig. 3 and 4, a transistor to be tested according to the present application may be located on the substrate 2. Illustratively, the substrate 2 may be constructed of a semiconductor material, an insulating material, a conductor material, or any combination of material types thereof. The substrate 2 may have a single-layer structure or a multilayer structure. For example, the substrate 2 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Or also for example, the substrate 2 may be a layered substrate comprising a stack of layers such as Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator, etc.
As an example, as shown in fig. 3 and 4, the substrate 2 may include a first type well region 21 and two second type doped regions 22 embedded in the first type well region 21 and spaced apart. The source 12 is in contact with one of the second type doped regions 22 and the drain 13 is in contact with the other second type doped region 22.
In step S100, an operating voltage is applied to the gate 11 of the transistor to be tested, the source 12 of the transistor to be tested is grounded, and a first current-voltage characteristic curve is obtained according to a variation relationship between a first test voltage applied to the drain 13 of the transistor to be tested and a first test current under the action of the first test voltage.
As an example, the first test voltage may include a plurality of first sub-voltages that dynamically vary, and the first test current may include a plurality of first sub-currents that one-to-one correspond to the plurality of first sub-voltages.
In some embodiments, the first type well region 21 may also be connected to a reference voltage when the source 12 of the transistor under test is grounded. As an example, the first type well region 21 may be grounded.
In step S200, the operating voltage is continuously applied to the gate 11, the drain 13 is grounded, and the second current-voltage characteristic curve is obtained according to the variation relationship between the second test voltage applied to the source 12 and the second test current under the action of the second test voltage.
As an example, the second test voltage may include a plurality of second sub-voltages that dynamically vary, and the second test current may include a plurality of second sub-currents that one-to-one correspond to the plurality of second sub-voltages.
In some embodiments, the first type well region 21 may be continued to be connected to the reference voltage while the drain 13 of the transistor under test is grounded. As an example, the first type well region 21 may be continued to be grounded.
It should be noted that, in the embodiment of the present application, the steps S100 and S200 are not limited in order, that is, any one of the steps is executed before or simultaneously is allowed.
For step S300, in some embodiments, the process of comparing the first current-voltage characteristic curve and the second current-voltage characteristic curve to obtain the difference degree may be specifically represented by the following steps S310 to S320.
In step S310, a first sampling point S1 and a second sampling point S2 are determined from the first current-voltage characteristic curve L1 and the second current-voltage characteristic curve L2, respectively; the first sub-voltage corresponding to the first sampling point s1 and the second sub-voltage corresponding to the second sampling point s2 have the same voltage value.
In step S320, the difference between the first sub-current corresponding to the first sampling point S1 and the second sub-current corresponding to the second sampling point S2 is taken as the degree of difference.
In some embodiments, the preset threshold may comprise an order of magnitude of current. That is, the degree of difference exceeding the preset threshold is: the degree of difference exceeds the current by an order of magnitude.
Illustratively, if the difference between the first sub-current corresponding to the first sampling point s1 and the second sub-current corresponding to the second sampling point s2 is greater than or equal to a multiple of 10, it is determined that the transistor under test is abnormal.
The voltage value of the first sub-voltage corresponding to the first sampling point is not particularly limited in the embodiment of the present application. In some embodiments, the voltage value of the first sub-voltage may be in a range of 0.8v to 1.5v; illustratively, the voltage value of the first sub-voltage may be 0.8V, 1V, 1.2V, 1.5V, or the like.
The voltage value of the second sub-voltage corresponding to the second sampling point is not limited in the embodiment of the present application. In some embodiments, the voltage value of the second sub-voltage may be in a range of 0.8v to 1.5v; illustratively, the voltage value of the second sub-voltage may be 0.8V, 1V, 1.2V, 1.5V, or the like.
As an example, the first sub-voltage and the second sub-voltage may have the same voltage value.
In some embodiments, the first sub-voltage and the second sub-voltage have the same voltage value and the same voltage value as the operating voltage.
In the following, the first current-voltage characteristic curve L1 and the second current-voltage characteristic curve L2 can be shown in fig. 5, taking the case where the operating voltage Vg applied to the transistor gate 11 to be measured is 1.2V as an example.
As understood in conjunction with fig. 5, the first sub-voltage corresponding to the first sampling point s1 and the second sub-voltage corresponding to the second sampling point s2 are both 1.2V; the first sub-current corresponding to the first sampling point s1 is 2.5X10-6 A, and the second sub-current corresponding to the second sampling point s2 is 2X 10-5 A; the difference is the difference between the first sub-current and the second sub-current, i.e. 1.75X10-5 A.
It will be appreciated that the degree of difference in the above examples is greater than an order of magnitude, i.e. exceeds a preset threshold. Therefore, the transistor to be tested can be judged to be abnormal.
In some embodiments, if the difference exceeds the preset threshold, and the first current-voltage characteristic curve L1 is located below the second current-voltage characteristic curve L2 as shown in fig. 5, it is determined that the source 12 of the transistor under test is abnormal.
As understood from fig. 3, according to the first test voltage applied to the drain electrode 13 of the transistor under test, the obtained first test current is low, and it can be determined that the conduction channel 21c of the transistor under test is open to a very weak degree under this condition. The smaller the voltage difference VG1,VG1 between the gate 11 and the position a1, the weaker the opening degree of the conductive channel 21c, and the higher the potential of the corresponding position a 1. It will be appreciated that the increase of the resistance at the source 12 increases the voltage division on the source 12, thereby pulling up the potential at the position a1, so that it can be determined that the source 12 of the transistor under test has a high resistance R, i.e. the source 12 of the transistor under test has an abnormality.
In addition, as understood in conjunction with fig. 4, a second test current is obtained according to a second test voltage applied to the source 12 of the transistor under test, and the opening degree of the conductive channel 21c is determined by the voltage difference VG2 between the gate 11 and the position a 2. For example, a standard transistor may be provided, as shown in fig. 6, an operating voltage is applied to the gate of the standard transistor, and the source is grounded, thereby obtaining a first standard current-voltage characteristic curve L1'; and continuously applying an operating voltage to the grid electrode of the standard transistor and grounding the drain electrode, thereby obtaining a second standard current-voltage characteristic curve L2'. It can be seen that the standard sub-voltage corresponding to the standard sampling point s2' is 1.2V, the corresponding standard sub-current is 2.5x-5 a, and there is no obvious difference between the standard sub-voltage and the second sub-current corresponding to the second sampling point s2, which indicates that the opening degree of the conducting channel 21c is normal at this time, and the potential of the position a2 is not pulled up, so that it can be determined that the drain electrode 13 of the transistor to be tested has no high resistance, that is, the drain electrode 13 of the transistor to be tested has no abnormality.
In other embodiments, if the difference exceeds the preset threshold and the second current-voltage characteristic curve L2 is below the first current-voltage characteristic curve L1, it is determined that the drain 13 of the transistor under test is abnormal.
In another aspect, the present application also provides a memory monitoring method according to some embodiments, which may be used to monitor a memory including a plurality of transistors. The structure of the transistor may be referred to in the foregoing description of the transistor to be tested in some embodiments. The memory may also include other necessary elements or components, which are not limited by the embodiments of the present application.
In some embodiments, the memory monitoring method may specifically include the following steps:
selecting a transistor to be tested from a plurality of transistors; the transistor under test is tested using the transistor test method described in some of the embodiments described above.
The memory monitoring method provided in the above embodiment includes a step of testing the transistor to be tested by using the transistor testing method, so that the technical effects achieved by the transistor testing method can be achieved, and the memory monitoring method can also be achieved, which will not be described in detail herein.
It will be appreciated that the transistors (including the transistor under test) involved in the various embodiments provided herein may be provided in a memory. The memory may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, or the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory.
By way of illustration, and not limitation, RAM can take many forms, such as static random access memory (Static Random Access Memory, SRAM for short) or dynamic random access memory (Dynamic Random Access Memory, DRAM for short), and the like.
Among them, SRAM is widely used in large-scale integrated circuits due to characteristics such as high writing/reading speed, low standby power consumption, and the like. The most widely used SRAM is the 6T Cell structure consisting of 6 transistors, which includes a symmetrical Cell structure consisting of two cross-coupled inverters, as shown in fig. 7. The 6 transistors are respectively: a left pass transistor PG_L, a right pass transistor PG_R, a left pull-up transistor PU_L, a right pull-up transistor PU_R, a left pull-down transistor PD_L, and a right pull-down transistor PD_R.
In the SRAM, any one of the six transistors has an electrical abnormality, and the writing or reading of the SRAM has a failure risk, thereby reducing the yield of the product.
It can be understood that the memory monitoring method provided by the embodiment of the application can be used for monitoring the SRAM, and any one transistor of six transistors in the SRAM can be tested by adopting the transistor testing method. That is, any one of the left pass transistor pg_l, the right pass transistor pg_r, the left pull-up transistor pu_l, the right pull-up transistor pu_r, the left pull-down transistor pd_l, and the right pull-down transistor pd_r may be tested using the aforementioned transistor test method.
The transistor testing method and the memory monitoring method provided by the application have the following unexpected beneficial effects:
In the embodiment of the application, working voltage is firstly applied to the grid electrode of the transistor to be tested, and the source electrode of the transistor to be tested is grounded, so that a first current-voltage characteristic curve can be obtained according to the change relation between the first test voltage applied to the drain electrode of the transistor to be tested and the first test current under the action of the first test voltage; and then, continuously applying working voltage to the grid electrode and grounding the drain electrode, so that a second current-voltage characteristic curve can be obtained according to the change relation between the second test voltage applied to the source electrode and the second test current under the action of the second test voltage. Obtaining the difference between the first current-voltage characteristic curve and the second current-voltage characteristic curve by comparing the two curves; when the difference exceeds a preset threshold, the drain electrode or the source electrode of the transistor to be tested is abnormal, and the transistor to be tested is judged to be abnormal. By adopting the embodiment of the application, whether the drain electrode is abnormal or the source electrode is abnormal can be found in time, so that whether the transistor to be tested has a defect or not can be comprehensively detected, the chip containing the defective transistor is prevented from flowing out, and the product yield is improved. The method has the advantages of simple steps, easy realization and high test efficiency, and can be conveniently applied to the chip production and manufacturing process.
In the description of the present specification, reference to the terms "some embodiments," "alternative embodiments," "other embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.