Disclosure of Invention
The invention mainly aims to provide a scanning driving circuit, a scanning driving method, a display panel and display equipment, and aims to solve the technical problem that high temperature picture difference caused by TFT electric leakage in the prior art affects display effect.
In order to achieve the above objective, the present invention provides a scan driving circuit, which includes a plurality of cascaded gate scan driving circuits, wherein the gate scan driving circuit includes an input module, a pull-down module, an output module and a pull-up control node, the input module, the output module and the pull-down module are respectively connected with the pull-up control node, the input module is connected with a first control signal, the output module is connected with a clock signal, and the pull-down module is connected with a first low level signal and a second low level signal;
The input module is used for pulling up the potential of the pull-up control node to a first potential according to the first control signal;
The pull-down module is used for adjusting off-state leakage current to a minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal when the potential of the pull-up control node is the first potential so as to maintain the first potential of the pull-up control node;
and the output module is used for outputting a scanning signal and a hierarchical signal according to the clock signal and the first control signal when the potential of the pull-up control node is the first potential.
Optionally, the gate scan driving circuit further includes an output pull-down module, a reverse control module, and a pull-down control node, where the pull-down module, the output pull-down module, and the reverse control module are all connected to the pull-down control node, the pull-down module and the reverse control module are all connected to the pull-up control node, the output pull-down module is connected to a second control signal, the reverse control module is connected to a power supply voltage, and the pull-down module is connected to the second control signal;
The pull-down module is further configured to pull down the potential of the pull-up control node to a second potential according to the second control signal;
The reverse control module is further configured to pull up the potential of the pull-down control node to a first potential and pull down the potential of the output end in the output module when the potential of the pull-up control node is a second potential;
the pull-down module is further used for maintaining a first potential of the pull-down control node;
the output pull-down module is used for pulling down the potential of the output end in the output module according to the second control signal when the potential of the pull-down control node is the first potential;
and the output module is also used for stopping outputting the scanning signal and the level transmission signal after the potential of the output end is pulled down.
Optionally, the pull-down module includes a first pull-down unit and a pull-down control unit, the first pull-down unit is connected to the second low-level signal, and the pull-down control unit is connected to the second control signal;
the first pull-down unit is used for adjusting the off-state leakage current to the minimum value according to the target off-state voltage;
the pull-down control unit is used for pulling down the potential of the pull-up control node to a second potential according to the second control signal.
Optionally, the first pull-down unit includes a first transistor, a second transistor and a third transistor, where the first transistor is connected in series with the second transistor, a first end of the first transistor is connected with a second end of the second transistor, control ends of the first transistor and the second transistor are both connected to the pull-down control node, the pull-up control node is connected with a first end of the second transistor and a control end of a third transistor, a second end of the first transistor is connected to the first low level signal, a first end of the third transistor is connected to the second low level signal, and a second end of the third transistor is connected to a second end of the second transistor;
the pull-down control unit comprises a fourth transistor, the control end of the fourth transistor is connected with the second control signal, the first end of the fourth transistor is connected with the pull-down control node, and the second end of the fourth transistor is connected with the first low-level signal.
Optionally, the pull-down module further includes a second pull-down unit, where the second pull-down unit includes a fifth transistor, a sixth transistor, and a seventh transistor, the fifth transistor is connected in series with the sixth transistor, a first end of the fifth transistor is connected to the second end of the sixth transistor, a second end of the fifth transistor is connected to the second end of the first transistor, a control end of the sixth transistor is connected to the second end of the fourth transistor, a control end of the seventh transistor, and a control end of the fifth transistor, a first end of the seventh transistor is connected to the second end of the sixth transistor, and a second end of the seventh transistor is connected to the second low-level signal.
Optionally, the input module includes an eighth transistor and a ninth transistor, a control end and a first end of the eighth transistor are respectively connected to the first control signal, a second end of the eighth transistor is connected to the first end of the ninth transistor, and a control end of the ninth transistor is connected to the second control signal.
Optionally, the output module includes tenth transistor, eleventh transistor and electric capacity, the output includes first output and second output, first output pass signal, the second output outputs scanning signal, the control end of tenth transistor with pull-up control node is connected, the second end of tenth transistor with first output is connected, the first end of tenth transistor inserts clock signal, the control end of eleventh transistor respectively with pull-up control node with the first end of electric capacity is connected, the second end of eleventh transistor respectively with the second end of electric capacity with the second output is connected, the first end of eleventh transistor inserts clock signal.
In order to achieve the above object, the present invention further provides a scan driving method, including:
pulling up the potential of the pull-up control node to a first potential according to the first control signal;
When the potential of the pull-up control node is the first potential, the off-state leakage current is adjusted to the minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal so as to maintain the first potential of the pull-up control node;
When the potential of the pull-up control node is the first potential, a scanning signal and a level transmission signal are output according to a clock signal and the first control signal.
In order to achieve the above object, the present invention further provides a display panel, which includes a display area and a non-display area, wherein the non-display area is provided with the scan driving circuit as described above, and the scan driving circuit is configured to provide a line scan signal for the display area.
In order to achieve the above objective, the present invention further provides a display device, which includes a backlight module and the display panel described above, wherein the backlight module is disposed corresponding to the display panel, and the backlight module is configured to provide a backlight source for the display panel.
The invention discloses a scanning driving circuit, which comprises a plurality of cascaded grid scanning driving circuits, wherein each grid scanning driving circuit comprises an input module, a pull-down module, an output module and a pull-up control node, the input module, the output module and the pull-down module are respectively connected with the pull-up control nodes, the input module is connected with a first control signal, the output module is connected with a clock signal, the pull-down module is connected with a first low-level signal and a second low-level signal, the input module is used for pulling up the potential of the pull-up control node to the first potential according to the first control signal, the pull-down module is used for adjusting the off-state leakage current to the minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal when the potential of the pull-up control node is the first potential, and outputting a scanning signal and a level transmission signal according to the clock signal and the first control signal when the potential of the pull-up control node is the first potential. Compared with the high-temperature picture difference caused by larger TFT leakage in the traditional GDL circuit, the invention can maintain the high potential of the Q point by controlling the off-state leakage current to be at the minimum value in the high potential stage of the Q point by adjusting the off-state voltage of the TFT in the pull-down module, thereby avoiding the occurrence of the high-temperature picture difference and improving the display effect.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear are used in the embodiments of the present invention) are merely for explaining the relative positional relationship, movement conditions, and the like between the components in a certain specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicators are changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Example 1
Referring to fig. 1, fig. 1 is a schematic diagram of a first embodiment of a scan driving circuit according to the present invention. The present invention proposes a first embodiment of a scan driving circuit.
In this embodiment, the scan driving circuit includes a plurality of cascaded gate scan driving circuits, where the gate scan driving circuit includes an input module 10, a pull-down module 20, an output module 30, and a pull-up control node Q (n), the input module 10, the output module 30, and the pull-down module 20 are all connected to the pull-up control node Q (n), the input module 10 is connected to the first control signal Carry (n-1), the output module is connected to the clock signal CLK (n), and the pull-down module 10 is connected to the first low level signal VGL1 and the second low level signal VGL2.
It should be noted that, the gate scan driving circuit, that is, the GDL circuit, where the scan driving circuit includes a plurality of cascaded gate scan driving circuits, it may be considered that N GDL circuits are cascaded (N > 1), each of which has the same structure, each of the GDL circuits may receive a clock signal in a step shape in a rising stage, and output a scan signal according to the clock signal, so as to drive pixels in a corresponding row in the display area, and phases of the clock signals received by any two adjacent GDL circuits may be different so as to output two scan signals at intervals for a period of time, so that progressive scanning of the pixels may be implemented. In this embodiment, an N-th stage GDL circuit is described as an example (1. Ltoreq.n. Ltoreq.N).
It will be understood that the pull-up control node Q (n), i.e. the Q point in the n-th stage GDL circuit, the clock signal CLK (n), i.e. the clock signal received by the n-th stage GDL circuit, may be set according to practical requirements, and the first control signal Carry (n-1) may be a level transmission signal of the previous stage GDL circuit (n-1-th stage GDL circuit) or may be a start signal, which is not limited in this embodiment. The first low level signal VGL1 and the second low level signal VGL2 are signals output by the low level terminal, wherein the second low level signal VGL2 outputs a dc low voltage, which can be dynamically adjusted according to the requirement.
It should be understood that the input module 10 is configured to pull up the potential of the pull-up control node Q (n) to a first potential according to the first control signal Carry (n-1), the pull-down module 20 is configured to adjust the off-state leakage current to a minimum value according to the target off-state voltages provided by the first low level signal VGL1 and the second low level signal VGL2 when the potential of the pull-up control node Q (n) is the first potential, so as to maintain the first potential of the pull-up control node Q (n), and the output module 30 is configured to output the scan signal Gout (n) and the level signal Carry (n) according to the clock signal CLK (n) and the first control signal Carry (n-1) when the potential of the pull-up control node Q (n) is the first potential.
In the present embodiment, the first potential is a high potential, and the second potential is a low potential. The target off-state voltage refers to a voltage corresponding to the minimum value of the off-state leakage current, the off-state voltage is usually VGL1-VGL2, and the second low-level signal VGL2 can be adjusted to achieve the corresponding target off-state voltage, so that the off-state leakage current is minimum, and the high potential of Q (n) can be maintained at the moment.
It will be appreciated that the scan signal Gout (n) is output separately from the stage signal Carry (n), typically using two different output terminals, the output scan signal Gout (n) may be used to drive the n-th row of pixels of the display region, and the output stage signal Carry (n) may be used for the activation of the next stage GDL circuit (n+1 stage GDL circuit).
It should be appreciated that the input module 10 may also have access to a Reset signal Reset, at which time the potential of the pull-up control node Q (n) may be pulled down in accordance with the Reset signal Reset.
In this embodiment, the scan driving circuit includes a plurality of cascaded gate scan driving circuits, the gate scan driving circuit includes an input module 10, a pull-down module 20, an output module 30 and a pull-up control node Q (n), the input module 10, the output module 30 and the pull-down module 20 are respectively connected to the pull-up control node Q (n), the input module 10 is connected to a first control signal Carry (n-1), the output module 30 is connected to a clock signal CLK (n), the pull-down module is connected to a first low level signal VGL1 and a second low level signal VGL2, the input module 10 is used for pulling up the potential of the pull-up control node Q (n) to a first potential according to the first control signal Carry (n-1), the pull-down module 20 is used for adjusting the off leakage current to a minimum value according to a target off-state voltage provided by the first low level signal l1 and the second low level signal VGL2 when the potential of the pull-up control node Q (n) is the first potential, and the pull-down module 20 is used for maintaining the first potential of the pull-up control node Q (n) when the first control signal VGL1 and the pull-up control node (n) are the first potential (n) and the first signal vgry) signal (n) is the potential according to the first signal Carry (n). Compared with the high-temperature picture difference caused by the larger TFT leakage in the traditional GDL circuit, the embodiment controls the off-state leakage current to be at the minimum value in the high-potential stage of the Q point by adjusting the off-state voltage in the pull-down module 20, so that the high-potential of the Q point can be maintained, the high-temperature picture difference is avoided, and the display effect is improved.
Example two
Referring to fig. 2, fig. 2 is a schematic diagram of a scan driving circuit according to a second embodiment of the present invention. Based on the first embodiment described above, the present invention proposes a second embodiment of the scan driving circuit.
In this embodiment, the gate scan driving circuit further includes an output pull-down module 40, a reverse control module 50, and a pull-down control node QB (n), where the pull-down module 20, the output pull-down module 40, and the reverse control module 50 are all connected to the pull-down control node QB (n), the pull-down module 20 and the reverse control module 50 are all connected to the pull-up control node Q (n), the output pull-down module 40 is connected to the second control signal Carry (n+1), the reverse control module 50 is connected to the power supply voltage VDD, and the pull-down module 20 is connected to the second control signal Carry (n+1).
Note that, the pull-down control node QB (n), i.e., the QB point in the n-th stage GDL circuit, is generally connected to the pull-down module 20 and the output pull-down module. The second control signal Carry (n+1) may be a transfer signal output by the GDL circuit of the next stage, which is not limited in this embodiment.
It will be appreciated that the pull-down module 20 is further configured to pull down the potential of the pull-up control node Q (n) to the second potential according to the second control signal Carry (n+1), the reverse control module 50 is further configured to pull up the potential of the pull-down control node QB (n) to the first potential and pull down the potential of the output terminal of the output module 30 when the potential of the pull-up control node Q (n) is the second potential, the pull-down module 20 is further configured to maintain the first potential of the pull-down control node QB (n), and the output pull-down module 40 is configured to pull down the potential of the output terminal of the output module 30 according to the second control signal Carry (n+1) when the potential of the pull-down control node QB (n) is the first potential, and the output module 30 is further configured to stop outputting the scan signal Gout (n) and the stage signal Carry (n) after the potential of the output terminal is pulled down.
It should be understood that after the output of the current stage (the scan signal output of the current stage and the stage signal output of the current stage) is completed, the pull-down module 20 pulls down the potential of the pull-up control node Q (n) to a low potential, and the reverse control module 50 pulls up the potential of the pull-down control node QB (n) to a high potential, and is capable of pulling down the potential of the output terminal of the output module 30, and the output pull-down module 40 pulls down the potential of the output terminal of the output module 30, and during this process, the pull-down module 20 maintains the high potential of the pull-down control node QB (n). The level of the n-th stage GDL circuit's stage signal Carry (n) drops rapidly by pulling down the potential of the output terminal in the output module 30 through the reverse control module 50 and the output pull-down module 40, thereby stopping the output of the n-th stage signal Carry (n) and the n-th stage scan signal Gout (n) in time.
It should be noted that, the output terminals of the pull-down level enabling potential of the reverse control module 50 and the output pull-down module 40 are different, the reverse control module 50 may be an output terminal corresponding to the pull-down level signaling Carry (n), and the output terminal corresponding to the pull-down level signaling Carry (n) and the output terminal corresponding to the scan signal Gout (n) may be an output terminal corresponding to the output pull-down module 40. The output pull-down module 40 is usually connected to a third low level signal VGL3, where the third low level signal VGL3 is a signal output by the low level terminal and can be dynamically adjusted according to the requirement.
It will be appreciated that, since both the inverse control module 50 and the output pull-down module 40 can pull down the potential of the output terminal in the output module 30, the potentials of the stage signal Carry (n) and the scan signal Gout (n) can be pulled down faster, the potential of the pull-up control node Q (n) of the GDL circuit can rise faster due to the capacitive coupling effect, the impedance of the output module 30 of the GDL circuit can fall faster, the scan signal Gout (n) output by the GDL circuit output module 30 can rise to the corresponding high potential faster when the clock signal CLK (n) is converted from the low potential to the high potential, the rising time of the scan signal output by the GDL circuit can be shortened, and the stability of the GDL circuit can be improved.
In this embodiment, the gate scan driving circuit further includes an output pull-down module 40, a reverse control module 50, and a pull-down control node QB (n), where the pull-down module 20, the output pull-down module 40, and the reverse control module 50 are respectively connected to the pull-down control node QB (n), the pull-down module 20 and the reverse control module 50 are respectively connected to the pull-up control node Q (n), the output pull-down module 40 is connected to the second control signal Carry (n+1), the reverse control module 50 is connected to the power supply voltage VDD, the pull-down module 20 is connected to the second control signal Carry (n+1), the pull-down module 20 is further configured to pull down the potential of the pull-up control node Q (n) to the second potential according to the second control signal Carry (n+1), and the reverse control module 50 is further configured to pull up the potential of the pull-down control node QB (n) to the first potential when the potential of the pull-up control node Q (n) is the second potential, and the pull-down module 20 is further configured to maintain the potential of the output terminal in the pull-down output module 30, and the pull-down control node QB (n) is further configured to maintain the first potential when the pull-down control node QB (n) is the first potential and the pull-down signal (n) is stopped according to the second potential, and the first potential signal Carry (n+1). In this embodiment, by adjusting the off-state voltage in the pull-down module 20, the off-state leakage current is controlled to be at the minimum value in the high-potential stage of the Q point, so that the high potential of the Q point can be maintained, the occurrence of high-temperature different drawing is avoided, and the display effect is improved.
Example III
Referring to fig. 3, fig. 3 is a schematic structural diagram of a third embodiment of a scan driving circuit according to the present invention. Based on the above embodiments, the present invention proposes a third example of the scan driving circuit.
In this embodiment, the pull-down module 20 includes a first pull-down unit 201 and a pull-down control unit 202, the first pull-down unit 201 is connected to the second low level signal VGL2, and the pull-down control unit 202 is connected to the second control signal Carry (n+1).
Further, the pull-down module 20 further includes a second pull-down unit 203, the second pull-down unit 203 is connected to the first pull-down unit 201 and the pull-down control unit 202, and the second pull-down unit 203 is connected to the second low level signal VGL2.
The first pull-down unit 201 is configured to adjust the off-state leakage current to a minimum value according to the target off-state voltage, and the pull-down control unit 202 is configured to pull down the potential of the pull-up control node Q (n) to a second potential according to the second control signal Carry (n+1).
It can be appreciated that the pull-down module 20 is formed by three parts of the first pull-down unit 201, the pull-down control unit 202 and the second pull-down unit 203, where the first pull-down unit 201 is generally connected to the pull-up control node Q (n) and the pull-down control node QB (n), and it can be considered that the first pull-down unit 201 needs to adjust the off-state leakage current to a minimum value, and the off-state voltage of the first pull-down unit 201 is adjusted to the target off-state voltage by adjusting the target off-state voltage to which the first pull-down unit is connected, so that the off-state leakage current of the first pull-down unit 201 is minimized.
It should be understood that the pull-down control unit 202 may pull down the potential of the pull-up control node Q (n) to a low potential according to the received second control signal Carry (n+1).
In this embodiment, the pull-down module 20 includes a first pull-down unit 201 and a pull-down control unit 202, where the first pull-down unit 201 is connected to a second low level signal VGL2, the pull-down control unit 202 is connected to a second control signal Carry (n+1), the first pull-down unit 201 is configured to adjust the off-state leakage current to a minimum value according to the target off-state voltage, and the pull-down control unit 202 is configured to pull down the potential of the pull-up control node Q (n) to a second potential according to the second control signal Carry (n+1). In this embodiment, by adjusting the off-state voltage in the pull-down module 20, the off-state leakage current is controlled to be at the minimum value in the high-potential stage of the Q point, so that the high potential of the Q point can be maintained, the occurrence of high-temperature different drawing is avoided, and the display effect is improved.
Example IV
Referring to fig. 4, fig. 4 is a schematic structural diagram of a fourth embodiment of a scan driving circuit according to the present invention. Based on the above embodiments, the present invention proposes a fifth embodiment of the scan driving circuit.
In this embodiment, the first pull-down unit 201 includes a first transistor T1, a second transistor T2, and a third transistor T3, the first transistor T1 is connected in series with the second transistor T2, a first end of the first transistor T1 is connected to a second end of the second transistor T2, control ends of the first transistor T1 and the second transistor T2 are both connected to a pull-down control node QB (n), a pull-up control node Q (n) is connected to a first end of the second transistor T2 and a control end of the third transistor T3, respectively, a second end of the first transistor T1 is connected to the first low level signal VGL1, a first end of the third transistor T3 is connected to the second low level signal VGL2, and a second end of the third transistor T3 is connected to a second end of the second transistor T2.
It should be noted that the target off-state voltage is the target off-state voltage of the second transistor T2, and the off-state leakage current is adjusted to a minimum value, i.e., the off-state leakage current of the second transistor T2 is adjusted to a minimum value. When the potential of the pull-up control node Q (n) is high and the potential of the pull-down control node QB (n) is low, the second transistor T2 is turned off, the third transistor is turned on, and when the potential of the pull-up control node Q (n) is low and the potential of the pull-down control node QB (n) is high, the second transistor T2 is turned on. The target off-state voltage may be determined from transistor characteristic data, where the transistor characteristic data refers to a characteristic curve of the transistor, such as an IV characteristic curve.
Further, the pull-down control unit 202 includes a fourth transistor T4, a control terminal of the fourth transistor T4 is connected to the second control signal Carry (n+1), a first terminal of the fourth transistor T4 is connected to the pull-down control node QB (n), and a second terminal of the fourth transistor T4 is connected to the first low level signal VGL1.
Further, the second pull-down unit 203 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, the fifth transistor T5 is connected in series with the sixth transistor T6, a first end of the fifth transistor T5 is connected to a second end of the sixth transistor T6, a second end of the fifth transistor T5 is connected to a second end of the first transistor T1, a control end of the sixth transistor T6 is connected to a second end of the fourth transistor T4, a control end of the seventh transistor T7, and a control end of the fifth transistor T5, a first end of the seventh transistor T7 is connected to a second end of the sixth transistor T6, and a second end of the seventh transistor T7 is connected to the second low level signal VGL2.
It can be understood that, as shown in fig. 5, in the conventional GDL circuit, the Q point is in the high potential period, the T1 'is turned on, the QB point potential is always in the low point (VGL 2), the gate voltage of T2' & T3 'is the low voltage VGL1, the gate voltage of T2' & T3 'is turned off, at this time, the gate voltage Vg is equal to VGL1, the source voltage Vs is also VGL1, the drain Vd point is the high point, for T2' or T3', vgs (gate source voltage difference) is equal to 0V, as shown in fig. 6, the vgs=0v leakage current is higher, the non-leakage current minimum point, and the off-state leakage of T2' causes the Q point high potential to be not maintained, especially, the leakage current is raised due to high temperature, and high temperature is easy to draw a difference. Referring to fig. 4, the pull-down module is optimized based on the conventional GDL circuit, when the Q point is high, the T3 is turned on, the drain voltage of the T3 is VGL2, the QB potential is low, the T2 is turned off, the gate voltage of the T2 vg=vgl2, the source voltage of the T2 vs=vgl3, and the off-state voltage vgs=vgl2-vgl3 not equal to 0 in the turned-off state of the optimized circuit T2, at this time, the VGL2 dc voltage can be dynamically adjusted to make the off-state voltage Vgs of the T2 at the voltage with the minimum leakage current, so that the Q point high potential is not pulled down due to the leakage current, and the off-state leakage current can be adjusted according to the IV characteristic curve at any time, so that the off-state leakage current is kept minimum in the Q point high potential stage, thereby avoiding high temperature variation.
Further, as shown in fig. 7, the input module 10 includes an eighth transistor T8 and a ninth transistor T9, the control terminal and the first terminal of the eighth transistor T8 are respectively connected to the first control signal Carry (n-1), the second terminal of the eighth transistor T8 is connected to the first terminal of the ninth transistor T9, and the control terminal of the ninth transistor T9 is connected to the second control signal Carry (n+1). The output module 30 includes a tenth transistor T10, an eleventh transistor T11, and a capacitor C, where the output end includes a first output end and a second output end, the first output end outputs the stage signal Carry (N), the second output end outputs the scan signal Gout (N), the control end of the tenth transistor T10 is connected to the pull-up control node Q (N), the second end of the tenth transistor T10 is connected to the first output end, the first end of the tenth transistor T10 is connected to the clock signal CLK (N), the control end of the eleventh transistor T11 is connected to the pull-up control node Q (N) and the first end of the capacitor C, the second end of the eleventh transistor T11 is connected to the second end of the capacitor C and the second output end, and the first end of the eleventh transistor T11 is connected to the clock signal CLK (N).
It should be appreciated that if the pull-up control node Q (n) is low, the pull-down control node QB (n) is high, T2 is on, the pull-up control node Q (n) is pulled low to VGL2, at which time T11 is off, and the stage output is over.
It will be appreciated that in this embodiment, the first terminal of the transistor is the source terminal, the second terminal of the transistor is the drain terminal, and the control terminal of the transistor is the gate terminal.
It should be noted that, in this embodiment, the voltage output by the second low level signal VGL2 may be adjusted according to the display state, so that the low potential of the pull-up control node Q (n) is adjusted.
Further, as shown in fig. 8, the output pull-down module 40 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16, the gate terminal of the twelfth transistor T12 is connected to the second control signal Carry (n+1), the drain terminal of the thirteenth transistor T13 is connected to the drain terminal of the twelfth transistor T12 and the drain terminal of the fourteenth transistor T14, the gate terminal of the thirteenth transistor T13 is connected to the pull-down control node QB (n), the source terminal of the thirteenth transistor T13 is connected to the source terminal and the first output terminal of the fourteenth transistor T14, the gate terminal of the thirteenth transistor T13 is connected to the gate terminal of the fifteenth transistor T15, the source terminal of the fifteenth transistor T15 is connected to the source terminal and the second output terminal of the sixteenth transistor T16, the drain terminal of the fifteenth transistor T15 is connected to the drain terminal of the sixteenth transistor T16, and the drain terminal of the fifteenth transistor T15 is connected to the third low level VGL3.
Further, referring to fig. 8, the reverse control module includes a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twenty-fourth transistor T24, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, and a twenty-fourth transistor T24, the source terminal of the seventeenth transistor T17 is connected to the power supply voltage, the seventeenth transistor T17 is connected to the gate terminal of the eighteenth transistor T18 and the source terminal of the nineteenth transistor T19, the source terminal of the eighteenth transistor T18 is connected to the source terminal of the seventeenth transistor T17, the gate terminal of the nineteenth transistor T19, the gate terminal of the twenty-first transistor T20, the gate terminal of the twenty-first transistor T21, and the gate terminal of the twenty-fourth transistor T22 are connected to the pull-up control node Q (n), the drain terminal of the eighteenth transistor T19 is connected to the drain terminal of the twenty-fourth transistor T20, the source terminal of the eighteenth transistor T18 is connected to the gate terminal of the eighteenth transistor T18 and the source terminal of the nineteenth transistor T18, the drain terminal of the twenty-fourth transistor T23 is connected to the drain terminal of the twenty-fourth transistor T24, and the drain terminal of the twenty-fourth transistor T24 is connected to the drain terminal of the twenty-fourth transistor T23.
It is understood that the transistors T1 to T24 in the present embodiment may be TFTs, which are not limited in this embodiment.
In this embodiment, the first pull-down unit 201 includes a first transistor T1, a second transistor T2, and a third transistor T3, the first transistor T1 is connected in series with the second transistor T2, a first end of the first transistor T1 is connected to a second end of the second transistor T2, control ends of the first transistor T1 and the second transistor T2 are both connected to a pull-down control node QB (n), a pull-up control node Q (n) is connected to a first end of the second transistor T2 and a control end of the third transistor T3, respectively, a second end of the first transistor T1 is connected to the first low level signal VGL1, a first end of the third transistor T3 is connected to the second low level signal VGL2, and a second end of the third transistor T3 is connected to a second end of the second transistor T2. In this embodiment, by adjusting the off-state voltage in the pull-down module 20, the off-state leakage current is controlled to be at the minimum value in the high-potential stage of the Q point, so that the high potential of the Q point can be maintained, the occurrence of high-temperature different drawing is avoided, and the display effect is improved.
Example five
Referring to fig. 9, fig. 9 is a flowchart of a fifth embodiment of a scan driving method according to the present invention. Based on the above embodiments, the present invention proposes a fifth example of the scan driving method.
In this embodiment, the scan driving method includes the steps of:
Step S10, according to the first control signal, the potential of the pull-up control node is pulled up to a first potential.
It should be noted that, the execution body of the embodiment is a scan driving circuit, the scan driving circuit includes a plurality of cascaded gate scan driving circuits, each gate scan driving circuit includes an input module, a pull-down module, an output module and a pull-up control node, and the specific structure can refer to fig. 1 to 8.
It will be understood that the Q point in the pull-up control node, i.e. the gate scan driving circuit (GDL circuit), the first control signal is usually a signal for controlling the potential pull-up of the Q point, and may be a level-pass signal output by the GDL circuit of the previous stage or a start signal, which is not limited in this embodiment.
It should be understood that, in this embodiment, the first potential is a high potential, the second potential is a low potential, and the potential of the Q point is pulled up to the high potential according to the received first control signal.
And step S20, when the potential of the pull-up control node is the first potential, the off-state leakage current is adjusted to the minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal so as to maintain the first potential of the pull-up control node.
It should be noted that the target off-state voltage refers to a voltage corresponding to the minimum value of the off-state leakage current, the first low-level signal and the second low-level signal are signals output by the low-level end, wherein the second low-level signal outputs a direct-current low voltage, and the direct-current low voltage can be dynamically adjusted according to requirements, so that the off-state voltage reaches the target off-state voltage, and the off-state leakage current is adjusted to the minimum value, and at the moment, the high potential of the Q point can be maintained.
And step S30, outputting a scanning signal and a level transmission signal according to a clock signal and the first control signal when the potential of the pull-up control node is the first potential.
It should be understood that the clock signal is a clock signal that is received in a step-like manner during the rising phase, and the phases of the clock signals received by any two adjacent GDL circuits may be different to output two scan signals separated by a period of time, so that progressive scanning of pixels may be achieved. The output scanning signals are used for driving the pixels of the corresponding row of the display area, and the output hierarchical transmission signals can be used for starting the GDL circuit of the next stage.
Further, the scan driving method further includes pulling down the potential of the pull-up control node to a second potential according to the second control signal, pulling up the potential of the pull-down control node to a first potential when the potential of the pull-up control node is the second potential, pulling down the potential of the output end, maintaining the first potential of the pull-down control node, pulling down the potential of the output end in the output module according to the second control signal when the potential of the pull-down control node is the first potential, and stopping outputting the scan signal and the cascade signal after the potential of the output end is pulled down.
Note that, the pull-down control node, that is, the QB point in the GDL circuit, the second control signal may be a level-pass signal output by the GDL circuit at the next stage, which is not limited in this embodiment.
It will be appreciated that after the output of the current stage (the scan signal output of the current stage and the stage signal output of the current stage) is completed, the potential at the Q point is pulled down to a low potential, the potential at the QB point is pulled up to a high potential, and the potential at the output terminal is pulled down, during which the high potential at the QB point is maintained. The level of the gradation signal of the GDL circuit can be rapidly reduced, thereby stopping outputting the gradation signal and the scan signal in time.
In this embodiment, the potential of the pull-up control node is pulled up to the first potential according to the first control signal, when the potential of the pull-up control node is the first potential, the off-state leakage current is adjusted to the minimum value according to the target off-state voltages provided by the first low-level signal and the second low-level signal, so as to maintain the first potential of the pull-up control node, and when the potential of the pull-up control node is the first potential, the scan signal and the gradation signal are output according to the clock signal and the first control signal. Compared with the high-temperature picture difference caused by larger TFT leakage in the traditional GDL circuit, the embodiment controls the off-state leakage current to be at the minimum value in the high-potential stage of the Q point by adjusting the off-state voltage, so that the high potential of the Q point can be maintained, the high-temperature picture difference is avoided, and the display effect is improved.
In order to achieve the above object, the present invention further provides a display panel, which includes a display area and a non-display area, wherein the non-display area is provided with the scan driving circuit as described above, and the scan driving circuit is used for providing a line scan signal for the display area. The specific structure of the scan driving circuit refers to the above embodiments, and since the technical solutions of all the embodiments can be adopted in the display panel, the scan driving circuit at least has the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein.
Referring to fig. 10, fig. 10 is a schematic structural diagram of an embodiment of a display device according to the present invention. In order to achieve the above objective, the present invention further provides a display device, which includes a backlight module 60 and a display panel 70 as described above, wherein the backlight module 60 is disposed corresponding to the display panel 70, and the backlight module 60 is configured to provide a backlight source for the display panel 70. The specific structure of the display panel 70 refers to the above embodiments, and since the present display device can adopt the technical solutions of all the embodiments, the present display device has at least the beneficial effects brought by the technical solutions of the embodiments, which are not described in detail herein.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.