Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a wake-up circuit, an SOC system and a wake-up method thereof, which are used for solving the problem that in the prior art, a sleep mode of an SOC circuit needs a separate pin for external wake-up, resulting in occupying a circuit pin.
To achieve the above and other related objects, the present invention provides a wake-up circuit applied to an SOC system, including:
the asynchronous module executes a setting task based on an external clock and generates an end mark as a wake-up signal when the setting task is completed;
the mode selection module is connected with the output end of the asynchronous module, starts system mode identification based on the wake-up signal, generates a high-frequency enabling signal when the SOC system is in an idle mode, and generates a low-frequency enabling signal when the SOC system is in a sleep mode;
the low-frequency source clock generation module is connected with the output end of the mode selection module, and is awakened based on the low-frequency enabling signal and generates a low-frequency source clock;
the low-frequency source clock stabilizing module is connected with the output end of the low-frequency source clock generating module, and after the low-frequency source clock generating module is awakened, the low-frequency source clock is stabilized through a first set time and a low-frequency stabilizing signal is generated;
the high-frequency source clock generation module is connected with the output ends of the mode selection module and the low-frequency source clock stabilization module, and is awakened and generates a high-frequency source clock based on the high-frequency enabling signal or the low-frequency stabilization signal;
the high-frequency source clock stabilizing module is connected with the output end of the high-frequency source clock generating module, and after the high-frequency source clock generating module is awakened, the high-frequency source clock is stabilized through a second set time and a high-frequency stabilizing signal is generated.
Optionally, the asynchronous module includes an asynchronous communication module, wherein the end flag includes an address matching completion flag bit or a data transmission termination bit.
Optionally, the mode selection module performs system mode identification based on the CPU status register and data stored in the mode status register.
Optionally, the low-frequency source clock generating module is implemented by a low-frequency oscillator, and the low-frequency source clock stabilizing module is implemented by at least one counter; the high-frequency source clock generation module is realized by a high-frequency oscillator, and the high-frequency source clock stabilization module is realized by at least one counter.
Optionally, the wake-up circuit further comprises: the clock frequency division and control module is connected with the output ends of the low-frequency source clock generation module and the high-frequency source clock generation module, performs frequency division processing on the low-frequency source clock and the high-frequency source clock to generate a plurality of working clocks, and performs output control on the working clocks based on the low-frequency stable signal and the high-frequency stable signal.
The present invention also provides an SOC system including: a wake-up circuit as claimed in any preceding claim.
The invention also provides a wake-up method of the SOC system, which comprises the following steps:
the asynchronous module executes a setting task based on an external clock, and generates an end mark as a wake-up signal when the setting task is completed;
the mode selection module starts system mode recognition based on the wake-up signal;
if the SOC system is in a sleep mode, the mode selection module generates a low-frequency enabling signal to enable the low-frequency source clock generation module to be awakened and generate a low-frequency source clock, the low-frequency source clock stabilization module stabilizes the low-frequency source clock and generates a low-frequency stabilization signal after a first set time, the high-frequency source clock generation module is awakened and generates a high-frequency source clock based on the low-frequency stabilization signal, and the high-frequency source clock stabilization module stabilizes the high-frequency source clock and generates a high-frequency stabilization signal after a second set time;
if the SOC system is in an idle mode, the mode selection module generates a high-frequency enabling signal to enable the high-frequency source clock generation module to be awakened and generate a high-frequency source clock, and the high-frequency source clock stabilization module stabilizes the high-frequency source clock and generates a high-frequency stabilization signal after a second set time;
if the SOC system is in the working mode, the mode selection module generates an invalid output.
Optionally, the asynchronous module includes an asynchronous communication module, wherein the method for generating the wake-up signal includes: and the asynchronous communication module generates an address matching completion flag bit as the wake-up signal when the address matching is completed, or generates a data transmission termination bit as the wake-up signal when the data transmission is completed.
Optionally, the method for performing system pattern recognition includes: the mode selection module judges that the SOC system is in an operating state or a non-operating state based on the data stored in the CPU state register, and judges that the SOC system is in an idle mode or a sleep mode based on the data stored in the mode state register when judging that the SOC system is in the non-operating state.
Optionally, the method for generating the low frequency stabilization signal comprises: the low-frequency source clock stabilizing module starts counting when the low-frequency source clock generating module is awakened, and generates the low-frequency stabilizing signal when the count value reaches a first set value;
the method for generating the high-frequency stable signal comprises the following steps: the high-frequency source clock stabilizing module starts counting when the high-frequency source clock generating module is awakened, and generates the high-frequency stabilizing signal when the count value reaches a second set value.
Optionally, the wake-up method further includes: the clock frequency division and control module performs frequency division processing on the low-frequency source clock to generate at least one low-frequency working clock, and generates a low-frequency gating signal based on the low-frequency stabilizing signal to perform output control on the low-frequency working clock; and frequency division processing is carried out on the high-frequency source clock to generate at least one high-frequency working clock, and a high-frequency gating signal is generated based on the high-frequency stabilizing signal to carry out output control on the high-frequency working clock.
As described above, the wake-up circuit, the SOC system and the wake-up method thereof, provided by the invention, utilize the asynchronous module to generate the wake-up signal, so that not only can the idle mode of the SOC system be woken up, but also the sleep mode of the SOC system can be woken up; because the asynchronous module does not need extra packaging pins, the problem that no redundant packaging pins realize external awakening when the circuit packaging pins are limited is avoided; in addition, the asynchronous module does not need high-frequency source clocks and low-frequency source clocks of the SOC system to participate in the operation, so that the SOC system can close the high-frequency source clocks and the low-frequency source clocks after corresponding tasks are completed and enter a sleep mode, and the power consumption of the system is reduced.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a wake-up circuit 100, which can be applied to an SOC system; the wake-up circuit 100 includes: an asynchronous module 101, a mode selection module 102, a low frequency source clock generation module 103, a low frequency source clock stabilization module 104, a high frequency source clock generation module 105, and a high frequency source clock stabilization module 106; further, the wake-up circuit 100 further includes: clock divide and control module 107.
The asynchronous module 101 performs a setting task based on an external clock and generates an end flag as a wakeup signal WK when the setting task is completed.
Because the asynchronous module 101 does not need a low-frequency source clock, a high-frequency source clock and derivative clocks thereof when working, the asynchronous module can normally work in an idle mode or a sleep mode and generate an end mark when finishing a set task; the present embodiment utilizes the above-described characteristics of the asynchronous module 101 to multiplex it as a wake-up signal generating circuit, thereby realizing wake-up in the idle mode or sleep mode. It should be noted that, the asynchronous module 101 is an original module in the SOC system, and therefore, the wake-up scheme of this embodiment does not occupy additional package pins.
By way of example, the asynchronous module 101 includes an asynchronous communication module, such as an asynchronous I2C module or an asynchronous UART module; the end mark comprises an address matching completion mark bit or a data transmission termination bit. Of course, the asynchronous module 101 may be other asynchronous functional modules besides the asynchronous communication module, which has no substantial effect on the present embodiment.
The mode selection module 102 is connected to the output terminal of the asynchronous module 101, starts system mode identification based on the wake-up signal WK, generates a high-frequency enable signal en_hf when the SOC system is in the idle mode, and generates a low-frequency enable signal en_lf when the SOC system is in the sleep mode. Further, the mode selection module 102 also generates an disable enable signal, such as no output, when the SOC system is in an operational mode.
As an example, the mode selection module 102 performs system mode identification based on the CPU status register and data stored in the mode status register; the method comprises the following steps: the mode selection module 102 determines whether the CPU is operating based on the data stored in the CPU status register, thereby determining whether the SOC system is in an operating state or an inactive state, and determines whether the SOC system is in an idle mode or a sleep mode based on the data stored in the mode status register when determining that the SOC system is in the inactive state.
If the mode selection module 102 wakes up and reads the data stored in the CPU status register based on the wake-up signal WK, if the data stored in the CPU status register is "START", indicating that the CPU is operating, the mode selection module 102 determines that the SOC system is in an operating state and generates an invalid enable signal;
if the data stored in the CPU status register is STOP, indicating that the CPU has stopped working, the mode selection module 102 determines that the SOC system is in a non-working state, and at this time, the mode selection module 102 reads the data stored in the mode status register;
if the data stored in the mode status register is "0", the mode selection module 102 determines that the SOC system is in the idle mode and generates the high frequency enable signal en_hf;
if the data stored in the mode status register is "1", the mode selection module 102 determines that the SOC system is in sleep mode and generates the low frequency enable signal EN_LF.
The low frequency source clock generation module 103 is connected to the output terminal of the mode selection module 102, and wakes up based on the low frequency enable signal en_lf and generates the low frequency source clock clk_lf.
As an example, the low frequency source clock generation module 103 is implemented with a low frequency oscillator, and the frequency thereof may be designed according to specific requirements, which is not limited in this embodiment.
The low frequency source clock stabilizing module 104 is connected to an output end of the low frequency source clock generating module 103, and is configured to stabilize the low frequency source clock clk_lf and generate a low frequency stabilizing signal flag_lf after the low frequency source clock generating module 103 is awakened for a first set time.
As an example, the low frequency source clock stabilization module 104 is implemented with at least one counter for starting counting when the low frequency source clock generation module 103 is woken up and generating the low frequency stabilization signal flag_lf when the count value reaches the first set value. In practical application, the length of the first setting time can be designed according to specific requirements through the size of the first setting value.
The high frequency source clock generation module 105 is connected to the output of the mode selection module 102 and the output of the low frequency source clock stabilization module 104, wakes up based on the high frequency enable signal en_hf or the low frequency stabilization signal flag_lf and generates the high frequency source clock clk_hf.
As an example, the high-frequency source clock generation module 105 is implemented with a high-frequency oscillator, the frequency of which can be designed according to specific requirements, which is not limited in this embodiment.
The high-frequency source clock stabilizing module 106 is connected to an output end of the high-frequency source clock generating module 105, and is configured to stabilize the high-frequency source clock clk_hf and generate a high-frequency stabilizing signal flag_hf after the high-frequency source clock generating module 105 is awakened for a second set time.
As an example, the high frequency source clock stabilization module 106 is implemented with at least one counter for starting counting when the high frequency source clock generation module 105 is woken up and generating the high frequency stabilization signal flag_hf when the count value reaches the second set value. In practical application, the length of the second set time can be designed according to specific requirements through the size of the second set value; the first setting value and the second setting value may be the same or different, but are generally different, and the first setting value is smaller than the second setting value.
The clock frequency division and control module 107 is connected to the output end of the low-frequency source clock generation module 103 and the output end of the high-frequency source clock generation module 105, and simultaneously is also connected to the output end of the low-frequency source clock stabilization module 104 and the output end of the high-frequency source clock stabilization module 106, and is used for performing frequency division processing on the low-frequency source clock clk_lf and the high-frequency source clock clk_hf to generate a plurality of working clocks, and performing output control on the plurality of working clocks based on the low-frequency stabilization signal flag_lf and the high-frequency stabilization signal flag_hf.
In practical applications, the clock dividing and controlling module 107 divides the low-frequency source clock clk_lf and the high-frequency source clock clk_hf according to specific requirements to generate working clocks with required frequencies, such as CPU clocks, system clocks, internal function clocks, peripheral clocks, etc.
Accordingly, as shown in fig. 2, the present embodiment further provides an SOC system 10, the SOC system 10 including: the wake-up circuit 100 described above.
Further, the SOC system 10 further includes a CPU circuit 200 and a plurality of functional circuits 300, such as functional circuit 1 to functional circuit n (n > 1), connected to the output terminal of the clock dividing and controlling module 107; wherein the CPU circuit 200 and the plurality of functional circuits 300 perform their own set tasks based on the respective operation clocks.
In addition, when the asynchronous module 101 is an asynchronous communication module, the SOC system 10 further includes a data processing circuit 400, connected to the output end of the asynchronous module 101 and the output end of the clock frequency dividing and controlling module 107, for receiving and storing communication data transmitted by the asynchronous module 101 based on a corresponding working clock; of course, the data processing circuit 400 may also perform corresponding data processing on the received communication data according to specific requirements.
Correspondingly, the embodiment also provides a wake-up method of the SOC system, which comprises the following steps: step 1) and step 2); further, the wake-up method further comprises the following steps: and 3) step 3). The SOC system is the SOC system 10 described above.
Step 1) the asynchronous module 101 performs a setting task based on the external clock clk_ext and generates an end flag as a wake-up signal WK when the setting task is completed.
By way of example, the asynchronous module 101 includes an asynchronous communication module, such as an asynchronous I2C module or an asynchronous UART module; at this time, the method of generating the wake-up signal includes: the asynchronous communication module generates an address matching completion flag bit as a wake-up signal WK when address matching is completed, or generates a data transmission termination bit as a wake-up signal WK when data transmission is completed.
Step 2) the mode selection module 102 starts system mode identification based on the wake-up signal WK.
As an example, a method of performing system pattern recognition includes: the mode selection module 102 determines that the SOC system is in an operating state or a non-operating state based on the data stored in the CPU status register, and determines that the SOC system is in an idle mode or a sleep mode based on the data stored in the mode status register when determining that the SOC system is in the non-operating state, where the specific determination method may be referred to above, and is not described herein.
2-1) if the SOC system is in the sleep mode (at this time, both the low-frequency source clock generation module 103 and the high-frequency source clock generation module 105 are turned off), the mode selection module 102 generates the low-frequency enable signal en_lf, so that the low-frequency source clock generation module 103 is awakened and generates the low-frequency source clock clk_lf, the low-frequency source clock stabilization module 104 stabilizes the low-frequency source clock clk_lf and generates the low-frequency stabilization signal flag_lf over a first set time, the high-frequency source clock generation module 105 is awakened and generates the high-frequency source clock clk_hf based on the low-frequency stabilization signal flag_lf, and the high-frequency source clock stabilization module 106 stabilizes the high-frequency source clock clk_hf and generates the high-frequency stabilization signal flag_hf over a second set time; in this way, the SOC system wakes up from the sleep mode and enters the operational mode.
As an example, the method of generating the low frequency stabilization signal flag_lf includes: the low frequency source clock stabilization module 104 starts counting when the low frequency source clock generation module 103 is awakened, and generates a low frequency stabilization signal flag_lf when the count value reaches a first set value.
As an example, the method of generating the high frequency stabilization signal flag_hf comprises: the high-frequency source clock stabilization module 106 starts counting when the high-frequency source clock generation module 105 is awakened, and generates a high-frequency stabilization signal flag_hf when the count value reaches a second set value.
In practical application, the first set time can be designed through the first set value and the second set time can be designed through the second set value according to specific requirements; the first setting value and the second setting value may be the same or different, but are generally different, and the first setting value is smaller than the second setting value.
2-2) if the SOC system is in the idle mode (at this time, the low frequency source clock generation module 103 is normally operated, the high frequency source clock generation module 105 is turned off), the mode selection module 102 generates the high frequency enable signal en_hf, so that the high frequency source clock generation module 105 is awakened and generates the high frequency source clock clk_hf, and the high frequency source clock stabilization module 106 stabilizes the high frequency source clock clk_hf and generates the high frequency stabilization signal flag_hf after a second set time; in this way, the SOC system wakes up from the idle mode and enters the operational mode.
2-3) if the SOC system is in the operation mode (at this time, both the low frequency source clock generation module 103 and the high frequency source clock generation module 105 are operating normally), the mode selection module 102 generates an invalid output, such as no output, so that the low frequency source clock generation module 103 and the high frequency source clock generation module 105 are not subjected to the enable control.
Step 3) the clock frequency dividing and controlling module 107 performs frequency dividing processing on the low-frequency source clock clk_lf to generate at least one low-frequency working clock, and generates a low-frequency gating signal based on the low-frequency stabilizing signal flag_lf to output and control the low-frequency working clock; and frequency-dividing the high-frequency source clock clk_hf to generate at least one high-frequency operation clock, and generating a high-frequency gating signal based on the high-frequency stabilizing signal flag_hf to output-control the high-frequency operation clock; thus, the corresponding working clock is provided for the corresponding circuit.
In summary, according to the wake-up circuit, the SOC system and the wake-up method thereof, the asynchronous module is utilized to generate the wake-up signal, so that not only can the idle mode of the SOC system be awakened, but also the sleep mode of the SOC system can be awakened; because the asynchronous module does not need extra packaging pins, the problem that no redundant packaging pins realize external awakening when the circuit packaging pins are limited is avoided; in addition, the asynchronous module does not need high-frequency source clocks and low-frequency source clocks of the SOC system to participate in the operation, so that the SOC system can close the high-frequency source clocks and the low-frequency source clocks after corresponding tasks are completed and enter a sleep mode, and the power consumption of the system is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.