技术领域Technical field
本发明属于半导体封装技术领域，特别涉及一种晶圆级非TSV 3D堆叠封装结构及方法。The invention belongs to the field of semiconductor packaging technology, and particularly relates to a wafer-level non-TSV 3D stacked packaging structure and method.
背景技术Background technique
传统无硅通孔 3D（ 非TSV 3D、Non-TSV 3D）堆叠封装技术是一种将多个芯片或组件在垂直方向上堆叠起来的技术。这种技术通过在芯片之间使用电气连接和机械连接来实现信号和电源的传输，同时保持紧凑的封装尺寸。Traditional non-through silicon via 3D (non-TSV 3D, Non-TSV 3D) stacked packaging technology is a technology that stacks multiple chips or components in a vertical direction. This technology enables the transmission of signals and power by using electrical and mechanical connections between chips while maintaining a compact package size.
传统非TSV 3D堆叠封装用金属线键合或者倒装技术或者两者结合的方式通过基板进行堆叠，大颗栅格阵列封装（LGA）/球栅阵列封装（BGA）基板作业都是单颗进行，作业效率没有晶圆级作业高。同时，由于将多个芯片需要借助基板在垂直方向上堆叠，封装后的芯片具有较大的厚度，基本都在80um以上，这可能会导致信号传输距离较长，从而增加信号传输延迟和功耗。Traditional non-TSV 3D stacked packaging uses metal wire bonding or flip-chip technology or a combination of both to stack through the substrate. Large Grid Array Package (LGA)/Ball Grid Array Package (BGA) substrate operations are all performed in a single package. , the operating efficiency is not as high as wafer-level operations. At the same time, since multiple chips need to be stacked in the vertical direction with the help of substrates, the packaged chips have a large thickness, basically above 80um, which may result in a longer signal transmission distance, thereby increasing signal transmission delay and power consumption. .
同时，传统非TSV 3D堆叠封装技术的制造成本较高。由于需要将多个芯片或组件在垂直方向上堆叠在一起，因此需要使用高精度的组装工艺和昂贵的封装材料。此外，需要使引脚或端子等连接器来实现电气连接,这也会增加封装的成本。At the same time, the manufacturing cost of traditional non-TSV 3D stacked packaging technology is relatively high. Since multiple chips or components need to be stacked vertically, high-precision assembly processes and expensive packaging materials are required. In addition, connectors such as pins or terminals are required to achieve electrical connections, which will also increase the cost of packaging.
发明内容Contents of the invention
为了解决上述问题，本发明提供了一种晶圆级非TSV 3D堆叠封装结构及方法，成本低廉、作业效率高，可以使得芯片厚度减薄，电性能损耗更小。In order to solve the above problems, the present invention provides a wafer-level non-TSV 3D stacked packaging structure and method, which is low in cost and high in operation efficiency. It can make the chip thickness thinner and reduce the electrical performance loss.
为此，本发明的技术方案是：一种晶圆级非TSV 3D堆叠封装结构，包括基板和若干堆叠设置的芯片单元层，所有芯片单元层互相堆叠在一起，置于基板上；所述芯片单元层包括至少一个倒置的芯片单元，芯片单元外侧设有塑封层，相邻芯片单元层之间设有重布线层，各芯片单元正面通过重布线层与侧面铜柱导通。To this end, the technical solution of the present invention is: a wafer-level non-TSV 3D stacked packaging structure, including a substrate and several stacked chip unit layers. All chip unit layers are stacked on each other and placed on the substrate; the chip The unit layer includes at least one inverted chip unit. A plastic sealing layer is provided on the outside of the chip unit. A rewiring layer is provided between adjacent chip unit layers. The front side of each chip unit is connected to the side copper pillars through the rewiring layer.
在上述方案的基础上并作为上述方案的优选方案：所述芯片单元包括芯片本体，芯片本体正面设有焊料凸点，焊料凸点通过重布线层与侧面铜柱电性连接。On the basis of the above solution and as a preferred solution of the above solution: the chip unit includes a chip body, the front side of the chip body is provided with solder bumps, and the solder bumps are electrically connected to the side copper pillars through the redistribution layer.
在上述方案的基础上并作为上述方案的优选方案：第一芯片单元层下方设有第一重布线层，第一重布线层上设有第一铜柱；所述第一芯片单元层包括至少一个第一芯片单元，第一芯片单元倒置在第一重布线层上，第一塑封层覆盖第一芯片单元和第一铜柱，且第一塑封层、第一芯片单元背面、第一铜柱同步减薄。On the basis of the above solution and as a preferred solution of the above solution: a first rewiring layer is provided under the first chip unit layer, and a first copper pillar is provided on the first rewiring layer; the first chip unit layer includes at least A first chip unit, the first chip unit is inverted on the first rewiring layer, the first plastic encapsulation layer covers the first chip unit and the first copper pillar, and the first plastic encapsulation layer, the back side of the first chip unit, and the first copper pillar Simultaneous thinning.
在上述方案的基础上并作为上述方案的优选方案：第二芯片单元层下方设有第二重布线层，第二重布线层上设有第二铜柱；所述第二芯片单元层包括至少一个第二芯片单元，第二芯片单元倒置在第二重布线层上；所述第二芯片单元外侧设有第二塑封层，第二塑封层覆盖第二芯片单元和第二铜柱，第二塑封层、第二芯片单元背面、第二铜柱同步减薄。On the basis of the above solution and as a preferred solution of the above solution: a second rewiring layer is provided under the second chip unit layer, and a second copper pillar is provided on the second rewiring layer; the second chip unit layer includes at least A second chip unit, the second chip unit is inverted on the second rewiring layer; a second plastic sealing layer is provided outside the second chip unit, and the second plastic sealing layer covers the second chip unit and the second copper pillar, and the second The plastic encapsulation layer, the back side of the second chip unit, and the second copper pillar are thinned simultaneously.
在上述方案的基础上并作为上述方案的优选方案：最顶层的芯片单元层上设有第三重布线层，第三重布线层上设有焊点，焊点由植球或电镀形成。Based on the above solution and as the preferred solution of the above solution: the topmost chip unit layer is provided with a third rewiring layer, and the third rewiring layer is provided with solder joints, and the solder joints are formed by ball planting or electroplating.
在上述方案的基础上并作为上述方案的优选方案：相邻芯片单元层之间设有多层第二重布线层，相邻第二重布线层之间设有介电层。Based on the above solution and as a preferred solution of the above solution: multiple second rewiring layers are provided between adjacent chip unit layers, and dielectric layers are provided between adjacent second rewiring layers.
本发明的另一个技术方案是：一种晶圆级非TSV 3D堆叠封装方法，包括以下步骤：Another technical solution of the present invention is: a wafer-level non-TSV 3D stacked packaging method, including the following steps:
1）制备多个芯片单元：在硅晶片正面完成晶圆级封装，制作出焊料凸点，并对硅晶片进行磨片、划片，得到芯片单元；1) Prepare multiple chip units: Complete wafer-level packaging on the front side of the silicon wafer, make solder bumps, and grind and scribe the silicon wafer to obtain chip units;
2）制备基板：在基板正面制作第一重布线层和第一铜柱；2) Prepare the substrate: Make the first rewiring layer and the first copper pillar on the front side of the substrate;
3）将至少一个第一芯片单元倒置在基板的第一重布线层上，第一芯片单元正面通过第一重布线层与第一铜柱导通；3) Invert at least one first chip unit on the first rewiring layer of the substrate, and the front side of the first chip unit is connected to the first copper pillar through the first rewiring layer;
4）对第一芯片单元进行塑封，塑封层覆盖第一芯片单元和第一铜柱；4) Plastic-pack the first chip unit, and the plastic-packing layer covers the first chip unit and the first copper pillar;
5）对基板正面进行磨片，裸露出第一铜柱和第一芯片单元的背面，形成第一芯片单元层；5) Grind the front side of the substrate to expose the first copper pillar and the back side of the first chip unit to form the first chip unit layer;
6）在第一芯片单元层上方设置第二重布线层和第二铜柱；6) Set the second rewiring layer and the second copper pillar above the first chip unit layer;
7）将至少一个第二芯片单元倒置在第二重布线层上，第二芯片单元正面通过第二重布线层与第二铜柱导通；7) Invert at least one second chip unit on the second rewiring layer, and the front side of the second chip unit is connected to the second copper pillar through the second rewiring layer;
8）重复步骤4）~6），形成第二芯片单元层；8) Repeat steps 4)~6) to form the second chip unit layer;
9）重复步骤7）~8），堆叠设置多个芯片单元层；9) Repeat steps 7)~8) to stack multiple chip unit layers;
10）当堆叠数量达到需求后，在最顶层芯片单元层上方进行植球或电镀工艺；10) When the number of stacks reaches the required number, the ball planting or electroplating process is performed above the top chip unit layer;
11）对步骤10）得到的封装体进行后处理，得到合格品芯片。11) Post-process the package obtained in step 10) to obtain a qualified chip.
在上述方案的基础上并作为上述方案的优选方案：所述步骤1）中，所有芯片单元可为相同类型芯片或不同类型芯片。On the basis of the above solution and as a preferred solution of the above solution: in step 1), all chip units may be the same type of chips or different types of chips.
在上述方案的基础上并作为上述方案的优选方案：所述步骤5）磨片后，芯片单元减薄至20~25μm。On the basis of the above solution and as the preferred solution of the above solution: after step 5), the chip unit is thinned to 20~25 μm.
在上述方案的基础上并作为上述方案的优选方案：所述步骤6）中，若芯片单元背面设有电极，电极可通过第二重布线层导出。Based on the above solution and as a preferred solution of the above solution: in step 6), if there are electrodes on the back of the chip unit, the electrodes can be derived through the second rewiring layer.
与现有技术相比，本发明的有益效果是：Compared with the prior art, the beneficial effects of the present invention are:
采用非TSV的晶圆级封装，相邻芯片单元之间不需要设置基板，使用PI/RDL的工艺实现互联，使得芯片厚度更薄电性能损耗更小；Using non-TSV wafer-level packaging, there is no need to set up a substrate between adjacent chip units, and the PI/RDL process is used to achieve interconnection, making the chip thinner and reducing electrical performance loss;
芯片单元倒装后，采用晶圆级底部填充工艺，实现芯片单元背面的完整填充；芯片单元背面可直接覆盖布线绝缘材料，无需环氧树脂类型的EMC材料；同时，可以实现芯片单元背面导通，如果芯片单元背面是电极，可以通过RDL导通出去；After the chip unit is flipped, a wafer-level underfill process is used to achieve complete filling of the backside of the chip unit; the backside of the chip unit can be directly covered with wiring insulating material, without the need for epoxy resin type EMC materials; at the same time, conduction on the backside of the chip unit can be achieved , if the back of the chip unit is an electrode, it can be connected through RDL;
采用标准工艺芯片厚度进行倒装，芯片背面与侧边的铜柱同步减薄，实现超薄结构，使得芯片最小厚度可至20um水平，从而可控制整体封装厚度，或者说在同等厚度下，可堆叠更多的芯片单元，实现更多功能；The chip thickness is flip-chip using a standard process, and the copper pillars on the back and sides of the chip are thinned simultaneously to achieve an ultra-thin structure, so that the minimum thickness of the chip can reach the 20um level, thereby controlling the overall packaging thickness, or in other words, at the same thickness, Stack more chip units to achieve more functions;
可基于产品要求堆叠多层芯片单元，同一层芯片单元层可平铺多个芯片单元，且芯片单元可选用相同芯片，也可以选择不同类型芯片，实现多样化功能设计，满足更多使用需求，通用性强。Multi-layer chip units can be stacked based on product requirements. Multiple chip units can be tiled on the same chip unit layer, and the chip units can use the same chip or different types of chips to achieve diversified functional design and meet more usage needs. Highly versatile.
附图说明Description of drawings
以下结合附图和本发明的实施方式来作进一步详细说明。Further detailed description will be given below with reference to the accompanying drawings and embodiments of the present invention.
图1为实施例1的封装结构示意图；Figure 1 is a schematic diagram of the packaging structure of Embodiment 1;
图2为实施例1的第一芯片单元的结构侧视图（a）和俯视图（b）；Figure 2 is a side view (a) and a top view (b) of the structure of the first chip unit in Embodiment 1;
图3为实施例1的第二芯片单元的结构侧视图（a）和俯视图（b）；Figure 3 is a side view (a) and a top view (b) of the structure of the second chip unit in Embodiment 1;
图4~图12为实施例1封装工艺步骤图：侧视图（a）和俯视图（b）；Figures 4 to 12 are diagrams of the packaging process steps of Embodiment 1: side view (a) and top view (b);
图13为实施例2的封装结构示意图；Figure 13 is a schematic diagram of the packaging structure of Embodiment 2;
图14为实施例3第一芯片单元层的结构侧视图（a）和俯视图（b）；Figure 14 is a side view (a) and a top view (b) of the structure of the first chip unit layer in Embodiment 3;
图15为实施例3的封装结构示意图。Figure 15 is a schematic diagram of the packaging structure of Embodiment 3.
图中标记为：基板1、第一芯片单元2、PI层一21、焊料凸点22、第二芯片单元3、第一重布线层4、第一铜柱5、第一塑封层6、PI层二7、第二重布线层8、第二铜柱9、第二塑封层10、PI层三11、第三重布线层12、球状凸起13、第三芯片单元14、第三铜柱15、第三塑封层16、PI层四17、第四重布线层18。Marked in the figure are: substrate 1, first chip unit 2, PI layer 21, solder bump 22, second chip unit 3, first rewiring layer 4, first copper pillar 5, first plastic encapsulation layer 6, PI Layer two 7, second rewiring layer 8, second copper pillar 9, second plastic encapsulation layer 10, PI layer three 11, third rewiring layer 12, ball bump 13, third chip unit 14, third copper pillar 15. The third plastic encapsulation layer 16, the PI layer 17, and the fourth rewiring layer 18.
具体实施方式Detailed ways
在本发明的描述中，需要说明的是，对于方位词，如有术语“中心”，“横向(X)”、“纵向(Y)”、“竖向(Z)”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示方位和位置关系为基于附图所示的方位或位置关系，仅是为了便于叙述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定方位构造和操作，不能理解为限制本发明的具体保护范围。In the description of the present invention, it should be noted that for directional words, such as the terms "center", "transverse direction (X)", "vertical direction (Y)", "vertical direction (Z)", "length", " "Width", "Thickness", "Top", "Bottom", "Front", "Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner" ”, “outside”, “clockwise”, “counterclockwise”, etc. indicate the orientation and positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply the direction or positional relationship. It is intended that a device or element must have a specific orientation, be constructed and operate in a specific orientation, and should not be construed as limiting the specific scope of the invention.
此外，如有术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或隐含指明技术特征的数量。由此，限定有“第一”、“第二”特征可以明示或者隐含包括一个或者多个该特征，在本发明描述中，“数个”、“若干”的含义是两个或两个以上，除非另有明确具体的限定。In addition, the terms "first" and "second" if used are for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present invention, “several” and “several” mean two or more Above, unless otherwise expressly and specifically limited.
实施例1Example 1
如图1所示，本实施例所述晶圆级非TSV 3D堆叠封装结构，包括基板1和两个堆叠设置的芯片单元，即为第一芯片单元2和第二芯片单元3。所述芯片单元包括芯片本体，芯片本体正面设有PI层一21和焊料凸点22。As shown in FIG. 1 , the wafer-level non-TSV 3D stacked packaging structure in this embodiment includes a substrate 1 and two stacked chip units, namely a first chip unit 2 and a second chip unit 3 . The chip unit includes a chip body, and a PI layer 21 and solder bumps 22 are provided on the front side of the chip body.
所述基板1正面设有第一重布线层4和第一铜柱5，第一芯片单元2倒置在第一重布线层4上，第一芯片单元2的焊料凸点22与第一重布线层4电性连接。所述第一芯片单元2背面进行塑封工艺，形成第一塑封层6，第一塑封层6覆盖第一芯片单元2和第一铜柱5；然后进行磨片，对第一塑封层进行减薄，第一塑封层减薄时，第一芯片单元2背面和第一铜柱5同步减薄，形成第一芯片单元层。The front side of the substrate 1 is provided with a first rewiring layer 4 and a first copper pillar 5. The first chip unit 2 is inverted on the first rewiring layer 4. The solder bumps 22 of the first chip unit 2 are in contact with the first rewiring layer. Layer 4 is electrically connected. A plastic sealing process is performed on the back of the first chip unit 2 to form a first plastic seal layer 6. The first plastic seal layer 6 covers the first chip unit 2 and the first copper pillar 5; then grinding is performed to thin the first plastic seal layer. , when the first plastic encapsulation layer is thinned, the back surface of the first chip unit 2 and the first copper pillar 5 are simultaneously thinned to form the first chip unit layer.
减薄后，在第一芯片单元2上方铺设PI层二7和第二重布线层8，相邻第二重布线层8之间可设置介电层，具体PI层和走线层（Metal）数视芯片实际走线来定，第一芯片单元的背面如果为电极，也可以通过第二重布线层导出。After thinning, lay the PI layer 27 and the second rewiring layer 8 above the first chip unit 2. A dielectric layer can be set between the adjacent second rewiring layers 8, specifically the PI layer and the wiring layer (Metal). The number depends on the actual wiring of the chip. If the back side of the first chip unit is an electrode, it can also be derived through the second rewiring layer.
所述第一芯片单元2背面最外侧的第二重布线层上设有第二铜柱9，第二芯片单元3倒置在第一芯片单元2的第二重布线层8上，第二芯片单元3上的焊料凸点与第二重布线层8电性连接。所述第二芯片单元3背面进行塑封工艺，形成第二塑封层10，第二塑封层10覆盖第二芯片单元3和第二铜柱9，第二塑封层减薄时，第二芯片单元背面和第二铜柱同步减薄，形成第二芯片单元层。The second copper pillar 9 is provided on the outermost second rewiring layer on the back of the first chip unit 2. The second chip unit 3 is inverted on the second rewiring layer 8 of the first chip unit 2. The second chip unit The solder bumps on 3 are electrically connected to the second rewiring layer 8 . The back of the second chip unit 3 undergoes a plastic sealing process to form a second plastic layer 10. The second plastic layer 10 covers the second chip unit 3 and the second copper pillar 9. When the second plastic layer is thinned, the back of the second chip unit It is thinned simultaneously with the second copper pillar to form the second chip unit layer.
减薄后，在第二芯片单元3上方铺设PI层三11和第三重布线层12，具体PI层和信号线（Metal）层数视芯片实际走线来定，第二芯片单元的背面如果为电极，也可以通过第三重布线层导出。After thinning, lay PI layer three 11 and third rewiring layer 12 above the second chip unit 3. The specific number of PI layers and signal line (Metal) layers depends on the actual wiring of the chip. If the back side of the second chip unit is an electrode, which can also be derived through the third rewiring layer.
在第二芯片单元3背面的第三重布线层12上设置UBM焊盘，UBM焊盘用于设置球状凸起13，球状凸起13可以通过植球或电镀工艺实现，凸块的形状可以基于产品要求实现BGA或者LGA的封装外观需求。UBM即为凸点底部金属化。A UBM pad is provided on the third rewiring layer 12 on the back of the second chip unit 3. The UBM pad is used to set a spherical bump 13. The spherical bump 13 can be realized by ball planting or electroplating process. The shape of the bump can be based on The product is required to meet the packaging appearance requirements of BGA or LGA. UBM is bottom bump metallization.
所有的芯片单元可为相同类型芯片或不同类型芯片。如图2、图3所示，本实施例堆叠了不同类型的第一芯片单元2和第二芯片单元3。All chip units can be chips of the same type or chips of different types. As shown in Figures 2 and 3, in this embodiment, different types of first chip units 2 and second chip units 3 are stacked.
本实施例的封装工艺如下：The packaging process of this embodiment is as follows:
1）制备多个芯片单元：在硅晶片正面完成晶圆级封装的凸块制作，制作出PI层一21和焊料凸点22；然后对并对硅晶片进行磨片、划片，得到符合要求的芯片单元；晶圆级封装(Wafer Level Packaging，缩写WLP)是一种先进的封装技术，因其具有尺寸小、电性能优良、散热好、成本低等优势，近年来发展迅速。不同于传统封装工艺，晶圆级封装是在芯片还在晶圆上的时候就对芯片进行封装，保护层可以黏接在晶圆的顶部或底部，然后连接电路，再将晶圆切成单个芯片。1) Prepare multiple chip units: Complete bump production for wafer-level packaging on the front side of the silicon wafer, and produce PI layer 21 and solder bumps 22; then grind and scribe the silicon wafer to obtain a product that meets the requirements Chip unit; Wafer Level Packaging (WLP) is an advanced packaging technology that has developed rapidly in recent years because of its advantages such as small size, excellent electrical performance, good heat dissipation, and low cost. Different from traditional packaging processes, wafer-level packaging encapsulates the chip while it is still on the wafer. The protective layer can be bonded to the top or bottom of the wafer, and then connected to the circuit, and then the wafer is cut into individual pieces. chip.
2）制备基板：在基板1正面制作第一重布线层4（RDL层）和第一铜柱5，如图4所示；2) Prepare the substrate: Make the first rewiring layer 4 (RDL layer) and the first copper pillar 5 on the front side of the substrate 1, as shown in Figure 4;
3）将第一芯片单元2倒置在基板1的第一重布线层4上，即使得第一芯片单元与基板实现电性连接，如图5所示；3) Place the first chip unit 2 upside down on the first rewiring layer 4 of the substrate 1, so that the first chip unit and the substrate are electrically connected, as shown in Figure 5;
4）对第一芯片单元2进行塑封工艺，使得第一芯片单元2和第一铜柱5外侧覆盖第一塑封层6，对第一芯片单元和第一铜柱起到保护作用，如图6所示；4) Perform a plastic packaging process on the first chip unit 2 so that the outside of the first chip unit 2 and the first copper pillar 5 are covered with the first plastic layer 6 to protect the first chip unit and the first copper pillar, as shown in Figure 6 shown;
5）对基板1正面进行磨片，第一塑封层6、第一铜柱5和第一芯片单元2背面同时进行减薄，裸露出第一铜柱和第一芯片单元的背面，第一芯片单元最小可减薄至20，如图7所示；5) Grind the front side of the substrate 1, thin the first plastic encapsulation layer 6, the first copper pillar 5 and the back side of the first chip unit 2 at the same time, exposing the first copper pillar and the back side of the first chip unit, and the first chip The minimum unit thickness can be reduced to 20, as shown in Figure 7;
6）在裸露的第一芯片单元2背面制作晶片凸块（Wafer bumping）以及增加第二铜柱9,其中晶片凸块上的PI层二7和第二重布线层8视芯片实际走线来定，如果第一芯片单元背面如果为电极，可以通过设置第二重布线层导出，如图8、图9所示；6) Make a wafer bump (Wafer bumping) on the back of the exposed first chip unit 2 and add a second copper pillar 9. The PI layer 2 7 and the second rewiring layer 8 on the wafer bump depend on the actual wiring of the chip. If the back side of the first chip unit is an electrode, it can be derived by setting a second rewiring layer, as shown in Figure 8 and Figure 9;
7）将第二芯片单元3倒置在第一芯片单元2的第二重布线层8上，使得两个芯片单元实现电性连接；7) Invert the second chip unit 3 on the second rewiring layer 8 of the first chip unit 2 so that the two chip units are electrically connected;
8）对第二芯片单元3进行塑封工艺，使得第二芯片单元3和第二铜柱9外侧覆盖第二塑封层10，对第二芯片单元和第二铜柱起到保护作用；8) Perform a plastic packaging process on the second chip unit 3 so that the outside of the second chip unit 3 and the second copper pillar 9 are covered with the second plastic layer 10 to protect the second chip unit and the second copper pillar;
9）对基板1正面进行磨片，第二塑封层10、第二铜柱9和第二芯片单元3背面同时进行减薄，裸露出第二铜柱和第二芯片单元的背面，如图10所示；9) Grind the front side of the substrate 1, and thin the second plastic encapsulation layer 10, the second copper pillar 9 and the back side of the second chip unit 3 at the same time, exposing the back side of the second copper pillar and the second chip unit, as shown in Figure 10 shown;
10）在裸露的第二芯片单元背面制作晶片凸块（Wafer bumping）和凸块（Bump）,其中具体PI层三11和第三重布线层12层数视芯片实际走线来定，球状凸起13可以通过植球或电镀工艺实现，凸块的形状可以基于产品要求实现BGA或者LGA的封装外观需求，如图11所示；10) Make wafer bumping and bumps on the back of the exposed second chip unit. The specific number of PI layer 311 and third rewiring layer 12 depends on the actual wiring of the chip. Spherical bumps 13 can be achieved through ball placement or electroplating process, and the shape of the bumps can meet the packaging appearance requirements of BGA or LGA based on product requirements, as shown in Figure 11;
11）对基板背面进行磨片、打印、背胶、划片，再进行测试，得到合格品芯片，即将芯片基板的背面磨平，将芯片的电路和其他必要信息打印或描绘在芯片表面，在芯片背面涂上胶水或粘合剂，用于固定芯片并保护其内部电路，将晶圆切割成单个芯片，并对每个芯片进行功能性和可靠性测试，根据测试结果，将芯片分类为合格品或不合格品，如图12所示。11) Grind, print, glue, and scribe the back of the substrate, and then test it to obtain a qualified chip. That is, grind the back of the chip substrate flat, and print or draw the circuit and other necessary information of the chip on the surface of the chip. Glue or adhesive is applied to the back of the chip to fix the chip and protect its internal circuitry. The wafer is cut into individual chips and each chip is tested for functionality and reliability. Based on the test results, the chip is classified as qualified. products or defective products, as shown in Figure 12.
实施例2Example 2
如图13所示，本实施例所述封装结构，包括基板1和三个堆叠设置的芯片单元，即为第一芯片单元2、第二芯片单元3和第三芯片单元14。其余结构与实施例1类似，区别在于：As shown in FIG. 13 , the packaging structure of this embodiment includes a substrate 1 and three stacked chip units, namely a first chip unit 2 , a second chip unit 3 and a third chip unit 14 . The rest of the structure is similar to Embodiment 1, the difference is:
在第二芯片单元3上方铺设PI层三11和第三重布线层12后，第二芯片单元背面最外侧的第三重布线层上设有第三铜柱15，第三芯片单元14倒置在第二芯片单元3的第三重布线层12上，第三芯片单元上的焊料凸点与第三重布线层电性连接。所述第三芯片单元14背面进行塑封工艺，形成第三塑封层16，第三塑封层16覆盖第三芯片单元14和第三铜柱15，第三塑封层减薄时，第三芯片单元背面和第三铜柱同步减薄。After laying the PI layer three 11 and the third rewiring layer 12 above the second chip unit 3, a third copper pillar 15 is provided on the outermost third rewiring layer on the back of the second chip unit, and the third chip unit 14 is placed upside down. On the third rewiring layer 12 of the second chip unit 3, the solder bumps on the third chip unit are electrically connected to the third rewiring layer. The back of the third chip unit 14 undergoes a plastic sealing process to form a third plastic layer 16. The third plastic layer 16 covers the third chip unit 14 and the third copper pillar 15. When the third plastic layer is thinned, the back of the third chip unit Simultaneous thinning with the third copper pillar.
减薄后，在第三芯片单元14上方铺设PI层四17和第四重布线层18，在第四重布线层上设置UBM焊盘，可以通过植球或电镀工艺实现Bump，Bump可以基于产品要求实现BGA或者LGA的封装外观需求。After thinning, lay the PI layer 17 and the fourth rewiring layer 18 above the third chip unit 14, and set the UBM pad on the fourth rewiring layer. Bump can be realized through ball planting or electroplating process, and the bump can be based on the product. It is required to achieve the packaging appearance requirements of BGA or LGA.
由此类推，本实施例所述封装结构还可以继续堆叠第四芯片单元、第五芯片单元等，实现封装芯片的多样化。By analogy, the packaging structure described in this embodiment can also continue to stack fourth chip units, fifth chip units, etc., to achieve diversification of packaged chips.
实施例3Example 3
实施例1和实施例2中，每一层芯片单元层都只设置了一片芯片单元，而本实施例的区别在于：某一层或所有的芯片单元层均可设置大于2数量的芯片单元。如图14所示，芯片单元层上平铺了两个芯片单元，这两个芯片单元互不干涉，芯片单元正面均通过重布线层与侧面铜柱实现导通。In Embodiment 1 and Embodiment 2, each chip unit layer is provided with only one chip unit, but the difference in this embodiment is that a certain layer or all chip unit layers can be provided with more than 2 chip units. As shown in Figure 14, two chip units are tiled on the chip unit layer. The two chip units do not interfere with each other. The front side of the chip unit is connected through the rewiring layer and the side copper pillars.
如图15所示，第一芯片单元层和第二芯片单元层均设有不止一个芯片单元，各个芯片单元层上芯片单元的数量可以一致也可以不一致，同层芯片单元的类型可以一样，也可以不一样，只要满足客户的实际需求即可。As shown in Figure 15, both the first chip unit layer and the second chip unit layer are provided with more than one chip unit. The number of chip units on each chip unit layer may be the same or different. The types of chip units in the same layer may be the same, or It can be different, as long as it meets the actual needs of customers.
以上所述仅是本发明的优选实施方式，本发明的保护范围并不仅局限于上述实施例，凡属于本发明思路下的技术方案均属于本发明的保护范围。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理前提下的若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above are only preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above-mentioned embodiments. All technical solutions that fall under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those of ordinary skill in the art, several improvements and modifications may be made without departing from the principles of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
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| CN202311613617.6ACN117316907A (en) | 2023-11-29 | 2023-11-29 | Wafer-level non-TSV 3D stacked packaging structure and method |
| Application Number | Priority Date | Filing Date | Title |
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| CN202311613617.6ACN117316907A (en) | 2023-11-29 | 2023-11-29 | Wafer-level non-TSV 3D stacked packaging structure and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118507462A (en)* | 2024-07-18 | 2024-08-16 | 格创通信(浙江)有限公司 | Chip packaging structure and preparation method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130105973A1 (en)* | 2011-11-02 | 2013-05-02 | Stmicroelectronics Pte Ltd. | Embedded wafer level package for 3d and package-on-package applications, and method of manufacture |
| CN103730434A (en)* | 2012-10-11 | 2014-04-16 | 台湾积体电路制造股份有限公司 | POP structure and its formation method |
| CN208460760U (en)* | 2018-05-04 | 2019-02-01 | 袁鹰 | Three-dimensional system level packaging structure |
| CN115206948A (en)* | 2022-05-30 | 2022-10-18 | 盛合晶微半导体(江阴)有限公司 | Three-dimensional fan-out type packaging structure of ultrahigh-density connection system and preparation method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130105973A1 (en)* | 2011-11-02 | 2013-05-02 | Stmicroelectronics Pte Ltd. | Embedded wafer level package for 3d and package-on-package applications, and method of manufacture |
| CN103730434A (en)* | 2012-10-11 | 2014-04-16 | 台湾积体电路制造股份有限公司 | POP structure and its formation method |
| CN208460760U (en)* | 2018-05-04 | 2019-02-01 | 袁鹰 | Three-dimensional system level packaging structure |
| CN115206948A (en)* | 2022-05-30 | 2022-10-18 | 盛合晶微半导体(江阴)有限公司 | Three-dimensional fan-out type packaging structure of ultrahigh-density connection system and preparation method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118507462A (en)* | 2024-07-18 | 2024-08-16 | 格创通信(浙江)有限公司 | Chip packaging structure and preparation method thereof |
| Publication | Publication Date | Title |
|---|---|---|
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