Disclosure of Invention
The embodiment of the application provides a pin arrangement structure and a high-speed differential signal chip, and the reflow ground pins can meet the signal integrity of the high-speed differential signal on the premise of not meeting the symmetrical distribution.
In a first aspect, a pin arrangement structure is provided, which includes a plurality of rows of pins, wherein each pin of an upper row and each pin of a lower row are staggered in two adjacent rows of pins;
at least one part of all the pins is a reflux ground pin, and at least one part of all the pins is a differential signal pin;
at least one part of the differential signal pins is a P-type pin, and at least one part of the differential signal pins is an N-type pin;
a P-type pin and an N-type pin form a differential signal pin pair, and two differential signal pins of the differential signal pin pair are distributed in two adjacent rows;
all differential signal pin pairs, at least a portion of which are a first differential signal pin pair and a second differential signal pin pair;
the pin arrangement structure comprises a diamond structure, wherein the diamond structure comprises four backflow ground pins, a first differential signal pin pair and a second differential signal pin pair, the four backflow ground pins form corners of the diamond structure, the first differential signal pin pair and the second differential signal pin pair, one differential signal pin is positioned at the center of the diamond structure, and the other three differential signal pins are respectively arranged in three rows which are continuously distributed and form the middle point of a diamond edge of the diamond structure.
In some embodiments, in the row direction, between two adjacent diamond-shaped formations, the differential signal pins located at the centers of the diamond-shaped formations are located in the same row.
In some embodiments, in the row direction, there are at least two adjacent diamond-shaped formations that share two return ground pins such that differential signal pins of the two adjacent diamond-shaped formations form a W-shaped distribution.
In some embodiments, in the row direction, two adjacent diamond-shaped formations are separated by at least n columns, where n is a natural number.
In some embodiments, in the column direction, two adjacent diamond-shaped formations are separated by at least n rows, where n is a natural number.
In some embodiments, between two adjacent diamond-shaped structures in the column direction, the differential signal pins located at the center of the diamond-shaped structures are separated by at least n columns, where n is a natural number.
In some embodiments, in the column direction, between two adjacent diamond-shaped formations, the differential signal pins located at the centers of the diamond-shaped formations are located in the same column.
In some embodiments, the spacing between adjacent two pins is 23.62mil, 27.56mil, 31.5mil, or 38.98mil.
In some embodiments, the distribution sequence of the two differential signal pins of the first differential signal pin pair and the two differential signal pins of the second differential signal pin pair in the diamond configuration in the row direction is:
the P-type pin of the first differential signal pin pair, the N-type pin of the first differential signal pin pair, the P-type pin of the second differential signal pin pair and the N-type pin of the second differential signal pin pair;
or the P-type pin of the first differential signal pin pair, the N-type pin of the second differential signal pin pair and the P-type pin of the second differential signal pin pair;
or the N-type pin of the first differential signal pin pair, the P-type pin of the second differential signal pin pair and the N-type pin of the second differential signal pin pair;
or the N-type pin of the first differential signal pin pair, the P-type pin of the first differential signal pin pair, the N-type pin of the second differential signal pin pair and the P-type pin of the second differential signal pin pair.
In a second aspect, there is provided a high-speed differential signal chip configured with a pin arrangement as described in any one of the above.
The beneficial effects that technical scheme that this application provided brought include:
the pin arrangement structure provided by the application can meet the signal integrity of high-speed differential signals on the premise of not meeting symmetrical distribution, and even the crosstalk is smaller than the scene of "+" differential signal pin arrangement.
The pin arrangement structure enables the chip to be more convenient when pins of the high-speed differential signals are arranged, and the pin arrangement structure is not limited to horizontal and vertical directions.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
Referring to fig. 4, an embodiment of the present application provides a pin arrangement structure, which includes a plurality of rows of pins, wherein each pin of a previous row and each pin of a next row are staggered in two adjacent rows of pins; at least one part of all the pins is a reflux ground pin, and at least one part of all the pins is a differential signal pin; at least one part of the differential signal pins is a P-type pin, and at least one part of the differential signal pins is an N-type pin; a P-type pin and an N-type pin form a differential signal pin pair, and two differential signal pins of the differential signal pin pair are distributed in two adjacent rows; all differential signal pin pairs have at least a portion of the first differential signal pin pair and at least a portion of the second differential signal pin pair.
The pin arrangement structure comprises a diamond structure, wherein the diamond structure comprises four backflow ground pins, a first differential signal pin pair and a second differential signal pin pair, the four backflow ground pins form corners of the diamond structure, the first differential signal pin pair and the second differential signal pin pair, one differential signal pin is positioned at the center of the diamond structure, and the other three differential signal pins are respectively arranged in three rows which are continuously distributed and form the middle point of a diamond edge of the diamond structure.
In the drawing, P is a P-type pin, which represents a negative terminal, N is an N-type pin, which represents a positive terminal, and numbers in front of P and N are serial numbers for distinguishing.
Referring to the diamond in fig. 4, four corners in the diamond are each arranged with one return ground pin GND, 1P and 1N as a first differential signal pin pair, 2P and 2N as a second differential signal pin pair, then 2N is located at the center of the diamond configuration, 2P, 1P and 1N are located in three rows distributed consecutively and between two return ground pins, forming the midpoint of the diamond, thus making the two pairs of differential signal pin pairs Cheng Duigou "v" shaped. Meanwhile, two sides of each differential signal pin are distributed with one backflow ground pin, for example, the upper right and lower left sides of 1P are respectively provided with one backflow ground pin, the left and right sides of 1N are respectively provided with one backflow ground pin, the upper right and lower right sides of 2N are respectively provided with one backflow ground pin, and the left and right sides of 2P are respectively provided with one backflow ground pin.
Therefore, in the pin arrangement structure provided by the application, in two adjacent rows of pins, each pin of the upper row and each pin corresponding to the lower row are distributed in a staggered manner, two differential signal pin pairs are arranged at the same time, two pins of the differential signal pin pairs are distributed in the two adjacent rows, the two differential signal pin pairs and four backflow ground pins can jointly form a diamond structure taking one differential signal pin as the center, the arrangement structure can be applied to design scenes when the backflow ground pins cannot meet the horizontal and vertical symmetrical distribution, the two differential signal pin pairs use four backflow ground pins, two sides of each differential signal pin can be distributed with one backflow ground pin, through simulation discovery, crosstalk is obviously optimized, and link signal integrity is improved.
It will be appreciated that for both differential signal pins of a differential signal pin pair, the differential signal pin of the upper row forms a differential signal pin pair with one of the differential signal pins of the next row that is adjacent to the differential signal pin.
It will be appreciated that the first differential signal pin pair and the second differential signal pin pair in the diamond configuration are distributed in three rows distributed in succession for a total of four differential signal pins.
For instance, as an example, referring to fig. 4, 2P is in the first row, 1P and 2N are in the second row, and 1N is in the third row; 4P is in the first row, 3P and 4N are in the second row, and 3N is in the third row.
As a preferred optimization, referring to fig. 4, between two adjacent diamond-shaped structures in the row direction, the differential signal pins located at the centers of the diamond-shaped structures are located in the same row. For example, 2N and 4N are located in the same row, and 7N and 9N are located in the same row.
As a preferred optimization, as shown in fig. 4, at least two adjacent diamond structures in the row direction share two return pins, so that the differential signal pins of the two adjacent diamond structures form a W-shaped distribution. As can be seen in fig. 4, the two bottom left and top right reflow pins of 3P are shared in two diamond configurations.
At this time, six reflux ground pins are used for four pairs of differential signal pins, and compared with the traditional pin arrangement structure in fig. 2 and 3, six reflux ground pins are used for four pairs of differential signal pins, the six reflux ground pins of the present application can be out of the same row and out of the same column, the chip design is more convenient, and as each differential signal pin has one reflux ground pin on two sides, the problem that the signal integrity of the high-speed differential signal is affected once the reflux ground pins cannot be symmetrically distributed in the traditional pin arrangement structure can be solved, and crosstalk increase and communication failure can be caused under serious conditions.
As shown in fig. 4, it is also possible to continue to share two return ground pins with other diamond-shaped configurations in the row direction, so that all differential signal pins can form an approximately wavy fold line extending in the row direction.
Further, as the midpoint of the remaining diamond-shaped edge of the diamond-shaped structure can be directly provided with the backflow ground pin or the differential signal pin, in practice, if the differential signal pin is provided, one diamond-shaped structure can be matched with a pair of differential signal pins and one backflow ground pin to form an isosceles trapezoid structure.
For example, in fig. 5, four return pins plus 1P, 1N,2P and 2N form a diamond configuration, where 3P and 3N may be added, and the return pins on the right side of 3N may be added, thereby forming an isosceles trapezoid configuration.
At this time, only five return ground pins are used for the three differential signal pin pairs.
It can be seen that in this application, designs can be made according to actual needs.
If a diamond configuration is used, four return ground pins are used for the two differential signal pin pairs.
If one differential signal pin pair is added on the basis of the rhombus structure, five reflux ground pins are used for three differential signal pin pairs.
If two diamond configurations share two return ground pins, six return ground pins are used for four differential signal pin pairs.
As a preferred optimization scheme, at least n columns of pins are separated between two adjacent diamond structures in the row direction, wherein n is a natural number, i.e. n can take values of 0, 1, 2 and the like.
For example, referring to fig. 6, n=1, where two adjacent diamond-shaped structures are separated by a column of pins in the row direction (see the vertical dashed line in fig. 6).
If n=0, the two diamond structures are just adjacent, the middle is not separated by the pins, and the pins of the reflow are not shared.
As a preferred optimization scheme, at least n rows of pins are separated between two adjacent diamond structures in the column direction, n is a natural number, that is, n can take values of 0, 1, 2 and the like.
For example, referring to fig. 4, n=1, where two adjacent diamond structures are separated by a row of pins in the column direction (see horizontal dashed line in fig. 4).
As another example, referring to fig. 5, n=0, where in the column direction, two diamond structures are just adjacent to each other, and the middle is not separated by a pin.
As a preferred optimization scheme, between two adjacent diamond structures in the column direction, the differential signal pins at the center of the diamond structures are at least separated by n columns of pins, n is a natural number, i.e. n can take values of 0, 1, 2, etc.
For example, referring to fig. 5, n=0, where in the column direction, between two adjacent diamond structures, the differential signal pins at the center of the diamond structures are separated by 0 columns, that is, they are just adjacent, the middle is neither separated by a pin, nor arranged in the same column, see two vertical dashed lines in fig. 5, 2N and 7N are just adjacent, separated by 0 columns.
As a preferred optimization scheme, between two adjacent diamond-shaped structures in the column direction, the differential signal pins located at the centers of the diamond-shaped structures are located in the same column.
For example, see the vertical dashed line shown in fig. 4, where 2N and 7N are in the same column.
In this application, the distribution sequence of the two differential signal pins of the first differential signal pin pair and the two differential signal pins of the second differential signal pin pair in the diamond structure in the row direction is:
the P-type pin of the first differential signal pin pair, the N-type pin of the first differential signal pin pair, the P-type pin of the second differential signal pin pair, and the N-type pin of the second differential signal pin pair.
Or the P-type pin of the first differential signal pin pair, the N-type pin of the second differential signal pin pair, and the P-type pin of the second differential signal pin pair.
Or the N-type pin of the first differential signal pin pair, the P-type pin of the second differential signal pin pair and the N-type pin of the second differential signal pin pair.
Or the N-type pin of the first differential signal pin pair, the P-type pin of the first differential signal pin pair, the N-type pin of the second differential signal pin pair and the P-type pin of the second differential signal pin pair.
It will be appreciated that the selection from the four distribution orders described above may be made according to actual design requirements.
When the pin arrangement structure is adopted for design, the distance between two adjacent pins can be determined according to actual design requirements, for example, the distance between two adjacent pins can be selected from 0.6mm (namely 23.62 mil), 0.7mm (namely 27.56 mil), 0.8mm (namely 31.5 mil) and 1mm (namely 38.98 mil).
For example, referring to fig. 8, the minimum pitch of two adjacent pins is 27.56 mils and the maximum pitch is 38.98 mils.
The present application is described in detail below by way of examples and comparative examples.
Comparative example 1
Comparative example 1 employed a "+" pin arrangement, as shown in fig. 7, with two adjacent pins having a minimum pitch of 27.56 mils and a maximum pitch of 38.98 mils.
Example 1
Example 1 with the pin arrangement provided herein, as shown in fig. 8, two adjacent pins have a minimum pitch of 27.56 mils and a maximum pitch of 38.98 mils.
Comparative example 2
Comparative example 2 employed a flat-bottomed W-type pin arrangement, as shown in fig. 25, with two adjacent pins having a minimum pitch of 27.56 mils and a maximum pitch of 38.98 mils.
The Pad radius of the differential signal pins and the return ground pins is 7 mils.
Simulations were performed under the same dimensions, lamination conditions to verify the signal integrity of the pin arrangement of the present application and the "+" pin arrangement, flat bottom W-type pin arrangement.
Crosstalk was simulated for three different types of pin distributions using ANSYS. The differential signal pins are simulated by adopting a coaxial port mode. In the mode of the through hole 10-layer PCB, adjacent differential signal pin crosstalk values are compared under the same lamination scene.
The lamination information is shown in table 1 below.
Referring to fig. 7, the "+" pin arrangement is a symmetrical structure, and there is crosstalk of the differential signal pins 1N to 2N, crosstalk of 1P to 2P, and crosstalk of 1P to 2N.
As shown in fig. 9, the crosstalk results of the differential signal pins 1N to 2N and 1P to 2P of the comparative example 1, specifically, -21.7137dB, are shown in the near-end crosstalk at 8GHz (pcie 4.0) scenario.
As shown in fig. 10, the far-end crosstalk is a crosstalk result of the differential signal pins 1N to 2N and 1P to 2P of the comparative example 1, specifically, -19.9905dB, in the 8GHz (pcie 4.0) scenario.
As shown in fig. 11, the crosstalk results of the differential signal pins 1N to 2N and 1P to 2P of the comparative example 1, specifically, -26.3855dB, are shown in the near-end crosstalk 4GHz (pcie 3.0) scenario.
As shown in fig. 12, the far-end crosstalk is a crosstalk result of the differential signal pins 1N to 2N and 1P to 2P of the comparative example 1, specifically, -26.0260dB, in a 4GHz (pcie 3.0) scenario.
As shown in fig. 13, the crosstalk results of the differential signal pins 1P to 2N of the comparative example 1, specifically, -24.4385dB, are the near-end crosstalk in the 8GHz (pcie 4.0) scenario.
As shown in fig. 14, the crosstalk results of the differential signal pins 1P to 2N of the comparative example 1, specifically, -22.5139dB, are the far-end crosstalk in the 8GHz (pcie 4.0) scenario.
As shown in fig. 15, the crosstalk results of the differential signal pins 1P to 2N of the comparative example 1, specifically, -29.0901dB, are the near-end crosstalk in the 4GHz (pcie 3.0) scenario.
As shown in fig. 16, the far-end crosstalk is a crosstalk result of the differential signal pins 1P to 2N of the comparative example 1, specifically, -28.5933dB, in a 4GHz (pcie 3.0) scenario.
Referring to fig. 8, the pin arrangement structure of embodiment 1 is not symmetrical, and under the same size, the crosstalk of the differential signal pins 1N to 2N and the crosstalk of 2N to 3P need to be considered.
As shown in fig. 17, the crosstalk results of the differential signal pins 1N to 2N of the embodiment 1 are specifically-22.6145 dB for near-end crosstalk in the 8GHz (pcie 4.0) scenario.
As shown in fig. 18, the crosstalk results of the differential signal pins 1N to 2N of the embodiment 1 are specifically-21.1616 dB for far-end crosstalk in the 8GHz (pcie 4.0) scenario.
As shown in fig. 19, the crosstalk results of the differential signal pins 1N to 2N of the embodiment 1 are specifically-27.8168 dB for near-end crosstalk in the 4GHz (pcie 3.0) scenario.
As shown in fig. 20, the crosstalk results of the differential signal pins 1N to 2N of the embodiment 1 are specifically-27.5516 dB for far-end crosstalk in the 4GHz (pcie 3.0) scenario.
As shown in fig. 21, the crosstalk results of the differential signal pins 2N to 3P of the embodiment 1 are specifically-29.9095 dB for near-end crosstalk in the 8GHz (pcie 4.0) scenario.
As shown in fig. 22, the crosstalk results of the differential signal pins 2N to 3P of the embodiment 1 are specifically-28.2050 dB for far-end crosstalk in the 8GHz (pcie 4.0) scenario.
As shown in fig. 23, the crosstalk results of the differential signal pins 2N to 3P of the embodiment 1 are specifically-34.9978 dB for near-end crosstalk in a 4GHz (pcie 3.0) scenario.
As shown in fig. 24, the crosstalk result of the differential signal pin 2N to 3P of embodiment 1 is specifically-34.5378 dB in the 4GHz (pcie 3.0) scenario.
Referring to the pin arrangement structure of comparative example 2 shown in fig. 25, crosstalk of differential signal pins 1P to 2N should be considered at the same size.
Referring to fig. 26, the crosstalk results of the differential signal pins 1P to 2N of comparative example 2 are-25.098 dB and-29.9221 dB in order, for near-end crosstalk in the 8GHz (pcie 4.0) and 4GHz (pcie 3.0) scenarios.
Referring to fig. 27, the crosstalk results of the differential signal pins 1P to 2N of comparative example 2 are-23.4118 dB and-29.4589 dB in order, for far-end crosstalk in the 8GHz (pcie 4.0) and 4GHz (pcie 3.0) scenarios.
The simulation results are summarized in table 2.
Where NEXT represents the near end, FEXT represents the far end, PCIe represents Peripheral Component Interconnect express.
As can be seen from the table, the pin arrangement of embodiment 1 has less far-end crosstalk and less near-end crosstalk than the "+" pin arrangement.
In the context of pcie 4.0:
near-end crosstalk of a 27.56mil pin was nearly 1dB improved, with near-end crosstalk improved by about 1.1 dB.
Near-end crosstalk of a pin of adjacent size 38.98mil is nearly 4.5dB improved, and far-end crosstalk is improved by about 5.7 dB.
In the context of pcie 3.0:
near-end crosstalk of a 27.56mil pin was approximately 1.4dB improved, with near-end crosstalk improved by about 1.5 dB.
Near-end crosstalk of a pin of adjacent size 38.98mil is nearly 5.9dB improved, and far-end crosstalk is improved by about 5.9 dB.
As can be seen from the table, the pin arrangement of example 1 has less far-end crosstalk and less near-end crosstalk than the flat-bottomed W-shaped pin arrangement.
In the context of pcie 4.0:
near-end crosstalk of a pin of 38.98mil adjacent size improved by approximately 4.9dB, and far-end crosstalk improved by approximately 4.8 dB.
In the context of pcie 3.0:
near-end crosstalk of a pin of adjacent size 38.98mil improved by approximately 5.0dB, and far-end crosstalk improved by approximately 5.0 dB.
Therefore, according to the pin arrangement structure, the reflow ground pins can meet the signal integrity of the high-speed differential signals on the premise of not meeting the symmetrical distribution, and even the crosstalk is smaller than the scene of "+" differential signal pin arrangement.
The pin arrangement structure enables the chip to be more convenient when pins of the high-speed differential signals are arranged, and the pin arrangement structure is not limited to horizontal and vertical directions.
In the description of the present application, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of description of the present application and simplification of the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
It should be noted that in this application, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is merely a specific embodiment of the application to enable one skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.