Disclosure of Invention
In order to solve at least one technical problem, the present invention provides a method, an apparatus and a storage medium for testing a chip, wherein adjacent read-write units are combined to form a larger super unit as a combined unit for each test. The super unit consists of a plurality of read-write units, and is used as a new read-write unit for testing. The testing method can more accurately locate the position where the error possibly occurs, improves testing efficiency and accuracy, and provides more comprehensive testing coverage.
A method of chip testing, comprising:
testing individual data units;
setting a test unit group according to a factory brand, wherein the test unit group comprises N data units;
setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist among the data units according to a test result of the test scheme;
the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group.
Preferably, the method further comprises:
m is less than or equal to N, when M=N, each test unit is only tested by one-time writing and reading;
and predicting M and N according to factory brands and fault big data.
Preferably, the method defined by N is the minimum interval between two adjacent error materials in the statistics of the same model chip.
Preferably, the setting of the test scheme according to the capacity of the chip and the test unit group includes:
n data units form a test unit group, each data unit is set as M test jump widths, and all readable and writable units of all LPDDR are covered; where N represents the set of possible cells that interfere with each other, or LPDDR allows a single instruction maximum where continuity can be written/read at a time, and M represents the distance that is statistically the most likely to interfere with each other physically.
Preferably, where N may be obtained from the recommended value of the factory brand, or a multiple of the recommended value, typically the maximum range that can be covered by a single instruction that is continuously writable.
Preferably, the minimum distance of the erroneous data in which the M value is set according to the maximum ratio of occurrence intervals of past read-write errors.
A chip testing system, the system comprising:
a first test unit for testing a single data unit;
the combination unit is used for setting a test unit group according to a factory brand, wherein the test unit group comprises N data units;
the second test unit is used for setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist between the data units according to the test result of the test scheme;
the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group.
A computer device comprising a memory and a processor, the memory having a computer program stored thereon, the processor implementing a method of chip testing as described above when executing the computer program;
the method for testing the chip comprises the following steps: testing individual data units;
setting a test unit group according to a factory brand, wherein the test unit group comprises N data units;
setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist among the data units according to the test result of the test scheme;
the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group.
A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement a method of chip testing as described above;
the method for testing the chip comprises the following steps: testing individual data units;
setting a test unit group according to a factory brand, wherein the test unit group comprises N data units;
setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist among the data units according to the test result of the test scheme;
the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group.
The invention is realized by testing a single data unit; setting a test unit group according to a factory brand, wherein the test unit group comprises N data units; setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist among the data units according to the test result of the test scheme; the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group. The test efficiency is improved, more errors can be captured in a single test by combining a plurality of read-write units into a super unit for test, and the test efficiency is improved. Accurately locating the error position: by considering the interference of adjacent units, the position where errors possibly occur can be more accurately positioned, and rapid fault detection and repair can be facilitated. Comprehensive test coverage: by testing the superunit, more combinations of read and write units can be covered, providing more comprehensive test coverage. The test accuracy is improved: by adopting the super unit as the test unit, the error caused by adjacent position interference can be reduced, and the accuracy of the test result is improved.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
According to the invention, a test unit group is set according to a factory brand, and the test unit group comprises N data units; setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist among the data units according to the test result of the test scheme; the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group. The test efficiency is improved, more errors can be captured in a single test by combining a plurality of read-write units into a super unit for test, and the test efficiency is improved. Accurately locating the error position: by considering the interference of adjacent units, the position where errors possibly occur can be more accurately positioned, rapid fault detection and repair can be facilitated, more read-write unit combinations are covered, and more comprehensive test coverage is provided. The test accuracy is improved, errors caused by adjacent position interference are reduced, and the accuracy of test results is improved.
Example 1
A method of chip testing, comprising:
testing individual data units;
a single data unit is used to store data, supporting both read data and write data, but in the read-write unit of the LPDDR. The invention judges whether the data unit has errors or not by testing the single data unit.
Setting a test unit group according to a factory brand, wherein the test unit group comprises N data units;
the sizes of the unit groups are flexibly set according to the factory brands, so that the chip test can be more targeted.
Setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist among the data units according to the test result of the test scheme;
the chip capacity=the number of units×the number of data lines, and the different chip capacities and sizes of the test unit groups determine the different test schemes.
In the internal cell design, the LPDD has a position disturbance with other cells in the vicinity of adjacent positions or in intermittent positions, and the disturbance occurs when writing or reading to the physically nearby positions continuously, but the error occurs only when writing to a plurality of continuous cells or when reading from a plurality of continuous cells, based on which the reading and writing of the LPDDR test takes 32bits (or 64 bits) as a reading and writing unit, and by collecting the data of the whole group when the reading and writing occur, the formed reading and writing unit "group" forms a larger super words as a combined unit for each test, and the combined unit is formed by a plurality of reading and writing units as a new reading and writing unit.
In some cases, a larger super words group may also be formed by collecting data from at least one unit before and after the occurrence of a read/write, and forming a read/write unit "group" as a combined unit for each test.
The first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group.
The invention randomly sets a first test starting point x, then calculates the stride M of forward jump test according to the capacity of the chip and the unit groups, and starts a second round of chip test from x+M after testing M unit groups. In chip design, in addition to the functional requirements, the most important is the performance requirements of the chip data transmission, which is also a very important parameter of the chip. The read-write performance test in the current chip verification is generally carried out at important chip design nodes, the main process is based on a simulation environment, a specific amount of data is sent through a test case, then a carrier wave shape is downloaded, and the time for manually calculating the data is spent, so that the bandwidth of a corresponding interface is estimated. However, with the rapid increase of the chip scale, the functional modules of the chip are more and more complex, and interface protocols between the modules, such as apb protocol, pcie protocol, ddr protocol, mbus protocol, etc., are more and more complex, and the conventional read-write performance test method consumes a great deal of time and effort of engineers, and when the design of the modules is changed, visual performance data cannot be timely given. The invention successively tests the failure of the LPDDR by setting a test starting point x and setting a test step length M until all data units are traversed.
Preferably, the method further comprises:
m is less than or equal to N, when M=N, each test unit is only tested by one-time writing and reading;
and predicting M and N according to factory brands and fault big data.
As the complexity of the chip is higher, more and more modules are inside the chip, the manufacturing process is more and more advanced, the corresponding failure modes are more and more, and how to test the whole chip completely and effectively, the proportion that needs to be considered in the design process is more and more. And the complexity of chips of different factory brands is different, and the modules are also different, so that the corresponding test schemes are also different, and M and N are predicted according to different factory brands and fault big data. How to ensure that the chip subjected to design process reaches the design target, how to ensure that the manufactured chip reaches the required yield, and how to ensure the quality and effectiveness of the test itself, so as to provide the customer with a product conforming to the product specification and qualified quality, which all require that the test scheme must be considered at the first time of design start. There are many methods of chip testing, for example: the SCAN is used for detecting whether the logic function of the chip is correct. During DFT design, the design compiler is used for inserting ScanChain, and then the ATPG is used for automatically generating the SCAN test vector. During SCAN test, the SCAN Shift mode is first entered, the ATE loads pattern to the register, and then the result is captured through the SCAN Capture mode. And when the next Shift mode is entered, outputting the result to ATE for comparison.
The Boundary SCAN is used to detect whether the chip pin functions correctly. Similar to SCAN, the Boundary SCAN is controlled by inserting a Boundary register between IO pins and using a JTAG interface to monitor the input/output status of the pins.
The number of memory tests is large, because the chip often integrates various types of memories (e.g., ROM/RAM/Flash), BIST (build-In self test) logic is often added In advance for the design for memory self-test In order to test memory read-write and storage functions. The chip enters various BIST functions through special pin configuration, and the BIST module feeds test results back to the Tester after the self-test is completed. The ROM checks the stored content for correctness by reading the data and performing a CRC check. In addition to detecting Read-Write and storage functions, some tests cover the description function of deep sleep and Margin Write/Read, etc. The Embedded Flash is required to test the erasing function in addition to the normal read-write and storage functions.
In the embodiment of the invention, read-write test is mainly performed, and ROM and RAM are tested. ROM code point data reading process: the address is written and the block head address of the specific data of the ROM is intended to be read. Setting voltage and configuration pins, entering ROM mode, and preparing to read data. Under the analog clock, ROM code point data is gradually shifted and output through the parallel IO port. Repeating the steps until all ROM code point data are read.
Preferably, the method defined by N is the minimum interval between two adjacent error materials in the statistics of the same model chip.
If N is 3, which means that a cell group has 3 data units, it is indicated that adjacent erroneous data may occur in 3 data units.
Preferably, the setting of the test scheme according to the capacity of the chip and the test unit group includes:
n data units form a test unit group, each data unit is set as M test jump widths, and all readable and writable units of all LPDDR are covered; where N represents the set of possible cells that interfere with each other, or LPDDR allows a single instruction maximum where continuity can be written/read at a time, and M represents the distance that is statistically the most likely to interfere with each other physically.
After the values of M and N are set, chip test is performed, so that all the read-write units of the LPDDR can be covered, and the test time of the LPDDR can be greatly shortened.
Preferably, where N may be obtained from the recommended value of the factory brand, or a multiple of the recommended value, typically the maximum range that can be covered by a single instruction that is continuously writable.
N is the number of data units of the test unit group, the number of data units of the test unit group of different factory brands is different, and the number of data units of the test unit group can be set according to the recommended value of the factory brands or the multiple of the recommended value.
Preferably, the minimum distance of the erroneous data in which the M value is set according to the maximum ratio of occurrence intervals of past read-write errors.
The stride M is the minimum distance of error data set according to the maximum ratio of the occurrence intermittent intervals of LPDDR read/write errors of different factory brands in the database.
In order to shorten the test time and improve the chip yield, the invention provides an algorithm for predicting the stride by combining the initial position of the test point. In order to avoid testing the same data units, the invention sets to start the next round of test from the point x+M, thereby completing the test of all the data units of the LPDDR, further effectively reducing the scale of single test points, effectively shortening the test time of the chip, and further shortening the design period of the chip.
Example 2
A chip testing system, the system comprising:
a first test unit for testing a single data unit;
the combination unit is used for setting a test unit group according to a factory brand, wherein the test unit group comprises N data units;
the second test unit is used for setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist between the data units according to the test result of the test scheme;
the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group.
The invention can improve the test efficiency when performing the LPDDR test: through combining a plurality of read-write units into a super unit for testing, more errors can be captured in a single test, and the test efficiency is improved. Accurately locating the error position: by considering the interference of adjacent units, the position where errors possibly occur can be more accurately positioned, and rapid fault detection and repair can be facilitated. Comprehensive test coverage: by testing the superunit, more combinations of read and write units can be covered, providing more comprehensive test coverage. The test accuracy is improved: by adopting the super unit as the test unit, the error caused by adjacent position interference can be reduced, and the accuracy of the test result is improved.
Example 3
A computer device comprising a memory and a processor, the memory having a computer program stored thereon, the processor implementing a method of chip testing as described above when executing the computer program;
the method for testing the chip comprises the following steps: testing individual data units;
setting a test unit group according to a factory brand, wherein the test unit group comprises N data units;
setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist among the data units according to the test result of the test scheme;
the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group.
Example 4
A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement a method of chip testing as described above;
the method for testing the chip comprises the following steps: testing individual data units;
setting a test unit group according to a factory brand, wherein the test unit group comprises N data units;
setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist among the data units according to the test result of the test scheme;
the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group.
Referring to fig. 2, fig. 2 is a schematic hardware structure diagram of a chip testing device according to an embodiment of the present application.
The computer device 2 comprises a processor 21, a memory 22, input means 23, output means 24. The processor 21, memory 22, input device 23, and output device 24 are coupled by connectors, including various interfaces, transmission lines or buses, etc., as not limited in this application. It should be understood that in various embodiments of the present application, coupled is intended to mean interconnected by a particular means, including directly or indirectly through other devices, e.g., through various interfaces, transmission lines, buses, etc.
The processor 21 may be one or more graphics processors (graphics processing unit, GPUs), which may be single-core GPUs or multi-core GPUs in the case where the processor 21 is a GPU. Alternatively, the processor 21 may be a processor group formed by a plurality of GPUs, and the plurality of processors are coupled to each other through one or more buses. In the alternative, the processor may be another type of processor, and the embodiment of the present application is not limited.
Memory 22 may be used to store computer program instructions as well as various types of computer program code for performing aspects of the present application. Optionally, the memory includes, but is not limited to, a random access memory (random access memory, RAM), a read-only memory (ROM), an erasable programmable read-only memory (erasable programmable read only memory, EPROM), or a portable read-only memory (compact disc read-only memory, CD-ROM) for associated instructions and data.
The input means 23 are for inputting data and/or signals and the output means 24 are for outputting data and/or signals. The output device 23 and the input device 24 may be separate devices or may be an integral device.
It will be appreciated that in embodiments of the present application, the memory 22 may be used to store not only relevant instructions, but that embodiments of the present application are not limited to the data specifically stored in the memory.
It will be appreciated that figure 2 shows only a simplified design of a computer device. In practical applications, the electronic device may further include other necessary components, including but not limited to any number of input/output devices, processors, memories, etc., and all video parsing devices capable of implementing the embodiments of the present application are within the scope of protection of the present application.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein. It will be further apparent to those skilled in the art that the descriptions of the various embodiments herein are provided with emphasis, and that the same or similar parts may not be explicitly described in different embodiments for the sake of convenience and brevity of description, and thus, parts not described in one embodiment or in detail may be referred to in the description of other embodiments.
In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital versatile disk (digital versatiledisc, DVD)), or a semiconductor medium, etc.
The invention is realized by testing a single data unit; setting a test unit group according to a factory brand, wherein the test unit group comprises N data units; setting a test scheme according to the capacity of the chip and the test unit group, and acquiring whether interference faults exist among the data units according to the test result of the test scheme; the first test starting point is x, the step length M of the forward jump test of the data unit is calculated, the next test starting point is x+M, and the test unit is the test unit group. The test efficiency is improved, more errors can be captured in a single test by combining a plurality of read-write units into a super unit for test, and the test efficiency is improved. Accurately locating the error position: by considering the interference of adjacent units, the position where errors possibly occur can be more accurately positioned, and rapid fault detection and repair can be facilitated. Comprehensive test coverage: by testing the superunit, more combinations of read and write units can be covered, providing more comprehensive test coverage. The test accuracy is improved: by adopting the super unit as the test unit, the error caused by adjacent position interference can be reduced, and the accuracy of the test result is improved.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.