Disclosure of Invention
Aiming at the technical problems existing in the prior art, the invention provides an all-digital clock generation circuit and an all-digital clock generation method.
According to a first aspect of the present invention, there is provided an all-digital clock generation circuit comprising a two-in-one multi-selector, an and gate, an exclusive-or gate, two D flip-flops and two configurable delay chains;
one input end of the AND gate is connected with an Enable signal end, the other input end of the AND gate is connected with the output end of the multi-selector, the output end of the AND gate is connected with the input end of a first configurable delay chain, the output end of the first configurable delay chain is connected with one input end of the exclusive-OR gate, the other input end of the exclusive-OR gate is respectively connected with the output end of the second configurable delay chain, the other input end of the exclusive-OR gate is connected with the 1 input end of the multi-selector through a first inverter, the 0 input end of the multi-selector is connected with a start starting signal, the gating end of the multi-selector is connected with the Q end of a first D trigger, the first D trigger is characterized in that a D end of the first D trigger is connected with a 1'b1 signal, the 1' b1 signal is a high level signal, the second configurable delay chain is connected with a Q end of the second D trigger, the Q end is also connected with the D end through an inverter, a Reset end of the first D trigger and a Reset end of the second D trigger are both connected with external Reset signals, a clock control end of the first D trigger and a clock control end of the second D trigger are both connected with an output end of the second configurable delay chain, and the Q end of the second D trigger outputs a periodic clock signal through a buffer to serve as a clock source of a chip.
On the basis of the technical scheme, the invention can also make the following improvements.
Optionally, the first configurable delay chain and the second configurable delay chain each include a base delay chain module and a plurality of configurable delay chain modules, each of the configurable delay chain modules is built at the 1 input end of a corresponding one of the two-out-of-one multi-selector, the plurality of multi-selectors are sequentially connected, the base delay chain is connected before the first multi-selector, signals enter the base delay chain, and after passing through the plurality of multi-selectors, the signals after delay are output through the last multi-selector.
Optionally, the multiple gates are used to adjust the period of the output clock signal by opening or closing the configurable delay chain module at the 1 input end of each multiple selector to realize the combination of the opening or closing states of the multiple configurable delay chain modules.
Optionally, the all-digital clock generating circuit and the digital chip are arranged on the same silicon chip and are in the same PVT environment, the all-digital clock generating circuit is composed of CMOS transistors, and the working characteristics of the transistors are changed along with the change of the PVT environment of the digital chip, so that the frequency of an output clock signal is changed, and the PVT function of tracking the digital chip is realized.
According to a second aspect of the present invention, there is provided an all-digital clock generation method, comprising:
the Enable signal is an Enable signal, when the Enable signal is 0, the whole circuit does not work, and when the Enable signal is 1, the circuit enters a waiting response state;
the Reset signal is an asynchronous Reset signal of the circuit, and when the Enable is 1, reset is carried out firstly, so that the initial value Q ends of the two D triggers are changed into 0;
when the circuit is reset, the Start signal is kept to be 0 and then sent to 1, and the circuit starts to work;
the method comprises the steps that 1 fed by a Start signal firstly passes through the 0 input end of a two-out-of-one multi-selector, then passes through an AND gate, a configurable delay chain and an exclusive OR gate, so that clock input ends of a first D trigger and a second D trigger generate a rising edge signal, the Q end of the first D trigger is set to be 1, at the moment, the two-out-of-one multi-selector gates a 1 port, and meanwhile, the 0 signal of the Q end of the second D trigger is fed into the D end through an inverter, and then the Q end of the second D trigger is set to be 1 again after rising edge comes;
the circuit forms a loop to generate a periodic clock signal at the clk_out port of the second D flip-flop.
According to the all-digital clock generation circuit and the all-digital clock generation method, the digital circuit can generate the periodical clock signal, and the clock source is provided for the digital chip, wherein the configurable delay chain can adjust the period of the clock signal, and after the level of the configurable delay chain is set, the clock module can also adjust the period of the clock signal according to the change of PVT of the chip. The all-digital clock generation module has the advantages of simple structure, small area and low power consumption, can provide a clock source for a chip, and can also improve the reliability of the chip. Particularly in a chip powered by near-threshold voltage, the all-digital generation module can well track PVT variation on the chip, so that the chip can always work stably and reliably.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. In addition, the technical features of each embodiment or the single embodiment provided by the invention can be combined with each other at will to form a feasible technical scheme, and the combination is not limited by the sequence of steps and/or the structural composition mode, but is necessarily based on the fact that a person of ordinary skill in the art can realize the combination, and when the technical scheme is contradictory or can not realize, the combination of the technical scheme is not considered to exist and is not within the protection scope of the invention claimed.
In the face of reliability challenges of chips at near-threshold voltages, researchers currently propose a series of solutions such as near-threshold digital standard cell library design, timing error detection and correction circuit design, low-voltage memory cell design, and PVT (process bias, voltage, temperature) sensor design. Compared with the methods, the invention provides a novel solution, and a clock capable of tracking PVT fluctuation on a chip is generated by adopting an all-digital circuit mode so as to improve the reliability of the chip, thereby reducing the design margin and improving the performance of the chip.
Fig. 1 provides an all-digital clock generation circuit of the present invention, comprising a two-in-one multi-selector, an and gate, an exclusive-or gate, two D flip-flops, and two configurable delay chains.
One input end of the AND gate is connected with an Enable signal end, the other input end of the AND gate is connected with the output end of the multi-selector, the output end of the AND gate is connected with the input end of a first configurable delay chain, the output end of the first configurable delay chain is connected with one input end of the exclusive-OR gate, the other input end of the exclusive-OR gate is respectively connected with the output end of a second configurable delay chain, the 0 input end of the multi-selector is connected with a start starting signal, the gating end of the multi-selector is connected with the Q end of a first D trigger, the D end of the first D trigger is connected with a 1'b1 signal, the 1' b1 signal is a high level signal, the second configurable delay chain is connected with the Q end of a second D trigger, the Q end is also connected with the D end through an inverter, the Reset end of the first D trigger and the Reset end of the second D trigger are both connected with external Reset signals, the gating end of the first D trigger and the Reset end of the second D trigger are connected with the Q end of the second D trigger, and the clock end of the second D trigger is connected with the Q end of the second clock chain.
It will be appreciated that the all-digital clock generation circuit proposed in fig. 1 comprises a configurable delay chain, for which there are a total of 2n And the delay chain time length can be finely adjusted by adjusting the input of the configuration bit.
Other modules: besides the configurable delay chain, other modules consist of 2D flip-flops, 1 two-for-one multi-selector, 1 AND gate, 1 exclusive OR gate, 2 inverters and 1 output buffer, and by inputting proper excitation, these components and the configurable delay chain can generate corresponding clock signals.
Referring to fig. 2, the first configurable delay chain and the second configurable delay chain each include a base delay chain module and a plurality of configurable delay chain modules, each configurable delay chain module is built at the 1 input end of a corresponding one of two-to-one multi-selector, the plurality of multi-selectors are sequentially connected, the base delay chain is connected before the first multi-selector, signals enter the base delay chain, and after passing through the plurality of multi-selectors, delayed signals are output through the last multi-selector.
The multiple gates realize the combination of the on or off states of the multiple configurable delay chain modules by opening or closing the configurable delay chain modules of the 1 input end of each multiple selector. Referring to fig. 2, the configurable delay chain includes 5 fixed delay chain modules, which are divided into a basic delay chain module and 4 configurable delay chain modules, and if T is set as the delay length of the delay chain, there is a relationship that the delay of the T delay chain 3 is equal to the delay of the 2*T delay chain 2 is equal to the delay of the 4*T delay chain 1 is equal to the delay of the 8*T delay chain 0; and 4 two-in-one multi-selector, which can select different delay chain modules and perform permutation and combination. Therefore, the configurable delay chain can realize 16 different levels of delay time lengths, interval units of adjacent delay time lengths are consistent, and the period of an output clock signal can be adjusted.
The all-digital clock generation circuit and the digital chip are arranged on the same silicon chip and are in the same PVT environment, the all-digital clock generation circuit is composed of digital unit transistors, and the working characteristics of the transistors are changed along with the change of the PVT environment of the digital chip, so that the frequency of an output clock signal is changed, and the PVT function of tracking the digital chip is realized.
Referring to fig. 3, the method for generating the all-digital clock based on the all-digital clock generating circuit of the invention comprises the following steps:
step 1, enabling an Enable signal, wherein when the Enable signal is 0, the whole circuit does not work, and when the Enable signal is 1, the circuit enters a waiting response state;
step 2, reset signals are asynchronous reset signals of the circuit, when Enable is 1, reset is carried out firstly, and the initial value Q ends of two D triggers are changed into 0;
step 3, after the circuit is reset, the Start signal is kept to be 0 and then sent to 1, and the circuit starts to work;
step 4, the 1 sent by the start signal firstly passes through the 0 input end of the two-in-one multi-selector, then passes through an AND gate, a configurable delay chain and an exclusive OR gate, so that clock input ends of the first D trigger and the second D trigger generate a rising edge signal, the Q end of the first D trigger is set to be 1, at the moment, the two-in-one multi-selector gates the 1 port, and meanwhile, the 0 signal of the Q end of the second D trigger is sent to the D end through an inverter, and then the Q end of the second D trigger is set to be 1 again after the rising edge comes, so that the AND gate does not work;
step 5, repeating steps 2 to 4, the circuit forming a loop, thereby generating a periodic clock signal at the clk_out port of the second D flip-flop.
The working principle of the all-digital clock generating circuit is as follows:
(1) During design, the initial value of the delay chain is 1000, namely when the level is 8, through matching the chip critical path, the clock period generated by the clock generating circuit is just slightly larger than the delay of the chip critical path. In addition, in the layout wiring, the clock generation circuit is placed close to the critical path of the chip.
(2) When the chip actually works, the initial value of the delay chain of the clock generating circuit is set to be 1000, then the clock generating circuit is started according to the description in the invention content, and then fine adjustment is carried out according to the working state of the chip, so that the generated clock frequency is optimal.
(3) The clock generating circuit is composed of digital units, so that the output clock frequency can be adaptively changed along with the process deviation, voltage and temperature on the chip, the tracking of PVT state on the chip can be realized, the chip can always work stably, and the working reliability of the chip is improved.
The invention provides an all-digital clock generation circuit and an all-digital clock generation method, which can generate a periodic clock signal through the cooperation of a two-in-one multi-selector, an AND gate, an exclusive OR gate, two D flip-flops and two configurable delay chains, wherein the configurable delay chains can adjust the period of the clock signal and can adjust the frequency of the clock signal according to the PVT change of a chip. The all-digital clock generation module has the advantages of simple structure, small area and low power consumption, can provide a clock source for a chip, and can also improve the reliability of the chip. Particularly in a chip powered by near-threshold voltage, the all-digital generation module can well track PVT variation on the chip, so that the chip can always work stably and reliably.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.