技术领域Technical field
本发明属于LED制备工艺技术领域，具体涉及一种高光效LED外延片及其制备方法、LED芯片。The invention belongs to the technical field of LED preparation technology, and specifically relates to a high-light-efficiency LED epitaxial wafer, a preparation method thereof, and an LED chip.
背景技术Background technique
目前，LED发光效率已经达到相当高的水平。在所有需要单色光的应用中，LED的性能已优于经过过滤的白炽灯。由于较高的发光效率和可调的禁带宽度（0.7～3.4 eV），InGaN 基 LED 在固态照明领域已吸引了研究人员们的大量关注。At present, LED luminous efficiency has reached a very high level. LEDs already outperform filtered incandescent lamps in all applications requiring monochromatic light. Due to their high luminous efficiency and adjustable band gap (0.7-3.4 eV), InGaN-based LEDs have attracted a lot of attention from researchers in the field of solid-state lighting.
在InGaN/GaN异质结构中，还存在极化的另一种类型，即压电极化，由于自发极化强度较弱，压电极化在InGaN/GaN LED 中起着更为重要作用，此压电场是由晶格失配（InN与GaN之间失配约为11%）导致异质界面产生极大应力而造成阳离子子晶格和阴离子子晶格移动引起的。对于传统InGaN/GaN量子阱LED来说，当有源区的失配应力导致压电极强度过高时，会对发光二极管造成诸多不良影响。强极化电场带来的主要问题有：第一，从某种程度上来说，InGaN量子阱有源区的巨大压电场会导致能带弯曲，造成有效禁带宽度变窄，发射波长红移；第二，InGaN 量子阱有源区的巨大压电场会造成多量子阱层的极化效应，导致平台量子阱中的电子和空穴产生空间分离，电子和空穴波函数重叠减少，振子强度减弱，辐射复合效率降低，从而致使 LED 内量子效率下降，降低发光二极管的发光效率，因此，需要一种新的技术方案加以改善。In the InGaN/GaN heterostructure, there is another type of polarization, namely piezoelectric polarization. Since the intensity of spontaneous polarization is weak, piezoelectric polarization plays a more important role in InGaN/GaN LEDs. This piezoelectric field is caused by the lattice mismatch (the mismatch between InN and GaN is about 11%), which causes great stress at the heterogeneous interface, causing the cation sublattice and anion sublattice to move. For traditional InGaN/GaN quantum well LEDs, when the mismatch stress in the active area causes the piezoelectrode strength to be too high, it will cause many adverse effects on the light-emitting diode. The main problems caused by strong polarization electric fields are: first, to some extent, the huge piezoelectric field in the active region of the InGaN quantum well will cause the energy band to bend, resulting in a narrowing of the effective band gap and a red shift of the emission wavelength. ; Second, the huge piezoelectric field in the active region of the InGaN quantum well will cause the polarization effect of the multi-quantum well layer, resulting in spatial separation of electrons and holes in the platform quantum well, reducing the overlap of the electron and hole wave functions, and oscillator The intensity weakens and the radiation recombination efficiency decreases, which causes the internal quantum efficiency of the LED to decrease and the luminous efficiency of the light-emitting diode. Therefore, a new technical solution is needed to improve it.
发明内容Contents of the invention
针对上述现有技术中的问题，本发明提供了一种高光效LED外延片及其制备方法、LED芯片，从而有效释放有源区的失配应力，防止能带弯曲并降低多量子阱层的极化效应，提升发光二极管的发光效率。In view of the above-mentioned problems in the prior art, the present invention provides a high-light-efficiency LED epitaxial wafer, a preparation method thereof, and an LED chip, thereby effectively releasing the mismatch stress in the active region, preventing energy band bending, and reducing the stress of the multi-quantum well layer. Polarization effect improves the luminous efficiency of light-emitting diodes.
本发明通过以下技术方案实施：一种高光效LED外延片，包括衬底及依次沉积在所述衬底上的缓冲层、非掺杂GaN层、n型GaN层、应力释放层、多量子阱层、电子阻挡层和P型GaN层，其中，所述应力释放层包括依次沉积在所述n型GaN层上的CrxAl1-xN层、CryGa1-yN/InGaN超晶格层，所述CryGa1-yN/InGaN超晶格层包括周期性交替层叠的CryGa1-yN层和InGaN层。The present invention is implemented through the following technical solutions: a high-light-efficiency LED epitaxial wafer, including a substrate and a buffer layer, an undoped GaN layer, an n-type GaN layer, a stress release layer, and a multi-quantum well deposited sequentially on the substrate. layer, an electron blocking layer and a P- type GaN layer, wherein the stress relief layer includesaCr The Cy Ga1-y N/InGaN superlattice layer includes periodically alternately stacked Cy Ga1-y N layers and InGaN layers.
进一步的，所述CrxAl1-xN层厚度为1nm～100nm，所述CryGa1-yN层的厚度为5nm～500nm，所述InGaN层的厚度为0.5nm～10nm。Further, the thickness of the Crx Al1-x N layer is 1 nm to 100 nm, the thickness of the Cry Ga1-y N layer is 5 nm to 500 nm, and the thickness of the InGaN layer is 0.5 nm to 10 nm.
进一步的，所述CrxAl1-xN层Cr组分为0.01～0.5，即x符合0.01～0.5，所述CryGa1-yN层Cr组分为0.01～0.1，即y符合0.01～0.1。Further, the Cr composition of the Crx Al1-x N layer is 0.01 to 0.5, that is, x conforms to 0.01 to 0.5, and the Cr composition of the Cry Ga1-y N layer is 0.01 to 0.1, that is, y conforms to 0.01 ~0.1.
进一步的，所述CryGa1-yN/InGaN超晶格层的周期数为1~20。Further, the period number of the Cry Ga1-y N/InGaN superlattice layer is 1 to 20.
进一步的，所述衬底为蓝宝石衬底、SiO2蓝宝石复合衬底、硅衬底、碳化硅衬底、氮化镓衬底、氧化锌衬底中的任一种；Further, the substrate is any one of a sapphire substrate, a SiO2 sapphire composite substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a zinc oxide substrate;
所述缓冲层为AlN层或GaN层；The buffer layer is an AlN layer or a GaN layer;
所述多量子阱层包括周期性交替堆叠的InGaN量子阱层和AlGaN量子垒层；The multiple quantum well layer includes periodically alternately stacked InGaN quantum well layers and AlGaN quantum barrier layers;
所述电子阻挡层为AlInGaN层。The electron blocking layer is an AlInGaN layer.
本发明还提供了一种高光效LED外延片的制备方法，用于制备上述的高光效LED外延片，所述高光效LED外延片的制备方法包括：The present invention also provides a method for preparing a high-light-efficiency LED epitaxial wafer, which is used to prepare the above-mentioned high-light-efficiency LED epitaxial wafer. The method for preparing a high-light-efficiency LED epitaxial wafer includes:
提供一衬底；provide a substrate;
在所述衬底上依次沉积缓冲层、非掺杂GaN层及、n型GaN层、应力释放层、多量子阱层、电子阻挡层和P型GaN层；sequentially depositing a buffer layer, an undoped GaN layer, an n-type GaN layer, a stress relief layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate;
其中，所述应力释放层包括依次沉积在所述n型GaN层上的CrxAl1-xN层、CryGa1-yN/InGaN超晶格层，所述CryGa1-yN/InGaN超晶格层包括周期性交替层叠的CryGa1-yN层和InGaN层。Wherein, the stress relief layer includes a Crx Al1-x N layer and a C y Ga1-y N/InGaN superlattice layer deposited sequentially on the n-type GaN layer. The CyGa1-y The N/InGaN superlattice layer includes periodically alternately stacked Cry Ga1-y N layers and InGaN layers.
进一步的，所述CrxAl1-xN层生长温度为900℃～1100℃，所述CryGa1-yN/InGaN超晶格层的生长温度为800℃～1000℃。Further, the growth temperature of the Crx Al1-x N layer is 900°C to 1100°C, and the growth temperature of the Cry Ga1-y N/InGaN superlattice layer is 800°C to 1000°C.
进一步的，所述应力释放层的生长压力为50torr～300torr。Further, the growth pressure of the stress relief layer is 50 torr to 300 torr.
进一步的，所述应力释放层的生长气氛为N2/NH3混合气，N2与NH3的流量体积比为2:3～3:2。Further, the growth atmosphere of the stress relief layer is N2 /NH3 mixed gas, and the flow volume ratio of N2 to NH3 is 2:3 to 3:2.
本发明还提供了一种LED芯片，包括上述的高光效LED外延片。The invention also provides an LED chip, including the above-mentioned high-light-efficiency LED epitaxial wafer.
本发明的有益效果是：通过在n型GaN层上沉积形成的应力释放层，以应力释放层中的CrxAl1-xN层引入压应力，以此缓解GaN外延层与衬底产生的张应力，引入的Cr成分可以降低晶轴扭转的势垒和应变驰豫，提升沉积外延层的晶体质量，以此提高发光二极管的电学性能；同时，交替堆叠CryGa1-yN/InGaN超晶格结构可以有效缓解因有源区中InGaN量子阱中的In含量较高InGaN阱与n型GaN之间存在较大的失配应力，提升电子空穴波函数的空间重叠度，可解决InGaN阱中的In组分并入难、晶体缺陷多和极化电场大等问题，防止能带弯曲并降低多量子阱层的极化效应，有效提高发光二极管的发光效率。The beneficial effects of the present invention are: by depositing a stress release layer on then -type GaN layer, compressive stress is introduced by theCr Tensile stress, the introduced Cr component can reduce the potential barrier and strain relaxation of crystal axis torsion, improve the crystal quality of the deposited epitaxial layer, thereby improving the electrical performance of the light-emitting diode; at the same time, alternately stack Cry Ga1-y N/InGaN The superlattice structure can effectively alleviate the large mismatch stress between the InGaN well and n-type GaN due to the high In content in the InGaN quantum well in the active area, and improve the spatial overlap of the electron-hole wave function, which can solve InGaN wells have problems such as difficulty in incorporating In components, many crystal defects, and large polarization electric fields. This prevents energy band bending and reduces the polarization effect of the multi-quantum well layer, effectively improving the luminous efficiency of light-emitting diodes.
附图说明Description of the drawings
图1为本发明实施例中高光效LED外延片的结构示意图。Figure 1 is a schematic structural diagram of a high-light-efficiency LED epitaxial wafer in an embodiment of the present invention.
图2为本发明实施例中高光效LED外延片的制备流程图；Figure 2 is a flow chart for the preparation of high-light-efficiency LED epitaxial wafers in an embodiment of the present invention;
附图说明：100-衬底、200-缓冲层、300-非掺杂GaN层、400-n型GaN层、500-应力释放层、510-CrxAl1-xN层、520-CryGa1-yN/InGaN超晶格结构、600-多量子阱层、700-电子阻挡层、800-P型GaN层。Description of the drawings: 100-substrate, 200-buffer layer, 300-undoped GaN layer, 400-n-type GaN layer, 500-stress release layer, 510-Crx Al1-x N layer, 520-Cry Ga1-y N/InGaN superlattice structure, 600-multiple quantum well layer, 700-electron blocking layer, 800-P-type GaN layer.
具体实施方式Detailed ways
下面针对说明书附图及实施例对本发明作进一步的详细描述。The present invention will be described in further detail below with reference to the accompanying drawings and examples.
需要说明的是，在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。It should be noted that in the present invention, unless otherwise clearly stated and limited, the terms "installation", "connection", "connection", "fixing" and other terms should be understood in a broad sense. For example, it can be a fixed connection or a fixed connection. It can be a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
实施例1Example 1
如图1所示，本实施例提供一种高光效LED外延片，包括衬底100及依次沉积在所述衬底100上的缓冲层200、非掺杂GaN层300、n型GaN层400、应力释放层500、多量子阱层600、电子阻挡层700和P型GaN层800，其中，所述应力释放层500包括依次沉积在所述n型GaN层400上的CrxAl1-xN层510、CryGa1-yN/InGaN超晶格层520，所述CryGa1-yN/InGaN超晶格层520包括周期性交替层叠的CryGa1-yN层和InGaN层。利用交替堆叠CryGa1-yN/InGaN超晶格结构，可以有效缓解因有源区中InGaN量子阱中的In含量较高InGaN阱与n型GaN之间存在较大的失配应力，提升电子空穴波函数的空间重叠度，防止能带弯曲并降低多量子阱层的极化效应，以此制成的发光二极管可获得良好的光效性能。As shown in Figure 1, this embodiment provides a high-light-efficiency LED epitaxial wafer, including a substrate 100 and a buffer layer 200, a non-doped GaN layer 300, and an n-type GaN layer 400 deposited on the substrate 100 in sequence. The stress relief layer 500, the multiple quantum well layer 600, the electron blocking layer 700 and the P-type GaN layer 800, wherein the stress relief layer 500 includes Crx Al1-x N deposited on the n-type GaN layer 400 in sequence. Layer 510, Cy Ga1-y N/InGaN superlattice layer 520 , the Cy Ga1-y N/InGaN superlattice layer 520 includes periodically alternately stacked Cy Ga1-y N layers and InGaN layer. The use of alternately stacked Cry Ga1-y N/InGaN superlattice structures can effectively alleviate the large mismatch stress between the InGaN quantum well and n-type GaN due to the high In content in the active area. By increasing the spatial overlap of the electron-hole wave function, preventing energy band bending and reducing the polarization effect of the multi-quantum well layer, the light-emitting diode made in this way can obtain good light efficiency performance.
本实施例还提供了一种高光效LED外延片的制备方法，用于制备上述的高光效LED外延片，包括以下步骤：This embodiment also provides a method for preparing a high-light-efficiency LED epitaxial wafer, which is used to prepare the above-mentioned high-light-efficiency LED epitaxial wafer, including the following steps:
S1：提供一衬底，衬底选用蓝宝石衬底，以此制成图形化衬底，由于蓝宝石是目前最常用的GaN基LED衬底材料，蓝宝石衬底具有制备工艺成熟、价格较低、易于清洗和处理，且高温下有很好的稳定性，以此作为后续工艺提供良好的作业条件；S1: Provide a substrate. The substrate is a sapphire substrate to make a patterned substrate. Since sapphire is currently the most commonly used GaN-based LED substrate material, the sapphire substrate has mature preparation technology, low price, and ease of use. Cleaning and processing, and has good stability under high temperature, which provides good operating conditions for subsequent processes;
S2：将衬底送入PVD设备中，在应用材料PVD中沉积AlN缓冲层，其厚度为15 nm，采用AlN缓冲层提供了与衬底取向相同的成核中心，释放了GaN和衬底之间的晶格失配产生的应力以及热膨胀系数失配所产生的热应力，进一步的生长提供了平整的成核表面，减少其成核生长的接触角使岛状生长的GaN晶粒在较小的厚度内能连成面，转变为二维外延生长；S2: The substrate is fed into the PVD equipment, and an AlN buffer layer is deposited in Applied Materials PVD with a thickness of 15 nm. The AlN buffer layer is used to provide a nucleation center with the same orientation as the substrate, releasing the gap between GaN and the substrate. The stress generated by the lattice mismatch and the thermal stress generated by the thermal expansion coefficient mismatch provide a flat nucleation surface for further growth, reducing the contact angle for nucleation growth and allowing the island-shaped GaN grains to grow in smaller sizes. The internal energy of the thickness connects into surfaces and transforms into two-dimensional epitaxial growth;
S3：采用中微A7 MOCVD(Metal-organic Chemical Vapor Deposition金属有机气相沉积，简称MOCVD)设备，高纯H2(氢气)、高纯N2(氮气)、高纯H2和高纯N2的混合气体中的一种作为载气，高纯NH3作为N源，三甲基镓(TMGa)及三乙基镓(TEGa)作为镓源，三甲基铟(TMIn)作为铟源，三甲基铝(TMAl)作为铝源，硅烷(SiH4)作为N型掺杂剂，二茂镁(CP2Mg)作为P型掺杂剂进行外延生长作业；S3: Using Zhongwei A7 MOCVD (Metal-organic Chemical Vapor Deposition, referred to as MOCVD) equipment, high-purity H2 (hydrogen), high-purity N2 (nitrogen), high-purity H2 and high-purity N2 One of the mixed gases is used as the carrier gas, high-purity NH3 is used as the N source, trimethylgallium (TMGa) and triethylgallium (TEGa) are used as the gallium source, trimethylindium (TMIn) is used as the indium source, and trimethylgallium (TMGa) is used as the indium source. Basic aluminum (TMAl) is used as the aluminum source, silane (SiH4 ) is used as the N-type dopant, and magnocene (CP2 Mg) is used as the P-type dopant for epitaxial growth;
将已镀完AlN缓冲层的蓝宝石衬底转入MOCVD中，在H2气氛进行预处理5min，处理温度为1100℃，再对蓝宝石衬底进行氮化处理，以此提升AlN缓冲层的晶体质量，并可有效提高后续沉积GaN外延层的晶体质量；The sapphire substrate that has been plated with the AlN buffer layer is transferred to MOCVD, and is pretreated in an H2 atmosphere for 5 minutes at a treatment temperature of 1100°C. The sapphire substrate is then nitrided to improve the crystal quality of the AlN buffer layer. , and can effectively improve the crystal quality of the subsequently deposited GaN epitaxial layer;
S4：在缓冲层上沉积非掺杂GaN层，其中非掺杂的GaN层生长温度为1100℃，压力150torr，厚度为2.5um；通过设置沉积生长条件，令非掺杂GaN层生长温度较高、压力较低，以此制备得到GaN的晶体质量较优，同时厚度随着GaN厚度的增加，压应力会通过堆垛层错释放，线缺陷减少，晶体质量提高，反向漏电降低，在沉积过程中随着厚度增加，相当于同质外延，其晶格失配大幅下降，因此可令压应力得到有效释放；S4: Deposit a non-doped GaN layer on the buffer layer. The growth temperature of the non-doped GaN layer is 1100°C, the pressure is 150torr, and the thickness is 2.5um. By setting the deposition growth conditions, the growth temperature of the non-doped GaN layer is higher. , the pressure is lower, and the GaN crystal quality prepared by this method is better. At the same time, as the thickness of GaN increases, the compressive stress will be released through stacking faults, line defects will be reduced, the crystal quality will be improved, and reverse leakage will be reduced. During deposition As the thickness increases during the process, it is equivalent to homoepitaxial growth, and its lattice mismatch is greatly reduced, so the compressive stress can be effectively released;
但提高GaN层厚度对Ga源材料消耗较大，大大提高了LED的外延成本，因此，目前LED外延片通常非掺杂GaN生长2~3um，不仅节约生产成本，而且可确保GaN材料又具有较高的晶体质量；However, increasing the thickness of the GaN layer consumes a lot of Ga source material, which greatly increases the epitaxial cost of LEDs. Therefore, currently, LED epitaxial wafers are usually grown with 2~3um undoped GaN, which not only saves production costs, but also ensures that the GaN material has a higher High crystal quality;
S5：在非掺杂GaN层上沉积Si掺杂n型GaN层，其中n型GaN层生长温度为1120℃，压力100torr，厚度为2.5um，n型GaN层中的Si掺杂浓度为2.5E19atoms/cm3，其中，n型GaN层为LED发光提供充足电子，其次n型GaN层的电阻率要比p-GaN上的透明电极的电阻率高，因此足够的Si掺杂，可以有效的降低n型GaN层电阻率，最后n型GaN足够的厚度可以有效释放应力，确保发光二极管的发光效率；S5: Deposit a Si-doped n-type GaN layer on the undoped GaN layer, where the growth temperature of the n-type GaN layer is 1120°C, the pressure is 100torr, the thickness is 2.5um, and the Si doping concentration in the n-type GaN layer is 2.5E19atoms /cm3 , among which, the n-type GaN layer provides sufficient electrons for LED light emission. Secondly, the resistivity of the n-type GaN layer is higher than that of the transparent electrode on p-GaN. Therefore, sufficient Si doping can effectively reduce the The resistivity of the n-type GaN layer, and finally the sufficient thickness of n-type GaN can effectively release stress and ensure the luminous efficiency of the light-emitting diode;
S6：在n型GaN层上沉积形成CrxAl1-xN层，然后在CrxAl1-xN层上沉积InGaN层，继续在InGaN层上沉积CryGa1-yN层，依例重复实施InGaN层、CryGa1-yN层的沉积作业，以此交替堆叠方式形成CryGa1-yN/InGaN超晶格层，以CrxAl1-xN层、CryGa1-yN/InGaN超晶格层共同组成应力释放层；S6: Deposit a Crx Al1-x N layer on the n-type GaN layer, then deposit an InGaN layer on the Crx Al1-x N layer, and continue to deposit a Cry Ga1-y N layer on the InGaN layer, and so on. Example: Repeat the deposition operation of the InGaN layer and the Cry Ga1-y N layer to form a Cry Ga1-y N/InGaN superlattice layer in an alternating stacking manner. The Crx Al1-x N layer, Cry The Ga1-y N/InGaN superlattice layer together forms the stress release layer;
在本实施例中，CrxAl1-xN层生长温度为1000℃，交替堆叠CryGa1-yN/InGaN超晶格层生长温度为870℃；CrxAl1-xN层、交替堆叠CryGa1-yN/InGaN超晶格层生长压力200torr，生长气氛中N2/NH3流量体积比为2:3，以此交替堆叠CryGa1-yN/InGaN超晶格层的周期数为6个，CrxAl1-xN层Cr组分为0.1，CryGa1-yN层Cr组分为0.05；In this embodiment, the growth temperature of Crx Al1-x N layer is 1000°C , and the growth temperature of alternately stacked Cry Ga 1-y N/InGaN superlattice layers is 870°C; The growth pressure of Cry Ga1-y N/InGaN superlattice layers is alternately stacked at 200torr, and the N2 /NH3 flow volume ratio in the growth atmosphere is 2:3, thereby alternately stacking Cry Ga1-y N/InGaN supercrystals. The number of periods of the grid layer is 6, the Cr composition of the Crx Al1-x N layer is 0.1, and the Cr composition of the Cry Ga1-y N layer is 0.05;
同时，CrN的晶格常数a=0.4150 nm，AlN晶格常数a=0.311 nm，GaN晶格常数a=0.389 nm，而CrxAl1-xN层Cr组分为0.01～0.5，经计算CrxAl1-xN层的晶格常数在0.311～0.363 nm，因此，CrxAl1-xN层的晶格常数是小于GaN层的晶格常数，其具体计算过程如下：At the same time, the lattice constant of CrN is a=0.4150 nm, the lattice constant of AlN is a=0.311 nm, and the lattice constant of GaN is a=0.389 nm. The Cr composition of the Crx Al1-x N layer is 0.01 to 0.5. After calculation, Cr The lattice constant ofthe x Al1-x N layer is between 0.311 and 0.363 nm. Therefore, the lattice constant of the Crx Al1-x N layer is smaller than the lattice constant of the GaN layer. The specific calculation process is as follows:
根据Vegard定律：CrxAl1-xN层的晶格常数aCrxAl1-xN=aAlN(1-x)+aCrNx,因为Cr组分为0.01～0.5，将Cr组分带入0.01时，Cr0.01Al0.99N层的晶格常数0.312 nm，将Cr组分带入0.5时，Cr0.01Al0.99N层的晶格常数0.363 nm，因此，由于CrxAl1-xN层的晶格常数小于GaN层的晶格常数，当沉积在n型GaN层上的CrxAl1-xN层晶格常数小于GaN晶格常数时，CrxAl1-xN层对GaN产生压应力, 以此缓解GaN外延层与衬底产生的张应力；According to Vegard's law: the lattice constant of the Crx Al1-x N layer aCrxAl1-xN =aAlN (1-x)+aCrN , the lattice constant of the Cr0.01 Al0.99 N layer is 0.312 nm. When the Cr component is brought into 0.5, the lattice constant of the Cr0.01 Al0.99 N layer is 0.363 nm. Therefore, due to the lattice of the Crx Al1-x N layer The constant is smaller than the lattice constant of the GaN layer. When the lattice constant of the Crx Al1-x N layer deposited on the n-type GaN layer is smaller than the GaN lattice constant, the Crx Al1-x N layer produces compressive stress on GaN. This relieves the tensile stress generated by the GaN epitaxial layer and the substrate;
通过本实施例的生长条件，制成CrxAl1-xN层厚度35nm，CryGa1-yN层厚度25nm，InGaN层厚度3nm；同时，得到以下技术效果：Through the growth conditions of this embodiment, the thickness of the Crx Al1-x N layer is 35 nm, the thickness of the Cry Ga1-y N layer is 25 nm, and the thickness of the InGaN layer is 3 nm; at the same time, the following technical effects are obtained:
1.借助CrxAl1-xN层引入压应力，以此缓解GaN外延层与衬底产生的张应力，引入Cr可以降低晶轴扭转的势垒和应变驰豫，提高沉积外延层的晶体质量，有效提升发光二极管的电学性能；1. Introduce compressive stress with the help oftheCr quality, effectively improving the electrical performance of light-emitting diodes;
2.交替堆叠CryGa1-yN/InGaN超晶格层可以有效缓解因有源区中InGaN量子阱中的In含量较高InGaN阱与n型GaN之间存在较大的失配应力，导致InGaN阱中的In组分并入难、晶体缺陷多和极化电场大等问题，提高电子空穴波函数的空间重叠度，有效提升发光二极管发光效率；2. Alternately stacking Cry Ga1-y N/InGaN superlattice layers can effectively alleviate the large mismatch stress between the InGaN quantum well and n-type GaN due to the high In content in the active area. This leads to problems such as difficulty in incorporating the In component in the InGaN well, many crystal defects, and large polarization electric fields. It improves the spatial overlap of electron-hole wave functions and effectively improves the luminous efficiency of light-emitting diodes;
S7：在应力释放层上沉积多量子阱层，多量子阱层由交替堆叠的InGaN量子阱层和AlGaN量子垒层形成，其堆叠周期数为10个，其中InGaN量子阱生长温度为795℃，厚度为3.5nm，压力200torr，In组分为0.22，AlGaN量子垒层生长温度为855℃，厚度为9.8nm，生长压力为200torr，Al组分为0.05，多量子阱为电子和空穴复合的区域，合理的结构设计可以显著增加电子和空穴波函数交叠程度，从而提高 LED 器件发光效率；S7: Deposit a multi-quantum well layer on the stress release layer. The multi-quantum well layer is formed by alternately stacking InGaN quantum well layers and AlGaN quantum barrier layers. The number of stacking cycles is 10, and the InGaN quantum well growth temperature is 795°C. The thickness is 3.5nm, the pressure is 200torr, the In composition is 0.22, the growth temperature of the AlGaN quantum barrier layer is 855°C, the thickness is 9.8nm, the growth pressure is 200torr, the Al composition is 0.05, and the multiple quantum wells are composed of electrons and holes. Area, reasonable structural design can significantly increase the degree of overlap of electron and hole wave functions, thereby improving the luminous efficiency of LED devices;
S8：在多量子阱层上沉积电子阻挡层AlInGaN，其厚度为15 nm，其中Al组分按照外延层的生长方向由0.01渐变至0.05，In组分浓度为0.01，生长温度965℃，生长压力200torr，既可以有效地限制电子溢流，也可以减少对空穴的阻挡，提升空穴向量子阱的注入效率，减少载流子俄歇复合，提高发光二极管的发光效率；S8: Deposit the electron blocking layer AlInGaN on the multiple quantum well layer, with a thickness of 15 nm, in which the Al component gradually changes from 0.01 to 0.05 according to the growth direction of the epitaxial layer, the In component concentration is 0.01, the growth temperature is 965°C, and the growth pressure 200torr, which can not only effectively limit the overflow of electrons, but also reduce the blocking of holes, improve the injection efficiency of holes into the quantum well, reduce the Auger recombination of carriers, and improve the luminous efficiency of light-emitting diodes;
S9：在电子阻挡层上沉积Mg掺杂P型GaN层，其中P型GaN层的生长温度985℃，厚度15nm，生长压力200 torr，Mg掺杂浓度2E+20 atoms/cm3，由于Mg掺杂浓度过高会破坏晶体质量，而掺杂浓度较低则会影响空穴浓度，通过设置合适的Mg掺杂浓度以同时确保晶体质量及空穴浓度；S9: Deposit a Mg-doped P-type GaN layer on the electron blocking layer. The growth temperature of the P-type GaN layer is 985°C, the thickness is 15nm, the growth pressure is 200 torr, and the Mg doping concentration is 2E+20 atoms/cm3 . Due to the Mg doping An excessively high doping concentration will destroy the crystal quality, while a low doping concentration will affect the hole concentration. By setting an appropriate Mg doping concentration, the crystal quality and hole concentration can be ensured at the same time;
同时，对于含V 形坑的LED结构来说，P型GaN层较高的生长温度也有利于合并V形坑，以此得到表面光滑的LED外延片，并可确保LED外延片具有较好的轴向光高光效性质。At the same time, for LED structures containing V-shaped pits, the higher growth temperature of the P-type GaN layer is also conducive to merging V-shaped pits, thereby obtaining an LED epitaxial wafer with a smooth surface and ensuring that the LED epitaxial wafer has better High light efficiency properties of axial light.
本实施例还包括一种LED芯片，所述LED芯片由本实施例中的LED外延片制成，以此获得高光效的LED芯片产品。This embodiment also includes an LED chip, which is made of the LED epitaxial wafer in this embodiment, thereby obtaining an LED chip product with high luminous efficiency.
实施例2Example 2
本实施例提供不同生长条件及参数的设置，具体包括以下步骤：This embodiment provides settings for different growth conditions and parameters, specifically including the following steps:
在n型GaN层上沉积形成CrxAl1-xN层，然后在CrxAl1-xN层上沉积InGaN层，继续在InGaN层上沉积CryGa1-yN层，依例重复实施InGaN层、CryGa1-yN层的沉积作业，以此交替堆叠方式形成CryGa1-yN/InGaN超晶格层，以CrxAl1-xN层、CryGa1-yN/InGaN超晶格层共同组成应力释放层；Deposit a Crx Al1-x N layer on the n-type GaN layer, then deposit an InGaN layer on the Crx Al1-x N layer, continue to deposit a Cry Ga1-y N layer on the InGaN layer, and repeat Implement the deposition operation of the InGaN layer and the Cry Ga1-y N layer to form a Cry Ga1-y N/InGaN superlattice layer in an alternating stacking manner. The Crx Al1-x N layer and Cry Ga1 -y N/InGaN superlattice layer together constitutes the stress release layer;
在本实施例中，CrxAl1-xN层生长温度为1100℃，交替堆叠CryGa1-yN/InGaN超晶格层生长温度为1000℃；CrxAl1-xN层、交替堆叠CryGa1-yN/InGaN超晶格层生长压力300torr，生长气氛中N2/NH3流量体积比为2:3，以此交替堆叠CryGa1-yN/InGaN超晶格层的周期数为6个，CrxAl1-xN层Cr组分为0.1，CryGa1-yN层Cr组分为0.05；In thisembodiment , thegrowth temperatureoftheCr The growth pressure of Cry Ga1-y N/InGaN superlattice layers is alternately stacked at 300torr, and the N2 /NH3 flow volume ratio in the growth atmosphere is 2:3, thereby alternately stacking Cry Ga1-y N/InGaN supercrystals. The number of periods of the grid layer is 6, the Cr composition of the Crx Al1-x N layer is 0.1, and the Cr composition of the Cry Ga1-y N layer is 0.05;
通过本实施例的生长条件，制成CrxAl1-xN层厚度50nm，CryGa1-yN层厚度30nm，InGaN层厚度3.5nm。Through the growth conditions of this embodiment, the thickness of the Crx Al1-x N layer is 50 nm, the thickness of the Cy Ga1-y N layer is 30 nm, and the thickness of the InGaN layer is 3.5 nm.
实施例3Example 3
本实施例提供不同生长条件及参数的设置，具体包括以下步骤：This embodiment provides settings for different growth conditions and parameters, specifically including the following steps:
在n型GaN层上沉积形成CrxAl1-xN层，然后在CrxAl1-xN层上沉积InGaN层，继续在InGaN层上沉积CryGa1-yN层，依例重复实施InGaN层、CryGa1-yN层的沉积作业，以此交替堆叠方式形成CryGa1-yN/InGaN超晶格层，以CrxAl1-xN层、CryGa1-yN/InGaN超晶格层共同组成应力释放层；Deposit a Crx Al1-x N layer on the n-type GaN layer, then deposit an InGaN layer on the Crx Al1-x N layer, continue to deposit a Cry Ga1-y N layer on the InGaN layer, and repeat Implement the deposition operation of the InGaN layer and the Cry Ga1-y N layer to form a Cry Ga1-y N/InGaN superlattice layer in an alternating stacking manner. The Crx Al1-x N layer and Cry Ga1 -y N/InGaN superlattice layer together constitutes the stress release layer;
在本实施例中，CrxAl1-xN层生长温度为900℃，交替堆叠CryGa1-yN/InGaN超晶格层生长温度为800℃；CrxAl1-xN层、交替堆叠CryGa1-yN/InGaN超晶格层生长压力50torr，生长气氛中N2/NH3流量体积比为2:3，以此交替堆叠CryGa1-yN/InGaN超晶格层的周期数为6个，CrxAl1-xN层Cr组分为0.1，CryGa1-yN层Cr组分为0.05；In this embodiment, the growth temperature of the Crx Al1-x N layer is 900°C , and the growth temperature of the alternately stacked Cry Ga 1-y N/InGaN superlattice layers is 800°C; The growth pressure of Cry Ga1-y N/InGaN superlattice layers is alternately stacked at 50torr, and the flow volume ratio of N2 /NH3 in the growth atmosphere is 2:3, thereby alternately stacking Cry Ga1-y N/InGaN supercrystals. The number of periods of the grid layer is 6, the Cr composition of the Crx Al1-x N layer is 0.1, and the Cr composition of the Cry Ga1-y N layer is 0.05;
通过本实施例的生长条件，制成CrxAl1-xN层厚度20nm，CryGa1-yN层厚度20nm，InGaN层厚度2.5nm。Through the growth conditions of this embodiment, the thickness of the Crx Al1-x N layer is 20 nm, the thickness of the Cy Ga1-y N layer is 20 nm, and the thickness of the InGaN layer is 2.5 nm.
实施例4Example 4
本实施例提供不同生长条件及参数的设置，具体包括以下步骤：This embodiment provides settings for different growth conditions and parameters, specifically including the following steps:
在n型GaN层上沉积形成CrxAl1-xN层，然后在CrxAl1-xN层上沉积InGaN层，继续在InGaN层上沉积CryGa1-yN层，依例重复实施InGaN层、CryGa1-yN层的沉积作业，以此交替堆叠方式形成CryGa1-yN/InGaN超晶格层，以CrxAl1-xN层、CryGa1-yN/InGaN超晶格层共同组成应力释放层；Deposit a Crx Al1-x N layer on the n-type GaN layer, then deposit an InGaN layer on the Crx Al1-x N layer, continue to deposit a Cry Ga1-y N layer on the InGaN layer, and repeat Implement the deposition operation of the InGaN layer and the Cry Ga1-y N layer to form a Cry Ga1-y N/InGaN superlattice layer in an alternating stacking manner. The Crx Al1-x N layer and Cry Ga1 -y N/InGaN superlattice layer together constitutes the stress release layer;
在本实施例中，CrxAl1-xN层生长温度为1000℃，交替堆叠CryGa1-yN/InGaN超晶格层生长温度为870℃；CrxAl1-xN层、交替堆叠CryGa1-yN/InGaN超晶格层生长压力200torr，生长气氛中N2/NH3流量体积比为2:3，以此交替堆叠CryGa1-yN/InGaN超晶格层的周期数为6个，CrxAl1-xN层Cr组分为0.15，CryGa1-yN层Cr组分为0.07；In this embodiment, the growth temperature of Crx Al1-x N layer is 1000°C , and the growth temperature of alternately stacked Cry Ga 1-y N/InGaN superlattice layers is 870°C; The growth pressure of Cry Ga1-y N/InGaN superlattice layers is alternately stacked at 200torr, and the N2 /NH3 flow volume ratio in the growth atmosphere is 2:3, thereby alternately stacking Cry Ga1-y N/InGaN supercrystals. The number of cycles of the grid layer is 6, the Cr composition of the Crx Al1-x N layer is 0.15, and the Cr composition of the Cry Ga1-y N layer is 0.07;
通过本实施例的生长条件，制成CrxAl1-xN层厚度35nm，CryGa1-yN层厚度25nm，InGaN层厚度3nm。Through the growth conditions of this embodiment, the thickness of the Crx Al1-x N layer is 35 nm, the thickness of the Cy Ga1-y N layer is 25 nm, and the thickness of the InGaN layer is 3 nm.
实施例5Example 5
本实施例提供不同生长条件及参数的设置，具体包括以下步骤：This embodiment provides settings for different growth conditions and parameters, specifically including the following steps:
在n型GaN层上沉积形成CrxAl1-xN层，然后在CrxAl1-xN层上沉积InGaN层，继续在InGaN层上沉积CryGa1-yN层，依例重复实施InGaN层、CryGa1-yN层的沉积作业，以此交替堆叠方式形成CryGa1-yN/InGaN超晶格层，以CrxAl1-xN层、CryGa1-yN/InGaN超晶格层共同组成应力释放层；Deposit a Crx Al1-x N layer on the n-type GaN layer, then deposit an InGaN layer on the Crx Al1-x N layer, continue to deposit a Cry Ga1-y N layer on the InGaN layer, and repeat Implement the deposition operation of the InGaN layer and the Cry Ga1-y N layer to form a Cry Ga1-y N/InGaN superlattice layer in an alternating stacking manner. The Crx Al1-x N layer and Cry Ga1 -y N/InGaN superlattice layer together constitutes the stress release layer;
在本实施例中，CrxAl1-xN层生长温度为1000℃，交替堆叠CryGa1-yN/InGaN超晶格层生长温度为870℃；CrxAl1-xN层、交替堆叠CryGa1-yN/InGaN超晶格层生长压力200torr，生长气氛中N2/NH3流量体积比为2:3，以此交替堆叠CryGa1-yN/InGaN超晶格层的周期数为6个，CrxAl1-xN层Cr组分为0.05，CryGa1-yN层Cr组分为0.02；In this embodiment, the growth temperature of Crx Al1-x N layer is 1000°C , and the growth temperature of alternately stacked Cry Ga 1-y N/InGaN superlattice layers is 870°C; The growth pressure of Cry Ga1-y N/InGaN superlattice layers is alternately stacked at 200torr, and the N2 /NH3 flow volume ratio in the growth atmosphere is 2:3, thereby alternately stacking Cry Ga1-y N/InGaN supercrystals. The number of cycles of the grid layer is 6, the Cr composition of the Crx Al1-x N layer is 0.05, and the Cr composition of the Cry Ga1-y N layer is 0.02;
通过本实施例的生长条件，制成CrxAl1-xN层厚度35nm，CryGa1-yN层厚度25nm，InGaN层厚度3nm。Through the growth conditions of this embodiment, the thickness of the Crx Al1-x N layer is 35 nm, the thickness of the Cy Ga1-y N layer is 25 nm, and the thickness of the InGaN layer is 3 nm.
实施例6Example 6
本实施例提供不同生长条件及参数的设置，具体包括以下步骤：This embodiment provides settings for different growth conditions and parameters, specifically including the following steps:
在n型GaN层上沉积形成CrxAl1-xN层，然后在CrxAl1-xN层上沉积InGaN层，继续在InGaN层上沉积CryGa1-yN层，依例重复实施InGaN层、CryGa1-yN层的沉积作业，以此交替堆叠方式形成CryGa1-yN/InGaN超晶格层，以CrxAl1-xN层、CryGa1-yN/InGaN超晶格层共同组成应力释放层；Deposit a Crx Al1-x N layer on the n-type GaN layer, then deposit an InGaN layer on the Crx Al1-x N layer, continue to deposit a Cry Ga1-y N layer on the InGaN layer, and repeat Implement the deposition operation of the InGaN layer and the Cry Ga1-y N layer to form a Cry Ga1-y N/InGaN superlattice layer in an alternating stacking manner. The Crx Al1-x N layer and Cry Ga1 -y N/InGaN superlattice layer together constitutes the stress release layer;
在本实施例中，CrxAl1-xN层生长温度为1000℃，交替堆叠CryGa1-yN/InGaN超晶格层生长温度为870℃；CrxAl1-xN层、交替堆叠CryGa1-yN/InGaN超晶格层生长压力200torr，生长气氛中N2/NH3流量体积比为1:1，以此交替堆叠CryGa1-yN/InGaN超晶格层的周期数为6个，CrxAl1-xN层Cr组分为0.1，CryGa1-yN层Cr组分为0.05；In this embodiment, the growth temperature of Crx Al1-x N layer is 1000°C , and the growth temperature of alternately stacked Cry Ga 1-y N/InGaN superlattice layers is 870°C; The growth pressure of Cry Ga1-y N/InGaN superlattice layers is alternately stacked at 200torr, and the N2 /NH3 flow volume ratio in the growth atmosphere is 1:1, thereby alternately stacking Cry Ga1-y N/InGaN supercrystals. The number of periods of the grid layer is 6, the Cr composition of the Crx Al1-x N layer is 0.1, and the Cr composition of the Cry Ga1-y N layer is 0.05;
通过本实施例的生长条件，制成CrxAl1-xN层厚度35nm，CryGa1-yN层厚度25nm，InGaN层厚度3nm。Through the growth conditions of this embodiment, the thickness of the Crx Al1-x N layer is 35 nm, the thickness of the Cy Ga1-y N layer is 25 nm, and the thickness of the InGaN layer is 3 nm.
实施例7Example 7
本实施例提供不同生长条件及参数的设置，具体包括以下步骤：This embodiment provides settings for different growth conditions and parameters, specifically including the following steps:
在n型GaN层上沉积形成CrxAl1-xN层，然后在CrxAl1-xN层上沉积InGaN层，继续在InGaN层上沉积CryGa1-yN层，依例重复实施InGaN层、CryGa1-yN层的沉积作业，以此交替堆叠方式形成CryGa1-yN/InGaN超晶格层，以CrxAl1-xN层、CryGa1-yN/InGaN超晶格层共同组成应力释放层；Deposit a Crx Al1-x N layer on the n-type GaN layer, then deposit an InGaN layer on the Crx Al1-x N layer, continue to deposit a Cry Ga1-y N layer on the InGaN layer, and repeat Implement the deposition operation of the InGaN layer and the Cry Ga1-y N layer to form a Cry Ga1-y N/InGaN superlattice layer in an alternating stacking manner. The Crx Al1-x N layer and Cry Ga1 -y N/InGaN superlattice layer together constitutes the stress release layer;
在本实施例中，CrxAl1-xN层生长温度为1000℃，交替堆叠CryGa1-yN/InGaN超晶格层生长温度为870℃；CrxAl1-xN层、交替堆叠CryGa1-yN/InGaN超晶格层生长压力200torr，生长气氛中N2/NH3流量体积比为3:2，以此交替堆叠CryGa1-yN/InGaN超晶格层的周期数为6个，CrxAl1-xN层Cr组分为0.1，CryGa1-yN层Cr组分为0.05；In this embodiment, the growth temperature of Crx Al1-x N layer is 1000°C , and the growth temperature of alternately stacked Cry Ga 1-y N/InGaN superlattice layers is 870°C; The growth pressure of Cry Ga1-y N/InGaN superlattice layers is alternately stacked at 200torr, and the N2 /NH3 flow volume ratio in the growth atmosphere is 3:2, thereby alternately stacking Cry Ga1-y N/InGaN supercrystals. The number of periods of the grid layer is 6, the Cr composition of the Crx Al1-x N layer is 0.1, and the Cr composition of the Cry Ga1-y N layer is 0.05;
通过本实施例的生长条件，制成CrxAl1-xN层厚度35nm，CryGa1-yN层厚度25nm，InGaN层厚度3nm。Through the growth conditions of this embodiment, the thickness of the Crx Al1-x N layer is 35 nm, the thickness of the Cy Ga1-y N layer is 25 nm, and the thickness of the InGaN layer is 3 nm.
实施例8Example 8
本实施例提供不同生长条件及参数的设置，具体包括以下步骤：This embodiment provides settings for different growth conditions and parameters, specifically including the following steps:
在n型GaN层上沉积形成CrxAl1-xN层，然后在CrxAl1-xN层上沉积InGaN层，继续在InGaN层上沉积CryGa1-yN层，依例重复实施InGaN层、CryGa1-yN层的沉积作业，以此交替堆叠方式形成CryGa1-yN/InGaN超晶格层，以CrxAl1-xN层、CryGa1-yN/InGaN超晶格层共同组成应力释放层；Deposit a Crx Al1-x N layer on the n-type GaN layer, then deposit an InGaN layer on the Crx Al1-x N layer, continue to deposit a Cry Ga1-y N layer on the InGaN layer, and repeat Implement the deposition operation of the InGaN layer and the Cry Ga1-y N layer to form a Cry Ga1-y N/InGaN superlattice layer in an alternating stacking manner. The Crx Al1-x N layer and Cry Ga1 -y N/InGaN superlattice layer together constitutes the stress release layer;
在本实施例中，CrxAl1-xN层生长温度为1000℃，交替堆叠CryGa1-yN/InGaN超晶格层生长温度为870℃；CrxAl1-xN层、交替堆叠CryGa1-yN/InGaN超晶格层生长压力200torr，生长气氛中N2/NH3流量体积比为2:3，以此交替堆叠CryGa1-yN/InGaN超晶格层的周期数为10个，CrxAl1-xN层Cr组分为0.1，CryGa1-yN层Cr组分为0.05；In this embodiment, the growth temperature of Crx Al1-x N layer is 1000°C , and the growth temperature of alternately stacked Cry Ga 1-y N/InGaN superlattice layers is 870°C; The growth pressure of Cry Ga1-y N/InGaN superlattice layers is alternately stacked at 200torr, and the N2 /NH3 flow volume ratio in the growth atmosphere is 2:3, thereby alternately stacking Cry Ga1-y N/InGaN supercrystals. The number of cycles of the grid layer is 10, the Cr composition of the Crx Al1-x N layer is 0.1, and the Cr composition of the Cry Ga1-y N layer is 0.05;
通过本实施例的生长条件，制成CrxAl1-xN层厚度35nm，CryGa1-yN层厚度25nm，InGaN层厚度3nm。Through the growth conditions of this embodiment, the thickness of the Crx Al1-x N layer is 35 nm, the thickness of the Cy Ga1-y N layer is 25 nm, and the thickness of the InGaN layer is 3 nm.
实施例9Example 9
本实施例提供不同生长条件及参数的设置，具体包括以下步骤：This embodiment provides settings for different growth conditions and parameters, specifically including the following steps:
在n型GaN层上沉积形成CrxAl1-xN层，然后在CrxAl1-xN层上沉积InGaN层，继续在InGaN层上沉积CryGa1-yN层，依例重复实施InGaN层、CryGa1-yN层的沉积作业，以此交替堆叠方式形成CryGa1-yN/InGaN超晶格层，以CrxAl1-xN层、CryGa1-yN/InGaN超晶格层共同组成应力释放层；Deposit a Crx Al1-x N layer on the n-type GaN layer, then deposit an InGaN layer on the Crx Al1-x N layer, continue to deposit a Cry Ga1-y N layer on the InGaN layer, and repeat Implement the deposition operation of the InGaN layer and the Cry Ga1-y N layer to form a Cry Ga1-y N/InGaN superlattice layer in an alternating stacking manner. The Crx Al1-x N layer and Cry Ga1 -y N/InGaN superlattice layer together constitutes the stress release layer;
在本实施例中，CrxAl1-xN层生长温度为1000℃，交替堆叠CryGa1-yN/InGaN超晶格层生长温度为870℃；CrxAl1-xN层、交替堆叠CryGa1-yN/InGaN超晶格层生长压力200torr，生长气氛中N2/NH3流量体积比为2:3，以此交替堆叠CryGa1-yN/InGaN超晶格层的周期数为3个，CrxAl1-xN层Cr组分为0.1，CryGa1-yN层Cr组分为0.05；In this embodiment, the growth temperature of Crx Al1-x N layer is 1000°C , and the growth temperature of alternately stacked Cry Ga 1-y N/InGaN superlattice layers is 870°C; The growth pressure of Cry Ga1-y N/InGaN superlattice layers is alternately stacked at 200torr, and the N2 /NH3 flow volume ratio in the growth atmosphere is 2:3, thereby alternately stacking Cry Ga1-y N/InGaN supercrystals. The number of periods of the grid layer is 3, the Cr composition of the Crx Al1-x N layer is 0.1, and the Cr composition of the Cry Ga1-y N layer is 0.05;
通过本实施例的生长条件，制成CrxAl1-xN层厚度35nm，CryGa1-yN层厚度25nm，InGaN层厚度3nm。Through the growth conditions of this embodiment, the thickness of the Crx Al1-x N layer is 35 nm, the thickness of the Cy Ga1-y N layer is 25 nm, and the thickness of the InGaN layer is 3 nm.
对比例1Comparative example 1
通过目前常规量产技术制备得到LED外延片结构（无应力释放层结构），以此制成的LED芯片作为A样品，其光效性质与现阶段产品性能持平（光效提升0%）。The LED epitaxial wafer structure (stress-free layer structure) is prepared through current conventional mass production technology. The LED chip made with this is used as sample A. Its light efficiency properties are the same as those of current products (light efficiency increased by 0%).
将实施例1中LED外延片制备得到的LED芯片作为B样品，将对比例1的A样品与实施例1的B样品使用相同芯片工艺条件制备成10 mil*24 mil芯片，两个样品分别抽取300颗LED芯片，在120 mA/ 60 mA电流下测试，得出B样品光电效率提升5%，同时，其他项电学性能良好，因此，实施例1所提供的制备方法可有效提高发光二极管的发光效率。The LED chip prepared from the LED epitaxial wafer in Example 1 was used as sample B. The A sample of Example 1 and the B sample of Example 1 were prepared into a 10 mil*24 mil chip using the same chip process conditions. The two samples were extracted separately. 300 LED chips were tested at a current of 120 mA/60 mA. It was found that the photoelectric efficiency of sample B increased by 5%. At the same time, other electrical properties were good. Therefore, the preparation method provided in Example 1 can effectively improve the luminescence of light-emitting diodes. efficiency.
将实施例1～实施例9提供制备方法得到的LED外延片制成LED芯片样品，通过电流测试光电效率，得出光效提升率如下表所示：The LED epitaxial wafers obtained by the preparation methods provided in Examples 1 to 9 were made into LED chip samples, and the photoelectric efficiency was tested through current. The light efficiency improvement rate was obtained as shown in the following table:
通过表中光效提升率可知，相对于现有技术（对比例1），实施例1～实施例9的LED芯片样品具有明显的光效提升优势，随CrxAl1-xN层厚度、CryGa1-yN层/InGaN层厚度、CrxAl1-xN层/堆叠CryGa1-yN层Cr组分、应力释放层N2/NH3流量体积比及CryGa1-yN/InGaN超晶格层周期数量的差异变化，只需变化量符合设定范围内，均能获得良好的光效提升效果。因此，借助本发明中应力释放层结构的性质，以应力释放层中的CrxAl1-xN层引入压应力，缓解GaN外延层与衬底产生的张应力，引入Cr可以降低晶轴扭转的势垒和应变驰豫，提高沉积外延层的晶体质量，提高发光二极管的电学性能。交替堆叠CryGa1-yN/InGaN超晶格层可以有效缓解因有源区中InGaN量子阱中的In含量较高InGaN阱与n型GaN之间存在较大的失配应力，导致InGaN阱中的In组分并入难、晶体缺陷多和极化电场大等问题，提高电子空穴波函数的空间重叠度，有效提升发光二极管产品的发光效率。It can be seen from the light efficiency improvement rate in the table that compared with the existing technology (Comparative Example 1), the LED chip samples of Examples 1 to 9 have obvious advantages in light efficiency improvement. With the Crx Al1-x N layer thickness, Cry Ga1-y N layer/InGaN layer thickness, Crx Al1-x N layer/stacked Cry Ga1-y N layer Cr composition, stress release layer N2 /NH3 flow volume ratio and Cry Ga Different changes in the number of cycles of the1-y N/InGaN superlattice layer can achieve good light efficiency improvement effects as long as the change amount is within the set range. Therefore,with the help of the properties of the stress release layer structure in the present invention, compressive stress is introduced into theCr The potential barrier and strain relaxation can improve the crystal quality of the deposited epitaxial layer and improve the electrical performance of the light-emitting diode. Alternately stacking Cry Ga1-y N/InGaN superlattice layers can effectively alleviate the large mismatch stress between the InGaN quantum well in the active region and the n-type GaN, resulting in InGaN Problems such as difficulty in incorporating the In component in the well, many crystal defects, and large polarization electric field can improve the spatial overlap of electron-hole wave functions and effectively improve the luminous efficiency of light-emitting diode products.
以上所述仅为本发明的优选实施例，并非针对本发明作出形式上的限制，应当理解，在权利要求书所限定的特征范围下，实施例还可作出其它等同形式的修改、变动，这些都应涵盖于本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention and do not impose any formal limitations on the present invention. It should be understood that within the scope of features defined by the claims, other equivalent modifications and changes may be made to the embodiments. All are covered by the protection scope of the present invention.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW439304B (en)* | 2000-01-05 | 2001-06-07 | Ind Tech Res Inst | GaN series III-V compound semiconductor devices |
| JP5060875B2 (en)* | 2007-08-28 | 2012-10-31 | Ｄｏｗａエレクトロニクス株式会社 | Group III nitride semiconductor and manufacturing method thereof |
| KR101979944B1 (en)* | 2012-10-18 | 2019-05-17 | 엘지이노텍 주식회사 | Light emitting device |
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|---|---|---|
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