Disclosure of Invention
The embodiment of the invention provides a memory access verification method, a memory access verification system, electronic equipment and a readable storage medium, which can solve the problem of poor memory access module verification effect in the prior art.
In order to solve the above problems, an embodiment of the present invention discloses a memory access verification method, which includes:
acquiring functional behavior information of a memory access module to be verified, wherein the functional behavior information is used for describing operation behaviors required by the memory access module to run;
constructing a test program based on the functional behavior information, wherein the test program at least comprises a first subprogram; the first subprogram is used for generating a memory access instruction and setting an instruction sending sequence, and the instruction sending sequence is used for representing the sequence of sending a loading instruction and a storage instruction in the memory access instruction to the memory access module;
And verifying the access module based on the first subprogram.
Optionally, the test program further includes a second subroutine and a third subroutine; the second subprogram is used for responding to the physical address acquisition request of the access module; and the third subprogram is used for responding to the data access request of the access module and returning preset response data in an out-of-order mode.
Optionally, the setting the instruction sending sequence includes:
acquiring verification requirement information;
determining a target test instruction from the memory access instruction generated by the first subprogram based on the verification requirement information;
and setting an instruction sending sequence for the target test instruction based on the verification requirement information.
Optionally, the determining, based on the verification requirement information, a target test instruction from the memory access instructions generated by the first subroutine includes:
under the condition that the verification requirement information characterizes basic access verification, determining a plurality of first loading instructions and a plurality of first storing instructions in access instructions generated by the first subprogram as target test instructions; the first load instruction is different from the first store instruction in access address;
The step of setting the instruction sending sequence for the target test instruction based on the verification requirement information comprises the following steps: and under the condition that the verification requirement information characterizes basic verification, setting the instruction sending sequence for the target test instruction to be out-of-order sending.
Optionally, the determining, based on the verification requirement information, a target test instruction from the memory access instructions generated by the first subroutine includes:
under the condition that the verification requirement information characterizes access violation verification, determining a plurality of access instruction groups in access instructions generated by the first subprogram as target test instructions; any one of the access instruction groups comprises a second loading instruction and a second storing instruction, wherein the second loading instruction and the second storing instruction have the same access address;
the step of setting the instruction sending sequence for the target test instruction based on the verification requirement information comprises the following steps: and setting the instruction sending sequence for each access instruction group in the target test instruction to be the second loading instruction before the second storing instruction under the condition that the verification requirement information characterizes access violation verification.
Optionally, the determining, based on the verification requirement information, a target test instruction from the memory access instructions generated by the first subroutine includes:
Under the condition that the verification requirement information characterizes access violation verification, determining a plurality of loading instruction groups in access instructions generated by the first subprogram as target test instructions; any one of the load instruction groups comprises a third load instruction and a fourth load instruction, wherein the access address of the third load instruction is the same as that of the fourth load instruction;
the step of setting the instruction sending sequence for the target test instruction based on the verification requirement information comprises the following steps: and setting an instruction sending sequence for each loading instruction group in the target test instruction to be that the third loading instruction is before the fourth loading instruction or that the fourth loading instruction is before the third loading instruction under the condition that the verification requirement information characterizes access violation verification.
Optionally, the verifying the access module based on the first subroutine includes:
based on the first subprogram, sending the target test instruction to the memory access module and the reference module according to the instruction sending sequence;
obtaining output data of the memory module in response to the target test instruction as a first output, and obtaining output data of the reference module in response to the target test instruction as a second output;
And under the condition that the first output is consistent with the second output, determining that the verification result of the access module meets the requirement.
In another aspect, an embodiment of the present invention discloses a memory access verification system, the system including:
the system comprises a functional behavior acquisition module, a verification module and a verification module, wherein the functional behavior acquisition module is used for acquiring functional behavior information of a memory access module to be verified, and the functional behavior information is used for describing operation behaviors required by the memory access module to run;
the program construction module is used for constructing a test program based on the functional behavior information, and the test program at least comprises a first subprogram; the first subprogram is used for generating a memory access instruction and setting an instruction sending sequence, and the instruction sending sequence is used for representing the sequence of sending a loading instruction and a storage instruction in the memory access instruction to the memory access module;
and the verification module is used for verifying the access module based on the first subprogram.
Optionally, the test program further includes a second subroutine and a third subroutine; the second subprogram is used for responding to the physical address acquisition request of the access module; and the third subprogram is used for responding to the data access request of the access module and returning preset response data in an out-of-order mode.
Optionally, the program construction module includes:
the demand acquisition sub-module is used for acquiring verification demand information;
the target determining submodule is used for determining a target test instruction from the memory access instruction generated by the first subprogram based on the verification requirement information;
and the order setting sub-module is used for setting the instruction sending order for the target test instruction based on the verification requirement information.
Optionally, the target determination submodule is specifically configured to:
under the condition that the verification requirement information characterizes basic access verification, determining a plurality of first loading instructions and a plurality of first storing instructions in access instructions generated by the first subprogram as target test instructions; the first load instruction is different from the first store instruction in access address;
the sequence setting submodule is specifically configured to:
and under the condition that the verification requirement information characterizes basic verification, setting the instruction sending sequence for the target test instruction to be out-of-order sending.
Optionally, the target determination submodule is specifically configured to:
under the condition that the verification requirement information characterizes access violation verification, determining a plurality of access instruction groups in access instructions generated by the first subprogram as target test instructions; any one of the access instruction groups comprises a second loading instruction and a second storing instruction, wherein the second loading instruction and the second storing instruction have the same access address;
The sequence setting submodule is specifically configured to:
and setting the instruction sending sequence for each access instruction group in the target test instruction to be the second loading instruction before the second storing instruction under the condition that the verification requirement information characterizes access violation verification.
Optionally, the target determination submodule is specifically configured to:
under the condition that the verification requirement information characterizes access violation verification, determining a plurality of loading instruction groups in access instructions generated by the first subprogram as target test instructions; any one of the load instruction groups comprises a third load instruction and a fourth load instruction, wherein the access address of the third load instruction is the same as that of the fourth load instruction;
the sequence setting submodule is specifically configured to: and setting an instruction sending sequence for each loading instruction group in the target test instruction to be that the third loading instruction is before the fourth loading instruction or that the fourth loading instruction is before the third loading instruction under the condition that the verification requirement information characterizes access violation verification.
Optionally, the verification module includes:
the sending sub-module is used for sending the target test instruction to the memory module and the reference module according to the instruction sending sequence based on the first sub-program;
The output acquisition sub-module is used for acquiring output data of the memory access module in response to the target test instruction as a first output, and acquiring output data of the reference module in response to the target test instruction as a second output;
and the result determining submodule is used for determining that the verification result of the access module meets the requirement under the condition that the first output is consistent with the second output.
In still another aspect, the embodiment of the invention also discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions, and the executable instructions enable the processor to execute the access verification method.
The embodiment of the invention also discloses a readable storage medium, which enables the electronic equipment to execute the access verification method when the instructions in the readable storage medium are executed by the processor of the electronic equipment.
The embodiment of the invention also discloses a computer program product containing instructions, which when run on a computer, cause the computer to execute the memory access verification method.
The embodiment of the invention has the following advantages:
the embodiment of the invention provides a memory access verification method, which is characterized in that functional behavior information of a memory access module to be verified is obtained, wherein the functional behavior information is used for describing operation behaviors required by running the memory access module; constructing a test program based on the functional behavior information, wherein the test program at least comprises a first subprogram; the first subprogram is used for generating a memory access instruction and setting an instruction sending sequence, and the instruction sending sequence is used for representing the sequence of sending a loading instruction and a storage instruction in the memory access instruction to the memory access module; and verifying the access module based on the first subprogram. Compared with the method for verifying through random instructions in the prior art, the access verification method provided by the embodiment of the invention has the advantages that the test program comprising the first subprogram is constructed, the access instructions can be generated through the first subprogram, and the instruction sending sequence is set, so that the constraint on the test is realized through the first subprogram, different access verification requirements can be met according to the instruction sending sequence, more test points are covered, the access verification effect is improved, and the problems of consuming a large amount of time and equipment resources caused by using the random instructions to cover the test points are avoided. Meanwhile, compared with a method for verifying the memory access module by constructing the whole peripheral circuit, the memory access verification method provided by the embodiment of the invention does not need to configure the peripheral circuit, only needs to construct a test program according to the functional behavior information of the memory access module, and greatly reduces the difficulty of constructing a test frame.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.
Method embodiment
Referring to fig. 1, a step flow diagram of an embodiment of a memory access verification method of the present invention is shown, where the method specifically may include the following steps:
Step 101, obtaining functional behavior information of a memory access module to be verified, wherein the functional behavior information is used for describing operation behaviors required by running of the memory access module.
102, constructing a test program based on the functional behavior information, wherein the test program at least comprises a first subprogram; the first subprogram is used for generating a memory access instruction and setting an instruction sending sequence, and the instruction sending sequence is used for representing the sequence of sending a loading instruction and a storage instruction in the memory access instruction to the memory access module.
Step 103, verifying the access module based on the first subprogram.
It should be noted that, for the steps 101 to 103, the memory access module in the present invention refers to a circuit design with a memory access function, which may belong to a processor to be verified, it is understood that one processor generally includes modules with different functions, and in order to verify the functions of the processor, different modules are generally verified respectively.
When the correctness verification is carried out on the access module, the embodiment of the invention firstly obtains the functional behavior information of the access module to be verified. It should be noted that the functional behavior information is used to describe the operation behavior required by the operation of the memory access module. Specifically, the operation behavior required by the operation of the memory access module refers to the instruction and data required by the memory access module in normal operation, that is, the minimum condition required by the memory access module in normal operation of the analog processor is usually provided by the peripheral circuit. Illustratively, for a processor executing out-of-order, its memory module execution flow includes: the method includes receiving access instructions, executing the access instructions out of order, and interacting with a cache, a translation lookaside buffer (Translation Lookaside Buffer, TLB).
Further, based on the description, the data dependency between the memory module and the peripheral circuit is strong, the memory module has a correlation in time, the number of interfaces of the memory module is large, and the interfaces often have a coupling relation in time, so that the difficulty of constructing the test program for the memory module and the peripheral circuit is high. In the embodiment of the invention, the test program is only built aiming at the functional behavior information of the memory access module, so that different test programs provide different operation behaviors, namely, instructions and data required by the operation of the memory access module are provided through the test program, and a real circuit simulation peripheral circuit does not need to be built for real response.
The test program may be understood as a test module for providing stimulus to the memory module in a test environment, and the instruction sending sequence may represent different types of stimulus, which may include basic memory stimulus and illegal stimulus, corresponding to different verification requirements. The stimulus (stinmutli) may be an instruction stream consisting of a plurality of memory instructions.
The memory access instruction includes a load instruction (load) and a store instruction (store), and it can be understood that the load instruction refers to an instruction for reading data, where the load instruction includes an access address of the data to be read, and is used for obtaining the data to be read from the access address. The storage instruction is an instruction for storing data, wherein the storage instruction comprises data to be stored and an access address of the data to be stored and is used for storing the data to be stored to the access address.
Further, the instruction sending sequence refers to the sending sequence of the load instruction and the store instruction, and the sending sequence characterizes the execution sequence of the memory access instruction by the memory access module to a certain extent. In particular, the verification requirements for the memory module typically include a plurality of different types, which require different instruction delivery sequences. Illustratively, the validation requirements include Store-load violation validation, which refers to the occurrence of a load and Store violation in an out-of-order execution processor if the load instruction is executed first and then subsequently, when the Store instruction and the load instruction operate at the same block address. Because the load instruction needs to obtain the data of the store instruction, but the store instruction has not yet executed when the load instruction executes, the load instruction may obtain erroneous data. In this case, the memory module is required to cancel the execution result of the load instruction, and execute the load instruction after the store instruction is executed. Therefore, store-load violation verification refers to verifying a processing operation of the memory module against Store-load violations, and at this time, the memory module needs to send a load instruction first and then send a Store instruction, so that the memory module executes the load instruction first and then executes the Store instruction, and access addresses of the two instructions are the same, thereby triggering Store-load violations of the memory module.
The instruction sending sequence can be set based on input information of a user, the user can input different instruction information according to actual verification requirements, and further, the different instruction sending sequences can be set based on the instruction information. Or, the instruction sending sequence may be sequentially adjusted according to the preset verification requirement sequence, so as to meet different verification requirements, which is not limited by the embodiment of the present invention.
Optionally, the test program further includes a second subroutine and a third subroutine, where the second subroutine is configured to respond to a physical address acquisition request of the memory access module; and the third subprogram is used for responding to the data access request of the access module and returning preset response data in an out-of-order mode.
The second subroutine is used to simulate the TLB module of the processor, which may be referred to as DTLB (Data Translation Lookaside Buffer) module, and is used to return the physical address and the address attribute to the memory module. Specifically, when the memory access module executes the memory access instruction, the destination address in the memory access instruction is a virtual address, and after the physical address corresponding to the virtual address is required to be obtained, the corresponding memory access operation is executed on the physical address. Therefore, the access module needs to interact with the TLB module to acquire the corresponding physical address. In the embodiment of the invention, the access module only needs to send the physical address acquisition request to the TLB module and receive the address returned by the TLB module, and the access module does not need to identify whether the physical address is accurate, so that the second subprogram in the embodiment of the invention can randomly return the address to the access module under the condition of receiving the physical address acquisition request of the access module. For example, the second subroutine may perform a regular operation as the physical address to be returned according to a preset rule, for example, on the basis of the address carried in the physical address acquisition request.
The third subroutine is used for responding to the data access request of the access module, which is equivalent to providing a cache space for the access module, and the cache module used for simulating the processor can be called as a DCache (Data Cache) module. Specifically, the cache stores data to be stored carried in the storage instruction when the memory access module executes the storage instruction, and returns data of a destination address carried in the loading instruction to the memory access module when the memory access module executes the loading instruction. Correspondingly, in the embodiment of the invention, the memory access module only needs to send the memory access request to the cache module and receive the response information of the cache module, and the memory access module does not need to identify whether the response of the cache module accords with the behavior of the real processor, so that the third subprogram in the embodiment of the invention can return random data or information representing the completion of data storage according to the data memory access request under the condition of receiving the data memory access request of the memory access module. Further, the third subroutine may also randomly return a miss request (corresponding data is not queried), a resend request or a release request (release), etc. to characterize that the execution of the data access request fails at this time. Accordingly, the preset response data may include the random data, information indicating that the data storage is completed, a missing request, a retransmission request, or a release request (release), etc.
According to the embodiment of the invention, the second subprogram and the third subprogram are constructed, the peripheral circuit of the memory access module can be abstracted through the second subprogram and the third subprogram, and corresponding data response is provided for the memory access module through the second subprogram and the second subprogram, so that the peripheral circuit is not required to be configured, and the difficulty in constructing a test frame is greatly reduced.
Compared with the method for verifying through random instructions in the prior art, the access verification method provided by the embodiment of the invention has the advantages that the test program comprising the first subprogram is constructed, the access instructions can be generated through the first subprogram, and the instruction sending sequence is set, so that the constraint on the test is realized through the first subprogram, different access verification requirements can be met according to the instruction sending sequence, more test points are covered, the access verification effect is improved, and the problems of consuming a large amount of time and equipment resources caused by using the random instructions to cover the test points are avoided. Meanwhile, compared with a method for verifying the memory access module by constructing the whole peripheral circuit, the memory access verification method provided by the embodiment of the invention does not need to configure the peripheral circuit, only needs to construct a test program according to the functional behavior information of the memory access module, and greatly reduces the difficulty of constructing a test frame.
In an alternative embodiment of the present invention, the operation of setting the instruction sending sequence in step 102 may specifically include the following steps:
a substep 1021 of obtaining verification requirement information;
and step 1022, determining a target test instruction from the memory access instructions generated by the first subprogram based on the verification requirement information.
And 1023, setting an instruction sending sequence for the target test instruction based on the verification requirement information.
The verification requirement information may be used to describe a verification requirement, and is used to indicate a type of a test case to be verified, and may include a base verification and a violation verification, that is, a base access incentive and a violation incentive in the foregoing, where the base verification may include a Store verification and a load verification, and the violation verification may include a Store-load violation verification and a load-load violation verification. Specifically, the verification requirement information may be determined by receiving input information of related personnel, or may sequentially and automatically generate different verification requirement information according to a preset verification sequence, which is not limited in the embodiment of the present invention.
The memory access instruction generated by the first subprogram may be randomly generated, and the first subprogram may randomly generate an operation code and an access address to form different memory access instructions. The memory access method can be a load instruction, a store instruction, and can have the same access address of a plurality of memory access instructions, or can generate memory access instructions different from those of other memory access instructions. The first subroutine may specifically generate the random access instruction by a random instruction generator (e.g., a RISCV-DV, etc. generator).
Further, the target test instruction refers to a memory instruction matched with the acquired verification requirement information in the memory instruction generated by the first subroutine, and the instruction sending sequence is also a sending sequence matched with the acquired verification requirement information.
According to the embodiment of the invention, the target test instruction and the instruction sending sequence can be determined according to the acquired verification requirement information, so that different target test instructions and instruction sending sequences can be determined according to different verification requirements, further, the verification of the memory module by a random instruction is avoided, different verification requirements can be met, and the validity of memory verification is improved. Meanwhile, the problems that a large amount of time is consumed and the comprehensiveness of the verification is improved due to the fact that the random instruction is used for verification are avoided, and verification time and occupation of the server resource can be saved.
Optionally, the operation of determining the target test instruction from the memory access instruction generated by the first subroutine in the above sub-step 1022 based on the verification requirement information may specifically include the following steps:
s11, under the condition that the verification requirement information characterizes basic memory access verification, determining a plurality of first loading instructions and a plurality of first storage instructions in memory access instructions generated by the first subprogram as target test instructions; the first load instruction is different from an access address of the first store instruction.
The operation of setting the instruction sending sequence for the target test instruction based on the verification requirement information in the above step 1023 may specifically include the following steps:
and S12, setting the instruction sending sequence for the target test instruction to be out-of-order sending under the condition that the verification requirement information characterizes the basic access verification.
Specifically, for the steps S11 to S12, the basic memory verification may be understood as verification of a basic memory function of the memory module, that is, verifying whether the memory module can execute the store and the load, and at this time, multiple load instructions and multiple store instructions with inconsistent access addresses may be obtained from the memory instruction generated by the first subroutine, which may be used as the target test instruction.
Accordingly, the verification of the basic memory function only needs to verify whether the memory module can execute corresponding memory operation according to the received memory instruction, so that under the condition that verification requirement information characterizes the basic memory verification, the instruction sending sequence can be set to be out-of-order, namely, a plurality of loading instructions and a plurality of storage instructions with inconsistent access addresses are sent to the memory module randomly.
In the embodiment of the invention, the load instruction and the store instruction with different access addresses are determined as the target test instruction, and the instruction sending sequence of out-of-order sending is set, so that the basic memory access function of the memory access module can be subjected to targeted verification, and invalid verification can be avoided to a certain extent.
Optionally, the operation of determining the target test instruction from the memory access instruction generated by the first subroutine in the above sub-step 1022 based on the verification requirement information may specifically include the following steps:
s21, under the condition that the verification requirement information characterizes access violation verification, determining a plurality of access instruction groups in access instructions generated by the first subprogram as target test instructions; and any one of the access instruction groups comprises a second loading instruction and a second storing instruction, wherein the second loading instruction and the second storing instruction have the same access address.
The operation of setting the instruction sending sequence for the target test instruction based on the verification requirement information in the above step 1023 may specifically include the following steps:
s22, setting an instruction sending sequence for each access instruction group in the target test instruction to be the second loading instruction before the second storing instruction under the condition that the verification requirement information characterizes access violation verification.
The memory violation verification refers to Store-load violation verification, and Store-load violation refers to load and Store violation if the Store instruction is executed first and then when the Store instruction and the load instruction operate the same block address. Because the load instruction needs to obtain the data of the store instruction, but the store instruction has not yet executed when the load instruction executes, the load instruction may obtain erroneous data. In this case, the memory module is required to cancel the execution result of the load instruction, and execute the load instruction after the store instruction is executed. Therefore, store-load violation verification refers to verifying a processing operation of the memory module against Store-load violations, and at this time, the memory module needs to send a load instruction first and then send a Store instruction, so that the memory module executes the load instruction first and then executes the Store instruction, and access addresses of the two instructions are the same, thereby triggering Store-load violations of the memory module.
Specifically, in the embodiment of the invention, a plurality of memory access instruction groups can be determined as target test instructions, each memory access instruction group can comprise a load instruction and a Store instruction with the same access address, and the load instruction is executed before the Store instruction by setting the instruction sending sequence to be the load instruction, namely, the load instruction is executed first, and the Store instruction is executed later, at this time, a Store-load violation of a memory access module can be triggered, and further, the pertinence verification of the memory access violation can be realized. Further, the instruction sending sequence may be set for different load instruction groups to be out of order, that is, different load instruction groups may be sent to the memory module randomly, but the sending sequence in any load instruction group is still that the load instruction precedes the store instruction.
According to the embodiment of the invention, the load instructions and the Store instructions with the same access addresses are determined as the target test instructions, and the instruction sending sequence is set to be that the load instructions precede the Store instructions, namely, the load instructions are executed first, and then the Store instructions are executed, so that Store-load violations of the access memory module can be triggered, further, the targeted verification of the access memory violations can be realized, the randomization with constraint is realized, and invalid verification is reduced to a certain extent.
Optionally, the operation of determining the target test instruction from the memory access instruction generated by the first subroutine in the above sub-step 1022 based on the verification requirement information may specifically include the following steps:
s31, under the condition that the verification requirement information characterizes access violation verification, determining a plurality of loading instruction groups in the access instruction generated by the first subprogram as target test instructions; any one of the load instruction groups comprises a third load instruction and a fourth load instruction, wherein the third load instruction has the same access address as the fourth load instruction.
The operation of setting the instruction sending sequence for the target test instruction based on the verification requirement information in the above step 1023 may specifically include the following steps:
And S32, setting an instruction sending sequence for each loading instruction group in the target test instruction to be that the third loading instruction is before the fourth loading instruction or that the fourth loading instruction is before the third loading instruction under the condition that the verification requirement information characterizes access violation verification.
The above access violation verification refers to load-load violation verification, specifically, for a multi-core processor, there may be a case that different processor cores access the same address, if in a process that one processor core executes two continuous load instructions with the same access address out of order, another processor core executes a store instruction with respect to the same address, at this time, the previously executed load instruction may not obtain correct data, and load-load violation occurs. Therefore, the load-load violation verification refers to verifying the processing operation of the memory module for handling the load-load violation, and at this time, two load instructions need to be sent to the memory module successively, and the access addresses of the two load instructions are the same, so as to construct a condition for triggering the load-load violation of the memory module. Further, after the condition of triggering the load-load violation of the memory module is established, since the third subroutine can randomly return preset response data, when the third subroutine responds to the data memory request of the second load instruction, if a release is returned, the load-load violation of the memory module can be triggered.
Specifically, in the embodiment of the invention, a plurality of load instruction groups can be determined as target test instructions, two load instructions with the same access address can be included in any load instruction group, and the instruction sending sequence is set to be that any load instruction is prior to the other load instruction, that is, the two load instructions are executed successively, so that the condition of triggering load-load violations of the access module can be met, and further, the verification of access violations can be guaranteed to be restrained to a certain extent. Further, the instruction sending sequence can be set for different load instruction groups to be out-of-order, that is, different load instruction groups can be randomly sent to the memory access module, but the sending sequence inside any load instruction group still exists in sequence.
According to the embodiment of the invention, the load instructions and the load instructions with the same access addresses are determined as the target test instructions, and the instruction sending sequence is set to be that one load instruction is executed before the other load instruction, namely, the one load instruction is executed before the other load instruction, so that the condition of triggering the load-load violation of the access memory module can be met, further, the constraint on the verification of the access violation can be ensured to a certain extent, invalid verification can be reduced to a certain extent, and the verification efficiency is improved.
Optionally, the operation of verifying the memory access module based on the first subroutine in step 103 may specifically include:
and step 1031, based on the first subprogram, sending the target test instruction to the memory module and the reference module according to the instruction sending sequence.
Sub-step 1032, obtaining output data of the memory module in response to the target test instruction as a first output, and obtaining output data of the reference module in response to the target test instruction as a second output.
And step 1033, determining that the verification result of the access module meets the requirement under the condition that the first output is consistent with the second output.
The reference module refers to a module that is built in advance to meet the requirement of the access function, and the reference module can be used as a comparison module for access verification and used for comparing with the access module, and can be a simulation model or a simulator which is built in advance. Specifically, fig. 2 is a schematic diagram of a frame of access verification provided by the embodiment of the present invention, as shown in fig. 2, the first sub-program, the second sub-program and the third sub-program may interact with the reference module and the access module at the same time, that is, when the first sub-program, the second sub-program and the third sub-program output instructions or data to the access module, the output instructions or data are output to the reference module at the same time, so as to ensure that the data or instructions received by the reference module and the access module are consistent, ensure accuracy of verification comparison, and correspondingly, the second sub-program and the third sub-program may also receive requests sent by the reference module and the access module and respond.
Further, the first subroutine can sequentially send the target test instructions to the memory access module and the reference module according to the set instruction sending sequence, so as to realize different verification requirements.
Further, by acquiring output data of the access module and the reference module aiming at the target test instruction, the output data of the access module and the reference module can be compared, when the output data are consistent, the execution process of the access module aiming at the target test instruction is consistent with that of the reference module, and at the moment, the verification result of the access module can be determined to meet the requirement.
Specifically, since the number of the target test instructions is often multiple, and the output data of the access module and the reference module aiming at the target test instructions is also multiple, a verification threshold can be further set, and when the number proportion of the first outputs consistent with the second outputs reaches the verification threshold, the verification result of the access module is determined to meet the requirement. The above verification threshold may be set by itself, for example, a higher verification threshold may be set under a higher verification requirement, and a lower verification threshold may be set under a lower verification requirement, which is not limited in the embodiment of the present invention.
According to the embodiment of the invention, the reference module is arranged, the target test instruction is sent to the access module and the reference module, and the verification of the access module can be realized by comparing the output data of the access module and the reference module responding to the target test instruction.
In summary, the embodiment of the invention provides a memory access verification method, by acquiring functional behavior information of a memory access module to be verified, wherein the functional behavior information is used for describing operation behaviors required by running the memory access module; constructing a test program based on the functional behavior information, wherein the test program at least comprises a first subprogram; the first subprogram is used for generating a memory access instruction and setting an instruction sending sequence, and the instruction sending sequence is used for representing the sequence of sending a loading instruction and a storage instruction in the memory access instruction to the memory access module; and verifying the access module based on the first subprogram. Compared with the method for verifying through random instructions in the prior art, the access verification method provided by the embodiment of the invention has the advantages that the test program comprising the first subprogram is constructed, the access instructions can be generated through the first subprogram, and the instruction sending sequence is set, so that the constraint on the test is realized through the first subprogram, different access verification requirements can be met according to the instruction sending sequence, more test points are covered, the access verification effect is improved, and the problems of consuming a large amount of time and equipment resources caused by using the random instructions to cover the test points are avoided. Meanwhile, compared with a method for verifying the memory access module by constructing the whole peripheral circuit, the memory access verification method provided by the embodiment of the invention does not need to configure the peripheral circuit, only needs to construct a test program according to the functional behavior information of the memory access module, and greatly reduces the difficulty of constructing a test frame.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
System embodiment
Referring to FIG. 3, a block diagram illustrating an embodiment of a memory verification system of the present invention is shown, which may include:
the functional behavior acquisition module 201 is configured to acquire functional behavior information of a memory access module to be verified, where the functional behavior information is used to describe operation behaviors required by the memory access module to run;
a program construction module 202, configured to construct a test program based on the functional behavior information, where the test program includes at least a first subroutine; the first subprogram is used for generating a memory access instruction and setting an instruction sending sequence, and the instruction sending sequence is used for representing the sequence of sending a loading instruction and a storage instruction in the memory access instruction to the memory access module;
And the verification module 203 is configured to verify the access module based on the first subroutine.
Optionally, the test program further includes a second subroutine and a third subroutine; the second subprogram is used for responding to the physical address acquisition request of the access module; and the third subprogram is used for responding to the data access request of the access module and returning preset response data in an out-of-order mode.
Optionally, the program building module 202 includes:
the demand acquisition sub-module is used for acquiring verification demand information;
the target determining submodule is used for determining a target test instruction from the memory access instruction generated by the first subprogram based on the verification requirement information;
and the order setting sub-module is used for setting the instruction sending order for the target test instruction based on the verification requirement information.
Optionally, the target determination submodule is specifically configured to:
under the condition that the verification requirement information characterizes basic access verification, determining a plurality of first loading instructions and a plurality of first storing instructions in access instructions generated by the first subprogram as target test instructions; the first load instruction is different from the first store instruction in access address;
The sequence setting submodule is specifically configured to:
and under the condition that the verification requirement information characterizes basic verification, setting the instruction sending sequence for the target test instruction to be out-of-order sending.
Optionally, the target determination submodule is specifically configured to:
under the condition that the verification requirement information characterizes access violation verification, determining a plurality of access instruction groups in access instructions generated by the first subprogram as target test instructions; any one of the access instruction groups comprises a second loading instruction and a second storing instruction, wherein the second loading instruction and the second storing instruction have the same access address;
the sequence setting submodule is specifically configured to:
and setting the instruction sending sequence for each access instruction group in the target test instruction to be the second loading instruction before the second storing instruction under the condition that the verification requirement information characterizes access violation verification.
Optionally, the target determination submodule is specifically configured to:
under the condition that the verification requirement information characterizes access violation verification, determining a plurality of loading instruction groups in access instructions generated by the first subprogram as target test instructions; any one of the load instruction groups comprises a third load instruction and a fourth load instruction, wherein the access address of the third load instruction is the same as that of the fourth load instruction;
The sequence setting submodule is specifically configured to: and setting an instruction sending sequence for each loading instruction group in the target test instruction to be that the third loading instruction is before the fourth loading instruction or that the fourth loading instruction is before the third loading instruction under the condition that the verification requirement information characterizes access violation verification.
Optionally, the verification module includes:
the sending sub-module is used for sending the target test instruction to the memory module and the reference module according to the instruction sending sequence based on the first sub-program;
the output acquisition sub-module is used for acquiring output data of the memory access module in response to the target test instruction as a first output, and acquiring output data of the reference module in response to the target test instruction as a second output;
and the result determining submodule is used for determining that the verification result of the access module meets the requirement under the condition that the first output is consistent with the second output.
In summary, the embodiment of the invention provides a memory access verification system, which is used for describing operation behaviors required by running a memory access module to be verified by acquiring functional behavior information of the memory access module to be verified; constructing a test program based on the functional behavior information, wherein the test program at least comprises a first subprogram; the first subprogram is used for generating a memory access instruction and setting an instruction sending sequence, and the instruction sending sequence is used for representing the sequence of sending a loading instruction and a storage instruction in the memory access instruction to the memory access module; and verifying the access module based on the first subprogram. Compared with the method for verifying through random instructions in the prior art, the access verification method provided by the embodiment of the invention has the advantages that the test program comprising the first subprogram is constructed, the access instructions can be generated through the first subprogram, and the instruction sending sequence is set, so that the constraint on the test is realized through the first subprogram, different access verification requirements can be met according to the instruction sending sequence, more test points are covered, the access verification effect is improved, and the problems of consuming a large amount of time and equipment resources caused by using the random instructions to cover the test points are avoided. Meanwhile, compared with a method for verifying the memory access module by constructing the whole peripheral circuit, the memory access verification method provided by the embodiment of the invention does not need to configure the peripheral circuit, only needs to construct a test program according to the functional behavior information of the memory access module, and greatly reduces the difficulty of constructing a test frame.
For system embodiments, the description is relatively simple as it is substantially similar to method embodiments, and reference is made to the description of method embodiments for relevant points.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The specific manner in which the various modules perform operations in connection with the memory verification system of the above-described embodiments has been described in detail in connection with embodiments of the method and will not be described in detail herein.
The embodiment of the invention also provides electronic equipment, which comprises: the memory device comprises a processor and a memory for storing processor executable instructions, wherein the processor is configured to execute the memory verification method.
Referring to fig. 4, a schematic structural diagram of an electronic device according to an embodiment of the present invention is shown. As shown in fig. 4, the electronic device includes: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing at least one executable instruction, and the executable instruction causes the processor to execute the access verification method of the foregoing embodiment.
It should be noted that, the electronic device in the embodiment of the present application includes a mobile electronic device and a non-mobile electronic device.
The processor may be a CPU (Central Processing Unit ), general purpose processor, DSP (Digital Signal Processor ), ASIC (Application Specific Integrated Circuit, application specific integrated circuit), FPGA (Field Programmble Gate Array, field programmable gate array) or other editable device, transistor logic device, hardware components, or any combination thereof. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, etc.
The communication bus may include a path to transfer information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture ) bus, or the like. The communication bus may be classified into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in fig. 4, but not only one bus or one type of bus.
The memory may be a ROM (Read Only memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only, electrically erasable programmable Read Only memory), a CD-ROM (Compact Disa Read Only, compact disc Read Only), a magnetic tape, a floppy disk, an optical data storage device, and the like.
The embodiments of the present invention also provide a non-transitory computer-readable storage medium, which when executed by a processor of an electronic device (server or terminal), enables the processor to perform the memory access verification method shown in fig. 1.
The embodiment of the invention also provides a computer program product containing instructions, which when run on a computer, cause the computer to execute the memory access verification method shown in fig. 1.
The embodiment of the application also provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the embodiment of the access verification method, and can achieve the same technical effect, so that repetition is avoided, and the repeated description is omitted.
It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may be implemented, in whole or in part, in software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
It should be noted that, in the embodiment of the present application, the various data-related processes are all performed under the condition of conforming to the corresponding data protection rule policy of the country of the location and obtaining the authorization given by the owner of the corresponding device.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The above description of the present invention provides a memory access verification method, system, electronic device and readable storage medium, and specific examples are applied to illustrate the principles and embodiments of the present invention, where the above description of the embodiments is only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.