技术领域Technical field
本发明涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。The present invention relates to the field of display technology, and in particular, to a pixel circuit, a driving method and a display device.
背景技术Background technique
在相关技术中，随着显示产品的尺寸增加，形态变更(横屏变竖屏)，导致一行扫描时间减小，相关的像素电路在同一时间段进行数据写入和阈值电压补偿，使得阈值电压补偿时间小于一行扫描时间，导致在高频、高分辨率下阈值电压补偿时间不够，影响画质。In related technologies, as the size of display products increases and the form changes (horizontal screen changes to vertical screen), the scanning time of one line decreases. The related pixel circuit performs data writing and threshold voltage compensation at the same time period, so that the threshold voltage The compensation time is less than the scanning time of one line, resulting in insufficient threshold voltage compensation time at high frequency and high resolution, affecting the image quality.
发明内容Contents of the invention
在一个方面中，本发明实施例提供一种像素电路，包括发光元件、驱动电路、第一储能电路、数据写入电路和补偿控制电路；In one aspect, an embodiment of the present invention provides a pixel circuit, including a light-emitting element, a driving circuit, a first energy storage circuit, a data writing circuit and a compensation control circuit;
所述第一储能电路的第一端与第一节点电连接，所述第一储能电路的第二端与第二节点电连接；所述第一储能电路用于储存电能；The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the second node; the first energy storage circuit is used to store electrical energy;
所述驱动电路的控制端与所述第一节点电连接，所述驱动电路的第一端与第三节点电连接，所述驱动电路的第二端与所述发光元件电连接，所述驱动电路用于在所述第一节点的电位的控制下，控制产生驱动所述发光元件的驱动电流；The control end of the drive circuit is electrically connected to the first node, the first end of the drive circuit is electrically connected to the third node, the second end of the drive circuit is electrically connected to the light-emitting element, and the drive circuit is electrically connected to the third node. The circuit is configured to control and generate a driving current for driving the light-emitting element under the control of the potential of the first node;
所述数据写入电路分别与写入控制线、数据线和所述第二节点电连接，用于在所述写入控制线提供的写入控制信号的控制下，控制所述数据线与所述第二节点之间连通或断开；The data writing circuit is electrically connected to the writing control line, the data line and the second node respectively, and is used to control the data line and the second node under the control of the writing control signal provided by the writing control line. The second nodes are connected or disconnected;
所述补偿控制电路分别与补偿控制线、所述第一节点和补偿节点电连接，用于在所述补偿控制线提供的补偿控制信号的控制下，控制所述第一节点和所述补偿节点之间连通或断开；The compensation control circuit is electrically connected to the compensation control line, the first node and the compensation node respectively, and is used to control the first node and the compensation node under the control of the compensation control signal provided by the compensation control line. connected or disconnected;
所述补偿节点为所述第三节点，或者，所述补偿节点与所述驱动电路的第二端电连接。The compensation node is the third node, or the compensation node is electrically connected to the second end of the driving circuit.
可选的，所述写入控制线和所述补偿控制线为不同的信号线，用于提供不同的信号。Optionally, the write control line and the compensation control line are different signal lines for providing different signals.
可选的，当所述补偿节点为所述第三节点时，所述像素电路还包括第二储能电路和第一初始化电路；Optionally, when the compensation node is the third node, the pixel circuit further includes a second energy storage circuit and a first initialization circuit;
所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与第四节点电连接，所述第二储能电路用于储存电能；The first end of the second energy storage circuit is electrically connected to the second node, the second end of the second energy storage circuit is electrically connected to the fourth node, and the second energy storage circuit is used to store electrical energy;
所述第一初始化电路分别与所述第一初始控制线、第一初始电压端和所述第四节点电连接，用于在所述第一初始控制线提供的第一初始控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述第四节点。The first initialization circuit is electrically connected to the first initial control line, the first initial voltage terminal and the fourth node respectively, for controlling the first initial control signal provided by the first initial control line. , writing the first initial voltage provided by the first initial voltage terminal into the fourth node.
可选的，本发明至少一实施例所述的像素电路还包括第二初始化电路；Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a second initialization circuit;
所述第二初始化电路分别与第二初始控制线、第二初始电压端和所述第二节点电连接，用于在所述第二初始控制线提供的第二初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述第二节点。The second initialization circuit is electrically connected to the second initial control line, the second initial voltage terminal and the second node respectively, and is used to control the second initialization circuit under the control of the second initial control signal provided by the second initial control line. The second initial voltage provided by the second initial voltage terminal is written into the second node.
可选的，所述写入控制线和所述第一初始控制线为同一控制线。Optionally, the write control line and the first initial control line are the same control line.
可选的，所述第一储能电路包括第一电容，所述驱动电路包括驱动晶体管，所述数据写入电路包括第一晶体管，所述补偿控制电路包括第二晶体管；Optionally, the first energy storage circuit includes a first capacitor, the driving circuit includes a driving transistor, the data writing circuit includes a first transistor, and the compensation control circuit includes a second transistor;
所述第一电容的第一端与第一节点电连接，所述第一电容的第二端与第二节点电连接；The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the second node;
所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与第三节点电连接，所述驱动晶体管的第二极与所述发光元件电连接；The gate electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the third node, and the second electrode of the driving transistor is electrically connected to the light-emitting element;
所述第一晶体管的栅极与所述写入控制线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述第二节点电连接；The gate electrode of the first transistor is electrically connected to the write control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second node. electrical connection;
所述第二晶体管的栅极与所述补偿控制线电连接，所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述补偿节点电连接。The gate of the second transistor is electrically connected to the compensation control line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the compensation node. connect.
可选的，所述第二储能电路包括第二电容，所述第一初始化电路包括第三晶体管；Optionally, the second energy storage circuit includes a second capacitor, and the first initialization circuit includes a third transistor;
所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与第四节点电连接；The first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is electrically connected to the fourth node;
所述第三晶体管的栅极与所述第一初始控制线电连接，所述第三晶体管的第一极与所述第一初始电压端电连接，所述第三晶体管的第二极与所述第四节点电连接。The gate of the third transistor is electrically connected to the first initial control line, the first pole of the third transistor is electrically connected to the first initial voltage terminal, and the second pole of the third transistor is electrically connected to the first initial control line. The fourth node is electrically connected.
可选的，所述第二初始化电路包括第四晶体管；Optionally, the second initialization circuit includes a fourth transistor;
所述第四晶体管的栅极与所述第二初始控制线电连接，所述第四晶体管的第一极与所述第二初始电压端电连接，所述第四晶体管的第二极与所述第二节点电连接。The gate of the fourth transistor is electrically connected to the second initial control line, the first pole of the fourth transistor is electrically connected to the second initial voltage terminal, and the second pole of the fourth transistor is electrically connected to the second initial control line. The second node is electrically connected.
可选的，当所述补偿节点与所述驱动电路的第二端电连接时，所述像素电路还包括第二储能电路和第三初始化电路；Optionally, when the compensation node is electrically connected to the second end of the driving circuit, the pixel circuit further includes a second energy storage circuit and a third initialization circuit;
所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与所述第三节点电连接，所述第二储能电路用于储存电能；The first end of the second energy storage circuit is electrically connected to the second node, the second end of the second energy storage circuit is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy;
所述第三初始化电路分别与第三初始控制线、第三初始电压端和所述第一节点电连接，用于在所述第三初始控制线提供的第三初始控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述第一节点。The third initialization circuit is electrically connected to the third initial control line, the third initial voltage terminal and the first node respectively, and is used to control the third initialization circuit under the control of the third initial control signal provided by the third initial control line. The third initial voltage provided by the third initial voltage terminal is written into the first node.
可选的，本发明至少一实施例所述的像素电路还包括第四初始化电路；Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a fourth initialization circuit;
所述第四初始化电路分别与第四初始控制线、第一电压端和所述第二节点电连接，用于在所述第四初始控制线提供的第四初始控制信号的控制下，控制所述第一电压端与所述第二节点之间连通或断开。The fourth initialization circuit is electrically connected to the fourth initial control line, the first voltage terminal and the second node respectively, and is used to control all the parameters under the control of the fourth initial control signal provided by the fourth initial control line. The first voltage terminal and the second node are connected or disconnected.
可选的，本发明至少一实施例所述的像素电路还包括第五初始化电路；Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a fifth initialization circuit;
所述第五初始化电路分别与第五初始控制线、所述第四节点和所述发光元件的第一极电连接，用于在所述第五初始控制线提供的第五初始控制信号的控制下，控制所述第四节点与所述发光元件的第一极之间连通或断开；The fifth initialization circuit is electrically connected to the fifth initial control line, the fourth node and the first pole of the light-emitting element respectively, and is used for controlling the fifth initial control signal provided on the fifth initial control line. Next, control the connection or disconnection between the fourth node and the first pole of the light-emitting element;
所述发光元件的第二极与第二电压端电连接。The second pole of the light-emitting element is electrically connected to the second voltage terminal.
可选的，本发明至少一实施例所述的像素电路还包括第一发光控制电路和/或第二发光控制电路；Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a first light emission control circuit and/or a second light emission control circuit;
所述第一发光控制电路分别与第一发光控制线、第一电压端和所述第三节点电连接，用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通或断开；The first light-emitting control circuit is electrically connected to the first light-emitting control line, the first voltage terminal and the third node respectively, and is used to control under the control of the first light-emitting control signal provided by the first light-emitting control line. The first voltage terminal is connected or disconnected from the first terminal of the driving circuit;
所述第二发光控制电路分别与第二发光控制线、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通或断开。The second light-emitting control circuit is electrically connected to the second light-emitting control line, the second end of the driving circuit and the first pole of the light-emitting element respectively, for providing the second light-emitting light in the second light-emitting control line. Under the control of the control signal, the second terminal of the driving circuit and the first pole of the light-emitting element are controlled to be connected or disconnected.
可选的，当所述像素电路包括第二发光控制电路时，所述像素电路还包括第六初始化电路；Optionally, when the pixel circuit includes a second light emission control circuit, the pixel circuit further includes a sixth initialization circuit;
所述第六初始化电路分别与第六初始控制线、第四初始电压端和所述发光元件的第一极电连接，用于在所述第六初始控制线提供的第六初始控制信号的控制下，将所述第四初始电压端提供的第四初始电压写入所述发光元件的第一极。The sixth initialization circuit is electrically connected to the sixth initial control line, the fourth initial voltage terminal and the first pole of the light-emitting element respectively, and is used for controlling the sixth initial control signal provided on the sixth initial control line. Next, the fourth initial voltage provided by the fourth initial voltage terminal is written into the first pole of the light-emitting element.
可选的，所述第二储能电路包括第二电容，所述第三初始化电路包括第五晶体管；Optionally, the second energy storage circuit includes a second capacitor, and the third initialization circuit includes a fifth transistor;
所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与所述第三节点电连接；The first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is electrically connected to the third node;
所述第五晶体管的栅极与所述第三初始控制线电连接，所述第五晶体管的第一极与所述第三初始电压端电连接，所述第五晶体管的第二极与所述第一节点电连接。The gate of the fifth transistor is electrically connected to the third initial control line, the first electrode of the fifth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the third initial control line. The first node is electrically connected.
可选的，所述第四初始化电路包括第六晶体管；Optionally, the fourth initialization circuit includes a sixth transistor;
所述第六晶体管的栅极与所述第四初始控制线电连接，所述第六晶体管的第一极与所述第一电压端电连接，所述第六晶体管的第二极与所述第二节点电连接。The gate of the sixth transistor is electrically connected to the fourth initial control line, the first electrode of the sixth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal. The second node is electrically connected.
可选的，所述第五初始化电路包括第七晶体管；Optionally, the fifth initialization circuit includes a seventh transistor;
所述第七晶体管的栅极与所述第五初始控制线电连接，所述第七晶体管的第一极与所述第四节点电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。The gate electrode of the seventh transistor is electrically connected to the fifth initial control line, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the light emitting The first pole of the component is electrically connected.
可选的，所述第一发光控制电路包括第八晶体管，所述第二发光控制电路包括第九晶体管；Optionally, the first lighting control circuit includes an eighth transistor, and the second lighting control circuit includes a ninth transistor;
所述第八晶体管的栅极与所述第一发光控制线电连接，所述第八晶体管的第一极与所述第一电压端电连接，所述第八晶体管的第二极与所述第三节点电连接；The gate electrode of the eighth transistor is electrically connected to the first light emitting control line, the first electrode of the eighth transistor is electrically connected to the first voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first voltage terminal. The third node is electrically connected;
所述第九晶体管的栅极与所述第二发光控制线电连接，所述第九晶体管的第一极与所述驱动电路的第二端电连接，所述第九晶体管的第二极与所述发光元件的第一极电连接。The gate electrode of the ninth transistor is electrically connected to the second light emitting control line, the first electrode of the ninth transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the ninth transistor is electrically connected to the second light emitting control line. The first electrode of the light-emitting element is electrically connected.
可选的，所述第六初始化电路包括第十晶体管；Optionally, the sixth initialization circuit includes a tenth transistor;
所述第十晶体管的栅极与所述第六初始控制线电连接，所述第十晶体管的第一极与所述第四初始电压端电连接，所述第十晶体管的第二极与所述发光元件的第一极电连接。The gate electrode of the tenth transistor is electrically connected to the sixth initial control line, the first electrode of the tenth transistor is electrically connected to the fourth initial voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth initial voltage terminal. The first electrode of the light-emitting element is electrically connected.
在第二个方面中，本发明实施例提供一种驱动方法，应用于上述的像素电路，显示周期包括相互独立的采样阶段和数据写入阶段；所述驱动方法包括：In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned pixel circuit. The display cycle includes a sampling phase and a data writing phase that are independent of each other; the driving method includes:
在采样阶段，补偿控制电路在补偿控制线提供的补偿控制信号的控制下，控制第一节点和补偿节点之间连通，以进行阈值电压补偿；In the sampling stage, the compensation control circuit controls the connection between the first node and the compensation node to perform threshold voltage compensation under the control of the compensation control signal provided by the compensation control line;
在数据写入阶段，数据写入电路在写入控制线提供的写入控制信号的控制下，控制数据线与第二节点之间连通，以将所述数据线提供的数据电压写入所述第二节点。In the data writing stage, the data writing circuit controls the connection between the data line and the second node under the control of the writing control signal provided by the writing control line, so as to write the data voltage provided by the data line into the Second node.
在第二个方面中，本发明实施例提供一种显示装置，包括上述的像素电路。In a second aspect, an embodiment of the present invention provides a display device including the above-mentioned pixel circuit.
附图说明Description of the drawings
图1是本发明至少一实施例所述的像素电路的结构图；Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;
图2是本发明至少一实施例所述的像素电路的结构图；Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;
图3是本发明至少一实施例所述的像素电路的结构图；Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;
图4是本发明至少一实施例所述的像素电路的结构图；Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;
图5是本发明至少一实施例所述的像素电路的结构图；Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;
图6是本发明至少一实施例所述的像素电路的电路图；Figure 6 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;
图7是图6所示的像素电路的至少一实施例的工作时序图；Figure 7 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 6;
图8是本发明至少一实施例所述的像素电路的电路图；Figure 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;
图9是本发明至少一实施例所述的像素电路的电路图；Figure 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;
图10是图9所示的像素电路的至少一实施例的工作时序图；Figure 10 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 9;
图11是本发明至少一实施例所述的像素电路的电路图。FIG. 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.
本发明所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。The transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate electrode, one pole is called the first pole and the other pole is called the second pole.
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, The second electrode may be a drain electrode.
本发明实施例所述的像素电路包括发光元件、驱动电路、第一储能电路、数据写入电路和补偿控制电路；The pixel circuit according to the embodiment of the present invention includes a light-emitting element, a driving circuit, a first energy storage circuit, a data writing circuit and a compensation control circuit;
所述第一储能电路的第一端与第一节点电连接，所述第一储能电路的第二端与第二节点电连接；所述第一储能电路用于储存电能；The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the second node; the first energy storage circuit is used to store electrical energy;
所述驱动电路的控制端与所述第一节点电连接，所述驱动电路的第一端与第三节点电连接，所述驱动电路的第二端与所述发光元件电连接，所述驱动电路用于在所述第一节点的电位的控制下，控制产生驱动所述发光元件的驱动电流；The control end of the drive circuit is electrically connected to the first node, the first end of the drive circuit is electrically connected to the third node, the second end of the drive circuit is electrically connected to the light-emitting element, and the drive circuit is electrically connected to the third node. The circuit is configured to control and generate a driving current for driving the light-emitting element under the control of the potential of the first node;
所述数据写入电路分别与写入控制线、数据线和所述第二节点电连接，用于在所述写入控制线提供的写入控制信号的控制下，控制所述数据线与所述第二节点之间连通或断开；The data writing circuit is electrically connected to the writing control line, the data line and the second node respectively, and is used to control the data line and the second node under the control of the writing control signal provided by the writing control line. The second nodes are connected or disconnected;
所述补偿控制电路分别与补偿控制线、所述第一节点和补偿节点电连接，用于在所述补偿控制线提供的补偿控制信号的控制下，控制所述第一节点和所述补偿节点之间连通或断开；The compensation control circuit is electrically connected to the compensation control line, the first node and the compensation node respectively, and is used to control the first node and the compensation node under the control of the compensation control signal provided by the compensation control line. connected or disconnected;
所述补偿节点为所述第三节点，或者，所述补偿节点与所述驱动电路的第二端电连接。The compensation node is the third node, or the compensation node is electrically connected to the second end of the driving circuit.
本发明实施例所述的像素电路将数据电压写入和阈值电压补偿分时段进行，以使得阈值电压补偿的时间得以延长，使得阈值电压补偿效果更加充分，并且可以支持高频显示。The pixel circuit described in the embodiment of the present invention performs data voltage writing and threshold voltage compensation in time intervals, so that the threshold voltage compensation time is extended, the threshold voltage compensation effect is more sufficient, and high-frequency display can be supported.
在相关技术中，随着显示产品的尺寸增加，形态变更(横屏变竖屏)，导致一行扫描时间减小，相关的像素电路在同一时间段进行数据写入和阈值电压补偿，使得阈值电压补偿时间小于一行扫描时间，导致在高频、高分辨率下阈值电压补偿时间不够，影响画质。基于此，本发明实施例将阈值电压补偿和数据电压写入分离，则阈值电压补偿时间可以大于一行扫描时间，使得阈值电压补偿时间更长，画质更优。In related technologies, as the size of display products increases and the form changes (horizontal screen changes to vertical screen), the scanning time of one line decreases. The related pixel circuit performs data writing and threshold voltage compensation at the same time period, so that the threshold voltage The compensation time is less than the scanning time of one line, resulting in insufficient threshold voltage compensation time at high frequency and high resolution, affecting the image quality. Based on this, embodiments of the present invention separate threshold voltage compensation and data voltage writing, so that the threshold voltage compensation time can be longer than one line of scanning time, so that the threshold voltage compensation time is longer and the image quality is better.
在本发明至少一实施例中，所述写入控制线和所述补偿控制线为不同的信号线，用于提供不同的信号。In at least one embodiment of the present invention, the write control line and the compensation control line are different signal lines for providing different signals.
在具体实施时，所述写入控制线和所述补偿控制线可以用于提供不同的信号，以保证数据写入和阈值电压补偿在不同的时间段进行。During specific implementation, the write control line and the compensation control line may be used to provide different signals to ensure that data writing and threshold voltage compensation are performed in different time periods.
如图1所示，本发明至少一实施例所述的像素电路包括发光元件E0、驱动电路11、第一储能电路12、数据写入电路13和补偿控制电路14；As shown in Figure 1, the pixel circuit according to at least one embodiment of the present invention includes a light-emitting element E0, a driving circuit 11, a first energy storage circuit 12, a data writing circuit 13 and a compensation control circuit 14;
所述第一储能电路12的第一端与第一节点N1电连接，所述第一储能电路12的第二端与第二节点N2电连接；所述第一储能电路12用于储存电能；The first end of the first energy storage circuit 12 is electrically connected to the first node N1, and the second end of the first energy storage circuit 12 is electrically connected to the second node N2; the first energy storage circuit 12 is used for store electrical energy;
所述驱动电路11的控制端与所述第一节点N1电连接，所述驱动电路11的第一端与第三节点N3电连接，所述驱动电路11的第二端与所述发光元件E0电连接，所述驱动电路11用于在所述第一节点N1的电位的控制下，控制产生驱动所述发光元件E0的驱动电流；The control end of the drive circuit 11 is electrically connected to the first node N1, the first end of the drive circuit 11 is electrically connected to the third node N3, and the second end of the drive circuit 11 is electrically connected to the light emitting element E0. Electrically connected, the driving circuit 11 is used to control the generation of a driving current for driving the light-emitting element E0 under the control of the potential of the first node N1;
所述数据写入电路13分别与写入控制线GX、数据线Data和所述第二节点N2电连接，用于在所述写入控制线GX提供的写入控制信号的控制下，控制所述数据线Data与所述第二节点N2之间连通或断开；The data writing circuit 13 is electrically connected to the writing control line GX, the data line Data and the second node N2 respectively, and is used to control the writing control signal provided by the writing control line GX. The data line Data is connected or disconnected from the second node N2;
所述补偿控制电路14分别与补偿控制线GB、所述第一节点N1和第三节点N3电连接，用于在所述补偿控制线GB提供的补偿控制信号的控制下，控制所述第一节点N1和所述第三节点N3之间连通或断开；The compensation control circuit 14 is electrically connected to the compensation control line GB, the first node N1 and the third node N3 respectively, and is used to control the first node under the control of the compensation control signal provided by the compensation control line GB. The node N1 and the third node N3 are connected or disconnected;
所述补偿节点为所述第三节点N3。The compensation node is the third node N3.
如图2所示，本发明至少一实施例所述的像素电路包括发光元件E0、驱动电路11、第一储能电路12、数据写入电路13和补偿控制电路14；As shown in Figure 2, the pixel circuit according to at least one embodiment of the present invention includes a light-emitting element E0, a driving circuit 11, a first energy storage circuit 12, a data writing circuit 13 and a compensation control circuit 14;
所述第一储能电路12的第一端与第一节点N1电连接，所述第一储能电路12的第二端与第二节点N2电连接；所述第一储能电路12用于储存电能；The first end of the first energy storage circuit 12 is electrically connected to the first node N1, and the second end of the first energy storage circuit 12 is electrically connected to the second node N2; the first energy storage circuit 12 is used for store electrical energy;
所述驱动电路11的控制端与所述第一节点N1电连接，所述驱动电路11的第一端与第三节点N3电连接，所述驱动电路11的第二端与所述发光元件E0电连接，所述驱动电路11用于在所述第一节点N1的电位的控制下，控制产生驱动所述发光元件E0的驱动电流；The control end of the drive circuit 11 is electrically connected to the first node N1, the first end of the drive circuit 11 is electrically connected to the third node N3, and the second end of the drive circuit 11 is electrically connected to the light emitting element E0. Electrically connected, the driving circuit 11 is used to control the generation of a driving current for driving the light-emitting element E0 under the control of the potential of the first node N1;
所述数据写入电路13分别与写入控制线GX、数据线Data和所述第二节点N2电连接，用于在所述写入控制线GX提供的写入控制信号的控制下，控制所述数据线Data与所述第二节点N2之间连通或断开；The data writing circuit 13 is electrically connected to the writing control line GX, the data line Data and the second node N2 respectively, and is used to control the writing control signal provided by the writing control line GX. The data line Data is connected or disconnected from the second node N2;
所述补偿控制电路14分别与补偿控制线GB、所述第一节点N1和补偿节点电连接，用于在所述补偿控制线GB提供的补偿控制信号的控制下，控制所述第一节点N1和所述补偿节点之间连通或断开；The compensation control circuit 14 is electrically connected to the compensation control line GB, the first node N1 and the compensation node respectively, and is used to control the first node N1 under the control of the compensation control signal provided by the compensation control line GB. Connected or disconnected from the compensation node;
所述补偿节点与所述驱动电路11的第二端电连接。The compensation node is electrically connected to the second terminal of the driving circuit 11 .
在本发明至少一实施例中，当所述补偿节点为所述第三节点时，所述像素电路还包括第二储能电路和第一初始化电路；In at least one embodiment of the present invention, when the compensation node is the third node, the pixel circuit further includes a second energy storage circuit and a first initialization circuit;
所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与第四节点电连接，所述第二储能电路用于储存电能；The first end of the second energy storage circuit is electrically connected to the second node, the second end of the second energy storage circuit is electrically connected to the fourth node, and the second energy storage circuit is used to store electrical energy;
所述第一初始化电路分别与所述第一初始控制线、第一初始电压端和所述第四节点电连接，用于在所述第一初始控制线提供的第一初始控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述第四节点。The first initialization circuit is electrically connected to the first initial control line, the first initial voltage terminal and the fourth node respectively, for controlling the first initial control signal provided by the first initial control line. , writing the first initial voltage provided by the first initial voltage terminal into the fourth node.
在具体实施时，当所述补偿节点为第三节点时，所述像素电路还可以包括第二储能电路和第一初始化电路，第二储能电路分别与第二节点和第四节点电连接，第一初始化电路在第一初始控制信号的控制下，将第一初始电压写入第四节点，以对第四节点的电位进行初始化。In specific implementation, when the compensation node is a third node, the pixel circuit may further include a second energy storage circuit and a first initialization circuit, and the second energy storage circuit is electrically connected to the second node and the fourth node respectively. , the first initialization circuit writes the first initial voltage into the fourth node under the control of the first initial control signal to initialize the potential of the fourth node.
本发明至少一实施例所述的像素电路还包括第二初始化电路；The pixel circuit according to at least one embodiment of the present invention further includes a second initialization circuit;
所述第二初始化电路分别与第二初始控制线、第二初始电压端和所述第二节点电连接，用于在所述第二初始控制线提供的第二初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述第二节点。The second initialization circuit is electrically connected to the second initial control line, the second initial voltage terminal and the second node respectively, and is used to control the second initialization circuit under the control of the second initial control signal provided by the second initial control line. The second initial voltage provided by the second initial voltage terminal is written into the second node.
在具体实施时，所述像素电路还可以包括第二初始化电路，第二初始化电路在第二初始控制信号的控制下，将第二初始电压写入第二节点，以对第二节点的电位进行初始化。In specific implementation, the pixel circuit may further include a second initialization circuit. The second initialization circuit writes the second initial voltage to the second node under the control of the second initial control signal to adjust the potential of the second node. initialization.
可选的，所述写入控制线和所述第一初始控制线为同一控制线。Optionally, the write control line and the first initial control line are the same control line.
在具体实施时，所述写入控制线和所述第一初始控制线可以为同一控制线，以节省布线空间。In specific implementation, the write control line and the first initial control line may be the same control line to save wiring space.
可选的，所述第一储能电路包括第一电容，所述驱动电路包括驱动晶体管，所述数据写入电路包括第一晶体管，所述补偿控制电路包括第二晶体管；Optionally, the first energy storage circuit includes a first capacitor, the driving circuit includes a driving transistor, the data writing circuit includes a first transistor, and the compensation control circuit includes a second transistor;
所述第一电容的第一端与第一节点电连接，所述第一电容的第二端与第二节点电连接；The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the second node;
所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与第三节点电连接，所述驱动晶体管的第二极与所述发光元件电连接；The gate electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the third node, and the second electrode of the driving transistor is electrically connected to the light-emitting element;
所述第一晶体管的栅极与所述写入控制线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述第二节点电连接；The gate electrode of the first transistor is electrically connected to the write control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second node. electrical connection;
所述第二晶体管的栅极与所述补偿控制线电连接，所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述补偿节点电连接。The gate of the second transistor is electrically connected to the compensation control line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the compensation node. connect.
可选的，所述第二储能电路包括第二电容，所述第一初始化电路包括第三晶体管；Optionally, the second energy storage circuit includes a second capacitor, and the first initialization circuit includes a third transistor;
所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与第四节点电连接；The first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is electrically connected to the fourth node;
所述第三晶体管的栅极与所述第一初始控制线电连接，所述第三晶体管的第一极与所述第一初始电压端电连接，所述第三晶体管的第二极与所述第四节点电连接。The gate of the third transistor is electrically connected to the first initial control line, the first pole of the third transistor is electrically connected to the first initial voltage terminal, and the second pole of the third transistor is electrically connected to the first initial control line. The fourth node is electrically connected.
可选的，所述第二初始化电路包括第四晶体管；Optionally, the second initialization circuit includes a fourth transistor;
所述第四晶体管的栅极与所述第二初始控制线电连接，所述第四晶体管的第一极与所述第二初始电压端电连接，所述第四晶体管的第二极与所述第二节点电连接。The gate of the fourth transistor is electrically connected to the second initial control line, the first pole of the fourth transistor is electrically connected to the second initial voltage terminal, and the second pole of the fourth transistor is electrically connected to the second initial control line. The second node is electrically connected.
在本发明至少一实施例中，当所述补偿节点与所述驱动电路的第二端电连接时，所述像素电路还包括第二储能电路和第三初始化电路；In at least one embodiment of the present invention, when the compensation node is electrically connected to the second end of the driving circuit, the pixel circuit further includes a second energy storage circuit and a third initialization circuit;
所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与所述第三节点电连接，所述第二储能电路用于储存电能；The first end of the second energy storage circuit is electrically connected to the second node, the second end of the second energy storage circuit is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy;
所述第三初始化电路分别与第三初始控制线、第三初始电压端和所述第一节点电连接，用于在所述第三初始控制线提供的第三初始控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述第一节点。The third initialization circuit is electrically connected to the third initial control line, the third initial voltage terminal and the first node respectively, and is used to control the third initialization circuit under the control of the third initial control signal provided by the third initial control line. The third initial voltage provided by the third initial voltage terminal is written into the first node.
在具体实施时，所述像素电路还可以包括第二储能电路和第三初始化电路，第二储能电路分别与第二节点和第三节点电连接，所述第三初始化电路在第三初始控制信号的控制下，将第三初始电压写入第一节点，以对第一节点的电位进行初始化。In specific implementation, the pixel circuit may further include a second energy storage circuit and a third initialization circuit. The second energy storage circuit is electrically connected to the second node and the third node respectively. The third initialization circuit performs a third initialization step. Under the control of the control signal, the third initial voltage is written into the first node to initialize the potential of the first node.
本发明至少一实施例所述的像素电路还包括第四初始化电路；The pixel circuit according to at least one embodiment of the present invention further includes a fourth initialization circuit;
所述第四初始化电路分别与第四初始控制线、第一电压端和所述第二节点电连接，用于在所述第四初始控制线提供的第四初始控制信号的控制下，控制所述第一电压端与所述第二节点之间连通或断开。The fourth initialization circuit is electrically connected to the fourth initial control line, the first voltage terminal and the second node respectively, and is used to control all the parameters under the control of the fourth initial control signal provided by the fourth initial control line. The first voltage terminal and the second node are connected or disconnected.
在具体实施时，所述像素电路还可以包括第四初始化电路，第四初始化电路在第四初始控制信号的控制下，控制所述第一电压端与第二节点之间连通，以对第二节点的电位进行初始化。In specific implementation, the pixel circuit may further include a fourth initialization circuit. The fourth initialization circuit controls the connection between the first voltage terminal and the second node under the control of the fourth initial control signal to control the second The potential of the node is initialized.
在本发明至少一实施例中，所述像素电路还包括第五初始化电路；In at least one embodiment of the present invention, the pixel circuit further includes a fifth initialization circuit;
所述第五初始化电路分别与第五初始控制线、所述第四节点和所述发光元件的第一极电连接，用于在所述第五初始控制线提供的第五初始控制信号的控制下，控制所述第四节点与所述发光元件的第一极之间连通或断开；The fifth initialization circuit is electrically connected to the fifth initial control line, the fourth node and the first pole of the light-emitting element respectively, and is used for controlling the fifth initial control signal provided on the fifth initial control line. Next, control the connection or disconnection between the fourth node and the first pole of the light-emitting element;
所述发光元件的第二极与第二电压端电连接。The second pole of the light-emitting element is electrically connected to the second voltage terminal.
在具体实施时，所述像素电路还可以包括第五初始化电路，第五初始化电路在第五初始控制信号的控制下，控制所述第四节点与发光元件的第一极之间连通，以对所述发光元件的第一极进行初始化，以控制所述发光元件不发光，并清除所述发光元件的第一极残留的电荷。In specific implementation, the pixel circuit may further include a fifth initialization circuit. The fifth initialization circuit controls the connection between the fourth node and the first pole of the light-emitting element under the control of the fifth initial control signal, so as to The first pole of the light-emitting element is initialized to control the light-emitting element not to emit light, and to clear the residual charge on the first pole of the light-emitting element.
本发明至少一实施例所述的像素电路还包括第一发光控制电路和/或第二发光控制电路；The pixel circuit according to at least one embodiment of the present invention further includes a first light emission control circuit and/or a second light emission control circuit;
所述第一发光控制电路分别与第一发光控制线、第一电压端和所述第三节点电连接，用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通或断开；The first light-emitting control circuit is electrically connected to the first light-emitting control line, the first voltage terminal and the third node respectively, and is used to control under the control of the first light-emitting control signal provided by the first light-emitting control line. The first voltage terminal is connected or disconnected from the first terminal of the driving circuit;
所述第二发光控制电路分别与第二发光控制线、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通或断开。The second light-emitting control circuit is electrically connected to the second light-emitting control line, the second end of the driving circuit and the first pole of the light-emitting element respectively, for providing the second light-emitting light in the second light-emitting control line. Under the control of the control signal, the second terminal of the driving circuit and the first pole of the light-emitting element are controlled to be connected or disconnected.
在具体实施时，所述像素电路可以包括第一发光控制电路和/或第二发光控制电路；所述第一发光控制电路在第一发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通或断开；所述第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通或断开，以进行发光控制。In specific implementation, the pixel circuit may include a first light-emitting control circuit and/or a second light-emitting control circuit; the first light-emitting control circuit controls the first voltage terminal and the The first terminal of the driving circuit is connected or disconnected; the second lighting control circuit controls the second terminal of the driving circuit and the first pole of the lighting element under the control of the second lighting control signal. connected or disconnected for lighting control.
可选的，当所述像素电路包括第二发光控制电路时，所述像素电路还包括第六初始化电路；Optionally, when the pixel circuit includes a second light emission control circuit, the pixel circuit further includes a sixth initialization circuit;
所述第六初始化电路分别与第六初始控制线、第四初始电压端和所述发光元件的第一极电连接，用于在所述第六初始控制线提供的第六初始控制信号的控制下，将所述第四初始电压端提供的第四初始电压写入所述发光元件的第一极。The sixth initialization circuit is electrically connected to the sixth initial control line, the fourth initial voltage terminal and the first pole of the light-emitting element respectively, and is used for controlling the sixth initial control signal provided on the sixth initial control line. Next, the fourth initial voltage provided by the fourth initial voltage terminal is written into the first pole of the light-emitting element.
可选的，所述第二储能电路包括第二电容，所述第三初始化电路包括第五晶体管；Optionally, the second energy storage circuit includes a second capacitor, and the third initialization circuit includes a fifth transistor;
所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与所述第三节点电连接；The first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is electrically connected to the third node;
所述第五晶体管的栅极与所述第三初始控制线电连接，所述第五晶体管的第一极与所述第三初始电压端电连接，所述第五晶体管的第二极与所述第一节点电连接。The gate of the fifth transistor is electrically connected to the third initial control line, the first electrode of the fifth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the third initial control line. The first node is electrically connected.
可选的，所述第四初始化电路包括第六晶体管；Optionally, the fourth initialization circuit includes a sixth transistor;
所述第六晶体管的栅极与所述第四初始控制线电连接，所述第六晶体管的第一极与所述第一电压端电连接，所述第六晶体管的第二极与所述第二节点电连接。The gate of the sixth transistor is electrically connected to the fourth initial control line, the first electrode of the sixth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal. The second node is electrically connected.
可选的，所述第五初始化电路包括第七晶体管；Optionally, the fifth initialization circuit includes a seventh transistor;
所述第七晶体管的栅极与所述第五初始控制线电连接，所述第七晶体管的第一极与所述第四节点电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。The gate electrode of the seventh transistor is electrically connected to the fifth initial control line, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the light emitting The first pole of the component is electrically connected.
可选的，所述第一发光控制电路包括第八晶体管，所述第二发光控制电路包括第九晶体管；Optionally, the first lighting control circuit includes an eighth transistor, and the second lighting control circuit includes a ninth transistor;
所述第八晶体管的栅极与所述第一发光控制线电连接，所述第八晶体管的第一极与所述第一电压端电连接，所述第八晶体管的第二极与所述第三节点电连接；The gate electrode of the eighth transistor is electrically connected to the first light emitting control line, the first electrode of the eighth transistor is electrically connected to the first voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first voltage terminal. The third node is electrically connected;
所述第九晶体管的栅极与所述第二发光控制线电连接，所述第九晶体管的第一极与所述驱动电路的第二端电连接，所述第九晶体管的第二极与所述发光元件的第一极电连接。The gate electrode of the ninth transistor is electrically connected to the second light emitting control line, the first electrode of the ninth transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the ninth transistor is electrically connected to the second light emitting control line. The first electrode of the light-emitting element is electrically connected.
所述第六初始化电路包括第十晶体管；The sixth initialization circuit includes a tenth transistor;
所述第十晶体管的栅极与所述第六初始控制线电连接，所述第十晶体管的第一极与所述第四初始电压端电连接，所述第十晶体管的第二极与所述发光元件的第一极电连接。The gate electrode of the tenth transistor is electrically connected to the sixth initial control line, the first electrode of the tenth transistor is electrically connected to the fourth initial voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth initial voltage terminal. The first electrode of the light-emitting element is electrically connected.
如图3所示，在图1所示的像素电路的至少一实施例的基础上，本发明至少一实施例所述的像素电路包括第二储能电路31、第一初始化电路32、第五初始化电路33和第一发光控制电路34；所述发光元件为微型发光二极管ML；As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit according to at least one embodiment of the present invention includes a second energy storage circuit 31, a first initialization circuit 32, a fifth Initialization circuit 33 and first light emitting control circuit 34; the light emitting element is a micro light emitting diode ML;
所述第二储能电路31的第一端与所述第二节点N2电连接，所述第二储能电路31的第二端与第四节点N4电连接，所述第二储能电路31用于储存电能；The first end of the second energy storage circuit 31 is electrically connected to the second node N2, and the second end of the second energy storage circuit 31 is electrically connected to the fourth node N4. The second energy storage circuit 31 Used to store electrical energy;
所述第一初始化电路32分别与所述第一扫描线Gate1、初始电压端I0和所述第四节点N4电连接，用于在所述第一扫描线Gate1提供的第一扫描信号的控制下，将所述初始电压端I0提供的初始电压Vinit写入所述第四节点N4；The first initialization circuit 32 is electrically connected to the first scan line Gate1, the initial voltage terminal I0 and the fourth node N4 respectively, for controlling the first scan signal provided by the first scan line Gate1. , write the initial voltage Vinit provided by the initial voltage terminal I0 into the fourth node N4;
所述第五初始化电路33分别与第二扫描线Gate2、所述第四节点N4和所述微型发光二极管ML的阳极电连接，用于在所述第二扫描线Gate2提供的第二扫描信号的控制下，控制所述第四节点与所述有机发光二极管ML的阳极之间连通或断开；The fifth initialization circuit 33 is electrically connected to the second scan line Gate2, the fourth node N4 and the anode of the micro light emitting diode ML respectively, and is used for the second scan signal provided on the second scan line Gate2. Under control, control the connection or disconnection between the fourth node and the anode of the organic light-emitting diode ML;
所述第一发光控制电路34分别与第一发光控制线EM1、高电压端VDD和所述第三节点N3电连接，用于在所述第一发光控制线EM1提供的第一发光控制信号的控制下，控制所述高电压端VDD与所述驱动电路11的第一端之间连通或断开；The first light-emitting control circuit 34 is electrically connected to the first light-emitting control line EM1, the high voltage terminal VDD and the third node N3 respectively, and is used for controlling the first light-emitting control signal provided by the first light-emitting control line EM1. Under control, control the connection or disconnection between the high voltage terminal VDD and the first terminal of the driving circuit 11;
所述微型发光二极管ML的阴极与低电压端VSS电连接；The cathode of the micro light-emitting diode ML is electrically connected to the low voltage terminal VSS;
所述数据写入电路13分别与第一扫描线Gate1、数据线Data和所述第二节点N2电连接，用于在所述第一扫描线Gate1提供的第一扫描信号的控制下，控制所述数据线Data与所述第二节点N2之间连通或断开；The data writing circuit 13 is electrically connected to the first scan line Gate1, the data line Data and the second node N2 respectively, and is used to control all the data under the control of the first scan signal provided by the first scan line Gate1. The data line Data is connected or disconnected from the second node N2;
所述补偿控制电路14分别与第三扫描线Gate3、所述第一节点N1和第三节点N3电连接，用于在所述第三扫描线Gate3提供的第三扫描信号的控制下，控制所述第一节点N1和所述第三节点N3之间连通或断开。The compensation control circuit 14 is electrically connected to the third scan line Gate3, the first node N1 and the third node N3 respectively, and is used to control all the scan signals under the control of the third scan signal provided by the third scan line Gate3. The first node N1 and the third node N3 are connected or disconnected.
可选的，所述第一电压端可以为高电压端。Optionally, the first voltage terminal may be a high voltage terminal.
在图3所示的至少一实施例中，第一初始控制线为第一扫描线Gate1，第五初始控制线为第二扫描线Gate2，所述写入控制线为第一扫描线Gate1，所述补偿控制线为第三扫描线Gate3，第一初始电压端为初始电压端I0，所述初始电压端I0用于提供初始电压Vinit。In at least one embodiment shown in FIG. 3, the first initial control line is the first scan line Gate1, the fifth initial control line is the second scan line Gate2, and the write control line is the first scan line Gate1, so The compensation control line is the third scan line Gate3, the first initial voltage terminal is the initial voltage terminal I0, and the initial voltage terminal I0 is used to provide the initial voltage Vinit.
如图4所示，在图1所示的像素电路的至少一实施例的基础上，本发明至少一实施例所述的像素电路包括第二储能电路31、第一初始化电路32、第五初始化电路33和第一发光控制电路34；所述发光元件为微型发光二极管ML；As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit according to at least one embodiment of the present invention includes a second energy storage circuit 31, a first initialization circuit 32, a fifth Initialization circuit 33 and first light emitting control circuit 34; the light emitting element is a micro light emitting diode ML;
所述第二储能电路31的第一端与所述第二节点N2电连接，所述第二储能电路31的第二端与第四节点N4电连接，所述第二储能电路31用于储存电能；The first end of the second energy storage circuit 31 is electrically connected to the second node N2, and the second end of the second energy storage circuit 31 is electrically connected to the fourth node N4. The second energy storage circuit 31 Used to store electrical energy;
所述第一初始化电路32分别与所述第一扫描线Gate1、初始电压端I0和所述第四节点N4电连接，用于在所述第一扫描线Gate1提供的第一扫描信号的控制下，将所述初始电压端I0提供的初始电压Vinit写入所述第四节点N4；The first initialization circuit 32 is electrically connected to the first scan line Gate1, the initial voltage terminal I0 and the fourth node N4 respectively, for controlling the first scan signal provided by the first scan line Gate1. , write the initial voltage Vinit provided by the initial voltage terminal I0 into the fourth node N4;
所述第五初始化电路33分别与第二扫描线Gate2、所述第四节点N4和所述微型发光二极管ML的阳极电连接，用于在所述第二扫描线Gate2提供的第二扫描信号的控制下，控制所述第四节点与所述有机发光二极管ML的阳极之间连通或断开；The fifth initialization circuit 33 is electrically connected to the second scan line Gate2, the fourth node N4 and the anode of the micro light emitting diode ML respectively, and is used for the second scan signal provided on the second scan line Gate2. Under control, control the connection or disconnection between the fourth node and the anode of the organic light-emitting diode ML;
所述第一发光控制电路34分别与第一发光控制线EM1、高电压端VDD和所述第三节点N3电连接，用于在所述第一发光控制线EM1提供的第一发光控制信号的控制下，控制所述高电压端VDD与所述驱动电路11的第一端之间连通或断开；The first light-emitting control circuit 34 is electrically connected to the first light-emitting control line EM1, the high voltage terminal VDD and the third node N3 respectively, and is used for controlling the first light-emitting control signal provided by the first light-emitting control line EM1. Under control, control the connection or disconnection between the high voltage terminal VDD and the first terminal of the driving circuit 11;
所述微型发光二极管ML的阴极与低电压端VSS电连接；The cathode of the micro light-emitting diode ML is electrically connected to the low voltage terminal VSS;
本发明至少一实施例所述的像素电路还包括第二初始化电路35；The pixel circuit according to at least one embodiment of the present invention also includes a second initialization circuit 35;
所述第二初始化电路35分别与初始控制线Gate、初始电压端I0和所述第二节点N2电连接，用于在所述初始控制线Gate提供的初始控制信号的控制下，将所述初始电压端I0提供的初始电压Vint写入所述第二节点N2；The second initialization circuit 35 is electrically connected to the initial control line Gate, the initial voltage terminal I0 and the second node N2 respectively, and is used to initialize the initialization circuit 35 under the control of the initial control signal provided by the initial control line Gate. The initial voltage Vint provided by the voltage terminal I0 is written into the second node N2;
所述微型发光二极管ML的阴极与低电压端VSS电连接；The cathode of the micro light-emitting diode ML is electrically connected to the low voltage terminal VSS;
所述数据写入电路13分别与第四扫描线Gate4、数据线Data和所述第二节点N2电连接，用于在所述第一扫描线Gate1提供的第一扫描信号的控制下，控制所述数据线Data与所述第二节点N2之间连通或断开；The data writing circuit 13 is electrically connected to the fourth scanning line Gate4, the data line Data and the second node N2 respectively, and is used to control all the data under the control of the first scanning signal provided by the first scanning line Gate1. The data line Data is connected or disconnected from the second node N2;
所述补偿控制电路14分别与第三扫描线Gate3、所述第一节点N1和第三节点N3电连接，用于在所述第三扫描线Gate3提供的第三扫描信号的控制下，控制所述第一节点N1和所述第三节点N3之间连通或断开。The compensation control circuit 14 is electrically connected to the third scan line Gate3, the first node N1 and the third node N3 respectively, and is used to control all the scan signals under the control of the third scan signal provided by the third scan line Gate3. The first node N1 and the third node N3 are connected or disconnected.
在图4所示的至少一实施例中，第二初始控制线为初始控制线Gate，第一初始控制线为第一扫描线Gate1，所述第五初始控制线为第二扫描线Gate2，所述写入控制线为第四扫描线Gate4，所述补偿控制线为第三扫描线Gate3。In at least one embodiment shown in FIG. 4 , the second initial control line is the initial control line Gate, the first initial control line is the first scan line Gate1, and the fifth initial control line is the second scan line Gate2, so The write control line is the fourth scan line Gate4, and the compensation control line is the third scan line Gate3.
如图5所示，在图2所示的像素电路的至少一实施例的基础上，本发明至少一实施例所述的像素的电路还包括第二储能电路31和第三初始化电路36；所述发光元件为微型发光二极管ML；第三节点N3与高电压端VDD电连接；As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit according to at least one embodiment of the present invention also includes a second energy storage circuit 31 and a third initialization circuit 36; The light-emitting element is a micro light-emitting diode ML; the third node N3 is electrically connected to the high voltage terminal VDD;
所述第二储能电路31的第一端与所述第二节点N2电连接，所述第二储能电路31的第二端与所述第三节点N3电连接，所述第二储能电路31用于储存电能；The first end of the second energy storage circuit 31 is electrically connected to the second node N2, and the second end of the second energy storage circuit 31 is electrically connected to the third node N3. The second energy storage circuit 31 is electrically connected to the third node N3. Circuit 31 is used to store electrical energy;
所述第三初始化电路36分别与复位控制线Re、初始电压端I0和所述第一节点N1电连接，用于在所述复位控制线Re提供的第复位控制信号的控制下，将所述初始电压端I0提供的初始电压Vinit写入所述第一节点N1；The third initialization circuit 36 is electrically connected to the reset control line Re, the initial voltage terminal I0 and the first node N1 respectively, and is used to reset the reset control signal under the control of the reset control signal provided by the reset control line Re. The initial voltage Vinit provided by the initial voltage terminal I0 is written into the first node N1;
所述像素电路还包括第四初始化电路37；The pixel circuit also includes a fourth initialization circuit 37;
所述第四初始化电路37分别与第三扫描线Gate3、高电压端VDD和所述第二节点N2电连接，用于在所述第三扫描线Gate3提供的第三扫描信号的控制下，控制所述高电压端VDD与所述第二节点N2之间连通或断开；The fourth initialization circuit 37 is electrically connected to the third scan line Gate3, the high voltage terminal VDD and the second node N2 respectively, and is used to control the third scan signal provided by the third scan line Gate3. The high voltage terminal VDD and the second node N2 are connected or disconnected;
所述像素电路还包括第二发光控制电路38和第六初始化电路39；The pixel circuit also includes a second light emission control circuit 38 and a sixth initialization circuit 39;
所述第二发光控制电路38分别与第二发光控制线EM2、所述驱动电路11的第二端和所述微型发光二极管ML的阳极电连接，用于在所述第二发光控制线EM2提供的第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述微型发光二极管ML的阳极之间连通或断开；The second light-emitting control circuit 38 is electrically connected to the second light-emitting control line EM2, the second end of the driving circuit 11 and the anode of the micro-light-emitting diode ML, respectively, and is used to provide power on the second light-emitting control line EM2. Under the control of the second light emitting control signal, control the connection or disconnection between the second end of the driving circuit 11 and the anode of the micro light emitting diode ML;
所述第六初始化电路39分别与复位控制线Re、初始电压端I0和所述微型发光二极管ML的阳极电连接，用于在所述复位控制线Re提供的复位控制信号的控制下，将所述初始电压端I0提供的初始电压Vinit写入所述微型发光二极管ML的阳极；所述微型发光二极管ML的阴极与低电压端VSS电连接；The sixth initialization circuit 39 is electrically connected to the reset control line Re, the initial voltage terminal I0 and the anode of the micro light-emitting diode ML, respectively, for controlling the reset control signal provided by the reset control line Re. The initial voltage Vinit provided by the initial voltage terminal I0 is written into the anode of the micro light-emitting diode ML; the cathode of the micro light-emitting diode ML is electrically connected to the low voltage terminal VSS;
所述数据写入电路13分别与第二扫描线Gate2、数据线Data和所述第二节点N2电连接，用于在所述第二扫描线Gate2提供的第二扫描信号的控制下，控制所述数据线Data与所述第二节点N2之间连通或断开；The data writing circuit 13 is electrically connected to the second scan line Gate2, the data line Data and the second node N2 respectively, and is used to control all the data under the control of the second scan signal provided by the second scan line Gate2. The data line Data is connected or disconnected from the second node N2;
所述补偿控制电路14分别与第一扫描线Gate1、所述第一节点N1和补偿节点N0电连接，用于在所述第一扫描线Gate1提供的第一扫描信号的控制下，控制所述第一节点N1和所述驱动电路11的第二端之间连通或断开。The compensation control circuit 14 is electrically connected to the first scan line Gate1, the first node N1 and the compensation node N0 respectively, and is used to control the first scan signal provided by the first scan line Gate1. The first node N1 and the second end of the driving circuit 11 are connected or disconnected.
在图5所示的像素电路的至少一实施例中,第三初始控制线为复位控制线Re，第四初始控制线为第三扫描线Gate3，第六初始控制线为复位控制线Re，写入控制线为第二扫描线Gate2，补偿控制线为第一扫描线Gate1。In at least one embodiment of the pixel circuit shown in FIG. 5, the third initial control line is the reset control line Re, the fourth initial control line is the third scan line Gate3, and the sixth initial control line is the reset control line Re. Write The input control line is the second scan line Gate2, and the compensation control line is the first scan line Gate1.
如图6所示，在图3所示的像素电路的至少一实施例的基础上，As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 3,
所述第一储能电路包括第一电容C1，所述驱动电路包括驱动晶体管T0，所述数据写入电路包括第一晶体管T1，所述补偿控制电路包括第二晶体管T2；The first energy storage circuit includes a first capacitor C1, the driving circuit includes a driving transistor T0, the data writing circuit includes a first transistor T1, and the compensation control circuit includes a second transistor T2;
所述第一电容C1的第一端与第一节点N1电连接，所述第一电容C1的第二端与第二节点N2电连接；The first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the second node N2;
所述驱动晶体管T0的栅极与所述第一节点N1电连接，所述驱动晶体管T0的源极与第三节点N3电连接，所述驱动晶体管N1的漏极与所述微型发光二极管ML的阳极电连接；ML的阴极与低电压端VSS电连接；The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the third node N3, and the drain of the driving transistor N1 is connected to the micro light emitting diode ML. The anode is electrically connected; the cathode of ML is electrically connected to the low voltage terminal VSS;
所述第一晶体管T1的栅极与第一扫描线Gate1电连接，所述第一晶体管的源极与所述数据线Data电连接，所述第一晶体管T1的漏极与所述第二节点N2电连接；The gate of the first transistor T1 is electrically connected to the first scan line Gate1, the source of the first transistor is electrically connected to the data line Data, and the drain of the first transistor T1 is electrically connected to the second node. N2 electrical connection;
所述第二晶体管T2的栅极与所述第三扫描线Gate3电连接，所述第二晶体管T2的源极与所述第一节点N1电连接，所述第二晶体管T2的漏极与所述第三节点N3电连接；The gate of the second transistor T2 is electrically connected to the third scan line Gate3, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the first node N1. The third node N3 is electrically connected;
所述第二储能电路包括第二电容C2，所述第一初始化电路包括第三晶体管T3；The second energy storage circuit includes a second capacitor C2, and the first initialization circuit includes a third transistor T3;
所述第二电容C2的第一端与所述第二节点N2电连接，所述第二电容C2的第二端与第三节点N3电连接；The first end of the second capacitor C2 is electrically connected to the second node N2, and the second end of the second capacitor C2 is electrically connected to the third node N3;
所述第三晶体管T3的栅极与所述第一扫描线Gate1电连接，所述第三晶体管T3的源极与所述初始电压端I0电连接，所述第三晶体管T3的漏极与所述第四节点N4电连接；所述初始电压端I0用于提供初始电压Vint；The gate of the third transistor T3 is electrically connected to the first scan line Gate1, the source of the third transistor T3 is electrically connected to the initial voltage terminal I0, and the drain of the third transistor T3 is electrically connected to the initial voltage terminal I0. The fourth node N4 is electrically connected; the initial voltage terminal I0 is used to provide an initial voltage Vint;
所述第五初始化电路包括第七晶体管T7；The fifth initialization circuit includes a seventh transistor T7;
所述第七晶体管T7的栅极与所述二扫描线Gate2电连接，所述第七晶体管T7的源极与所述第四节点N4电连接，所述第七晶体管T7的漏极与所述微型发光二极管ML的阳极电连接；The gate of the seventh transistor T7 is electrically connected to the second scan line Gate2, the source of the seventh transistor T7 is electrically connected to the fourth node N4, and the drain of the seventh transistor T7 is electrically connected to the second scan line Gate2. The anode of the micro light-emitting diode ML is electrically connected;
所述第一发光控制电路包括第八晶体管T8；The first lighting control circuit includes an eighth transistor T8;
所述第八晶体管T8的栅极与所述第一发光控制线EM1电连接，所述第八晶体管T8的源极与高电压端VDD电连接，所述第八晶体管T8的漏极与所述第三节点N3电连接。The gate of the eighth transistor T8 is electrically connected to the first light emitting control line EM1, the source of the eighth transistor T8 is electrically connected to the high voltage terminal VDD, and the drain of the eighth transistor T8 is electrically connected to the first light emitting control line EM1. The third node N3 is electrically connected.
在图6所示的像素电路的至少一实施例中，所有晶体管都为NMOS晶体管；其中，T3可以为氧化物薄膜晶体管，也可以为a-Si(硅)或P-Si制作的N型TFT(薄膜晶体管)。In at least one embodiment of the pixel circuit shown in FIG. 6 , all transistors are NMOS transistors; T3 may be an oxide thin film transistor, or an N-type TFT made of a-Si (silicon) or P-Si. (thin film transistor).
如图7所示，图6所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、采样阶段S2、数据写入阶段S3和发光阶段S4；As shown in Figure 7, when at least one embodiment of the pixel circuit shown in Figure 6 is working, the display cycle may include an initialization phase S1, a sampling phase S2, a data writing phase S3 and a lighting phase S4 that are set successively;
在初始化阶段S1，Gate1、Gate2和Gate3都提供高电压信号，EM1提供高电压信号，Data提供初始电压Vint，T1、T2、T3、T7和T8都打开，N2的电位为Vint，VDD提供的高电压信号Vdd通过T8和T2写入第一节点N1，T0打开，N3的电位为Vint，Vint通过T7写入ML的阳极，ML不发光；In the initialization phase S1, Gate1, Gate2 and Gate3 all provide high voltage signals, EM1 provides high voltage signals, Data provides the initial voltage Vint, T1, T2, T3, T7 and T8 are all turned on, the potential of N2 is Vint, and the high voltage provided by VDD The voltage signal Vdd is written into the first node N1 through T8 and T2, T0 is turned on, the potential of N3 is Vint, Vint is written into the anode of ML through T7, and ML does not emit light;
在采样阶段S2，Gate1、Gate2和Gate3都提供高电压信号，EM1提供低电压信号，Data提供初始电压Vint，T8关闭，T3和T1打开，N2的电位和N3的电位维持为Vint，In the sampling phase S2, Gate1, Gate2 and Gate3 all provide high voltage signals, EM1 provides low voltage signals, Data provides the initial voltage Vint, T8 is closed, T3 and T1 are opened, the potential of N2 and the potential of N3 are maintained at Vint,
在采样阶段S2开始时，N1的电位经过T2、T0、T7和T3向I0放电，当N1的电位变为Vint+Vth时，T0关闭，此时C1的两端电位差为Vth，其中，Vth为T0的阈值电压；At the beginning of the sampling phase S2, the potential of N1 is discharged to I0 through T2, T0, T7 and T3. When the potential of N1 becomes Vint+Vth, T0 is turned off. At this time, the potential difference between the two ends of C1 is Vth, where, Vth is the threshold voltage of T0;
在数据写入阶段S3，Gate1提供高电压信号，Gate2提供低电压信号，Gate3提供低电压信号，EM1提供低电压信号，Data提供数据电压Vdata，T1打开，以将Vdata写入N2，T3打开，Vint写入N3，N1的电位由于C1的存在，在N2的电位变化时跟着跳变，变为Vdata+Vth，C2的两端电位差为Vdata+Vint；In the data writing phase S3, Gate1 provides a high voltage signal, Gate2 provides a low voltage signal, Gate3 provides a low voltage signal, EM1 provides a low voltage signal, Data provides the data voltage Vdata, T1 is turned on to write Vdata to N2, T3 is turned on, Vint is written to N3. Due to the existence of C1, the potential of N1 jumps when the potential of N2 changes and becomes Vdata+Vth. The potential difference between the two ends of C2 is Vdata+Vint;
在发光阶段S4，Gate1提供低电压信号，Gate2提供高电压信号，Gate3提供低电压信号，EM1提供高电压信号，T7、T8和T0打开，T0驱动ML发光，在上一时刻，N1的电位为Vdata+Vth，N3的电位为Vint，T0的栅源电压Vgs为Vdata+Vth-Vint，在发光阶段S4，ML的阳极电位改变，但T7保持开启，因此N1的电位和N2的电位随之改变，Vgs保持不变，所以驱动电流的电流值为K×(Vdata-Vint)2，其中，K为T0的电流系数。In the light-emitting phase S4, Gate1 provides a low-voltage signal, Gate2 provides a high-voltage signal, Gate3 provides a low-voltage signal, EM1 provides a high-voltage signal, T7, T8 and T0 are turned on, and T0 drives ML to emit light. At the last moment, the potential of N1 is Vdata+Vth, the potential of N3 is Vint, and the gate-source voltage Vgs of T0 is Vdata+Vth-Vint. During the light-emitting phase S4, the anode potential of ML changes, but T7 remains on, so the potential of N1 and the potential of N2 change accordingly. , Vgs remains unchanged, so the current value of the driving current is K×(Vdata-Vint)2 , where K is the current coefficient of T0.
本发明图6所示的像素电路的至少一实施例在工作时，采样和数据写入分开进行，在采样阶段进行阈值电压补偿，在数据写入阶段进行数据电压写入，这样阈值电压补偿时间不受一行扫描时间的限制，可以延长阈值电压补偿时间，使得补偿更充分，从而降低mura(显示不均匀)，同时也能够支持高刷新频率。When at least one embodiment of the pixel circuit shown in FIG. 6 of the present invention is working, sampling and data writing are performed separately, threshold voltage compensation is performed in the sampling stage, and data voltage writing is performed in the data writing stage. In this way, the threshold voltage compensation time Not limited by the scanning time of one line, the threshold voltage compensation time can be extended to make the compensation more sufficient, thereby reducing mura (display unevenness) and also supporting high refresh frequencies.
本发明图6所示的像素电路的至少一实施例在工作时，在发光阶段，驱动电流的电流值与VDD提供的高电压信号的电压值无关，IR Drop(压降)影响变小。When at least one embodiment of the pixel circuit shown in FIG. 6 of the present invention is working, in the light-emitting phase, the current value of the driving current has nothing to do with the voltage value of the high-voltage signal provided by VDD, and the influence of IR Drop (voltage drop) becomes smaller.
本发明图6所示的像素电路的至少一实施例采用的晶体管的个数较少，在layout(布局)方便难度小，相比于相关的像素电路可以支持高PPI(像素密度)。At least one embodiment of the pixel circuit shown in FIG. 6 of the present invention uses a smaller number of transistors, is less difficult to facilitate in layout, and can support higher PPI (pixel density) than related pixel circuits.
图8所示的像素电路的至少一实施例与图6所示的像素电路的至少一实施例的区别如下：The differences between at least one embodiment of the pixel circuit shown in FIG. 8 and the at least one embodiment of the pixel circuit shown in FIG. 6 are as follows:
图8所示的像素电路的至少一实施例还包括第二初始化电路；At least one embodiment of the pixel circuit shown in Figure 8 further includes a second initialization circuit;
所述第二初始化电路包括第四晶体管T4；The second initialization circuit includes a fourth transistor T4;
所述第四晶体管T4的栅极与所述初始控制线Gate电连接，所述第四晶体管T4的源极与所述初始电压端I0电连接，所述第四晶体管T4的漏极与所述第二节点N2电连接；The gate of the fourth transistor T4 is electrically connected to the initial control line Gate, the source of the fourth transistor T4 is electrically connected to the initial voltage terminal I0, and the drain of the fourth transistor T4 is electrically connected to the initial control line Gate. The second node N2 is electrically connected;
T1的栅极与第四扫描线Gate4电连接。The gate of T1 is electrically connected to the fourth scan line Gate4.
本发明图8所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段、采样阶段、数据写入阶段和发光阶段；When at least one embodiment of the pixel circuit shown in FIG. 8 of the present invention is working, the display cycle may include an initialization phase, a sampling phase, a data writing phase and a light-emitting phase that are set successively;
在初始化阶段和采样阶段，Gate4提供低电压信号，Gate提供高电压信号，T4打开，以将所述初始电压端I0提供的初始电压Vint写入第二节点N2，T1关断；In the initialization phase and sampling phase, Gate4 provides a low voltage signal, Gate provides a high voltage signal, T4 is turned on to write the initial voltage Vint provided by the initial voltage terminal I0 into the second node N2, and T1 is turned off;
在数据写入阶段，Gate4提供高电压信号，Gate提供低电压信号，T4关断，T1打开，数据线Data提供数据电压Vdata至第二节点N2；In the data writing phase, Gate4 provides a high voltage signal, Gate provides a low voltage signal, T4 is turned off, T1 is turned on, and the data line Data provides the data voltage Vdata to the second node N2;
在发光阶段，Gate4和Gate都提供低电压信号，T1和T4都关断。During the light-emitting phase, both Gate4 and Gate provide low-voltage signals, and both T1 and T4 are turned off.
如图9所示，在图5所示的像素电路的至少一实施例的基础上，所述发光元件为微型发光二极管ML；As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 5, the light-emitting element is a micro light-emitting diode ML;
所述第一储能电路包括第一电容C1，所述驱动电路包括驱动晶体管T0，所述数据写入电路包括第一晶体管T1，所述补偿控制电路包括第二晶体管；The first energy storage circuit includes a first capacitor C1, the driving circuit includes a driving transistor T0, the data writing circuit includes a first transistor T1, and the compensation control circuit includes a second transistor;
所述第一电容C1的第一端与第一节点N1电连接，所述第一电容C1的第二端与第二节点N2电连接；The first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the second node N2;
所述驱动晶体管T0的栅极与所述第一节点N1电连接，所述驱动晶体管T0的源极与第三节点N3电连接；The gate of the driving transistor T0 is electrically connected to the first node N1, and the source of the driving transistor T0 is electrically connected to the third node N3;
所述第一晶体管T1的栅极与所述第二扫描线Gate2电连接，所述第一晶体管T1的源极与所述数据线Data电连接，所述第一晶体管T1的漏极与所述第二节点N2电连接；The gate of the first transistor T1 is electrically connected to the second scan line Gate2, the source of the first transistor T1 is electrically connected to the data line Data, and the drain of the first transistor T1 is electrically connected to the data line Data. The second node N2 is electrically connected;
所述第二晶体管T2的栅极与所述第一扫描线Gate1电连接，所述第二晶体管T2的源极与所述第一节点N1电连接，所述第二晶体管T2的漏极与T0的漏极电连接；The gate of the second transistor T2 is electrically connected to the first scan line Gate1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to T0. The drain electrical connection;
所述第二储能电路包括第二电容C2，所述第三初始化电路包括第五晶体管T5；The second energy storage circuit includes a second capacitor C2, and the third initialization circuit includes a fifth transistor T5;
所述第二电容C2的第一端与所述第二节点N2电连接，所述第二电容C2的第二端与所述第三节点N3电连接；The first end of the second capacitor C2 is electrically connected to the second node N2, and the second end of the second capacitor C2 is electrically connected to the third node N3;
所述第五晶体管T5的栅极与所述复位控制线Re电连接，所述第五晶体管T5的源极与所述初始电压端I0电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；The gate of the fifth transistor T5 is electrically connected to the reset control line Re, the source of the fifth transistor T5 is electrically connected to the initial voltage terminal I0, and the drain of the fifth transistor T5 is electrically connected to the reset control line Re. The first node N1 is electrically connected;
所述第四初始化电路包括第六晶体管T6；The fourth initialization circuit includes a sixth transistor T6;
所述第六晶体管T6的栅极与所述第三扫描线Gate3电连接，所述第六晶体管T6的源极与所述高电压端VDD电连接，所述第六晶体管T6的漏极与所述第二节点N2电连接；The gate of the sixth transistor T6 is electrically connected to the third scan line Gate3, the source of the sixth transistor T6 is electrically connected to the high voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the high voltage terminal VDD. The second node N2 is electrically connected;
所述第二发光控制电路包括第九晶体管T9；The second light emitting control circuit includes a ninth transistor T9;
所述第九晶体管T9的栅极与所述第二发光控制线EM2电连接，所述第九晶体管T9的源极与所述驱动晶体管T0的漏极电连接，所述第九晶体管T9的漏极与所述微型发光二极管ML的阳极电连接；所述微型发光二极管ML的阴极与低电压端VSS电连接；The gate of the ninth transistor T9 is electrically connected to the second light emitting control line EM2, the source of the ninth transistor T9 is electrically connected to the drain of the driving transistor T0, and the drain of the ninth transistor T9 The pole is electrically connected to the anode of the micro light-emitting diode ML; the cathode of the micro light-emitting diode ML is electrically connected to the low voltage terminal VSS;
所述第六初始化电路包括第十晶体管T10；The sixth initialization circuit includes a tenth transistor T10;
所述第十晶体管T10的栅极与复位控制线Re电连接，所述第十晶体管T10的源极与所述初始电压端I0电连接，所述第十晶体管T10的漏极与所述微型发光二极管ML的阳极电连接；The gate of the tenth transistor T10 is electrically connected to the reset control line Re, the source of the tenth transistor T10 is electrically connected to the initial voltage terminal I0, and the drain of the tenth transistor T10 is electrically connected to the micro-luminescence terminal. The anode of diode ML is electrically connected;
所述微型发光二极管ML的阴极与低电压端VSS电连接。The cathode of the micro light-emitting diode ML is electrically connected to the low voltage terminal VSS.
在图9所示的像素电路的至少一实施例中，所有晶体管都为PMOS晶体管，其中，所有晶体管都为LTPS(低温多晶硅)TFT(薄膜晶体管)，但不以此为限，图9中的晶体管也可以为其他类型的P型TFT。In at least one embodiment of the pixel circuit shown in Figure 9, all transistors are PMOS transistors, wherein all transistors are LTPS (low temperature polysilicon) TFT (thin film transistor), but are not limited to this. In Figure 9 The transistors may also be other types of P-type TFTs.
如图10所示，本发明图9所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、采样阶段S2、数据写入阶段S3和发光阶段S4；As shown in Figure 10, when at least one embodiment of the pixel circuit shown in Figure 9 of the present invention is working, the display cycle may include an initialization phase S1, a sampling phase S2, a data writing phase S3 and a lighting phase S4 that are set successively;
在初始化阶段S1，Gate1、Gate2和EM2都提供高电压信号，Gate3和Re提供低电压信号，T5、T10和T6打开，VDD提供的高电压信号通过T6写入第二节点N2，所述初始电压端I0提供的初始电压Vint经过T5和T10分别写入N1和ML的阳极，ML不发光；所述高电压信号的电压值为Vdd；In the initialization phase S1, Gate1, Gate2 and EM2 all provide high voltage signals, Gate3 and Re provide low voltage signals, T5, T10 and T6 are turned on, the high voltage signal provided by VDD is written to the second node N2 through T6, the initial voltage The initial voltage Vint provided by terminal I0 is written into the anodes of N1 and ML through T5 and T10 respectively, and ML does not emit light; the voltage value of the high voltage signal is Vdd;
在采样阶段S2，Gate1和Gate3提供低电压信号，Re、Gate2和EM2都提供高电压信号，T2、T0和T6都打开，N2的电位维持为Vdd，高电压信号通过T0、T2和T6为电容充电，以提升N1的电位，直至N1的电位变为Vdd+Vth，T0关断；其中，Vth为T0的阈值电压；In the sampling phase S2, Gate1 and Gate3 provide low voltage signals, Re, Gate2 and EM2 all provide high voltage signals, T2, T0 and T6 are all turned on, the potential of N2 is maintained at Vdd, and the high voltage signal passes through T0, T2 and T6 as capacitors Charge to increase the potential of N1 until the potential of N1 becomes Vdd+Vth and T0 turns off; where Vth is the threshold voltage of T0;
在数据写入阶段S3，Gate2提供低电压信号，Re、Gate1、Gate3和EM2都提供高电压信号，T1打开，数据线Data提供数据电压Vdata至第二节点N2，N1的电位由于C1的存在随数据电压写入跳变为Vdd+Vth，N3的电位保持为Vdd，C1的两端压差为Vth；In the data writing phase S3, Gate2 provides a low voltage signal, Re, Gate1, Gate3 and EM2 all provide high voltage signals. T1 is turned on, and the data line Data provides the data voltage Vdata to the second node N2. The potential of N1 changes due to the existence of C1. The data voltage writing jumps to Vdd+Vth, the potential of N3 remains at Vdd, and the voltage difference between the two ends of C1 is Vth;
在发光阶段S4，Re、Gate1、Gate2和Gate3都提供高电压信号，EM2提供低电压信号，T9打开，T0打开，T0驱动ML发光；In the light-emitting stage S4, Re, Gate1, Gate2 and Gate3 all provide high-voltage signals, EM2 provides low-voltage signals, T9 is turned on, T0 is turned on, and T0 drives ML to emit light;
在发光阶段S4，N3的电位维持为Vdd，通过C2维持N2的电位为Vdata，再通过C1维持N1的电位为Vdata+Vth，T0的栅源电压为Vdata+Vth-Vdd，T0产生的驱动电流Id为K×(Vdata-Vdd)2；K为T0的电流系数。In the light-emitting phase S4, the potential of N3 is maintained at Vdd, the potential of N2 is maintained at Vdata through C2, and the potential of N1 is maintained at Vdata+Vth through C1. The gate-source voltage of T0 is Vdata+Vth-Vdd, and the driving current generated by T0 Id is K×(Vdata-Vdd)2 ; K is the current coefficient of T0.
本发明图9所示的像素电路的至少一实施例在工作时，在采样阶段进行阈值电压补偿，在数据写入阶段进行数据电压写入，采用将阈值电压补偿和数据电压写入分时段进行的方法，使得阈值电压补偿时间得以延长，补偿效果更加充分，可以支持高频。并且，本发明图11所示的像素电路的至少一实施例采用的晶体管的个数较少，在layout(布局)方便难度小，相比于相关的像素电路可以支持高PPI(像素密度)。When at least one embodiment of the pixel circuit shown in FIG. 9 of the present invention is working, threshold voltage compensation is performed in the sampling stage, and data voltage writing is performed in the data writing stage. The threshold voltage compensation and data voltage writing are performed in time periods. This method extends the threshold voltage compensation time, makes the compensation effect more sufficient, and can support high frequencies. Moreover, at least one embodiment of the pixel circuit shown in FIG. 11 of the present invention uses a smaller number of transistors, making layout convenient and less difficult, and can support higher PPI (pixel density) than related pixel circuits.
如图11所示，在本发明图9所示的像素电路的至少一实施例的基础上，本发明至少一实施例所述的像素电路还包括第八晶体管T8；As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 9 of the present invention, the pixel circuit according to at least one embodiment of the present invention further includes an eighth transistor T8;
所述第八晶体管T8的栅极与所述第一发光控制线EM1电连接，所述第八晶体管T8的源极与所述高电压端VDD电连接，所述第八晶体管T8的漏极与所述第三节点N3电连接。The gate of the eighth transistor T8 is electrically connected to the first light emitting control line EM1, the source of the eighth transistor T8 is electrically connected to the high voltage terminal VDD, and the drain of the eighth transistor T8 is electrically connected to the first light emitting control line EM1. The third node N3 is electrically connected.
在图11所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管。In at least one embodiment of the pixel circuit shown in FIG. 11, all transistors are p-type transistors.
本发明图11所示的像素电路的至少一实施例在工作时，在初始化阶段，EM1提供高电压信号，T8关断，在采样阶段、数据写入阶段和发光阶段，EM1提供低电压信号，T8打开。When at least one embodiment of the pixel circuit shown in Figure 11 of the present invention is working, in the initialization phase, EM1 provides a high voltage signal and T8 is turned off. In the sampling phase, data writing phase and light emitting phase, EM1 provides a low voltage signal. T8 opens.
本发明图11所示的像素电路的至少一实施例在工作时，在初始化阶段、N1的电位为Vint，N2的电位为Vdd，N3处于浮空状态；When at least one embodiment of the pixel circuit shown in Figure 11 of the present invention is working, in the initialization stage, the potential of N1 is Vint, the potential of N2 is Vdd, and N3 is in a floating state;
在采样阶段，N1的电位为Vdd+Vth，N2的电位为Vdd，N3的电位为Vdd；During the sampling phase, the potential of N1 is Vdd+Vth, the potential of N2 is Vdd, and the potential of N3 is Vdd;
在数据写入阶段，N1的电位为Vdata+Vth，N2的电位为Vdata，N3的电位为Vdd；In the data writing phase, the potential of N1 is Vdata+Vth, the potential of N2 is Vdata, and the potential of N3 is Vdd;
在发光阶段，T0产生的驱动电流的电流值为K×(Vdata-Vdd)2。In the light-emitting stage, the current value of the driving current generated by T0 is K×(Vdata-Vdd)2 .
本发明图11所示的像素电路的至少一实施例在工作时，在采样阶段进行阈值电压补偿，在数据写入阶段进行数据电压写入，采用将阈值电压补偿和数据电压写入分时段进行的方法，使得阈值电压补偿时间得以延长，补偿效果更加充分，可以支持高频。并且，本发明图11所示的像素电路的至少一实施例采用的晶体管的个数较少，在layout(布局)方便难度小，相比于相关的像素电路可以支持高PPI(像素密度)。When at least one embodiment of the pixel circuit shown in FIG. 11 of the present invention is working, threshold voltage compensation is performed in the sampling stage, and data voltage writing is performed in the data writing stage. The threshold voltage compensation and data voltage writing are performed in time intervals. This method extends the threshold voltage compensation time, makes the compensation effect more sufficient, and can support high frequencies. Moreover, at least one embodiment of the pixel circuit shown in FIG. 11 of the present invention uses a smaller number of transistors, making layout convenient and less difficult, and can support higher PPI (pixel density) than related pixel circuits.
本发明实施例所述的驱动方法，应用于上述的像素电路，显示周期包括相互独立的采样阶段和数据写入阶段；所述驱动方法包括：The driving method described in the embodiment of the present invention is applied to the above-mentioned pixel circuit. The display cycle includes a sampling phase and a data writing phase that are independent of each other; the driving method includes:
在采样阶段，补偿控制电路在补偿控制线提供的补偿控制信号的控制下，控制第一节点和补偿节点之间连通，以进行阈值电压补偿；In the sampling stage, the compensation control circuit controls the connection between the first node and the compensation node to perform threshold voltage compensation under the control of the compensation control signal provided by the compensation control line;
在数据写入阶段，数据写入电路在写入控制线提供的写入控制信号的控制下，控制数据线与第二节点之间连通，以将所述数据线提供的数据电压写入所述第二节点。In the data writing stage, the data writing circuit controls the connection between the data line and the second node under the control of the writing control signal provided by the writing control line, so as to write the data voltage provided by the data line into the Second node.
本发明实施例所述的驱动方法将数据电压写入和阈值电压补偿分时段进行，以使得阈值电压补偿的时间得以延长，使得阈值电压补偿效果更加充分，并且可以支持高频显示。The driving method described in the embodiment of the present invention divides data voltage writing and threshold voltage compensation into time periods, so that the threshold voltage compensation time is extended, the threshold voltage compensation effect is more sufficient, and high-frequency display can be supported.
本发明实施例所述的显示装置包括上述的像素电路。The display device according to the embodiment of the present invention includes the above-mentioned pixel circuit.
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above is the preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications can also be made. should be regarded as the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
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| CN202310597795.8ACN117037656A (en) | 2023-05-24 | 2023-05-24 | Pixel circuit, driving method and display device |
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| CN202310597795.8ACN117037656A (en) | 2023-05-24 | 2023-05-24 | Pixel circuit, driving method and display device |
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| CN118571172A (en)* | 2024-06-24 | 2024-08-30 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2025194375A1 (en)* | 2024-03-20 | 2025-09-25 | 京东方科技集团股份有限公司 | Pixel circuit, pixel unit, and driving method |
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| WO2025194375A1 (en)* | 2024-03-20 | 2025-09-25 | 京东方科技集团股份有限公司 | Pixel circuit, pixel unit, and driving method |
| CN118571172A (en)* | 2024-06-24 | 2024-08-30 | 京东方科技集团股份有限公司 | Display panel and display device |
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