技术领域Technical field
本申请涉及显示技术领域，具体是涉及一种显示面板、阵列基板及其制作方法。The present application relates to the field of display technology, specifically to a display panel, an array substrate and a manufacturing method thereof.
背景技术Background technique
随着液晶显示面板的技术日益成熟，掩膜版(Photo mask)，又称光罩、光掩膜、光刻掩膜版等，是微电子制造，显示器制造中光刻工艺所使用的图形母版，由不透明的遮光薄膜在透明基板上形成掩膜图形并通过曝光将图形转印到产品基板上。现有5Mask工艺良率较稳定，膜层结构也更优秀，但是投入的人力、时间成本太大，产能不高。4Mask工艺产能更高，层叠覆盖效果会更好，但是对工艺的要求更高，良率也较低，膜层结构相比5Mask工艺更差。As the technology of liquid crystal display panels becomes increasingly mature, photo masks, also known as photomasks, photomasks, photolithography masks, etc., are graphic masters used in photolithography processes in microelectronics manufacturing and display manufacturing. The mask pattern is formed by an opaque light-shielding film on a transparent substrate and the pattern is transferred to the product substrate through exposure. The existing 5Mask process yield is relatively stable and the film structure is better, but the manpower and time costs are too high and the production capacity is not high. The 4Mask process has higher production capacity and better lamination coverage effect, but it has higher process requirements, lower yield, and worse film structure than the 5Mask process.
发明内容Contents of the invention
有鉴于此，本申请提供一种显示面板、阵列基板及其制作方法，以解决现有技术中5Mask工艺存在的成本高、产能低，以及4Mask工艺存在的工艺要求高、良率低的问题。In view of this, this application provides a display panel, an array substrate and a manufacturing method thereof to solve the problems of high cost and low productivity of the 5Mask process in the existing technology, as well as the high process requirements and low yield of the 4Mask process.
为了解决上述技术问题，本申请提供的第一个技术方案为：提供一种阵列基板的制作方法，包括以下步骤：In order to solve the above technical problems, the first technical solution provided by this application is to provide a method for manufacturing an array substrate, which includes the following steps:
S10：提供衬底基板，在所述衬底基板上形成第一金属层，采用第一道光罩工艺对所述第一金属层进行图案化处理以形成栅极，在所述栅极和所述衬底基板上依次形成栅极绝缘层、半导体层以及第二金属层，所述栅极绝缘层的材料为氧化硅或氮化硅；其中，所述第二金属层包括第一区域和第二区域；S10: Provide a base substrate, form a first metal layer on the base substrate, use a first mask process to pattern the first metal layer to form a gate electrode, between the gate electrode and the A gate insulating layer, a semiconductor layer and a second metal layer are sequentially formed on the base substrate, and the material of the gate insulating layer is silicon oxide or silicon nitride; wherein the second metal layer includes a first region and a second metal layer. Second area;
S20：采用第二道光罩工艺对所述第一区域的第二金属层以及所述半导体层进行图案化处理以形成源极、漏极以及非晶硅岛；所述非晶硅岛的边缘大于所述源极的边缘以及所述漏极的边缘；S20: Use a second mask process to pattern the second metal layer and the semiconductor layer in the first area to form a source electrode, a drain electrode and an amorphous silicon island; the edge of the amorphous silicon island is larger than The edge of the source electrode and the edge of the drain electrode;
S25：采用第三道光罩对所述第二区域的第二金属层进行图案化，以形成走线区；S25: Use a third photomask to pattern the second metal layer in the second area to form a wiring area;
S30：在所述栅极绝缘层、所述源极以及所述漏极上形成钝化层，采用第四道光罩工艺对所述钝化层进行图案化处理，以形成过孔；以及S30: Form a passivation layer on the gate insulation layer, the source electrode and the drain electrode, and use a fourth mask process to pattern the passivation layer to form via holes; and
S40：采用第五道光罩工艺在所述钝化层上图案化形成像素电极，所述像素电极通过所述过孔与所述漏极连接。S40: Use a fifth mask process to pattern a pixel electrode on the passivation layer, and the pixel electrode is connected to the drain electrode through the via hole.
可选地，步骤S20包括以下步骤：Optionally, step S20 includes the following steps:
S201：在所述第一区域的第二金属层上涂覆光阻材料；S201: Coat a photoresist material on the second metal layer in the first area;
S202：采用所述第二道光罩对所述光阻材料曝光显影以形成第一光阻层；S202: Use the second photomask to expose and develop the photoresist material to form a first photoresist layer;
S203：刻蚀去除所述第一光阻层未覆盖的所述第一区域的第二金属层；S203: Etch and remove the second metal layer in the first area not covered by the first photoresist layer;
S204：对所述第一光阻层进行灰化处理以形成第二光阻层，所述第二光阻层对应于所述源极和所述漏极；S204: Perform ashing treatment on the first photoresist layer to form a second photoresist layer, where the second photoresist layer corresponds to the source electrode and the drain electrode;
S205：对所述第一区域的第二金属层进行刻蚀处理以形成所述源极和所述漏极；S205: Perform an etching process on the second metal layer in the first region to form the source electrode and the drain electrode;
S206：剥离所述第二光阻层；以及S206: Peel off the second photoresist layer; and
S207：刻蚀去除未被所述源极以及所述漏极遮盖的所述半导体层。S207: Etch and remove the semiconductor layer that is not covered by the source electrode and the drain electrode.
其中，所述半导体层包括非晶硅层和N+非晶硅层，步骤S207还包括，刻蚀去除所述沟道区的所述N+非晶硅层以露出所述非晶硅层。Wherein, the semiconductor layer includes an amorphous silicon layer and an N+ amorphous silicon layer. Step S207 further includes etching and removing the N+ amorphous silicon layer in the channel region to expose the amorphous silicon layer.
其中，所述第一区域的第二金属层对应于晶体管区域的元件区；所述第二区域的第二金属层对应于晶体管区域的所述走线区。The second metal layer in the first region corresponds to the component region of the transistor region; the second metal layer in the second region corresponds to the wiring region of the transistor region.
可选地，步骤S25包括以下步骤：Optionally, step S25 includes the following steps:
S251：在所述第二区域的第二金属层上涂覆光阻材料；S251: Coat a photoresist material on the second metal layer in the second area;
S252：采用所述第三道光罩对所述光阻材料曝光显影以形成第一光阻层；S252: Use the third photomask to expose and develop the photoresist material to form a first photoresist layer;
S253：刻蚀去除所述第一光阻层未覆盖的所述第二区域的第二金属层；S253: Etch and remove the second metal layer in the second area not covered by the first photoresist layer;
S254：对所述第一光阻层进行灰化处理以形成第二光阻层，所述第二光阻层对应于所述走线区；S254: Perform ashing treatment on the first photoresist layer to form a second photoresist layer, and the second photoresist layer corresponds to the wiring area;
S255：对所述第二区域的第二金属层进行刻蚀处理以形成所述走线区。S255: Perform an etching process on the second metal layer in the second area to form the wiring area.
其中，所述走线区设置于所述非晶硅岛、所述源极和所述漏极的侧面，用于对膜层间的电路进行连接。Wherein, the wiring area is provided on the side of the amorphous silicon island, the source electrode and the drain electrode, and is used to connect circuits between film layers.
其中，在所述阵列基板的正投影方向，所述源极的边缘与所述漏极的边缘长度相等；所述第二道光罩为半色调掩膜版。Wherein, in the orthographic projection direction of the array substrate, the edge of the source electrode is equal to the length of the edge of the drain electrode; the second photomask is a half-tone mask.
为了解决上述技术问题，本申请提供的第二个技术方案为：提供一种阵列基板，包括衬底基板、栅极、栅极绝缘层、非晶硅岛、源极、漏极、钝化层和像素电极；栅极位于所述衬底基板上；栅极绝缘层覆盖所述栅极和所述衬底基板；非晶硅岛设置于所述栅极绝缘层上；源极、漏极设置于所述非晶硅岛上，所述源极和所述漏极之间形成沟道区；钝化层设置于所述栅极绝缘层、所述源极以及所述漏极上，所述钝化层上设置有过孔；以及像素电极设置于所述钝化层上，所述像素电极通过所述过孔与所述漏极连接；其中，述非晶硅岛的边缘大于所述源极的边缘以及所述漏极的边缘。In order to solve the above technical problems, the second technical solution provided by this application is to provide an array substrate, including a substrate substrate, a gate electrode, a gate insulating layer, an amorphous silicon island, a source electrode, a drain electrode, and a passivation layer and a pixel electrode; a gate electrode is located on the base substrate; a gate insulating layer covers the gate electrode and the base substrate; an amorphous silicon island is provided on the gate insulating layer; source and drain electrodes are provided On the amorphous silicon island, a channel region is formed between the source electrode and the drain electrode; a passivation layer is provided on the gate insulating layer, the source electrode and the drain electrode, the A via hole is provided on the passivation layer; and a pixel electrode is provided on the passivation layer, and the pixel electrode is connected to the drain electrode through the via hole; wherein, the edge of the amorphous silicon island is larger than the source the edge of the pole and the edge of the drain.
其中，所述非晶硅岛包括非晶硅层和N+非晶硅层，所述N+非晶硅层对应于所述源极和所述漏极，所述非晶硅层对应于所述源极、所述漏极以及沟道区。Wherein, the amorphous silicon island includes an amorphous silicon layer and an N+ amorphous silicon layer, the N+ amorphous silicon layer corresponds to the source electrode and the drain electrode, and the amorphous silicon layer corresponds to the source electrode. electrode, the drain electrode and the channel region.
其中，所述非晶硅岛、所述源极和所述漏极形成于第二金属层的第一区域。Wherein, the amorphous silicon island, the source electrode and the drain electrode are formed in the first region of the second metal layer.
其中，所述阵列基板还包括走线区，形成于所述第二金属层的第二区域；所述走线区设置于所述非晶硅岛、所述源极和所述漏极的侧面，并通过所述走线区导通所述非晶硅岛和所述漏极。Wherein, the array substrate further includes a wiring area formed in the second area of the second metal layer; the wiring area is provided on the side of the amorphous silicon island, the source electrode and the drain electrode. , and conduct the amorphous silicon island and the drain electrode through the wiring area.
为了解决上述技术问题，本申请提供的第三个技术方案为：提供一种显示面板，包括阵列基板、彩膜基板和液晶层，所述阵列基板为上述任一项所述的阵列基板；彩膜基板与所述阵列基板相对设置；液晶层设置于所述阵列基板与所述彩膜基板之间。In order to solve the above technical problems, the third technical solution provided by this application is to provide a display panel, including an array substrate, a color filter substrate and a liquid crystal layer. The array substrate is the array substrate described in any one of the above; The film substrate is arranged opposite to the array substrate; the liquid crystal layer is arranged between the array substrate and the color filter substrate.
本申请的有益效果：区别于现有技术，本申请的阵列基板及其制作方法，采用第二道光罩工艺对第一区域的第二金属层以及半导体层进行图案化处理以形成源极、漏极以及非晶硅岛；非晶硅岛的边缘大于源极的边缘以及漏极的边缘；采用第三道光罩对第二区域的第二金属层进行图案化形成走线区。本申请结合4Mask工艺和5Mask工艺，通过将第二金属层划分为第一区域和第二区域进行分开制备，通过第二道光罩对第一区域的第二金属层以及半导体层进行图案化，获得膜层结构更优秀的源极、漏极以及非晶硅岛；通过第三道光罩对第二金属层的第二区域进行图案化，形成膜层间Overlay(层叠覆盖)更优秀、对位效果更优的走线区，通过对半导体层(ACT)、源漏金属层(SD)和S-HTM(Half-Tone Mask，半色调掩膜版)的设计，使非晶硅基板的良率更高，膜层结构更优秀，Overlay的效果更好。从而克服4Mask工艺和5Mask工艺的缺陷，达到提高良率、加强膜层结构的目的。Beneficial effects of this application: Different from the prior art, the array substrate and its manufacturing method of this application use a second mask process to pattern the second metal layer and semiconductor layer in the first area to form the source and drain electrodes. electrode and the amorphous silicon island; the edge of the amorphous silicon island is larger than the edge of the source electrode and the edge of the drain electrode; a third photomask is used to pattern the second metal layer in the second area to form a wiring area. This application combines the 4Mask process and the 5Mask process, by dividing the second metal layer into a first area and a second area for separate preparation, and patterning the second metal layer and the semiconductor layer in the first area through a second photomask to obtain The source, drain and amorphous silicon island have better film structure; the second area of the second metal layer is patterned through the third photomask to form a better overlay between film layers and better alignment effect Better wiring areas, through the design of the semiconductor layer (ACT), source-drain metal layer (SD) and S-HTM (Half-Tone Mask, half-tone mask), improve the yield of amorphous silicon substrates. High, the film structure is better, and the overlay effect is better. Thereby overcoming the shortcomings of the 4Mask process and the 5Mask process, achieving the purpose of improving yield and strengthening the film structure.
附图说明Description of the drawings
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.
图1是本申请提供的阵列基板的制作方法的流程框图；Figure 1 is a flow chart of the manufacturing method of the array substrate provided by the present application;
图2是图1提供的步骤S20的子步骤的流程框图；Figure 2 is a flow chart of the sub-steps of step S20 provided in Figure 1;
图3A是本申请提供的在栅极和衬底基板上依次形成栅极绝缘层、半导体层以及第二金属层的工艺示意图；Figure 3A is a schematic diagram of the process provided by the present application for sequentially forming a gate insulating layer, a semiconductor layer and a second metal layer on a gate electrode and a base substrate;
图3B是本申请提供的通过半色调掩膜版形成第二金属层的工艺示意图；Figure 3B is a schematic diagram of the process of forming a second metal layer through a half-tone mask provided by this application;
图3C是本申请提供的形成元件区的工艺示意图；Figure 3C is a schematic diagram of a process for forming a component region provided by this application;
图3D是本申请提供的通过湿法蚀刻工艺对第二金属层的第一区域进行蚀刻的工艺示意图；Figure 3D is a process schematic diagram of etching the first region of the second metal layer through a wet etching process provided by this application;
图3E是本申请提供的通过干法蚀刻工艺对第一区域进行图案化处理以形成源极和漏极的工艺示意图；Figure 3E is a schematic diagram of the process provided by this application for patterning the first region through a dry etching process to form the source and drain electrodes;
图3F是本申请提供的通过干法蚀刻工艺对半导体层进行图案化处理的工艺示意图；Figure 3F is a process schematic diagram of patterning a semiconductor layer through a dry etching process provided by this application;
图3G是本申请提供的通过湿法蚀刻工艺对半导体层进行图案化处理以形成非晶硅岛、非晶硅层和N+非晶硅层的工艺示意图；Figure 3G is a schematic diagram of the process provided by this application for patterning a semiconductor layer through a wet etching process to form amorphous silicon islands, amorphous silicon layers and N+ amorphous silicon layers;
图3H是本申请提供的形成钝化层的工艺示意图；Figure 3H is a schematic diagram of the process for forming a passivation layer provided by this application;
图3I是本申请提供的对钝化层进行图案化处理以形成过孔的工艺示意图；Figure 3I is a schematic diagram of the process provided by this application for patterning the passivation layer to form via holes;
图3J是本申请提供的形成像素电极与过孔连接的工艺示意图；Figure 3J is a schematic diagram of the process for forming the connection between the pixel electrode and the via hole provided by this application;
图4是本申请提供的通过半色调掩膜版形成第二金属层的元件区和走线区的俯视结构示意图以及局部结构放大图；Figure 4 is a schematic top structural view and an enlarged view of the partial structure of the component area and wiring area where the second metal layer is formed through a half-tone mask provided by this application;
图5A是本申请提供的通过第三道光罩以及干法蚀刻工艺对半导体层进行图案化处理的工艺示意图；Figure 5A is a schematic diagram of the process of patterning the semiconductor layer through the third photomask and dry etching process provided by this application;
图5B是本申请提供的沉积第二金属层的工艺示意图；Figure 5B is a schematic diagram of a process for depositing a second metal layer provided by this application;
图5C是本申请提供的对第二金属层的第二区域进行图案化处理以形成走线区的工艺示意图；Figure 5C is a schematic diagram of the process provided by the present application for patterning the second area of the second metal layer to form a wiring area;
图5D是本申请提供的在走线区远离半导体层的一侧形成钝化层的工艺示意图；Figure 5D is a schematic diagram of the process provided by this application for forming a passivation layer on the side of the wiring area away from the semiconductor layer;
图5E是本申请提供的对走线区的钝化层进行图案化处理以形成过孔的工艺示意图；Figure 5E is a schematic diagram of the process provided by this application for patterning the passivation layer in the wiring area to form via holes;
图5F是本申请提供在走线区形成像素电极与过孔连接的工艺示意图；Figure 5F is a schematic diagram of the process provided by this application for forming pixel electrodes and via-hole connections in the wiring area;
图6是本申请提供的阵列基板的结构示意图；Figure 6 is a schematic structural diagram of the array substrate provided by this application;
图7是本申请提供的显示面板的结构示意图。Figure 7 is a schematic structural diagram of a display panel provided by this application.
附图标记说明：Explanation of reference symbols:
10-衬底基板，20-第一金属层，201-栅极，21-第二掩膜版，30-栅极绝缘层，40-半导体层，401-非晶硅层，402-N+非晶硅层，50-非晶硅岛，60-第二金属层，61-元件区，62-走线区，63-半导体层延伸部，601-源极，602-漏极，603-沟道区，70-钝化层，701-过孔，80-像素电极，100-第一光阻层，200-第二光阻层，300-阵列基板，301-液晶层，3011-液晶子单元，302-彩膜基板，400-显示面板。10-Substrate, 20-First metal layer, 201-Gate, 21-Second mask, 30-Gate insulation layer, 40-Semiconductor layer, 401-Amorphous silicon layer, 402-N+ amorphous Silicon layer, 50-amorphous silicon island, 60-second metal layer, 61-component area, 62-wiring area, 63-semiconductor layer extension, 601-source, 602-drain, 603-channel area , 70-passivation layer, 701-via hole, 80-pixel electrode, 100-first photoresist layer, 200-second photoresist layer, 300-array substrate, 301-liquid crystal layer, 3011-liquid crystal sub-unit, 302 -Color filter substrate, 400-display panel.
具体实施方式Detailed ways
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.
本申请中的术语“第一”、“第二”、仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、的特征可以明示或者隐含地包括至少一个该特征。本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。The terms "first" and "second" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined by "first" and "second" may explicitly or implicitly include at least one of these features. All directional indications (such as up, down, left, right, front, back...) in the embodiments of this application are only used to explain the relative positional relationship between components in a specific posture (as shown in the drawings). , sports conditions, etc., if the specific posture changes, the directional indication will also change accordingly. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。Reference herein to "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
掩膜版是显示器制造过程中的图形“底片”，用于转移高精密电路设计，承载了图形设计和工艺技术等知识产权信息。掩模版用于显示器非晶硅基板的批量生产，是下游生产流程衔接的关键部分，是基板精度和质量的决定因素之一。The mask is the graphic "negative" in the display manufacturing process. It is used to transfer high-precision circuit designs and carries intellectual property information such as graphic design and process technology. The mask is used for the mass production of display amorphous silicon substrates. It is a key part of the downstream production process and one of the determinants of substrate accuracy and quality.
目前制作非晶硅基板用的基本为5Mask工艺，即需要五道光刻工艺，包括：第一道光刻工艺：形成栅电极图形；第二道光刻工艺：形成半导体图案化；第三道光刻工艺：形成源漏金属层；第四道光刻工艺：形成接触孔；第五道光刻工艺：形成ITO电极。每一道光刻工艺都包含了成膜、曝光、显影、刻蚀和剥离五个步骤。虽然5Mask工艺良率较稳定，膜层结构也更优秀，但是投入的人力，时间成本太大，产能不高，由此产生4Mask工艺。Currently, the 5Mask process is basically used to make amorphous silicon substrates, which requires five photolithography processes, including: the first photolithography process: forming the gate electrode pattern; the second photolithography process: forming semiconductor patterning; the third photolithography process: Photolithography process: forming source and drain metal layers; fourth photolithography process: forming contact holes; fifth photolithography process: forming ITO electrodes. Each photolithography process includes five steps: film formation, exposure, development, etching and stripping. Although the yield rate of the 5Mask process is more stable and the film structure is better, the manpower and time cost are too high and the production capacity is not high. This resulted in the 4Mask process.
4Mask和5Mask一样，只是4Mask为半色调掩膜版结构，与半导体层和源漏金属层用一张Mask。即4Mask工艺将半导体层与源漏金属层采用同一道Mask制作，产能更高，Overlay(层叠覆盖)效果更好，但是对工艺的要求更高，良率也较低，膜层结构相比5Mask更差。4Mask is the same as 5Mask, except that 4Mask has a half-tone mask structure and uses a mask with the semiconductor layer and source and drain metal layers. That is to say, the 4Mask process uses the same mask to make the semiconductor layer and the source and drain metal layers. It has higher productivity and better overlay effect, but it has higher process requirements and lower yield. Compared with 5Mask, the film layer structure worse.
为了解决上述问题，本申请结合4Mask工艺和5Mask工艺，提供了一种新的显示面板、阵列基板及其制作方法。In order to solve the above problems, this application combines the 4Mask process and the 5Mask process to provide a new display panel, array substrate and manufacturing method.
请参阅图1、图3A至图3F，图1是本申请提供的阵列基板的制作方法的流程框图；图3A是本申请提供的在栅极和衬底基板上依次形成栅极绝缘层、半导体层以及第二金属层的工艺示意图；图3B是本申请提供的通过半色调掩膜版形成第二金属层的工艺示意图；图3C是本申请提供的形成元件区的工艺示意图；图3D是本申请提供的通过湿法蚀刻工艺对第二金属层的第一区域进行蚀刻的工艺示意图；图3E是本申请提供的通过干法蚀刻工艺对第一区域进行图案化处理以形成源极和漏极的工艺示意图；图3F是本申请提供的通过干法蚀刻工艺对半导体层进行图案化处理的工艺示意图。Please refer to Figure 1, Figure 3A to Figure 3F. Figure 1 is a flow chart of the manufacturing method of the array substrate provided by the present application; Figure 3A is a method of sequentially forming a gate insulating layer, a semiconductor layer on a gate electrode and a base substrate provided by the present application. layer and the second metal layer; Figure 3B is a schematic diagram of the process of forming the second metal layer through a half-tone mask provided by the present application; Figure 3C is a schematic diagram of the process of forming the component region provided by the present application; Figure 3D is a schematic diagram of the process of forming the component region provided by the present application; The process schematic diagram provided by the application for etching the first area of the second metal layer through a wet etching process; Figure 3E is a patterning process provided by the application for the first area through a dry etching process to form the source and drain electrodes. 3F is a process schematic diagram of patterning a semiconductor layer through a dry etching process provided by this application.
本申请提供的阵列基板300的制作方法，可以包括以下步骤：The manufacturing method of the array substrate 300 provided by this application may include the following steps:
S10：提供衬底基板10，在衬底基板10上形成第一金属层20，采用第一道光罩工艺对第一金属层20进行图案化处理以形成栅极201，在栅极201和衬底基板10上依次形成栅极绝缘层30、半导体层40以及第二金属层60。S10: Provide a base substrate 10, form a first metal layer 20 on the base substrate 10, use a first mask process to pattern the first metal layer 20 to form a gate electrode 201, between the gate electrode 201 and the liner A gate insulating layer 30, a semiconductor layer 40 and a second metal layer 60 are formed on the base substrate 10 in sequence.
具体的，如图3A所示，可采用物理气相沉积工艺沉积第一金属层20，第一金属层20的材料可以为铜、铝或钼；通过第一道光罩工艺对第一金属层20进行曝光、显影以及刻蚀处理，以在衬底基板10上形成栅极201。需要说明的是，本实施例图3A至图3J中省略了栅极201的形成过程，即第一道光罩的制备工艺均省略了，具体制程是从第二道光罩，也就是本申请的改进点开始的。Specifically, as shown in FIG. 3A , a physical vapor deposition process can be used to deposit the first metal layer 20 , and the material of the first metal layer 20 can be copper, aluminum or molybdenum; the first metal layer 20 can be deposited through a first mask process. Exposure, development and etching processes are performed to form the gate electrode 201 on the base substrate 10 . It should be noted that the formation process of the gate 201 is omitted in FIGS. 3A to 3J of this embodiment, that is, the preparation process of the first photomask is omitted. The specific process is from the second photomask, which is the process of this application. Start with improvements.
如图3A所示，在栅极201和衬底基板10上沉积栅极绝缘层30，在栅极绝缘层30上沉积半导体层40，在半导体层40上沉积第二金属层60；栅极绝缘层30的材料可以为氧化硅或氮化硅。如图3D所示，半导体层40包括层叠设置的非晶硅层401和N+非晶硅层402，非晶硅层401形成于栅极绝缘层30上，N+非晶硅层402形成于非晶硅层401上。As shown in Figure 3A, a gate insulating layer 30 is deposited on the gate 201 and the base substrate 10, a semiconductor layer 40 is deposited on the gate insulating layer 30, and a second metal layer 60 is deposited on the semiconductor layer 40; gate insulation The material of layer 30 may be silicon oxide or silicon nitride. As shown in FIG. 3D , the semiconductor layer 40 includes a stacked amorphous silicon layer 401 and an N+ amorphous silicon layer 402 . The amorphous silicon layer 401 is formed on the gate insulating layer 30 , and the N+ amorphous silicon layer 402 is formed on the amorphous silicon layer 401 . on the silicon layer 401.
S20：采用第二道光罩工艺对第一区域的第二金属层60以及半导体层40进行图案化处理以形成源极601、漏极602以及非晶硅岛50，在阵列基板300的正投影方向，源极601的边缘与漏极602的边缘长度相等，且非晶硅岛50的边缘大于源极601的边缘以及漏极602的边缘。即，源极601的边缘与漏极602的边缘相对于非晶硅层401和N+非晶硅层402在两侧的长度相等。而在阵列基板300的正投影方向，非晶硅岛50的边缘大于源极601的边缘以及漏极602的边缘，使得在如图3D等图中所示的侧视方向，非晶硅岛50的长度在两侧均长于源极601的以及漏极602的长度。S20: Use a second mask process to pattern the second metal layer 60 and the semiconductor layer 40 in the first area to form the source electrode 601, the drain electrode 602 and the amorphous silicon island 50, in the orthographic projection direction of the array substrate 300 , the edge of the source electrode 601 and the edge of the drain electrode 602 are equal in length, and the edge of the amorphous silicon island 50 is larger than the edge of the source electrode 601 and the edge of the drain electrode 602 . That is, the edges of the source electrode 601 and the edge of the drain electrode 602 are equal in length on both sides relative to the amorphous silicon layer 401 and the N+ amorphous silicon layer 402 . In the orthographic projection direction of the array substrate 300, the edge of the amorphous silicon island 50 is larger than the edge of the source electrode 601 and the edge of the drain electrode 602, so that in the side view direction as shown in Figure 3D and other figures, the edge of the amorphous silicon island 50 The length of is longer than the length of the source electrode 601 and the drain electrode 602 on both sides.
具体的，如图3C至图3F所示，第一区域的第二金属层60对应于晶体管区域的元件区61，该元件区61即包括上述的源极601、漏极602以及非晶硅岛50，以形成TFT器件。通过单独的第二道光罩(如图3B所示的第二掩码版21)形成上述元件区61，通过第一光阻层100对第一区域进行刻蚀，避免形成源极601、漏极602以及非晶硅岛50的边缘对不齐等情况，从而使得形成的产品性能更好，避免形成上述边缘对不齐等情况，可以使得形成的源极601、漏极602以及非晶硅岛50等结构的膜层间Overlay(层叠覆盖)更优秀，对位效果更好，且导电性和透光率更好。在本实施例中，第二道光罩具体可以为半色调掩膜板。Specifically, as shown in FIGS. 3C to 3F , the second metal layer 60 in the first region corresponds to the element region 61 of the transistor region. The element region 61 includes the above-mentioned source electrode 601, drain electrode 602 and amorphous silicon island. 50, to form a TFT device. The above-mentioned component region 61 is formed through a separate second mask (the second mask 21 shown in FIG. 3B), and the first region is etched through the first photoresist layer 100 to avoid forming the source electrode 601 and the drain electrode. 602 and the edge misalignment of the amorphous silicon island 50, so that the formed product has better performance, avoiding the above edge misalignment, etc., can make the formed source electrode 601, drain electrode 602 and amorphous silicon island The overlay between the film layers of the 50 and other structures is better, the alignment effect is better, and the conductivity and light transmittance are better. In this embodiment, the second photomask may be a halftone mask.
需要说明的是，对半导体层40进行图案化处理以形成非晶硅岛50，包括对非晶硅层401和N+非晶硅层402均进行图案化处理，以去除非晶硅层尾纤和N+非晶硅层尾纤。It should be noted that patterning the semiconductor layer 40 to form the amorphous silicon island 50 includes patterning both the amorphous silicon layer 401 and the N+ amorphous silicon layer 402 to remove the amorphous silicon layer pigtails and N+ amorphous silicon layer pigtail.
进一步的，如图2所示，步骤S20具体可以包括以下步骤：Further, as shown in Figure 2, step S20 may specifically include the following steps:
具体请参阅图2、图3G至3J，图2是图1提供的步骤S20的子步骤的流程框图；图3G是本申请提供的通过湿法蚀刻工艺对半导体层进行图案化处理以形成非晶硅岛、非晶硅层和N+非晶硅层的工艺示意图；For details, please refer to Figure 2 and Figures 3G to 3J. Figure 2 is a flow chart of the sub-steps of step S20 provided in Figure 1; Figure 3G is a method of patterning the semiconductor layer through a wet etching process to form an amorphous layer provided by the present application. Process schematic diagram of silicon island, amorphous silicon layer and N+ amorphous silicon layer;
图3H是本申请提供的形成钝化层的工艺示意图；图3I是本申请提供的对钝化层进行图案化处理以形成过孔的工艺示意图；图3J是本申请提供的形成像素电极与过孔连接的工艺示意图。Figure 3H is a schematic diagram of the process of forming a passivation layer provided by this application; Figure 3I is a schematic diagram of the process of patterning the passivation layer to form via holes provided by this application; Figure 3J is a schematic diagram of the process of forming pixel electrodes and vias provided by this application Process diagram of hole connection.
S201：在第一区域的第二金属层60上涂覆光阻材料。S201: Coat a photoresist material on the second metal layer 60 in the first area.
S202：采用第二道光罩对光阻材料曝光显影以形成第一光阻层100。S202: Use a second photomask to expose and develop the photoresist material to form the first photoresist layer 100.
如图3B所示，通过第二掩码版21在第二金属层60远离半导体层40的一侧形成第一光阻层100，第一光阻层100具体可以为光刻胶层。如图3B所示，采用半色调掩膜板对光阻材料进行曝光、显影，以除去位于两侧边缘和对应沟道区603的部分光阻材料，保留下来的光阻材料形成第一光阻层100，对应沟道区603的第一光阻层100的厚度小于对应其它区域的第一光阻层100的厚度。As shown in FIG. 3B , a first photoresist layer 100 is formed on the side of the second metal layer 60 away from the semiconductor layer 40 through the second mask 21 . The first photoresist layer 100 may be a photoresist layer. As shown in FIG. 3B , a half-tone mask is used to expose and develop the photoresist material to remove part of the photoresist material located on both sides of the edge and corresponding to the channel area 603 , and the remaining photoresist material forms the first photoresist. Layer 100, the thickness of the first photoresist layer 100 corresponding to the channel region 603 is smaller than the thickness of the first photoresist layer 100 corresponding to other regions.
S203：刻蚀去除第一光阻层100未覆盖的第一区域的第二金属层60。S203: Etch and remove the second metal layer 60 in the first area not covered by the first photoresist layer 100.
具体的，如图3C所示，通过第一光阻层100对第二金属层60进行部分覆盖，然后通过干法刻蚀或者湿法刻蚀的方式去除未被第一光阻层100覆盖的区域，从而得到元件区61。例如可以采用湿法刻蚀的方式，由于湿法刻蚀具有各向同性，经湿法刻蚀处理之后的第一区域的第二金属层60(元件区61)在衬底基板10上的正投影位于第一光阻层100在衬底基板10上的正投影内，也就是说，至少未被第一光阻层100遮盖的第一区域的第二金属层60被去除，得到如图3C所示的元件区61。Specifically, as shown in FIG. 3C , the second metal layer 60 is partially covered by the first photoresist layer 100 , and then the parts not covered by the first photoresist layer 100 are removed by dry etching or wet etching. area, thereby obtaining component area 61. For example, wet etching can be used. Since wet etching is isotropic, the second metal layer 60 (component area 61) in the first region after wet etching is in the same direction on the base substrate 10. The projection is located within the orthographic projection of the first photoresist layer 100 on the base substrate 10 , that is to say, at least the second metal layer 60 in the first area not covered by the first photoresist layer 100 is removed, as shown in FIG. 3C Component area 61 is shown.
如图3D所示，通过湿法刻蚀工艺得到元件区61之后，可以进一步通过湿法刻蚀的工艺非晶硅岛50进行刻蚀，形成非晶硅层401和N+非晶硅层402。由于现有技术中半导体层临近其他第二金属层形成的导线有漏电风险，因此本申请中将刻蚀后的非晶硅层401和N+非晶硅层402的边缘在阵列基板300的正投影方向的整体长度相比于元件区61的边缘更长，可以避免漏电的问题。如图3D和3E所示，本申请因为在元件区61应用了四道光罩的制程，使得半导体层40和源极601、漏极602通过一道光罩形成，因此元件区61膜层结构的对位精度高，元件尺寸更精确，且元件性能更佳。As shown in FIG. 3D , after the element region 61 is obtained through a wet etching process, the amorphous silicon island 50 can be further etched through a wet etching process to form an amorphous silicon layer 401 and an N+ amorphous silicon layer 402 . Since in the prior art, there is a risk of leakage when the semiconductor layer is close to the wires formed by other second metal layers, in this application, the edges of the etched amorphous silicon layer 401 and the N+ amorphous silicon layer 402 are projected onto the orthogonal projection of the array substrate 300 The overall length of the direction is longer than the edge of the component area 61, which can avoid the problem of leakage. As shown in Figures 3D and 3E, this application uses a four-pass mask process in the component area 61, so that the semiconductor layer 40, the source electrode 601, and the drain electrode 602 are formed through one mask. Therefore, the layer structure of the component area 61 is opposite. High bit accuracy results in more accurate component dimensions and better component performance.
S204：对第一光阻层100进行灰化处理以形成第二光阻层200，第二光阻层200对应于源极601和漏极602。S204: The first photoresist layer 100 is ashed to form a second photoresist layer 200. The second photoresist layer 200 corresponds to the source electrode 601 and the drain electrode 602.
具体的，如图3E所示，对应于沟道区603的光阻材料被去除，保留下来的光阻材料形成第二光阻层200，第二光阻层200对应于后续需制备的源极601和漏极602。Specifically, as shown in FIG. 3E , the photoresist material corresponding to the channel region 603 is removed, and the remaining photoresist material forms the second photoresist layer 200 , and the second photoresist layer 200 corresponds to the source electrode to be prepared subsequently. 601 and drain 602.
S205：对第一区域的第二金属层60进行刻蚀处理以形成源极601和漏极602。S205: Etch the second metal layer 60 in the first region to form the source electrode 601 and the drain electrode 602.
同样地，如图3F和3G所示，可以采用湿法刻蚀的方式以去除对应沟道区603的元件区61，保留下来的第一区域的第二金属层60形成源极601和漏极602。具体可以先通过掩膜工艺去除元件区61中心的部分，即去除不需要保留的部分，剩下的区域即位于去除区域的两侧，分别形成源极601和漏极602。如图3G所示，在源极601和漏极602之间的区域进行进一步刻蚀，形成位于源极601和漏极602之间的沟道区603。Similarly, as shown in FIGS. 3F and 3G , wet etching can be used to remove the element region 61 corresponding to the channel region 603 , and the remaining second metal layer 60 in the first region forms the source electrode 601 and the drain electrode. 602. Specifically, the central portion of the element region 61 can be removed through a mask process, that is, the portion that does not need to be retained is removed, and the remaining regions are located on both sides of the removed region to form the source electrode 601 and the drain electrode 602 respectively. As shown in FIG. 3G , the area between the source electrode 601 and the drain electrode 602 is further etched to form a channel region 603 between the source electrode 601 and the drain electrode 602 .
S206：剥离第二光阻层200。S206: Peel off the second photoresist layer 200.
具体的，如图3G所示，将第二光阻层200从源极601和漏极602上剥离，使得源极601、漏极602以及沟道区603均裸露出来。在实际操作过程中，形成沟道区603的步骤以及剥离第二光阻层200的步骤可以在两个步骤中形成，也可以同步进行，本申请对此不做限制。Specifically, as shown in FIG. 3G , the second photoresist layer 200 is peeled off from the source electrode 601 and the drain electrode 602, so that the source electrode 601, the drain electrode 602 and the channel region 603 are all exposed. In actual operation, the step of forming the channel region 603 and the step of peeling off the second photoresist layer 200 can be formed in two steps, or can be performed simultaneously, and this application does not limit this.
S207：刻蚀去除未被源极601以及漏极602遮盖的半导体层40。S207: Etch and remove the semiconductor layer 40 that is not covered by the source electrode 601 and the drain electrode 602.
具体的，半导体层40包括非晶硅层401和N+非晶硅层402，步骤S207还可以包括干法刻蚀工艺去除位于沟道区603的N+非晶硅层402以露出非晶硅层401。Specifically, the semiconductor layer 40 includes an amorphous silicon layer 401 and an N+ amorphous silicon layer 402. Step S207 may also include a dry etching process to remove the N+ amorphous silicon layer 402 located in the channel region 603 to expose the amorphous silicon layer 401. .
同样地，采用干法刻蚀工艺去除位于沟道区603的N+非晶硅层402以露出非晶硅层401，从而完全除去位于沟道区603的N+非晶硅尾纤，即如图3H所示，位于沟道区603的N+非晶硅尾纤，使得非晶硅层401露出，进而形成TFT器件。由于无N+非晶硅尾纤的结构可以降低源极601和漏极602的金属面积，从而缩小TFT器件尺寸，节省版图空间。在本实施例中，去除沟道区的N+非晶硅层的厚度为以使得在保证TFT器件的功能完整的基础上，缩小TFT器件。Similarly, a dry etching process is used to remove the N+ amorphous silicon layer 402 located in the channel region 603 to expose the amorphous silicon layer 401, thereby completely removing the N+ amorphous silicon pigtail located in the channel region 603, as shown in Figure 3H As shown, the N+ amorphous silicon pigtail located in the channel region 603 exposes the amorphous silicon layer 401, thereby forming a TFT device. The structure without N+ amorphous silicon pigtails can reduce the metal area of the source electrode 601 and the drain electrode 602, thereby reducing the size of the TFT device and saving layout space. In this embodiment, the thickness of the N+ amorphous silicon layer removed from the channel region is This enables the TFT device to be reduced in size while ensuring the complete functionality of the TFT device.
请参阅图4至5F，图4是本申请提供的通过半色调掩膜版形成第二金属层的元件区和走线区的俯视结构示意图以及局部结构放大图；图5A至5F是本申请提供的通过5Mask工艺制备第二金属层的走线区的工艺流程图。具体的，图5A是本申请提供的通过第三道光罩以及干法蚀刻工艺对半导体层进行图案化处理的工艺示意图；图5B是本申请提供的沉积第二金属层的工艺示意图；图5C是本申请提供的对第二金属层的第二区域进行图案化处理以形成走线区的工艺示意图；图5D是本申请提供的在走线区远离半导体层的一侧形成钝化层的工艺示意图；图5E是本申请提供的对走线区的钝化层进行图案化处理以形成过孔的工艺示意图；图5F是本申请提供在走线区形成像素电极与过孔连接的工艺示意图。Please refer to Figures 4 to 5F. Figure 4 is a schematic top structural view and an enlarged view of the partial structure of the component area and wiring area of the second metal layer formed through a half-tone mask provided by this application; Figures 5A to 5F are provided by this application. The process flow chart of preparing the wiring area of the second metal layer through the 5Mask process. Specifically, FIG. 5A is a schematic diagram of the process of patterning the semiconductor layer through a third photomask and a dry etching process provided by this application; FIG. 5B is a schematic diagram of the process of depositing the second metal layer provided by this application; FIG. 5C is This application provides a schematic diagram of the process for patterning the second area of the second metal layer to form a wiring area; FIG. 5D is a schematic diagram of the process provided by this application for forming a passivation layer on the side of the wiring area away from the semiconductor layer. ; Figure 5E is a schematic diagram of the process provided by this application for patterning the passivation layer in the wiring area to form a via hole; Figure 5F is a schematic diagram of the process provided by this application for forming a connection between the pixel electrode and the via hole in the wiring area.
S25：采用第三道光罩对第二区域的第二金属层60进行图案化处理，以形成走线区62。S25: Use a third photomask to pattern the second metal layer 60 in the second area to form the wiring area 62.
具体的，如图5B和5C所示，第二区域的第二金属层60对应于晶体管区域的走线区62，该走线区62设置于非晶硅岛50、源极601和漏极602的侧面，用于对膜层间的电路进行连接。从图5B中的第二金属层60形成图5C中的走线区62同样可以湿法刻蚀的工艺进行，此处不再赘述。由于走线区62的线路数量繁多且距离较近，采用单独的第三道光罩形成上述走线区62，可以使得多个走线之间的距离保持地比较清楚明确，不容易发生短路，且走线区62和元件区61分开制作，使得每层走线的效果发挥地更好。采用第三道光罩对走线区62进行图案化的步骤如图5A至5F所示。需要说明的是，图5A至5F中省略了栅极201的形成过程，即第一道光罩的制备工艺均省略了，具体制程是从第二道光罩，也就是本申请的改进点开始的。Specifically, as shown in FIGS. 5B and 5C , the second metal layer 60 in the second region corresponds to the wiring region 62 in the transistor region, and the wiring region 62 is provided on the amorphous silicon island 50 , the source electrode 601 and the drain electrode 602 The side is used to connect the circuit between the film layers. Forming the wiring area 62 in FIG. 5C from the second metal layer 60 in FIG. 5B can also be performed by wet etching, which will not be described again here. Since the wiring area 62 has a large number of lines and a short distance, using a separate third photomask to form the wiring area 62 can keep the distance between multiple lines clear and clear, making short circuits less likely to occur, and The wiring area 62 and the component area 61 are manufactured separately, so that the wiring effect of each layer can be better exerted. The steps of using the third mask to pattern the wiring area 62 are shown in Figures 5A to 5F. It should be noted that the formation process of the gate 201 is omitted in Figures 5A to 5F, that is, the preparation process of the first photomask is omitted. The specific process starts from the second photomask, which is the improvement point of this application. .
设计时把第二金属层60的第一区域和半导体层40的图案分开设计，曝光时需要曝光两次(即5Mask工艺)，分别留下源极601、漏极602以及半导体层40的图案。During design, the patterns of the first region of the second metal layer 60 and the semiconductor layer 40 are designed separately, and two exposures (ie, 5Mask process) are required to leave the patterns of the source electrode 601, the drain electrode 602, and the semiconductor layer 40 respectively.
具体的，步骤S20和S25制作时，先通过半色调掩膜版曝光一次，如图4所示，在衬底基板10上留下Overlay更优秀的元件区61的图案，如图4中的A2部分和B2部分，其均具有半导体延伸部63，该半导体延伸部63具体为延伸至第二金属层60外侧、且没有被第二金属层60完全覆盖的半导体层40。Specifically, during the production of steps S20 and S25, first expose through the half-tone mask once, as shown in Figure 4, leaving a pattern of the component area 61 with better Overlay on the base substrate 10, as shown in A2 in Figure 4 The semiconductor extension portion 63 is the semiconductor layer 40 that extends to the outside of the second metal layer 60 and is not completely covered by the second metal layer 60 .
再对其他部分曝光两次，如图5C、图4中的A1部分和B1部分所示，留下膜层结构更优秀的走线区62的图案，从而使得既能保证元件区61的层叠效果，节省工序，又能防止走线区62的线路距离过近发生短路。从图4中的A1部分和B1部分可以看出，通过两次曝光形成走线区62的图中，不具有半导体延伸部63。Expose other parts twice, as shown in Figure 5C and Part A1 and Part B1 in Figure 4, leaving a pattern of wiring area 62 with a better film structure, thereby ensuring the stacking effect of component area 61 , saves processes, and prevents short circuits in the wiring area 62 from being too close. As can be seen from parts A1 and B1 in FIG. 4 , in the figure in which the wiring area 62 is formed by two exposures, there is no semiconductor extension part 63 .
本实施例提供的制作方法实际上是在5Mask的工艺中，对元件区61采用4Mask工艺形成TFT元件区61。具体的曝光步骤为正常曝光流程，可以包括成膜、涂布、显影、曝光、刻蚀和剥离等。The manufacturing method provided in this embodiment actually uses a 4Mask process for the element area 61 to form the TFT element area 61 in a 5Mask process. The specific exposure steps are the normal exposure process, which can include film formation, coating, development, exposure, etching and stripping.
S30：在栅极绝缘层30、源极601以及漏极602上形成钝化层70，采用第四道光罩工艺对钝化层70进行图案化处理，以形成过孔701。S30: Form a passivation layer 70 on the gate insulating layer 30, the source electrode 601 and the drain electrode 602, and use a fourth mask process to pattern the passivation layer 70 to form a via hole 701.
具体的，如图3H和图5D所示，可以采用物理气相沉积的方法沉积钝化层70，钝化层70的材料可以为氧化物、氮化物或者氧氮化合物。如图5E所示，再通过第四道光罩工艺对钝化层70进行曝光、显影和刻蚀处理以形成过孔701，如图3I所示。Specifically, as shown in FIG. 3H and FIG. 5D , the passivation layer 70 can be deposited using a physical vapor deposition method, and the material of the passivation layer 70 can be an oxide, a nitride, or an oxygen-nitride compound. As shown in FIG. 5E , the passivation layer 70 is exposed, developed and etched through a fourth mask process to form a via hole 701 , as shown in FIG. 3I .
S40：采用第五道光罩工艺在钝化层上图案化形成像素电极80，像素电极80通过过孔701与漏极602连接。S40: Use the fifth mask process to pattern the pixel electrode 80 on the passivation layer. The pixel electrode 80 is connected to the drain electrode 602 through the via hole 701.
具体的，在第二金属层60的第一区域，如图3I和3J所示，过孔701形成后，可通过溅射或热蒸发的方法沉积形成透明导电层(图未示)，然后通过第四道光罩工艺对透明导电层进行曝光、显影和刻蚀处理以形成像素电极80，像素电极80通过第一区域的过孔701与漏极602连接。Specifically, in the first area of the second metal layer 60, as shown in Figures 3I and 3J, after the via hole 701 is formed, a transparent conductive layer (not shown) can be deposited by sputtering or thermal evaporation, and then passed through The fourth mask process exposes, develops and etches the transparent conductive layer to form the pixel electrode 80. The pixel electrode 80 is connected to the drain electrode 602 through the via hole 701 in the first region.
在第二金属层60的第二区域，如图5E和图5F所示，过孔701形成后，可通过溅射或热蒸发的方法沉积形成透明导电层(图未示)，然后通过第五道光罩工艺对透明导电层进行曝光、显影和刻蚀处理以形成像素电极80，像素电极80通过第一区域的过孔701与漏极602连接通过第二区域的过孔701与走线区62连接。In the second area of the second metal layer 60, as shown in Figure 5E and Figure 5F, after the via hole 701 is formed, a transparent conductive layer (not shown) can be deposited by sputtering or thermal evaporation, and then passed through a fifth The mask process exposes, develops and etches the transparent conductive layer to form the pixel electrode 80. The pixel electrode 80 is connected to the drain electrode 602 through the via hole 701 in the first area and through the via hole 701 in the second area and the wiring area 62. connect.
可以理解的是，相比传统的4Mask工艺和5Mask，采用本申请提供的制作方法形成的阵列基板300，其裸露在源极601和漏极602外的非晶硅尾纤的长度仅为经过步骤S205中的湿法刻蚀处理后，源极601和漏极602退至第二光阻层200后的距离，且该步骤中采用的湿法刻蚀方式仅刻蚀源极601和漏极602，后退距离较小，故可有效缩小形成的非晶硅岛50的面积，进而缩小TFT器件尺寸，且有效提升高背光强度下大尺寸高分辨液晶面板的显示质量。It can be understood that, compared with the traditional 4Mask process and 5Mask, the length of the amorphous silicon pigtail exposed outside the source electrode 601 and the drain electrode 602 of the array substrate 300 formed using the manufacturing method provided by this application is only After the wet etching process in S205, the source electrode 601 and the drain electrode 602 retreat to the distance behind the second photoresist layer 200, and the wet etching method used in this step only etch the source electrode 601 and the drain electrode 602. , the retreat distance is small, so the area of the formed amorphous silicon island 50 can be effectively reduced, thereby reducing the size of the TFT device, and effectively improving the display quality of a large-size, high-resolution liquid crystal panel under high backlight intensity.
请参阅图7，图7是本申请提供的阵列基板的结构示意图。Please refer to FIG. 7 , which is a schematic structural diagram of the array substrate provided by the present application.
本申请还提供了一种阵列基板300，该阵列基板300包括衬底基板10、栅极201、栅极绝缘层30、非晶硅岛50、源极601、漏极602、钝化层70以及像素电极80。其中，栅极201位于衬底基板10上，栅极绝缘层30覆盖栅极201和衬底基板10，非晶硅岛50设置于栅极绝缘层30上。源极601和漏极602设置于非晶硅岛50上，源极601和漏极602之间形成沟道区603，钝化层70设置于栅极绝缘层30、源极601以及漏极602上，钝化层70上设置有过孔701，像素电极80设置于钝化层70上，像素电极80通过过孔701与漏极602连接导通。This application also provides an array substrate 300. The array substrate 300 includes a base substrate 10, a gate electrode 201, a gate insulating layer 30, an amorphous silicon island 50, a source electrode 601, a drain electrode 602, a passivation layer 70 and Pixel electrode 80. Among them, the gate electrode 201 is located on the base substrate 10 , the gate insulating layer 30 covers the gate electrode 201 and the base substrate 10 , and the amorphous silicon island 50 is disposed on the gate insulating layer 30 . The source electrode 601 and the drain electrode 602 are disposed on the amorphous silicon island 50. A channel region 603 is formed between the source electrode 601 and the drain electrode 602. The passivation layer 70 is disposed on the gate insulating layer 30, the source electrode 601 and the drain electrode 602. On the passivation layer 70 , a via hole 701 is provided, the pixel electrode 80 is provided on the passivation layer 70 , and the pixel electrode 80 is connected to the drain electrode 602 through the via hole 701 .
其中，在阵列基板300的正投影方向，源极601的边缘与漏极602的边缘长度相等，非晶硅岛50的边缘大于源极601的边缘以及漏极602的边缘。In the orthographic projection direction of the array substrate 300 , the edge lengths of the source electrode 601 and the drain electrode 602 are equal, and the edges of the amorphous silicon island 50 are longer than the edges of the source electrode 601 and the drain electrode 602 .
非晶硅岛50、源极601和漏极602形成于第二金属层60的第一区域，且非晶硅岛50、源极601和漏极602位于元件区61，具体可以参考前述内容以及图3A至图5F，此处不再赘述。The amorphous silicon island 50, the source electrode 601 and the drain electrode 602 are formed in the first region of the second metal layer 60, and the amorphous silicon island 50, the source electrode 601 and the drain electrode 602 are located in the element region 61. For details, please refer to the foregoing content and Figures 3A to 5F will not be described again here.
走线区62形成于第二金属层60的第二区域，走线区62设置于非晶硅岛50、源极601和漏极602的侧面，并通过走线区62导通非晶硅岛50和漏极602。The wiring area 62 is formed in the second area of the second metal layer 60. The wiring area 62 is disposed on the side of the amorphous silicon island 50, the source electrode 601 and the drain electrode 602, and conducts the amorphous silicon island through the wiring area 62. 50 and drain 602.
非晶硅岛50包括非晶硅层401和N+非晶硅层402，N+非晶硅层402对应于源极601和漏极602，非晶硅层401对应于源极601、漏极602以及沟道区603；非晶硅层401位于衬底基板10上，N+非晶硅层402位于非晶硅层401上，具体可以参考前述内容以及图3A至图5F，此处不再赘述。由于对应源极601的外侧和漏极602的外侧的栅极绝缘层30上无非晶硅尾纤和N+非晶硅尾纤，对应沟道区603的非晶硅层401上无N+非晶硅尾纤，因此能够避免折射或反射的光线照射到TFT器件裸露在外的部分半导体层40上时，导致TFT器件的漏电流增加的情况发生，进而提高TFT器件的光稳定性，同时能够缩小非晶硅岛50面积，进而缩小了TFT器件尺寸，有利于节省版图。The amorphous silicon island 50 includes an amorphous silicon layer 401 and an N+ amorphous silicon layer 402. The N+ amorphous silicon layer 402 corresponds to the source electrode 601 and the drain electrode 602, and the amorphous silicon layer 401 corresponds to the source electrode 601, the drain electrode 602 and the Channel region 603; amorphous silicon layer 401 is located on the base substrate 10, and N+ amorphous silicon layer 402 is located on the amorphous silicon layer 401. For details, please refer to the foregoing content and Figures 3A to 5F, which will not be described again here. Since there are no amorphous silicon pigtails and N+ amorphous silicon pigtails on the gate insulating layer 30 corresponding to the outside of the source electrode 601 and the outside of the drain electrode 602, there is no N+ amorphous silicon on the amorphous silicon layer 401 corresponding to the channel region 603. The pigtail can prevent the refracted or reflected light from irradiating the exposed part of the semiconductor layer 40 of the TFT device, resulting in an increase in the leakage current of the TFT device, thereby improving the light stability of the TFT device and at the same time shrinking the amorphous The silicon island area is 50%, which reduces the size of the TFT device and helps save layout.
请参阅图7，图7是本申请提供的显示面板的结构示意图。Please refer to FIG. 7 , which is a schematic structural diagram of a display panel provided by this application.
本申请还提供了一种显示面板400，包括阵列基板300、彩膜基板302和液晶层301，阵列基板300为上述任一项的阵列基板300，此处不再赘述。This application also provides a display panel 400, which includes an array substrate 300, a color filter substrate 302, and a liquid crystal layer 301. The array substrate 300 is any one of the above array substrates 300, which will not be described again here.
彩膜基板302与阵列基板300相对设置；彩膜基板302包括衬底(图未示)、位于衬底靠近阵列基板300一侧的滤光层(图未示)、黑矩阵(图未示)和透明导电层(图未示)，以及位于衬底远离阵列基板300一侧的偏光片(图未示)。滤光层包括红、蓝、绿三个颜色的滤光膜。彩膜基板302还可以包括其他功能层，此处不做限制。The color filter substrate 302 is arranged opposite to the array substrate 300; the color filter substrate 302 includes a substrate (not shown), a filter layer (not shown) located on the side of the substrate close to the array substrate 300, and a black matrix (not shown) and a transparent conductive layer (not shown), and a polarizer (not shown) located on the side of the substrate away from the array substrate 300 . The filter layer includes filter films of three colors: red, blue, and green. The color filter substrate 302 may also include other functional layers, which are not limited here.
液晶层301设置于阵列基板300与彩膜基板302之间，液晶层301包括多个间隔设置的液晶子单元3011，用于透射入射到显示面板400的光线。The liquid crystal layer 301 is disposed between the array substrate 300 and the color filter substrate 302. The liquid crystal layer 301 includes a plurality of liquid crystal sub-units 3011 arranged at intervals for transmitting light incident on the display panel 400.
本申请提供的阵列基板及其制作方法，采用第二道光罩工艺对第一区域的第二金属层以及半导体层进行图案化处理以形成源极、漏极以及非晶硅岛；非晶硅岛的边缘大于源极的边缘以及漏极的边缘；采用第三道光罩对第二区域的第二金属层进行图案化形成走线区。本申请结合4Mask工艺和5Mask工艺，通过将第二金属层划分为第一区域和第二区域进行分开制备，通过第二道光罩对第一区域的第二金属层以及半导体层进行图案化，获得膜层结构更优秀的源极、漏极以及非晶硅岛；通过第三道光罩对第二金属层的第二区域进行图案化，形成膜层间Overlay(层叠覆盖)更优秀、对位效果更优的走线区，从而克服4Mask工艺和5Mask工艺的缺陷，达到提高良率、加强膜层结构的目的。The array substrate and its manufacturing method provided by this application use a second mask process to pattern the second metal layer and semiconductor layer in the first area to form the source electrode, the drain electrode and the amorphous silicon island; the amorphous silicon island The edge is larger than the edge of the source electrode and the edge of the drain electrode; a third photomask is used to pattern the second metal layer in the second area to form a wiring area. This application combines the 4Mask process and the 5Mask process, by dividing the second metal layer into a first area and a second area for separate preparation, and patterning the second metal layer and the semiconductor layer in the first area through a second photomask to obtain The source, drain and amorphous silicon island have better film structure; the second area of the second metal layer is patterned through the third photomask to form a better overlay between film layers and better alignment effect A better routing area can overcome the defects of the 4Mask process and the 5Mask process to achieve the purpose of improving yield and strengthening the film structure.
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。The above descriptions are only embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies fields are equally included in the scope of patent protection of this application.
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| CN202310802606.6ACN116978863A (en) | 2023-06-30 | 2023-06-30 | Display panel, array substrate and manufacturing method thereof |
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| CN202310802606.6ACN116978863A (en) | 2023-06-30 | 2023-06-30 | Display panel, array substrate and manufacturing method thereof |
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|---|---|
| CN (1) | CN116978863A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117637772A (en)* | 2023-12-12 | 2024-03-01 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method thereof and display panel |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117637772A (en)* | 2023-12-12 | 2024-03-01 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method thereof and display panel |
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