本申请基于并要求于2022年4月25日在韩国知识产权局提交的第10-2022-0051031号韩国专利申请和于2022年7月22日在韩国知识产权局提交的第10-2022-0091318号韩国专利申请的优先权，所述韩国专利申请的公开通过引用全部包含于此。This application is based on and requires Korean Patent Application No. 10-2022-0051031 filed with the Korean Intellectual Property Office on April 25, 2022, and Korean Patent Application No. 10-2022-0091318 filed with the Korean Intellectual Property Office on July 22, 2022. No. Korean Patent Application No., the disclosure of which is incorporated herein by reference in its entirety.
技术领域Technical field
发明构思涉及用于优化多列(rank)的片上终结(on-die termination，ODT)设置的存储器系统、存储器系统的操作方法及存储器控制器，更具体地，涉及有效地将关于存储器列(memory rank，又称为存储器排)的信息存储在存储器列中的信息存储单元中并且执行存储器访问的方法，关于存储器列的信息允许目标列或非目标列的识别。The inventive concept relates to a memory system, an operating method of the memory system, and a memory controller for optimizing on-die termination (ODT) settings of multiple ranks, and more particularly, to effectively integrating information about a memory rank. A method in which information about a rank, also known as a memory rank, is stored in an information storage unit in a memory column and a memory access is performed. The information about the memory column allows the identification of a target column or a non-target column.
背景技术Background technique
面向移动的存储器装置(诸如，低功率双倍数据速率(LPDDR)同步动态随机存取存储器(SDRAM))主要用于移动电子器件(诸如，智能电话、平板PC和超级本)。随着移动操作系统(OS)的容量增加以支持在移动电子装置上执行的多任务操作，需要具有高速操作性能同时具有更低功耗特性的移动电子装置。Mobile-oriented memory devices such as low power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM) are primarily used in mobile electronic devices such as smartphones, tablet PCs, and ultrabooks. As the capacity of mobile operating systems (OS) increases to support multi-task operations performed on mobile electronic devices, mobile electronic devices with high-speed operating performance while having lower power consumption characteristics are required.
高速存储器系统可包括多个LPDDR SDRAM芯片(在下文中，称为“LPDDR存储器芯片”)和存储器控制器。存储器控制器可从诸如功率控制、地址指定和存储器访问的角度将来自多个LPDDR存储器芯片的各个芯片划分成逻辑组和/或物理组。例如，多个LPDDR存储器芯片可被包括在多个列中的一个列中，多个列可被划分成目标列和非目标列。目标列可包括根据存储器重播(memory recast)执行存储器访问的存储器芯片，并且非目标列可包括不执行存储器访问的存储器芯片。在多列存储器系统中，可通过激活目标列的芯片选择信号(CS)来选择该列。此后，对于被加载读取/写入数据以用于目标列的读取或写入操作的数据线，可能需要ODT操作。例如，对于在列到列操作时被加载第一列的写入数据和第二列的读取数据的数据线，需要tODToff参数时段。tODToff参数指示断开第一列的ODT电路所需的延迟时间，第一列的ODT电路从存储器控制器接收写入数据。在tODToff参数时段之后，从第二列输出的读取数据可通过数据线被发送到存储器控制器。列到列操作可被设置为对第一列执行读取操作，然后对第二列执行写入操作。在这种情况下，需要tODTon参数时段。tODTon参数指示接通第二列的ODT电路所需的延迟时间，第二列的ODT电路接收写入数据。The high-speed memory system may include a plurality of LPDDR SDRAM chips (hereinafter, referred to as "LPDDR memory chips") and a memory controller. The memory controller may divide individual chips from multiple LPDDR memory chips into logical groups and/or physical groups from perspectives such as power control, address designation, and memory access. For example, a plurality of LPDDR memory chips may be included in one of a plurality of columns, and the plurality of columns may be divided into target columns and non-target columns. The target columns may include memory chips that perform memory accesses according to memory recast, and the non-target columns may include memory chips that do not perform memory accesses. In a multi-column memory system, a column is selected by activating the chip select signal (CS) of the target column. Thereafter, an ODT operation may be required for the data line that is loaded with read/write data for the read or write operation of the target column. For example, for a data line that is loaded with write data for the first column and read data for the second column during column-to-column operation, the tODToff parameter period is required. The tODToff parameter indicates the delay time required to turn off the ODT circuit of the first column that receives write data from the memory controller. After the tODToff parameter period, the read data output from the second column may be sent to the memory controller via the data line. Column-to-column operations can be set up to perform a read operation on the first column and then a write operation on the second column. In this case, the tODTon parameter period is required. The tODTon parameter indicates the delay time required to turn on the ODT circuit of the second column, which receives the write data.
然而，在用于通过芯片选择信号(CS)和ODT操作来实现向目标列的转换的存储器芯片的情况下，硬件配置变得复杂，功耗增加，并且由于对ODT的响应延迟，高速操作性能不好。However, in the case of a memory chip for realizing conversion to a target column through a chip select signal (CS) and an ODT operation, the hardware configuration becomes complicated, power consumption increases, and high-speed operation performance decreases due to a delay in response to ODT not good.
发明内容Contents of the invention
发明构思提供了能够有效地将关于存储器列的信息存储在存储器列中的信息存储单元中并且在没有复杂的硬件和时序延迟的情况下执行存储器访问的存储器装置，关于存储器列的信息允许目标列或非目标列的识别。The inventive concept provides a memory device capable of efficiently storing information about a memory column, the information about the memory column allowing a target column, in an information storage unit in the memory column and performing memory access without complex hardware and timing delays. or identification of non-target columns.
根据发明构思的一些实施例，提供了一种存储器系统，所述存储器系统包括：主机系统，包括存储器控制器，存储器控制器被配置为基于多个存储器列的目标信息或非目标信息来控制对所述多个存储器列的读取操作或写入操作；以及多列存储器装置，包括存储设备，存储设备被配置为存储存储器列的片上终结(ODT)信息。这里，存储器控制器还被配置为：确定将被读取或写入的目标列，并且将关于确定的目标列的信息发送到多列存储器装置，并且多列存储器装置还被配置为：执行对存储在存储设备中的存储器列的ODT信息与从存储器控制器接收的目标信息或非目标信息的比较，并且基于从存储器控制器接收的目标信息并基于所述比较的结果来更改目标列的ODT值。According to some embodiments of the inventive concept, a memory system is provided, the memory system including: a host system, including a memory controller configured to control a target based on target information or non-target information of a plurality of memory columns. a read operation or a write operation of the plurality of memory ranks; and a multi-rank memory device including a storage device configured to store on-die termination (ODT) information for the memory ranks. Here, the memory controller is further configured to determine a target column to be read or written, and send information about the determined target column to the multi-column memory device, and the multi-column memory device is further configured to: perform the Comparing the ODT information of the memory column stored in the storage device with the target information or non-target information received from the memory controller, and changing the ODT of the target column based on the target information received from the memory controller and based on the result of the comparison value.
根据发明构思的一些实施例，提供了一种操作存储器系统的方法，存储器系统包括被配置为共享信号线的多个存储器列。所述方法包括：通过包括存储器控制器的主机系统，基于多个存储器列的目标信息或非目标信息来控制对所述多个存储器列的读取操作或写入操作；以及将存储器列的片上终结(ODT)信息存储在多列存储器装置的存储设备中。控制对所述多个存储器列的读取操作或写入操作的步骤包括：确定将被读取或写入的目标列，并且将关于确定的目标列的信息发送到多列存储器装置；将存储在存储设备中的存储器列的ODT信息与从存储器控制器接收的目标信息或非目标信息进行比较；以及基于从存储器控制器接收的目标信息并基于所述比较的结果来更改目标列的ODT值。According to some embodiments of the inventive concept, a method of operating a memory system including a plurality of memory columns configured to share signal lines is provided. The method includes: controlling, by a host system including a memory controller, a read operation or a write operation on a plurality of memory columns based on target information or non-target information of the plurality of memory columns; and converting an on-chip memory column to Termination (ODT) information is stored in the storage device of the multi-rank memory device. The step of controlling read operations or write operations on the plurality of memory columns includes: determining a target column to be read or written, and sending information about the determined target column to the multi-column memory device; storing Comparing the ODT information of the memory column in the storage device with the target information or non-target information received from the memory controller; and changing the ODT value of the target column based on the target information received from the memory controller and based on the result of the comparison. .
发明构思的一些实施例包括一种主机系统，所述主机系统包括存储器装置和存储器控制器。存储器控制器被配置为控制对存储器装置的读取操作或写入操作，存储器装置包括共享信号线的多个存储器列。存储器控制器还被配置为控制存储器装置以确定将被读取或写入的目标列，并且将关于确定的目标列的信息发送到存储器装置。存储器控制器还被配置为将存储在存储器装置的存储设备中的存储器列的片上终结(ODT)信息与从存储器控制器接收的目标信息或非目标信息进行比较，并且基于目标信息并基于所述比较的结果来更改目标列的ODT值。Some embodiments of the inventive concepts include a host system including a memory device and a memory controller. The memory controller is configured to control read operations or write operations to a memory device including a plurality of memory columns sharing signal lines. The memory controller is further configured to control the memory device to determine a target column to be read or written, and to send information about the determined target column to the memory device. The memory controller is further configured to compare on-die termination (ODT) information for a memory rank stored in a storage device of the memory device with target information or non-target information received from the memory controller, and based on the target information and based on the The comparison result is used to change the ODT value of the target column.
附图说明Description of the drawings
通过以下结合附图的详细描述，将更清楚地理解实施例，其中：The embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:
图1是示出根据一些实施例的电子装置的框图；Figure 1 is a block diagram illustrating an electronic device according to some embodiments;
图2和图3是示出图1的存储器装置的框图；Figures 2 and 3 are block diagrams illustrating the memory device of Figure 1;
图4是示出根据一些实施例的目标列在存储器系统中执行读取操作的情况的框图；4 is a block diagram illustrating a target column performing a read operation in a memory system according to some embodiments;
图5是示出根据一些实施例的在存储器系统中的目标列中执行写入操作的情况的框图；Figure 5 is a block diagram illustrating a scenario in which a write operation is performed in a target column in a memory system, in accordance with some embodiments;
图6是示出根据一些实施例的在存储器系统中执行读取操作的情况的时序图；Figure 6 is a timing diagram illustrating a situation in which a read operation is performed in a memory system according to some embodiments;
图7是示出根据一些实施例的在存储器系统中执行写入操作的情况的时序图；7 is a timing diagram illustrating a situation in which a write operation is performed in a memory system according to some embodiments;
图8和图9示出根据一些实施例的在存储器系统中的目标列中执行写入操作的情况；Figures 8 and 9 illustrate a situation in which a write operation is performed in a target column in a memory system according to some embodiments;
图10和图11示出根据一些实施例的在存储器系统中的目标列中执行读取操作的情况；Figures 10 and 11 illustrate execution of a read operation in a target column in a memory system in accordance with some embodiments;
图12是根据一些实施例的存储器系统的操作方法的流程图；Figure 12 is a flowchart of a method of operating a memory system in accordance with some embodiments;
图13是根据一些实施例的存储器系统的操作方法中的目标列的读取操作的流程图；Figure 13 is a flowchart of a read operation of a target column in a method of operating a memory system according to some embodiments;
图14是根据一些实施例的存储器系统的操作方法中的目标列的写入操作的流程图；以及14 is a flowchart of a write operation of a target column in a method of operating a memory system according to some embodiments; and
图15是根据一些实施例的将存储器系统应用于移动装置的示例的框图。Figure 15 is a block diagram of an example of applying a memory system to a mobile device, in accordance with some embodiments.
具体实施方式Detailed ways
图1是示出根据一些实施例的电子装置的框图。Figure 1 is a block diagram illustrating an electronic device according to some embodiments.
参照图1，电子装置100可包括主机系统110和多列存储器装置120。电子装置100可包括在个人计算机(PC)或移动电子装置中。移动电子装置可被实现为膝上型计算机、移动电话、智能电话、平板PC、个人数字助理(PDA)、企业数字助理(EDA)、数字相机、数字摄像机、便携式多媒体播放器(PMP)、个人导航装置或便携式导航装置(PND)、手持式游戏机、移动互联网装置(MID)、可穿戴计算机、物联网(IoT)装置、万物联网(IoE)装置或无人机。Referring to FIG. 1 , the electronic device 100 may include a host system 110 and a multi-rank memory device 120 . Electronic device 100 may be included in a personal computer (PC) or a mobile electronic device. Mobile electronic devices may be implemented as laptop computers, mobile phones, smartphones, tablet PCs, personal digital assistants (PDA), enterprise digital assistants (EDA), digital cameras, digital camcorders, portable multimedia players (PMP), personal Navigation device or Portable Navigation Device (PND), handheld game console, Mobile Internet Device (MID), wearable computer, Internet of Things (IoT) device, Internet of Everything (IoE) device or drone.
主机系统110是电子装置100的处理和管理命令的主要组件，并且主要负责操作系统和应用的执行。此外，主机系统110可允许将工作负载分配给多个计算实体，使得工作负载可被并行处理以解决复杂任务。主机系统110是被配置为执行可由一个或多个机器或软件、固件或它们的组合执行的命令的功能块。主机系统110可使用用于在电子装置100中执行计算和其他操作(例如，控制操作、配置操作等)的硬件(即，各种电路元件和装置)来实现。The host system 110 is the main component of the electronic device 100 for processing and managing commands, and is mainly responsible for the execution of operating systems and applications. Additionally, host system 110 may allow workloads to be distributed to multiple computing entities so that workloads may be processed in parallel to solve complex tasks. Host system 110 is a functional block configured to execute commands executable by one or more machines or software, firmware, or a combination thereof. Host system 110 may be implemented using hardware (ie, various circuit elements and devices) for performing calculations and other operations (eg, control operations, configuration operations, etc.) in electronic device 100 .
主机系统110可被实现为集成电路(IC)、片上系统(SoC)、应用处理器(AP)、移动AP、芯片集或芯片组。作为示例，主机系统110可以是用于执行存储器控制功能的半导体装置，并且可包括存储器控制器112。主机系统110还可包括RAM、中央处理器(CPU)、图形处理器(GPU)和/或调制解调器。Host system 110 may be implemented as an integrated circuit (IC), system on a chip (SoC), application processor (AP), mobile AP, chipset, or chipset. As an example, host system 110 may be a semiconductor device for performing memory control functions and may include memory controller 112 . Host system 110 may also include RAM, a central processing unit (CPU), a graphics processing unit (GPU), and/or a modem.
多列存储器装置120由执行电子装置100的存储器(例如，主存储器)的操作的功能块组成，并且可被实现为LPDDR SDRAM。LPDDR SDRAM可包括存储器电路，并且可处理对存储在存储器电路中的数据和命令的存取，并执行其他控制或配置操作。LPDDR SDRAM是“动态”存储器电路。动态存储器电路使用电路元件(诸如，由于泄漏和/或其他电荷损失机制而随时间损失电荷的电容器)来存储信息(例如，诸如数据和命令的信息位)。由一个晶体管和一个存储电容器组成的DRAM单元显示出可变的数据保持特性，并且通过周期性地执行刷新操作再次存储DRAM单元数据来防止存储信息的丢失。The multi-column memory device 120 is composed of functional blocks that perform operations of the memory (eg, main memory) of the electronic device 100 and may be implemented as LPDDR SDRAM. LPDDR SDRAM may include memory circuitry and may handle access to data and commands stored in the memory circuitry and perform other control or configuration operations. LPDDR SDRAM is a "dynamic" memory circuit. Dynamic memory circuits use circuit elements, such as capacitors that lose charge over time due to leakage and/or other charge loss mechanisms, to store information (eg, bits of information such as data and commands). A DRAM cell consisting of a transistor and a storage capacitor exhibits variable data retention characteristics, and the loss of stored information is prevented by periodically performing a refresh operation to store the DRAM cell data again.
多列存储器装置120可包括多个存储器芯片121和122。例如，多个存储器芯片121和122中的每个包括存储器单元阵列，并且存储器单元阵列包括包含多个存储体的多个存储体组，并且每个存储体可包括多个存储器单元行(或页)。Multi-rank memory device 120 may include multiple memory chips 121 and 122 . For example, each of the plurality of memory chips 121 and 122 includes a memory cell array, and the memory cell array includes a plurality of memory bank groups including a plurality of memory banks, and each memory bank may include a plurality of memory cell rows (or pages). ).
多个存储器芯片121和122可包括LPDDR SDRAM，并且可在逻辑上和/或物理上被划分成至少两列。在一些实施例中，示出多列存储器装置120具有2列结构，但是实施例限于此，并且多列存储器装置120可具有各种列结构。在以下实施例中，为了便于描述，存储器芯片121可被称为第一列121，并且存储器芯片122可被称为第二列122。此外，第一列121和第二列122以及术语RANK0和RANK1可互换使用。The plurality of memory chips 121 and 122 may include LPDDR SDRAM, and may be logically and/or physically divided into at least two columns. In some embodiments, the multi-column memory device 120 is shown as having a 2-column structure, but embodiments are limited thereto and the multi-column memory device 120 may have various column structures. In the following embodiments, for convenience of description, the memory chips 121 may be referred to as the first column 121 , and the memory chips 122 may be referred to as the second column 122 . Furthermore, the first column 121 and the second column 122 and the terms RANK0 and RANK1 may be used interchangeably.
图1的存储器控制器112是用于管理和控制主机系统110与多列存储器装置120之间的交互以及以另外的方式处理交互的功能块。例如，存储器控制器112可代表主机系统110执行存储器访问(即，读取、写入等)，并且执行用于多列存储器装置120的配置和控制操作和/或其他操作。存储器控制器112可通过通道130与多列存储器装置120通信。通道130可被实现为总线，该总线包括传输时钟信号CK_t和CK_c(在下文中，称为“CK”)、数据时钟信号WCK_t和WCK_c(在下文中，称为“WCK”)以及读取数据选通信号RDQS_t和RDQS_c(在下文中，称为“RDQS”)的时钟信号线、传输命令/地址CMD/ADDR的CA信号线(在下文中，称为“CA”)、以及传输数据的DQ线(在下文中，称为“DQ”)。Memory controller 112 of Figure 1 is a functional block for managing, controlling, and otherwise handling interactions between host system 110 and multi-rank memory device 120. For example, memory controller 112 may perform memory accesses (ie, reads, writes, etc.) on behalf of host system 110 and perform configuration and control operations for multi-rank memory device 120 and/or other operations. Memory controller 112 may communicate with multi-rank memory device 120 via channel 130 . The channel 130 may be implemented as a bus including transmission clock signals CK_t and CK_c (hereinafter, referred to as "CK"), data clock signals WCK_t and WCK_c (hereinafter, referred to as "WCK"), and read data strobes. The clock signal line No. RDQS_t and RDQS_c (hereinafter, referred to as "RDQS"), the CA signal line transmitting the command/address CMD/ADDR (hereinafter, referred to as "CA"), and the DQ line transmitting data (hereinafter, referred to as "CA") , called "DQ").
这里，主机系统110可通过存储器控制器112向多列存储器装置120发送根据读取操作或写入操作的包含ODT信息的命令CA_ODT。包含ODT信息的命令CA_ODT可包含确定目标列的ODT信息，并且将参照图4和图5详细描述对目标列执行读取操作或写入操作的情况。Here, the host system 110 may send the command CA_ODT including the ODT information according to the read operation or the write operation to the multi-column memory device 120 through the memory controller 112 . The command CA_ODT containing ODT information may contain ODT information that determines the target column, and the case of performing a read operation or a write operation on the target column will be described in detail with reference to FIGS. 4 and 5 .
图2和图3是示出图1的多列存储器装置120的框图。2 and 3 are block diagrams illustrating the multi-column memory device 120 of FIG. 1 .
参照图2，根据一些实施例的多列存储器装置120包括多个存储器列121、122、……等。在下文中，为了便于描述，将描述关于第一列121RANK0和第二列122RANK1的实施例，但是实施例还可包括包含多个存储器列的情况。Referring to Figure 2, a multi-column memory device 120 according to some embodiments includes a plurality of memory columns 121, 122, . . . , etc. Hereinafter, for convenience of description, the embodiment will be described with respect to the first column 121RANK0 and the second column 122RANK1, but the embodiment may also include a case where a plurality of memory columns are included.
根据一些实施例的存储器列121和122可分别包括存储设备121a和122a。关于相应的存储器列RANK0和RANK1的信息可分别预存储在存储设备121a和122a中。这里，存储设备121a和122a可包括非易失性存储器装置，但不限于此。Memory columns 121 and 122 according to some embodiments may include storage devices 121a and 122a, respectively. Information about corresponding memory columns RANK0 and RANK1 may be pre-stored in storage devices 121a and 122a respectively. Here, the storage devices 121a and 122a may include non-volatile memory devices, but are not limited thereto.
此外，为了便于描述，多列存储器装置120的存储器列121和122可被分类为第一列121RANK0和第二列122RANK1。这里，基于从主机系统110接收的信息，第一列121RANK0可被定义为将被读取或写入的目标存储器列。此外，第二列122RANK1可被定义为不被读取或写入的非目标列。这同样适用于下面将描述的第一列和第二列的描述。Furthermore, for convenience of description, the memory columns 121 and 122 of the multi-column memory device 120 may be classified into a first column 121RANK0 and a second column 122RANK1. Here, based on the information received from the host system 110, the first column 121RANKO may be defined as the target memory column to be read or written. Additionally, the second column 122RANK1 may be defined as a non-target column that is not read or written. The same applies to the description of the first and second columns, which will be described below.
存储器控制器112可控制上述第一列121和第二列122的读取或写入操作。例如，主机系统110的存储器控制器112可通过CA线将包括读取或写入命令的命令发送到多个存储器列121和122。由存储器控制器112发送的命令可包含指定目标列的信息。The memory controller 112 may control the read or write operations of the first column 121 and the second column 122. For example, memory controller 112 of host system 110 may send commands including read or write commands to multiple memory columns 121 and 122 over the CA line. The command sent by memory controller 112 may include information specifying the target column.
此外，存储器控制器112可将第一列121和第二列122分类为目标列和非目标列。存储器控制器112可通过使用通过CA信号线传输的命令来区分目标列与非目标列。例如，存储器控制器112可将目标列的信息包括在通过通道130的CA信号线传输的读取或写入命令中。存储器控制器112可读取存储在第一列121的存储设备121a和第二列122的存储设备122a中的列信息。存储器控制器112可通过通道130的CA信号线接收存储在存储设备121a和122a中的列信息。存储器控制器112可将从第一列121和第二列122读取的列信息与作为默认值存储在存储器控制器112中的第一列121和第二列122的列信息进行比较。作为比较的结果，如果从第一列121和第二列122读取的列信息与作为默认值存储在存储器控制器112中的第一列121和第二列122的列信息不相同，则存储器控制器112可将第一列121和第二列122的列信息更改为读取的列信息并存储读取的列信息。In addition, the memory controller 112 may classify the first column 121 and the second column 122 into target columns and non-target columns. The memory controller 112 may distinguish target columns from non-target columns using commands transmitted over the CA signal line. For example, memory controller 112 may include the target column's information in a read or write command transmitted over the CA signal line of channel 130 . The memory controller 112 may read column information stored in the storage device 121a of the first column 121 and the storage device 122a of the second column 122. Memory controller 112 may receive column information stored in memory devices 121a and 122a through the CA signal line of channel 130. The memory controller 112 may compare the column information read from the first column 121 and the second column 122 with the column information of the first column 121 and the second column 122 stored as default values in the memory controller 112 . As a result of the comparison, if the column information read from the first column 121 and the second column 122 is not the same as the column information of the first column 121 and the second column 122 stored in the memory controller 112 as a default value, the memory The controller 112 may change the column information of the first column 121 and the second column 122 to the read column information and store the read column information.
例如，第一列121的存储设备121a可将其列信息设置为单个“0”比特值。第二列122的存储设备122a可将其列信息设置为单个“1”比特值。根据一些实施例，如果多列存储器装置120包括比两列结构多的列，则可使用两个或更多个比特来存储列信息。For example, storage device 121a of first column 121 may have its column information set to a single "0" bit value. The storage device 122a of the second column 122 may have its column information set to a single "1" bit value. According to some embodiments, if multi-column memory device 120 includes more columns than a two-column structure, two or more bits may be used to store column information.
为了准确地执行针对目标列的存储器操作，存储器控制器112可使用第一列121和第二列122中的每个的列信息作为相应列的ODT信息。In order to accurately perform the memory operation for the target column, the memory controller 112 may use the column information of each of the first column 121 and the second column 122 as the ODT information of the corresponding column.
另外，存储器控制器112可对存储器列121和122执行刷新操作。例如，存储器控制器112可在对目标列执行读取或写入操作之后执行恢复目标列的刷新操作。Additionally, memory controller 112 may perform refresh operations on memory columns 121 and 122 . For example, memory controller 112 may perform a refresh operation to restore the target column after performing a read or write operation on the target column.
参照图3，第一列121可通过通道130的时钟信号线、CA信号线和数据总线连接到存储器控制器112。Referring to FIG. 3 , the first column 121 may be connected to the memory controller 112 through the clock signal line, CA signal line, and data bus of the channel 130 .
由存储器控制器112生成的时钟信号CK可通过时钟信号线被提供给第一列121。例如，时钟信号CK可与反相时钟信号(CKB)一起被提供为连续交替的反相信号。因为可从时钟信号对(CK、CKB)的交叉点检测上升/下降沿，所以时钟信号对(CK、CKB)可提高时序精度。时钟信号线可使用时钟信号对(CK、CKB)来传输互补的连续交替的反相信号。在这种情况下，时钟信号线可由用于传输时钟信号CK和CKB的两条信号线组成。实施例中描述的时钟信号CK可被描述为时钟信号对(CK、CKB)。为了便于描述，时钟信号对(CK、CKB)被统称为时钟信号CK。The clock signal CK generated by the memory controller 112 may be provided to the first column 121 through the clock signal line. For example, the clock signal CK may be provided together with an inverted clock signal (CKB) as a continuously alternating inverted signal. The clock signal pair (CK, CKB) improves timing accuracy because rising/falling edges can be detected from the intersection point of the clock signal pair (CK, CKB). The clock signal line may use a clock signal pair (CK, CKB) to transmit complementary, continuously alternating inverted signals. In this case, the clock signal line may be composed of two signal lines for transmitting the clock signals CK and CKB. The clock signal CK described in the embodiment can be described as a clock signal pair (CK, CKB). For convenience of description, the clock signal pair (CK, CKB) is collectively referred to as the clock signal CK.
从存储器控制器112发送的命令信号可通过CA信号线被提供给第一列121。另外，由存储器控制器112发出的地址信号可通过CA信号线被提供给第一列121。命令信号或地址信号可经由CA信号线通过以时间序列接收的命令/地址信号的组合被发出。The command signal sent from the memory controller 112 may be provided to the first column 121 through the CA signal line. In addition, the address signal issued by the memory controller 112 may be provided to the first column 121 through the CA signal line. A command signal or an address signal may be issued via the CA signal line by a combination of command/address signals received in a time sequence.
数据DQ可通过用于存储器控制器112与第一列121之间的数据接口的数据总线来传输。例如，由存储器控制器112提供的写入数据DQ可通过数据总线被发送到第一列121。在第一列121中读取的读取数据DQ可通过数据总线被发送到存储器控制器112。Data DQ may be transmitted through a data bus for the data interface between memory controller 112 and first column 121 . For example, the write data DQ provided by the memory controller 112 may be sent to the first column 121 through the data bus. The read data DQ read in the first column 121 may be sent to the memory controller 112 through the data bus.
第一列121可包括模式寄存器310、控制电路320和ODT电路(ODT)330。控制电路320通常可控制第一列121的操作。控制电路320可生成控制信号以执行写入操作、读取操作和/或刷新操作。The first column 121 may include a mode register 310, a control circuit 320, and an ODT circuit (ODT) 330. Control circuit 320 may generally control the operation of first column 121 . Control circuit 320 may generate control signals to perform write operations, read operations, and/or refresh operations.
模式寄存器310可对第一列121的功能、特性和/或模式进行编程。模式寄存器310可由模式寄存器设置(MRS)命令编程并且可编程为用户定义的变量。取决于功能、特性和/或模式，模式寄存器310可被划分成各种字段。由于并非模式寄存器310中的所有寄存器都具有定义的默认值，因此模式寄存器310的内容可被初始化。也就是说，可在复位之后对模式寄存器310的内容进行编程以用于上电和/或校正操作。另外，模式寄存器310的内容可由于在正常操作期间重新执行模式寄存器设置(MRS)命令而被改变。因此，第一列121的功能、特性和/或模式可被更新。Mode register 310 may program the functionality, features, and/or modes of first column 121 . Mode register 310 is programmable by a mode register set (MRS) command and programmable as user-defined variables. Mode register 310 may be divided into various fields depending on functionality, features and/or mode. Since not all registers in mode register 310 have defined default values, the contents of mode register 310 may be initialized. That is, the contents of mode register 310 may be programmed after reset for power-up and/or calibration operations. Additionally, the contents of mode register 310 may be changed due to re-execution of a mode register set (MRS) command during normal operation. Accordingly, the functions, properties and/or modes of the first column 121 may be updated.
例如，模式寄存器310可存储用于控制突发长度(BL)、读取突发类型(RBT)、列地址选通(CAS)延迟(CL)、测试模式、延迟锁定环(DLL)复位、DLL启用/禁用、输出驱动强度、附加延迟(AL)、输出缓冲器启用/禁用、CAS写入延迟、断电模式、数据掩码功能、写入数据总线反转(DBI)功能、读取DBI功能等的数据。For example, mode register 310 may store information used to control burst length (BL), read burst type (RBT), column address strobe (CAS) delay (CL), test mode, delay locked loop (DLL) reset, DLL Enable/disable, output drive strength, additive delay (AL), output buffer enable/disable, CAS write delay, power-down mode, data mask function, write data bus inversion (DBI) function, read DBI function Waiting data.
另外，模式寄存器310可存储用于控制第一列121和第二列122中的每个的ODT功能的信息。用于控制ODT功能的信息可包括SoC ODT功能、CK ODT功能、CS ODT功能、CA ODT功能和/或DQ ODT功能。可提供SoC ODT功能以通过调整在存储器控制器112与第一列121之间传输的信号的摆动宽度和/或驱动器强度来改善信号完整性(SI)。CK ODT功能用于执行时钟信号接收器的ODT启用或禁用操作。在CS ODT功能中，当存储器装置120以多列配置实现时，可执行片选(CS)信号接收器的ODT启用或禁用操作，以便确保适合于多列配置的操作。CA ODT功能用于执行连接到CA信号线的接收器的ODT启用或禁用操作(例如，基于多个存储器列的目标信息或非目标信息来执行连接到CA信号线的CA信号线接收器的ODT启用或禁用操作)。DQ ODT功能用于执行连接到数据总线的接收器的ODT启用或禁用操作(例如，基于多个存储器列的目标信息或非目标信息来执行连接到数据总线的数据总线接收器的ODT启用或禁用操作)。另外，可提供CA ODT功能和DQ ODT功能以设置CA信号线接收器和DQ总线接收器的ODT值。In addition, the mode register 310 may store information for controlling the ODT function of each of the first column 121 and the second column 122 . The information used to control the ODT function may include SoC ODT function, CK ODT function, CS ODT function, CA ODT function and/or DQ ODT function. SoC ODT functionality may be provided to improve signal integrity (SI) by adjusting the swing width and/or driver strength of signals transmitted between the memory controller 112 and the first column 121 . The CK ODT function is used to perform the ODT enable or disable operation of the clock signal receiver. In the CS ODT function, when the memory device 120 is implemented in a multi-rank configuration, an ODT enable or disable operation of a chip select (CS) signal receiver may be performed to ensure operation suitable for the multi-rank configuration. The CA ODT function is used to perform an ODT enable or disable operation for a receiver connected to a CA signal line (e.g., perform an ODT for a CA signal line receiver connected to a CA signal line based on target information or non-target information for multiple memory columns). enable or disable the operation). The DQ ODT function is used to perform an ODT enable or disable operation for a receiver connected to the data bus (e.g., perform an ODT enable or disable for a data bus receiver connected to the data bus based on target information or non-target information for multiple memory columns). operate). In addition, the CA ODT function and the DQ ODT function can be provided to set the ODT values of the CA signal line receiver and the DQ bus receiver.
图4是示出根据一些实施例的目标列在存储器系统中执行读取操作的情况的框图，并且图5是示出根据一些实施例的在存储器系统中的目标列中执行写入操作的情况的框图。4 is a block diagram illustrating a situation in which a target column performs a read operation in a memory system according to some embodiments, and FIG. 5 is a block diagram illustrating a situation in which a write operation is performed in a target column in a memory system according to some embodiments. block diagram.
参照图4和图5，根据一些实施例的存储器控制器112包括驱动器112a和缓冲器112b。此外，存储器列121和122分别包括存储其存储体信息的存储设备121a和122a、通过DQ总线将存储在存储器列121和122中的数据发送到存储器控制器112的驱动器121b和122b、以及通过DQ总线从存储器控制器112接收数据的缓冲器121c和122c。这里，假设第一列121是目标列，并且第二列122是非目标列。Referring to Figures 4 and 5, memory controller 112 according to some embodiments includes driver 112a and buffer 112b. In addition, the memory columns 121 and 122 respectively include storage devices 121a and 122a that store bank information thereof, drivers 121b and 122b that transmit data stored in the memory columns 121 and 122 to the memory controller 112 through the DQ bus, and drivers 121b and 122b through the DQ bus. The bus receives buffers 121c and 122c of data from memory controller 112. Here, it is assumed that the first column 121 is a target column and the second column 122 is a non-target column.
参照图4，根据一些实施例，当读取存储在多列存储器装置120中的数据时，可不同地设置存储器控制器112的驱动器112a的阻抗值和第二列122的驱动器122b的阻抗值。例如，存储器控制器112的驱动器112a的阻抗值被设置为1.5Zo，并且第二列122的驱动器122b的阻抗值可被设置为3Zo。这里，第一列121的阻抗值可以是目标读取ODT值，并且第二列122的阻抗值可以是非目标读取ODT值。4, according to some embodiments, when reading data stored in the multi-column memory device 120, the impedance value of the driver 112a of the memory controller 112 and the impedance value of the driver 122b of the second column 122 may be set differently. For example, the impedance value of the driver 112a of the memory controller 112 is set to 1.5Zo, and the impedance value of the driver 122b of the second column 122 may be set to 3Zo. Here, the impedance values of the first column 121 may be target read ODT values, and the impedance values of the second column 122 may be non-target read ODT values.
也就是说，根据一些实施例，当读取存储在多列存储器器装置120中的数据时，目标列可具有目标读取ODT值，并且存储器装置120可对目标列执行读取操作。然而，非目标列具有非目标读取ODT值，并且多列存储器装置120不对非目标列执行读取操作。另外，存储器控制器112的驱动器112a的阻抗值和/或第二列122的驱动器122b的阻抗值可被存储在第二列122的模式寄存器310(图3)中。That is, according to some embodiments, when reading data stored in multi-column memory device 120, the target column may have a target read ODT value, and memory device 120 may perform a read operation on the target column. However, the non-target columns have non-target read ODT values, and multi-column memory device 120 does not perform read operations on the non-target columns. Additionally, the impedance value of the driver 112a of the memory controller 112 and/or the impedance value of the driver 122b of the second column 122 may be stored in the mode register 310 of the second column 122 (FIG. 3).
基于存储器控制器112的驱动器112a的阻抗值和第二列122的驱动器122b的阻抗值，可在存储器控制器112的缓冲器112b中接收从第一列121的驱动器121b输出的读取数据。Based on the impedance value of the driver 112a of the memory controller 112 and the impedance value of the driver 122b of the second column 122, the read data output from the driver 121b of the first column 121 may be received in the buffer 112b of the memory controller 112.
例如，为了读取存储在第一列121中的数据，存储器控制器112可通过通道130的CA信号线将包含关于第一列121的信息的命令发送到多列存储器装置120。将参照图10和图11详细描述包含关于第一列121的信息的读取命令。For example, to read data stored in first column 121 , memory controller 112 may send a command containing information about first column 121 to multi-column memory device 120 through the CA signal line of channel 130 . The read command including the information on the first column 121 will be described in detail with reference to FIGS. 10 and 11 .
参照图5，根据一些实施例，当将数据写入多列存储器装置120时，可不同地设置第一列121的驱动器121b的阻抗值和第二列122的驱动器122b的阻抗值。例如，第一列的驱动器121b的阻抗值被设置为3Zo，并且第二列122的驱动器122b的阻抗值可被设置为1.5Zo。第一列121的驱动器121b的阻抗值可被设置在第一列121的存储设备中，并且第二列122的驱动器122b的阻抗值可被设置在第二列122的存储设备122a中。这里，第一列121的阻抗值可以是目标写入ODT值，并且第二列122的阻抗值可以是非目标写入ODT值。Referring to FIG. 5, according to some embodiments, when writing data to the multi-column memory device 120, the impedance value of the driver 121b of the first column 121 and the impedance value of the driver 122b of the second column 122 may be set differently. For example, the impedance value of the driver 121b of the first column is set to 3Zo, and the impedance value of the driver 122b of the second column 122 may be set to 1.5Zo. The impedance value of the driver 121b of the first column 121 may be set in the storage device of the first column 121, and the impedance value of the driver 122b of the second column 122 may be set in the storage device 122a of the second column 122. Here, the impedance values of the first column 121 may be target write ODT values, and the impedance values of the second column 122 may be non-target write ODT values.
也就是说，根据一些实施例，当数据被写入多列存储器装置120中时，目标列可具有目标写入ODT值，并且多列存储器装置120可对目标列执行写入操作。然而，非目标列具有非目标写入ODT值，并且多列存储器装置120不对非目标列执行写入操作。That is, according to some embodiments, when data is written into the multi-column memory device 120, the target column may have a target write ODT value, and the multi-column memory device 120 may perform a write operation on the target column. However, the non-target columns have non-target write ODT values, and multi-column memory device 120 does not perform write operations on the non-target columns.
将参照图8和图9详细描述包含关于第一列121的信息的写入命令。The write command including the information on the first column 121 will be described in detail with reference to FIGS. 8 and 9 .
然而，ODT值仅是示例，只要可将目标列与非目标列区分开，就可配置具有单独阻抗值的ODT值。However, the ODT values are only examples, and ODT values with separate impedance values can be configured as long as the target column can be distinguished from the non-target column.
图6是示出根据一些实施例的在存储器系统中执行读取操作的情况的时序图，并且图7是示出根据一些实施例的在存储器系统中执行写入操作的情况的时序图。在图6和图7中，“ODT RANK0”表示第一列121的ODT信息，并且“ODT RANK1”表示第二列122的ODT信息。也就是说，“ODT RANK0”可表示目标列的ODT信息，并且“ODT RANK1”可表示非目标列的ODT信息。6 is a timing diagram illustrating a situation in which a read operation is performed in a memory system according to some embodiments, and FIG. 7 is a timing diagram illustrating a situation in which a write operation is performed in a memory system according to some embodiments. In FIGS. 6 and 7 , “ODT RANK0” represents the ODT information of the first column 121 , and “ODT RANK1 ” represents the ODT information of the second column 122 . That is, "ODT RANK0" may represent the ODT information of the target column, and "ODT RANK1" may represent the ODT information of the non-target column.
参照图6，当根据一些实施例的存储器系统的第一列121的读取操作在时间点T1至时间点T2之间的时段内被执行时，作为目标列的第一列121的数据总线ODT可处于断开状态，并且作为非目标列的第二列122可处于ODT接通状态(READ_NT_ODT on)。在时间点T1之前，为了对目标列执行数据读取操作，包括第一列121的列信息的命令将通过CA信号线被发送到存储器列121和122。Referring to FIG. 6 , when a read operation of the first column 121 of the memory system according to some embodiments is performed during a period between time point T1 and time point T2 , the data bus ODT of the first column 121 as the target column It may be in an off state, and the second column 122, which is a non-target column, may be in an ODT on state (READ_NT_ODT on). Before the time point T1, in order to perform a data read operation on the target column, a command including the column information of the first column 121 will be sent to the memory columns 121 and 122 through the CA signal line.
参照图7，当根据一些实施例的存储器系统的第二列122的写入操作在时间点T3与时间点T4之间的时段内被执行时，作为目标列的第一列121的ODT可处于接通状态(WRITE_NT_ODT on)，并且作为非目标列的第二列122可处于ODT接通状态。在时间点T3之前，为了对目标列执行数据写入操作，包括第一列121的列信息的命令将通过CA信号线被发送到存储器列121和122。Referring to FIG. 7 , when the write operation of the second column 122 of the memory system is performed during the period between time point T3 and time point T4 according to some embodiments, the ODT of the first column 121 as the target column may be in On state (WRITE_NT_ODT on), and the second column 122 as the non-target column may be in the ODT on state. Before time point T3, in order to perform a data write operation on the target column, a command including the column information of the first column 121 will be sent to the memory columns 121 and 122 through the CA signal line.
图8和图9是示出根据一些实施例的在存储器系统10中用于将目标列与非目标列区分开的写入命令的示图。图8和图9示出指示写入命令可存取的列位置的数量的突发长度BL为24的情况。在图8和图9中，“RANK0”表示第一列121，并且“RANK1”表示第二列122。也就是说，“RANK0”可表示目标列，并且“RANK1”可表示非目标列。8 and 9 are diagrams illustrating write commands used in memory system 10 to distinguish target columns from non-target columns, in accordance with some embodiments. Figures 8 and 9 show the case where the burst length BL is 24, indicating the number of column locations accessible to the write command. In FIGS. 8 and 9 , “RANK0” represents the first column 121 , and “RANK1 ” represents the second column 122 . That is, "RANK0" may represent the target column, and "RANK1" may represent the non-target column.
参照图8和图9，在芯片选择信号(CS)和命令地址CA[0]至CA[3]中提供写入命令的操作数。这里，可在时钟边沿CK_T edge的上升或下降时提供包括在芯片选择信号(CS)和命令地址CA[0]至CA[3]中的信息。Referring to FIGS. 8 and 9 , the operands of the write command are provided in the chip select signal (CS) and command addresses CA[0] to CA[3]. Here, the information included in the chip select signal (CS) and the command addresses CA[0] to CA[3] may be provided at the rising or falling of the clock edge CK_T edge.
例如，在写入命令的情况下，可在第一时钟上升沿R1处在芯片选择信号CS：H和命令地址CA[0]至CA[3]中提供操作数。另外，第一时钟上升沿R1可包括用于传输数据的命令同步信号WS。可在第一时钟CK下降沿F1、第二时钟CK上升沿R2和第二时钟CK下降沿F2处输入附加操作数。操作数(指示写入命令的特定方面的变量、字段或值)可包括由LPDDR规范提供的WS、AP、BG0至BG1、BA0至BA1、C0至C5以及D.ODT。BG0至BG1可指示存储体组地址，BA0至BA1可指示存储体地址，并且C0至C5可指示列地址。For example, in the case of a write command, the operands may be provided in the chip select signal CS:H and the command addresses CA[0] to CA[3] at the first clock rising edge R1. In addition, the first clock rising edge R1 may include a command synchronization signal WS for transmitting data. Additional operands may be input at the falling edge F1 of the first clock CK, the rising edge R2 of the second clock CK, and the falling edge F2 of the second clock CK. Operands (variables, fields, or values indicating specific aspects of the write command) may include WS, AP, BGO to BG1, BA0 to BA1, C0 to C5, and D.ODT provided by the LPDDR specification. BG0 to BG1 may indicate bank group addresses, BA0 to BA1 may indicate bank addresses, and C0 to C5 may indicate column addresses.
这里，第二上升时钟沿R2可包括关于在其中执行读取操作的第一列121的信息。关于第一列121的信息可被用作第一列121的ODT信息。关于第一列121的信息可被称为动态ODT信号D.ODT。为了便于描述，关于第一列121的信息和动态ODT信号D.ODT可互换使用。例如，在图8中，当动态ODT信号D.ODT被施加为“0”时，第一列121可根据至目标列的写入命令来执行写入操作。此时，在第一列121的存储设备121a中，动态ODT信号D.ODT可被设置为“0”。Here, the second rising clock edge R2 may include information about the first column 121 in which the read operation is performed. Information about the first column 121 may be used as the ODT information of the first column 121 . The information about the first column 121 may be referred to as the dynamic ODT signal D.ODT. For ease of description, the information about the first column 121 and the dynamic ODT signal D.ODT are used interchangeably. For example, in FIG. 8, when the dynamic ODT signal D.ODT is applied to "0", the first column 121 may perform a write operation according to a write command to the target column. At this time, in the storage device 121a of the first column 121, the dynamic ODT signal D.ODT may be set to "0".
在图9中，如果动态ODT信号D.ODT被施加为“0”，则第二列122可作为写入命令的非目标列来操作。此时，在第二列122的存储设备122a中，动态ODT信号D.ODT可被设置为“1”。In Figure 9, if the dynamic ODT signal D.ODT is applied to "0", the second column 122 may operate as a non-target column for a write command. At this time, in the storage device 122a of the second column 122, the dynamic ODT signal D.ODT may be set to "1".
图10和图11示出根据一些实施例的在存储器系统10中的目标列中执行读取操作的情况。在图10和图11中，“RANK0”表示第一列121，并且“RANK1”表示第二列122。也就是说，“RANK0”可表示目标列，并且“RANK1”可表示非目标列。Figures 10 and 11 illustrate a situation in which a read operation is performed in a target column in memory system 10 in accordance with some embodiments. In FIGS. 10 and 11 , “RANK0” represents the first column 121 , and “RANK1 ” represents the second column 122 . That is, "RANK0" may represent the target column, and "RANK1" may represent the non-target column.
参照图10和图11，在芯片选择信号(CS)和命令地址CA[0]至CA[3]中提供读取命令的操作数。这里，可在时钟边沿CK_t edge的上升或下降时提供包括在芯片选择信号(CS)和命令地址CA[0]至CA[3]中的信息。Referring to FIGS. 10 and 11 , the operands of the read command are provided in the chip select signal (CS) and command addresses CA[0] to CA[3]. Here, the information included in the chip select signal (CS) and the command addresses CA[0] to CA[3] may be provided at the rising or falling of the clock edge CK_t edge.
例如，在读取命令READ CMD的情况下，可在第一时钟上升沿R1处在芯片选择信号(CS：H)和命令地址CA[0]至CA[3]中提供操作数。另外，第一时钟上升沿R1可包括用于传输数据的命令同步信号WS。可在第一时钟CK下降沿F1、第二时钟CK上升沿R2和第二时钟CK下降沿F2处输入附加操作数。操作数(指示读取命令的特定方面的变量、字段或值)可包括由LPDDR规范提供的WS、AP、BG0至BG1、BA0至BA1、C0至C5和D.ODT。BG0至BG1可指示存储体组地址，BA0至BA1可指示存储体地址，并且C0至C5可指示列地址。For example, in the case of the read command READ CMD, the operands may be provided in the chip select signal (CS:H) and the command addresses CA[0] to CA[3] at the first clock rising edge R1. In addition, the first clock rising edge R1 may include a command synchronization signal WS for transmitting data. Additional operands may be input at the falling edge F1 of the first clock CK, the rising edge R2 of the second clock CK, and the falling edge F2 of the second clock CK. Operands (variables, fields, or values indicating specific aspects of the read command) may include WS, AP, BGO to BG1, BA0 to BA1, C0 to C5, and D.ODT provided by the LPDDR specification. BG0 to BG1 may indicate bank group addresses, BA0 to BA1 may indicate bank addresses, and C0 to C5 may indicate column addresses.
这里，第二上升时钟沿R2可包括关于在其中执行读取操作的第一列121的信息。例如，在图10中，当动态ODT信号D.ODT被施加为“0”时，第一列121可根据至目标列的读取命令READ CMD来执行读取操作。此时，在第一列121的存储设备121a中，动态ODT信号D.ODT可被设置为“0”。Here, the second rising clock edge R2 may include information about the first column 121 in which the read operation is performed. For example, in FIG. 10 , when the dynamic ODT signal D.ODT is applied to “0”, the first column 121 may perform a read operation according to the read command READ CMD to the target column. At this time, in the storage device 121a of the first column 121, the dynamic ODT signal D.ODT may be set to "0".
在图11中，如果动态ODT信号D.ODT被施加为“0”，则第二列122可作为读取命令READ CMD的非目标列来操作。此时，在第二列122的存储设备122a中，动态ODT信号D.ODT可被设置为“1”。In Figure 11, if the dynamic ODT signal D.ODT is applied to "0", the second column 122 may operate as a non-target column of the read command READ CMD. At this time, in the storage device 122a of the second column 122, the dynamic ODT signal D.ODT may be set to "1".
图12是根据一些实施例的存储器系统10的操作方法的流程图。Figure 12 is a flowchart of a method of operating memory system 10 in accordance with some embodiments.
参照图12，主机系统110通过存储器控制器112将存储器列121和122的ODT信息(Rank ODT_Info)和多个命令(CMD)发送到多列存储器装置120(S110)。这里，存储器列121和122的ODT信息(Rank ODT_Info)可包括目标列的ODT信息和非目标列的ODT信息。Referring to FIG. 12 , the host system 110 sends the ODT information (Rank ODT_Info) and the plurality of commands (CMD) of the memory ranks 121 and 122 to the multi-rank memory device 120 through the memory controller 112 ( S110 ). Here, the ODT information (Rank ODT_Info) of the memory columns 121 and 122 may include ODT information of the target column and ODT information of the non-target column.
另外，多列存储器装置120可将读取D.ODT信息设置到目标列RANK0121和非目标列RANK1 122的熔丝(S120)。这里，熔丝仅为示例并且可由另外的存储装置替换。此外，D.ODT信息可以是在存储器列中设置的唯一阻抗值。Additionally, the multi-column memory device 120 may set the read D.ODT information to the fuses of the target column RANK0 121 and the non-target column RANK1 122 (S120). Here, the fuse is only an example and may be replaced by another memory device. Additionally, the D.ODT information may be a unique impedance value set in the memory column.
主机系统110可将读取命令READ CMD发送到多列存储器装置120，以便读取存储在存储器列121和122中的数据(S130)。此外，多列存储器装置120可向主机系统110发送每个存储器列的D.ODT信息和从主机系统110接收每个存储器列的D.ODT信息(S140)。The host system 110 may send a read command READ CMD to the multi-column memory device 120 in order to read data stored in the memory columns 121 and 122 (S130). In addition, the multi-rank memory device 120 may transmit and receive the D.ODT information of each memory rank to and from the host system 110 (S140).
这里，主机系统110的存储器控制器112可将目标列RANK0 121的信息与存储器列121和122的D.ODT信息进行比较(S150)。例如，为了确定目标列RANK0 121，存储器控制器112可将多个存储器列之中的具有与读取ODT值相同的D.ODT的存储器列确定为目标列RANK0 121。另外，存储器控制器112可向多列存储器装置120发送确定的目标列RANK0 121的信息。Here, the memory controller 112 of the host system 110 may compare the information of the target column RANK0 121 with the D.ODT information of the memory columns 121 and 122 (S150). For example, to determine the target column RANK0 121 , the memory controller 112 may determine a memory column among the plurality of memory columns that has the same D.ODT value as the read ODT value as the target column RANK0 121 . Additionally, the memory controller 112 may send information of the determined target column RANK0 121 to the multi-column memory device 120 .
如果目标列RANK0 121被确定，则存储器控制器112可将ODT值更改为目标列的D.ODT值(S160)。例如，存储器控制器112可将具有与读取ODT值相同的ODT值的存储器列确定为目标列RANK0 121，并且可将ODT值设置为目标列的D.ODT值。If the target column RANK0 121 is determined, the memory controller 112 may change the ODT value to the D.ODT value of the target column (S160). For example, the memory controller 112 may determine the memory column having the same ODT value as the read ODT value as the target column RANK0 121 and may set the ODT value to the D.ODT value of the target column.
如果ODT值被更改，则主机系统110对目标列RANK0 121执行读取操作(S170)。If the ODT value is changed, the host system 110 performs a read operation on the target column RANK0 121 (S170).
图13是根据一些实施例的存储器系统10的操作方法中的目标列的读取操作的流程图。13 is a flowchart of a target column read operation in a method of operating memory system 10 according to some embodiments.
参照图13，存储器控制器112可将控制模式设置为读取ODT模式，以便对多列存储器装置120的至少一个存储器装置执行读取操作(S210)。Referring to FIG. 13 , the memory controller 112 may set the control mode to the read ODT mode to perform a read operation on at least one memory device of the multi-column memory device 120 ( S210 ).
当多列存储器装置120的读取操作被执行时，根据一些实施例的第一列和第二列的ODT信息可被预先存储在存储器控制器112中(S220)。这里，第一列表示目标列，并且第二列表示非目标列。例如，关于每个存储器列的ODT信息可被预先存储在多列存储器装置的存储设备121a和122a中，并且存储器控制器112可预先存储关于存储的存储器列的ODT信息。这里，存储设备121a和122a可以是熔丝或非易失性存储器装置，但不限于此。When the read operation of the multi-column memory device 120 is performed, the ODT information of the first column and the second column according to some embodiments may be pre-stored in the memory controller 112 (S220). Here, the first column represents the target column, and the second column represents the non-target column. For example, ODT information about each memory column may be stored in advance in the storage devices 121a and 122a of the multi-column memory device, and the memory controller 112 may store ODT information about the stored memory columns in advance. Here, the storage devices 121a and 122a may be fuses or non-volatile memory devices, but are not limited thereto.
当第一列和第二列的ODT信息被存储时，存储器控制器将读取命令和第一列的ODT信息发送到多列存储器装置120(S230)。这里，第一列的ODT信息可以是读取ODT信息。另外，第一列的ODT信息可被包括在命令地址信号CA中并且被发送到多列存储器装置120。关于第一列的ODT信息可包括D.ODT信息。When the ODT information of the first column and the second column is stored, the memory controller sends a read command and the ODT information of the first column to the multi-column memory device 120 (S230). Here, the ODT information in the first column may be read ODT information. Additionally, the ODT information of the first column may be included in the command address signal CA and sent to the multi-column memory device 120 . The ODT information about the first column may include D.ODT information.
当读取命令和第一列的ODT信息被发送到多列存储器装置120时，存储器控制器112将预先存储的第一列的信息与包括在读取命令信号中的第一列的信息进行比较(S240)。这里比较的信息可以是包括在读取命令信号中的D.ODT信息和存储在存储器列121和122的存储设备121a和122a中的存储器列的D.ODT信息。When the read command and the ODT information of the first column are sent to the multi-column memory device 120 , the memory controller 112 compares the pre-stored information of the first column with the information of the first column included in the read command signal. (S240). The information compared here may be the D.ODT information included in the read command signal and the D.ODT information of the memory columns stored in the memory devices 121a and 122a of the memory columns 121 and 122.
作为将预先存储的第一列的信息与包括在读取命令信号中的第一列的信息进行比较的结果，存储器控制器112将具有与包括在读取命令中的D.ODT信息相同的D.ODT信息的列确定为目标列，并且将ODT设置值更改为与目标列的D.ODT值相同的值(S250)。如果ODT设置值被更改，则仅对目标列的读取操作被执行，并且非目标列无法识别读取命令。在一个实施例中，操作S240和操作S250可由多列存储器装置120执行。As a result of comparing the pre-stored information of the first column with the information of the first column included in the read command signal, the memory controller 112 will have the same D.ODT information included in the read command. The column of .ODT information is determined as the target column, and the ODT setting value is changed to the same value as the D.ODT value of the target column (S250). If the ODT setting value is changed, only the read operation for the target column is performed, and the read command is not recognized for non-target columns. In one embodiment, operations S240 and S250 may be performed by the multi-rank memory device 120 .
图14是根据一些实施例的存储器系统10的操作方法中的目标列的写入操作的流程图。14 is a flowchart of a target column write operation in a method of operating memory system 10 in accordance with some embodiments.
参照图14，存储器控制器112可将控制模式设置为写入ODT模式，以便对多列存储器装置120中的至少一个存储器装置执行写入操作(S310)。Referring to FIG. 14 , the memory controller 112 may set the control mode to the write ODT mode to perform a write operation on at least one memory device among the multi-column memory devices 120 ( S310 ).
当多列存储器装置120的写入操作被执行时，根据一些实施例的第一列和第二列的ODT信息可被预先存储在存储器控制器112中(S320)。这里，存储设备121a和122a可以是熔丝或非易失性存储器装置，但不限于此。此外，第一列表示目标列，第二列表示非目标列。例如，关于每个存储器列的ODT信息可被预先存储在多列存储器装置的存储设备121a和122a中，并且存储器控制器112可预先存储关于存储的存储器列的ODT信息。When the write operation of the multi-column memory device 120 is performed, the ODT information of the first column and the second column according to some embodiments may be pre-stored in the memory controller 112 (S320). Here, the storage devices 121a and 122a may be fuses or non-volatile memory devices, but are not limited thereto. Furthermore, the first column represents the target column and the second column represents the non-target column. For example, ODT information about each memory column may be stored in advance in the storage devices 121a and 122a of the multi-column memory device, and the memory controller 112 may store ODT information about the stored memory columns in advance.
当第一列和第二列的ODT信息被存储时，存储器控制器将写入命令和第一列的ODT信息发送到多列存储器装置120(S330)。这里，第一列的ODT信息可以是写入ODT信息。在存储器控制器中，写入命令信号可包含第一列的ODT信息，第一列的ODT信息可被包括在命令地址信号CA中并且被发送到多列存储器装置120。关于第一列的ODT信息可包括D.ODT信息。When the ODT information of the first column and the second column is stored, the memory controller sends the write command and the ODT information of the first column to the multi-column memory device 120 (S330). Here, the ODT information in the first column may be write ODT information. In the memory controller, the write command signal may include the ODT information of the first column, and the ODT information of the first column may be included in the command address signal CA and sent to the multi-column memory device 120 . The ODT information about the first column may include D.ODT information.
当写入命令和第一列的ODT信息被发送到多列存储器装置120时，存储器控制器112将预先存储的第一列的信息与包括在写入命令信号中的第一列的信息进行比较(S340)。这里比较的信息可以是包括在写入命令信号中的D.ODT信息和存储在存储器列121和122的存储设备121a和122a中的存储器列的D.ODT信息。When the write command and the ODT information of the first column are sent to the multi-column memory device 120 , the memory controller 112 compares the previously stored information of the first column with the information of the first column included in the write command signal. (S340). The information compared here may be the D.ODT information included in the write command signal and the D.ODT information of the memory columns stored in the storage devices 121a and 122a of the memory columns 121 and 122.
作为将预先存储的第一列的信息与包括在写入命令信号中的第一列的信息进行比较的结果，存储器控制器112将具有与包括在写入命令中的D.ODT信息相同的D.ODT信息的列确定为目标列，并且将ODT设置值更改为与目标列的D.ODT值相同的值(S350)。当ODT设置值被更改时，目标列的ODT值变得与非目标列的ODT值不同，仅对目标列的写入操作被执行，并且非目标列无法识别写入命令。在一个实施例中，操作340和操作S350可由多列存储器装置120执行。As a result of comparing the pre-stored information of the first column with the information of the first column included in the write command signal, the memory controller 112 will have the same D as the D.ODT information included in the write command. The column of .ODT information is determined as the target column, and the ODT setting value is changed to the same value as the D.ODT value of the target column (S350). When the ODT setting value is changed, the ODT value of the target column becomes different from the ODT value of the non-target column, only the write operation to the target column is performed, and the non-target column does not recognize the write command. In one embodiment, operations 340 and S350 may be performed by the multi-rank memory device 120 .
图15是根据一些实施例的将存储器系统10应用于移动装置的示例的框图。Figure 15 is a block diagram of an example of application of memory system 10 to a mobile device in accordance with some embodiments.
这里，移动装置可包括移动电话、智能电话、计算平板电脑、支持无线的电子阅读器和可穿戴计算装置。Here, mobile devices may include mobile phones, smartphones, computing tablets, wireless-enabled e-readers, and wearable computing devices.
参照图15，移动装置1100包括全球移动通信系统(GSM)块1110、近场通信(NFC)收发器1120、输入/输出块1130、应用块1140、存储器1150和显示器1160。图15中示例性地示出移动装置1100的组件/块。移动装置1100可包括更多或更少的组件/块。另外，根据一些实施例，示出使用GSM技术，但是可使用其他技术(诸如，码分多址(CDMA))来实现移动装置1100。图15的块可以以集成电路的形式实现。根据一些实施例，一些块可以以集成电路的形式实现，并且其他块可以以单独的形式实现。Referring to FIG. 15 , the mobile device 1100 includes a Global System for Mobile Communications (GSM) block 1110 , a near field communication (NFC) transceiver 1120 , an input/output block 1130 , an application block 1140 , a memory 1150 and a display 1160 . The components/blocks of the mobile device 1100 are exemplarily shown in FIG. 15 . Mobile device 1100 may include more or fewer components/blocks. Additionally, according to some embodiments, the mobile device 1100 is shown using GSM technology, but the mobile device 1100 may be implemented using other technologies, such as code division multiple access (CDMA). The blocks of Figure 15 may be implemented in the form of integrated circuits. According to some embodiments, some blocks may be implemented in the form of integrated circuits and other blocks may be implemented in separate forms.
GSM块1110可连接到天线1111，并且可操作为以已知的方式提供无线电话操作。GSM块1110可在内部包括接收器和发送器，从而执行相应的接收操作和发送操作。GSM block 1110 is connectable to antenna 1111 and is operable to provide radiotelephone operation in a known manner. The GSM block 1110 may internally include a receiver and a transmitter to perform corresponding receiving operations and transmitting operations.
NFC收发器1120可被配置为使用无线通信的感应耦合来发送和接收NFC信号。无线通信可包括私域网络(诸如，蓝牙)、短程网络(诸如，WiFi)、和/或宽范围网络(诸如，WiMAX)、或其他无线通信。NFC收发器1120可将NFC信号提供给NFC天线匹配网络系统(NFCAMNS)1121，并且NFC天线匹配网络系统1121可通过感应耦合来发送NFC信号。NFC天线匹配网络系统1121可接收从另外的NFC装置提供的NFC信号，并且将接收到的NFC信号提供给NFC收发器1120。NFC transceiver 1120 may be configured to send and receive NFC signals using inductive coupling of wireless communications. Wireless communications may include private area networks (such as Bluetooth), short-range networks (such as WiFi), and/or wide-range networks (such as WiMAX), or other wireless communications. The NFC transceiver 1120 may provide the NFC signal to the NFC antenna matching network system (NFCAMNS) 1121, and the NFC antenna matching network system 1121 may transmit the NFC signal through inductive coupling. The NFC antenna matching network system 1121 may receive NFC signals provided from another NFC device and provide the received NFC signals to the NFC transceiver 1120 .
应用块1140可包括硬件电路(例如，一个或多个主机系统)，并且可操作为提供由移动装置1100提供的各种用户应用。用户应用可包括语音呼叫操作、数据传送和数据交换。应用块1140可与GSM块1110和/或NFC收发器1120一起操作，以提供GSM块1110和/或NFC收发器1120的操作特征。在一些实施例中，应用块1140可包括用于销售点(POS)的程序。这些程序可使用移动电话(即，智能电话)提供信用卡购买和支付功能。Application block 1140 may include hardware circuitry (eg, one or more host systems) and may be operable to provide various user applications provided by mobile device 1100 . User applications may include voice call operations, data transfer and data exchange. Application block 1140 may operate with GSM block 1110 and/or NFC transceiver 1120 to provide operating characteristics of GSM block 1110 and/or NFC transceiver 1120 . In some embodiments, application block 1140 may include programs for point of sale (POS). These programs can provide credit card purchasing and payment functionality using mobile phones (ie, smart phones).
显示器1160可响应于从应用块1140接收的显示信号来显示图像。图像可由应用程序块1140提供或由嵌入于移动装置1100中的相机产生。显示器1160内部包括用于临时存储像素值的帧缓冲器，并且可由液晶显示屏及相关控制电路组成。Display 1160 may display images in response to display signals received from application block 1140 . Images may be provided by application block 1140 or generated by a camera embedded in mobile device 1100 . The display 1160 internally includes a frame buffer for temporarily storing pixel values, and may be composed of a liquid crystal display screen and related control circuitry.
输入/输出块1130向用户提供输入功能，并提供将通过应用块1140接收的输出。输入/输出块1130示出与和用户的交互相关联的硬件装置和软件组件。输入/输出块1130可操作为管理显示器1160和/或音频系统的一些硬件。例如，通过麦克风或音频装置的输入可被提供为应用块1140。当显示器1160包括触摸屏时，显示器1160可用作可部分地由输入/输出块1130管理的输入装置。为了提供由输入/输出块1130管理的输入/输出(I/O)功能，在移动装置1100中可存在附加的按键或开关。输入/输出块1130可管理可包括在移动装置1100中的装置(诸如，加速器、相机、光学传感器或其他环境传感器、陀螺仪、全球定位系统(GPS)或其他硬件)。Input/output block 1130 provides input functionality to the user and provides output to be received through application block 1140 . Input/output block 1130 illustrates hardware devices and software components associated with interaction with a user. Input/output block 1130 is operable to manage some hardware of display 1160 and/or the audio system. For example, input via a microphone or audio device may be provided as application block 1140 . When display 1160 includes a touch screen, display 1160 may serve as an input device that may be managed in part by input/output block 1130 . Additional keys or switches may be present in mobile device 1100 in order to provide input/output (I/O) functionality managed by input/output block 1130 . Input/output block 1130 may manage devices that may be included in mobile device 1100 (such as accelerometers, cameras, optical or other environmental sensors, gyroscopes, global positioning systems (GPS), or other hardware).
存储器1150存储将由应用块1140使用的程序(命令)和/或数据，并且可包括RAM、ROM、闪存等。因此，存储器1150不仅可包括易失性存储元件，还可包括非易失性存储元件。例如，存储器1150可包括参照图1至图10描述的存储器系统10。Memory 1150 stores programs (commands) and/or data to be used by application block 1140, and may include RAM, ROM, flash memory, etc. Accordingly, memory 1150 may include not only volatile storage elements, but also non-volatile storage elements. For example, memory 1150 may include memory system 10 described with reference to FIGS. 1-10 .
存储器1150可包括与存储器控制器共享一条或多条信号线的多列存储器装置。存储器控制器基于多列中被识别为目标列的列，可确定与多列共享的信号线是否应当处于未终结的ODT状态，并且可确定信号线应当处于终结的ODT状态的列。存储器控制器可根据确定的结果，向多列的所有存储器装置广播与多列共享的信号线的ODT状态信息。多列存储器装置可在多列的每个存储器装置处接收从存储器控制器广播的共享信号线的ODT状态信息，并且将接收到的ODT状态信息存储在模式寄存器中。多列的每个存储器装置可基于存储在模式寄存器中的信号线的ODT状态信息，更改连接到信号线的存储器装置的内部的ODT设置，更改提供给连接到信号线的输入缓冲器的参考电压电平，或者更改连接到信号线的输入缓冲器的类型。Memory 1150 may include multiple rank memory devices that share one or more signal lines with a memory controller. The memory controller may determine whether a signal line shared with the plurality of columns should be in an unterminated ODT state based on the column of the plurality of columns that is identified as the target column, and may determine the column for which the signal line should be in a terminated ODT state. The memory controller may broadcast the ODT status information of the signal line shared with the multiple columns to all memory devices of the multiple columns according to the determination result. The multi-column memory device may receive ODT status information of the shared signal line broadcast from the memory controller at each memory device of the multi-column and store the received ODT status information in the mode register. Each memory device of the plurality of columns can change the internal ODT settings of the memory device connected to the signal line and change the reference voltage provided to the input buffer connected to the signal line based on the ODT status information of the signal line stored in the mode register. level, or change the type of input buffer connected to the signal line.
虽然已经参照发明构思的实施例具体示出和描述了发明构思，但是将理解，在不脱离所附权利要求的精神和范围的情况下，可在其中进行形式和细节上的各种改变。Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.
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| KR1020220091318AKR20230151422A (en) | 2022-04-25 | 2022-07-22 | Memory system for optimizing on-die termination (ODT) settings of multi-ranks, method of operation of memory system, and memory controller |
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| CN116954493Atrue CN116954493A (en) | 2023-10-27 |
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| CN202310450699.0APendingCN116954493A (en) | 2022-04-25 | 2023-04-24 | Memory system, operating method of memory system, and electronic device |
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