Disclosure of Invention
The invention aims to provide a key parameter monitoring display system combining a typical sample and dynamic data, which uses FPGA to realize monitoring on each characteristic pattern and real-time key data comparison, can effectively monitor the data integrity of a CPU and GPU path, improves the shielding fault interval time and ensures the flight safety.
The invention aims at realizing the following technical scheme:
a key parameter monitoring display system combining a typical sample and dynamic data comprises an interface module, a graph generating module, a video processing module and a display;
the interface module mainly comprises an IOM_CPU, wherein the IOM_CPU extracts key parameters from each path of sensor data, generates a frame serial number and sends the frame serial number to the graph generating module;
the graphic generation module comprises a GPM_CPU, wherein the GPM_CPU draws a HUD display picture and a corresponding characteristic pattern according to key parameters, places the HUD display picture in a display area of a picture, places a state and a parameter value of the key parameters, a frame serial number and the characteristic pattern in a hidden area of the picture, and transmits the picture to the video processing module;
the video processing module comprises Video processing FPGA and a Monitor FPGA, and the pictures are sent to a display for display through Video processing FPGA and are transmitted to the Monitor FPGA for monitoring;
the Monitor FPGA compares the characteristic pattern in the pattern with the standard template, if the frame pattern is inconsistent, the Monitor FPGA judges that the screen is turned off if the continuous frame is wrong.
Preferably, the Monitor FPGA performs binarization, coordinate generation, template matching on the feature pattern in the hidden area of the image to detect whether the feature pattern is consistent with the standard template.
Preferably, the binarization is to compare the red component, the green component and the blue component in the input RGB data with preset color component values respectively, and if the red component, the green component and the blue component are equal to each other, the output is 1, otherwise, the output is 0.
Preferably, the coordinates are generated by calculating the position coordinates of each of the incoming binarized pixel data in the whole image based on the video line, the field sync signal, and the data valid signal. The upper left corner of the drawing is generally taken as the origin of coordinates, the coordinates cor_x in the X direction are counted at the rising edge of DE, and during the period that DE is high, the cor_x performs 1 adding operation at the rising edge of each CLK and performs zero clearing operation at the falling edge of DE, thus the cycle is repeated; the Y-direction coordinate cor_y is started and cleared at the beginning of each video frame, i.e., at the rising edge of the VS signal (VS is active high), and then at the falling edge of each DE, cor_y is incremented by 1 until the rising edge of the VS of the next video frame comes, and so on and off.
Preferably, the iom_cpu also transmits the frame sequence number and key parameters to the Monitor FPGA; the Monitor FPGA also receives the frame sequence number and the parameter value of the key parameter from the SPI channel, then compares the parameter value of the key parameter received from the IOM_CPU with the parameter value of the key parameter hidden in the drawing sheet under the condition that the frame sequence number is the same, if the error quantity of the key parameter exceeds the limit value, the frame parameter is recorded to be wrong, and a plurality of frames are continued to be wrong, and then the screen is judged to be turned off.
The invention has the beneficial effects that:
1. based on an actual effective display picture, the same fonts and a plurality of specific rotation angles are used as monitoring digital and letter samples, and meanwhile, graphic samples of lines, triangles, circles, plane symbols and a plurality of specific rotation angles are added, and the graphic capability of the GPU is judged by identifying the samples through a Monitor FPGA;
2. and then judging the correctness of the data from the CPU to the GPU by comparing the value of the video channel of the same frame with the value consistency of the SPI channel.
3. The two methods together represent the integrity of the CPU + GPU, thus playing a role in monitoring.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples.
As shown in fig. 1, a key parameter monitoring display system for combining a typical sample and dynamic data in this embodiment includes an interface module, a graphics generating module, a video processing module, a power module, and a display.
The sensor data of each path on the aircraft are transmitted to an interface module of the display system through an AFDX bus, the interface module mainly comprises an IOM_CPU, and the IOM_CPU extracts key parameters and non-key parameters from the sensor data of each path and generates a frame serial number. Key parameters include airspeed, altitude, pitch, roll, metric altitude, mach number, flight guidance, radio altitude, barometric pressure reference values, which are closely related to the safety of the aircraft and are displayed by the HUD. The key parameter is present in the plurality of sensor data, such as airspeed, with airspeed values communicated from the flight control, and also with airspeed communicated from inertial navigation, and the iom_cpu will select the airspeed values communicated from the flight control as the key parameter. Non-critical parameters include cabin door status information, external power information, air conditioning fuel pumps, etc. parameters that are not closely related to safety. The IOM_CPU sends the key parameters, the non-key parameters and the frame sequence number to the graphics generation module through PCIe. In addition, the IOM_CPU directly transmits the frame sequence number and key parameters to the Monitor FPGA through the SPI.
The graphics generation module contains a gpm_cpu, and the mapping of non-critical parameters is not relevant to the present invention and is not discussed here. The GPM_CPU draws the HUD display picture and the corresponding characteristic pattern according to the key parameters, places the HUD display picture in the display area of the picture, places the state and parameter values of the key parameters, the frame serial number and the characteristic pattern in the hidden area of the picture, and transmits the picture to the video processing module.
Under the actual running environment, according to the characteristics of the HUD display screen, airspeed, altitude, metric altitude, mach number, radio altitude and barometric pressure reference values in key parameters are numbers or letters, and pitch, roll and flight guidance are symbols. Then, according to the mapping mode of the gpm_cpu, the number or letter class is a mode using a lift map, the error mode thereof can be classified into one class, then, a digital sample with a partial rotation function is given to indicate the rotation function, and for the parameter of the symbol class, the test point, the line, the circle and the typical symbol are taken as samples. According to the display characteristics of the key parameters of the HUD, the sample of the HUD is composed of a group of symbols, see Table 1, which contains typical symbols, numbers and letters of all key parameters, effectively covering all the HUD display graphics, so that the monitored static characters can ensure effective monitoring of the HUD display.
TABLE 1
As shown in FIG. 2, the inside of the convex frame is the display area of the HUD display screen, the outside of the convex frame is the monitored characteristic pattern, these are all generated by the GPU by the same function, and each frame of the characteristic pattern is the same and is outside the HUD effective display area, i.e. the pilot cannot see the screen outside the convex frame. The upper left corner is the monitored row of key parameters, in which the frame sequence number and the real-time status (display mode) and parameter values of the current frame key parameters are stored. The current parameter is represented in terms of pixel values of all white and all black, for example frame_fsn, which is stored in pixel4 to pixel11 of the monitor line.
a. When the pixelX (4 < =x < =11) value is 24' hfffff, the corresponding frame_fsn [ X-4] =1;
b. when the pixelX value is 0, the corresponding frame_fsn [ X-4] =0;
c. frame_fsn=8 'hfff, recorded as a failure state, when there is neither 24' hfffff nor 0 in pixelX.
And similarly, obtaining the state and the parameter value of the key parameter.
The video processing module comprises Video processing FPGA and Monitor FPGA, and the pictures are sent to the display for display through Video processing FPGA and are transmitted to the Monitor FPGA for monitoring.
And comparing the key parameters in the Monitor FPGA, and comparing the characteristic patterns, if the characteristic patterns in the image are consistent with the standard templates, and meanwhile, if the image is consistent with the key parameters in the SPI channel, the image is considered to pass, and if the image is inconsistent with the key parameters in the SPI channel, the display is closed, so that the functional integrity of the CPU and the GPU is effectively ensured.
The Monitor FPGA executes the functions of binarization, coordinate generation and template matching on the characteristic pattern in the hidden area of the picture, detects whether the characteristic pattern is consistent with a standard template (existing in the FPGA), if so, the pattern is recorded correctly, and if not, the pattern is recorded incorrectly. This function demonstrates that the graphics capability of the GPU is not a problem.
A) Binarization
Binarization is to convert an RGB data stream with 24-bit width of a hidden area in an input picture into a single-bit data stream, so that resources are saved, and the subsequent processing procedures of coordinate generation, template matching and the like are simplified.
The binarization of the image is essentially a filtering algorithm, filtering out useless background data and extracting the required characteristic pattern. The binarization algorithm is various, and the binarization principle of the design based on color extraction is shown in fig. 3. And respectively comparing the red component, the green component and the blue component in the input 24-bit RGB data with preset color component values, outputting 1 if the red component, the green component and the blue component are equal, and outputting 0 if the red component, the green component and the blue component are equal.
B) Coordinate generation
And calculating the position coordinates of each pixel data after binarization flowing in according to the video line, the field synchronous signal and the data effective signal. The upper left corner of the drawing is generally selected as the origin of coordinates, and an image with the size of 1280×1024 is taken as an example, and the corresponding relationship between coordinates and pixel points is shown in fig. 3.
The X-direction coordinate cor_x is generated according to the input video data valid signal DE and the pixel clock CLK, as shown in fig. 3. The rising edge of DE starts the cor_x count and during the high period of DE, cor_x performs an add 1 operation on each rising edge of CLK and a clear operation on the falling edge of DE, and so on and off. For 1280×1024 video data, for 1280 pixels per line of video, the range of cor_x is [0,1279].
The generation timing of the Y-direction coordinates cor_y is shown in fig. 3. The cor_y is started and cleared at the beginning of each video frame, i.e. at the rising edge of the VS signal, and then added 1 at the falling edge of each DE until the rising edge of the VS of the next video frame comes, and so on and off in a round-robin manner. For 1280×1024 video data, for a total of 1024 lines of valid data, the range of cor_y is [0,1023].
C) Template matching
As shown in fig. 2, each line of samples is binarized and then used as a template, so that 12 templates are all used, when monitoring, after binarizing an image, a line of characteristic patterns is intercepted at the same position of the image and compared with the corresponding templates, whether the characteristic patterns are matched or not is judged, if the characteristic patterns are matched, the characteristic patterns pass through, if the characteristic patterns are not matched, the pattern errors are recorded, and any of the following recording symbol errors occur:
1. the first 5 rows are numbers and letters, which fall into one category, if more than three rows are wrong;
2. the last 7 rows are symbol classes, if more than three rows are in error;
3. any 1 of the first 5 rows are in error while any 1 of the last 7 rows are in error.
The Monitor FPGA also receives the frame sequence number and the parameter value of the key parameter from the SPI channel, then compares the frame sequence number with the parameter value of the key parameter hidden in the drawing sheet under the condition that the frame sequence number is the same, and records the parameter error if more than three parameters are in error at the same time; if so, the parameters are recorded correctly. This function proves the correctness of the data calculation.
When parameter errors or graphic errors occur in the same frame of picture, the frame errors are considered, a plurality of frame errors are continued, and screen closing is judged.
It will be understood that equivalents and modifications will occur to those skilled in the art in light of the present invention and their spirit, and all such modifications and substitutions are intended to be included within the scope of the present invention as defined in the following claims.