技术领域Technical field
本发明属于半导体技术领域，尤其涉及一种半导体结构及其制备方法、半导体器件及半导体晶圆。The invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor structure and a preparation method thereof, a semiconductor device and a semiconductor wafer.
背景技术Background technique
近年来化合物半导体材料发展迅速，越来越广泛地应用于很多领域。化合物半导体材料主要的优点是电子迁移率较高和禁带宽度较大，使得其在半导体领域具有广阔的应用前景。In recent years, compound semiconductor materials have developed rapidly and are increasingly used in many fields. The main advantages of compound semiconductor materials are high electron mobility and large band gap, which make them have broad application prospects in the semiconductor field.
传统的半导体结构例如肖特基二极管采用N型掺杂半导体材料，如N型掺杂的硅材料，通过N型掺杂半导体材料中自由电子的移动实现其导通。采用N型掺杂半导体材料制作的半导体器件的电流密度较低，开关速度较慢。Traditional semiconductor structures such as Schottky diodes use N-type doped semiconductor materials, such as N-type doped silicon materials, and conduction is achieved through the movement of free electrons in the N-type doped semiconductor material. Semiconductor devices made of N-type doped semiconductor materials have lower current density and slower switching speed.
发明内容Contents of the invention
根据本发明实施例的第一方面，提供一种半导体结构，包括：According to a first aspect of an embodiment of the present invention, a semiconductor structure is provided, including:
第一结构层；The first structural layer;
第二结构层；second structural layer;
其中，所述第一结构层的材料为金刚石，所述第二结构层的材料为AlN，所述第一结构层和所述第二结构层形成异质结结构。Wherein, the material of the first structural layer is diamond, the material of the second structural layer is AlN, and the first structural layer and the second structural layer form a heterojunction structure.
在一些实施例中，所述第一结构层作为衬底层；或，In some embodiments, the first structural layer serves as a substrate layer; or,
所述半导体结构包括衬底，所述衬底位于所述第一结构层背离所述第二结构层的一侧表面。The semiconductor structure includes a substrate located on a side surface of the first structural layer facing away from the second structural layer.
在一些实施例中，所述第一结构层作为衬底层的，所述第一结构层的厚度为100μm-300μm，所述半导体结构包括衬底的，所述第一结构层的厚度为0.2um-5um；和/或，In some embodiments, the first structural layer serves as a substrate layer, and the thickness of the first structural layer is 100 μm-300 μm. The semiconductor structure includes a substrate, and the thickness of the first structural layer is 0.2um. -5um; and/or,
所述第二结构层的厚度为3nm-30nm。The thickness of the second structural layer is 3nm-30nm.
在一些实施例中，述第一结构层作为沟道层，所述第二结构层作为势垒层，所述半导体结构包括：In some embodiments, the first structural layer serves as a channel layer, the second structural layer serves as a barrier layer, and the semiconductor structure includes:
帽层，设于所述第二结构层背离所述第一结构层的表面。A cap layer is provided on the surface of the second structural layer facing away from the first structural layer.
根据本发明实施例的第二方面，提供一种半导体器件，所述半导体器件包括如上所述的半导体结构，及位于所述异质结结构至少部分膜层背离所述衬底一侧的电极结构。According to a second aspect of an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes the semiconductor structure as described above, and an electrode structure located on at least part of the film layer of the heterojunction structure on a side facing away from the substrate. .
在一些实施例中，所述电极结构包括阴极和阳极；其中，所述半导体结构中设有帽层的，In some embodiments, the electrode structure includes a cathode and an anode; wherein a cap layer is provided in the semiconductor structure,
所述帽层覆盖所述第二结构层，所述阳极和所述阴极位于所述帽层背离所述第一结构层的表面；The cap layer covers the second structural layer, and the anode and the cathode are located on the surface of the cap layer facing away from the first structural layer;
或者，or,
所述第二结构层的部分表面未被所述帽层覆盖，所述阳极与所述第二结构层的表面直接接触，所述阴极位于所述帽层背离所述第一结构层的表面；或者，Part of the surface of the second structural layer is not covered by the cap layer, the anode is in direct contact with the surface of the second structural layer, and the cathode is located on the surface of the cap layer away from the first structural layer; or,
所述第二结构层的部分表面未被所述帽层覆盖，所述第二结构层未被所述帽层覆盖的区域设有第一通孔，所述阳极包括第一电极部和与所述第一电极部相连的第二电极部，所述第一电极部位于所述第一通孔内且与所述第一结构层的表面接触，所述第二电极部位于所述第二结构层背离所述第一结构层的表面；所述阴极位于所述帽层背离所述第一结构层的表面；或者，Part of the surface of the second structural layer is not covered by the cap layer, a first through hole is provided in the area of the second structural layer that is not covered by the cap layer, and the anode includes a first electrode part and a first through hole. A second electrode part connected to the first electrode part, the first electrode part is located in the first through hole and in contact with the surface of the first structural layer, the second electrode part is located in the second structure The surface of the cap layer facing away from the first structural layer; the cathode is located on the surface of the cap layer facing away from the first structural layer; or,
所述帽层包括N型掺杂区和未掺杂区，所述阳极位于所述未掺杂区背离所述第一结构层的表面，所述阴极位于所述N型掺杂区背离所述第一结构层的表面。The cap layer includes an N-type doped region and an undoped region, the anode is located on the surface of the undoped region facing away from the first structural layer, and the cathode is located on the N-type doped region facing away from the surface of the first structural layer. The surface of the first structural layer.
在一些实施例中，所述电极结构包括阴极和阳极；其中，所述半导体结构中设有帽层的，In some embodiments, the electrode structure includes a cathode and an anode; wherein a cap layer is provided in the semiconductor structure,
所述阴极包括第三电极部和与所述第三电极部相连的第四电极部；The cathode includes a third electrode part and a fourth electrode part connected to the third electrode part;
所述阳极位于所述帽层背离所述第一结构层的表面；所述帽层设有第二通孔，所述第三电极部位于所述第二通孔内，且与所述第二结构层背离所述第一结构层的表面接触，所述第四电极部位于所述帽层背离所述第一结构层的表面；或者，The anode is located on the surface of the cap layer away from the first structural layer; the cap layer is provided with a second through hole, and the third electrode part is located in the second through hole and connected with the second The surface of the structural layer facing away from the first structural layer is in contact, and the fourth electrode portion is located on the surface of the cap layer facing away from the first structural layer; or,
所述阳极位于所述帽层背离所述第一结构层的表面；所述半导体结构设有贯穿所述帽层及所述第二结构层的第三通孔，所述第三电极部位于所述第三通孔内，且与所述第一结构层的表面接触，所述第四电极部位于所述帽层背离所述第一结构层的表面。The anode is located on a surface of the cap layer away from the first structural layer; the semiconductor structure is provided with a third through hole penetrating the cap layer and the second structural layer, and the third electrode portion is located on the surface of the cap layer away from the first structural layer. The fourth electrode part is located in the third through hole and in contact with the surface of the first structural layer, and is located on the surface of the cap layer away from the first structural layer.
在一些实施例中，所述半导体器件为发光二极管，肖特基二极管，或场效应晶体管。In some embodiments, the semiconductor device is a light emitting diode, a Schottky diode, or a field effect transistor.
在一些实施例中，所述半导体器件包括钝化层，所述钝化层包覆阴极、阳极的侧壁及所述帽层背离所述第一结构层的表面。In some embodiments, the semiconductor device includes a passivation layer covering the cathode, sidewalls of the anode and a surface of the cap layer facing away from the first structural layer.
在一些实施例中，所述电极结构包括源极、栅极及漏极；其中，所述半导体结构中未设有帽层的，所述源极、栅极及漏极位于所述第二结构层背离所述第一结构层的表面；In some embodiments, the electrode structure includes a source electrode, a gate electrode and a drain electrode; wherein, if there is no cap layer in the semiconductor structure, the source electrode, gate electrode and drain electrode are located in the second structure. a surface of the layer facing away from the first structural layer;
所述半导体结构中设有帽层的，所述帽层覆盖所述第二结构层的，所述源极、栅极及漏极位于所述帽层背离所述第一结构层的表面。The semiconductor structure is provided with a cap layer, the cap layer covers the second structural layer, and the source, gate and drain are located on the surface of the cap layer away from the first structural layer.
在一些实施例中，所述半导体器件为HEMT器件。In some embodiments, the semiconductor device is a HEMT device.
根据本发明实施例的第三方面，提供一种半导体晶圆，包括多个如上所述的半导体器件，多个所述半导体器件阵列排布。According to a third aspect of an embodiment of the present invention, a semiconductor wafer is provided, including a plurality of semiconductor devices as described above, and a plurality of the semiconductor devices are arranged in an array.
根据本发明实施例的第四方面，提供一种半导体结构的制备方法，包括：According to a fourth aspect of embodiments of the present invention, a method for manufacturing a semiconductor structure is provided, including:
形成第一结构层；Form the first structural layer;
在所述第一结构层表面形成第二结构层；Form a second structural layer on the surface of the first structural layer;
其中，所述第一结构层的材料为金刚石，所述第二结构层的材料为AlN，所述第一结构层和所述第二结构层形成异质结结构。Wherein, the material of the first structural layer is diamond, the material of the second structural layer is AlN, and the first structural layer and the second structural layer form a heterojunction structure.
在一些实施例中，采用高压高温(HPHT)方法和化学气相沉积(CVD)技术形成第一结构层。In some embodiments, a high pressure high temperature (HPHT) method and a chemical vapor deposition (CVD) technology are used to form the first structural layer.
在一些实施例中，在形成第一结构层之前，所述方法包括：In some embodiments, before forming the first structural layer, the method includes:
提供衬底；Provide a substrate;
所述形成第一结构层，包括：The forming the first structural layer includes:
在所述衬底之上形成第一结构层。A first structural layer is formed over the substrate.
在一些实施例中，在提供衬底之后，所述方法包括：In some embodiments, after providing the substrate, the method includes:
对所述衬底表面进行抛光及清洗处理；Polishing and cleaning the substrate surface;
所述在所述衬底之上形成第一结构层包括：The forming the first structural layer on the substrate includes:
在经抛光及清洗处理后的衬底表面形成第一结构层。A first structural layer is formed on the polished and cleaned substrate surface.
在一些实施例中，在形成第二结构层之后，所述方法包括：In some embodiments, after forming the second structural layer, the method includes:
在所述第二结构层背离所述第一结构层的表面形成帽层。A cap layer is formed on the surface of the second structural layer facing away from the first structural layer.
基于上述技术方案，上述异质结结构的第一结构层的材料采用金刚石，第二结构层的材料采用AlN，第一结构层的禁带宽度小于第二结构层的禁带宽度，使得在二者的界面处形成二维电子气，与传统的半导体器件依靠半导体材料中的自由电子从N型半导体向金属移动来实现半导体器件的导通相比，本申请实施例提供的半导体结构中，第一结构层与第二结构层的界面处形成的二维电子气具有更高的电子迁移率和更高的电子密度，使得半导体器件具有更高的电流密度和更高的输出功率、更快的开关速度、更低的正向导通压降、更低的反向电流及更高的工作电压。Based on the above technical solution, the material of the first structural layer of the above-mentioned heterojunction structure is diamond, and the material of the second structural layer is AlN. The bandgap width of the first structural layer is smaller than the bandgap width of the second structural layer, so that in the second structural layer A two-dimensional electron gas is formed at the interface between the two. Compared with traditional semiconductor devices that rely on free electrons in the semiconductor material to move from the N-type semiconductor to the metal to achieve conduction of the semiconductor device, in the semiconductor structure provided by the embodiment of the present application, The two-dimensional electron gas formed at the interface between the first structural layer and the second structural layer has higher electron mobility and higher electron density, allowing the semiconductor device to have higher current density, higher output power, and faster switching speed, lower forward voltage drop, lower reverse current and higher operating voltage.
附图说明Description of the drawings
图1为本发明的一实施例提供的一种半导体结构的剖视图；Figure 1 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present invention;
图2为本发明的一实施例提供的另一种半导体结构的剖视图；Figure 2 is a cross-sectional view of another semiconductor structure provided by an embodiment of the present invention;
图3为本发明的一实施例提供的又一种半导体结构的剖视图；Figure 3 is a cross-sectional view of another semiconductor structure provided by an embodiment of the present invention;
图4为本发明的一实施例提供的一种异质结结构的能带示意图；Figure 4 is a schematic energy band diagram of a heterojunction structure provided by an embodiment of the present invention;
图5为本发明的一实施例提供的一种半导体器件的剖视图；Figure 5 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;
图6为本发明的一实施例提供的另一种半导体器件的剖视图；Figure 6 is a cross-sectional view of another semiconductor device according to an embodiment of the present invention;
图7为本发明的一实施例提供的另一种半导体器件的剖视图；Figure 7 is a cross-sectional view of another semiconductor device according to an embodiment of the present invention;
图8为本发明的一实施例提供的另一种半导体器件的剖视图；Figure 8 is a cross-sectional view of another semiconductor device according to an embodiment of the present invention;
图9为本发明的一实施例提供的另一种半导体器件的剖视图；Figure 9 is a cross-sectional view of another semiconductor device according to an embodiment of the present invention;
图10为本发明的一实施例提供的另一种半导体器件的剖视图；Figure 10 is a cross-sectional view of another semiconductor device according to an embodiment of the present invention;
图11为本发明的一实施例提供的另一种半导体器件的剖视图；Figure 11 is a cross-sectional view of another semiconductor device according to an embodiment of the present invention;
图12为本发明的一实施例提供的一种半导体器件的俯视图；Figure 12 is a top view of a semiconductor device according to an embodiment of the present invention;
图13为本发明的一实施例提供的另一种半导体器件的俯视图；Figure 13 is a top view of another semiconductor device according to an embodiment of the present invention;
图14为本发明的一实施例提供的又一种半导体器件的剖视图；Figure 14 is a cross-sectional view of another semiconductor device according to an embodiment of the present invention;
图15为本发明的一实施例提供的一种半导体晶圆的结构示意图；Figure 15 is a schematic structural diagram of a semiconductor wafer provided by an embodiment of the present invention;
图16为本发明的一实施例提供的一种半导体结构的制备方法的流程图；Figure 16 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;
图17至图19为本发明的一实施例提供的一种半导体结构的制备工艺图。17 to 19 are process diagrams of a semiconductor structure according to an embodiment of the present invention.
具体实施方式Detailed ways
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本发明相一致的所有实施方式。在本发明使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the invention. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
本申请提供一种半导体结构及其制备方法、半导体器件及半导体晶圆。半导体结构，包括第一结构层及第二结构层；其中，所述第一结构层的材料为金刚石，所述第二结构层的材料为AlN，所述第一结构层和所述第二结构层形成异质结结构。上述异质结结构的第一结构层的材料采用金刚石，第二结构层的材料采用AlN，第一结构层的禁带宽度小于第二结构层的禁带宽度，使得在二者的界面处形成二维电子气，与传统的半导体器件依靠半导体材料中的自由电子从N型半导体向金属移动来实现半导体器件的导通相比，本申请实施例提供的半导体结构中，第一结构层与第二结构层的界面处形成的二维电子气具有更高的电子迁移率和更高的电子密度，使得半导体器件具有更高的电流密度和更高的输出功率、更快的开关速度、更低的正向导通压降、更低的反向电流及更高的工作电压。This application provides a semiconductor structure and a preparation method thereof, a semiconductor device and a semiconductor wafer. Semiconductor structure, including a first structural layer and a second structural layer; wherein, the material of the first structural layer is diamond, the material of the second structural layer is AlN, the first structural layer and the second structural layer The layers form a heterojunction structure. The material of the first structural layer of the above-mentioned heterojunction structure is diamond, and the material of the second structural layer is AlN. The bandgap width of the first structural layer is smaller than the bandgap width of the second structural layer, so that a band gap is formed at the interface between the two. Two-dimensional electron gas, compared with traditional semiconductor devices that rely on free electrons in the semiconductor material to move from the N-type semiconductor to the metal to achieve conduction of the semiconductor device, in the semiconductor structure provided by the embodiment of the present application, the first structural layer and the third The two-dimensional electron gas formed at the interface of the two structural layers has higher electron mobility and higher electron density, allowing semiconductor devices to have higher current density, higher output power, faster switching speed, and lower forward voltage drop, lower reverse current and higher operating voltage.
下面结合图1至图17对所述半导体结构及其制备方法、半导体器件及半导体晶圆进行详细描述。The semiconductor structure and its preparation method, semiconductor device and semiconductor wafer will be described in detail below with reference to FIGS. 1 to 17 .
首先，请结合图1至图4所示，对所述半导体结构进行描述。First, please describe the semiconductor structure with reference to Figures 1 to 4.
图1为本发明的一实施例提供的一种半导体结构10的剖视图。图4为本发明的一实施例提供的一种异质结结构的能带示意图。请参照图1，并在必要时结合图4所示，半导体结构10包括第一结构层1及第二结构层2。其中，所述第一结构层1的材料为金刚石，所述第二结构层2的材料为AlN，所述第一结构层1和所述第二结构层2形成异质结结构。FIG. 1 is a cross-sectional view of a semiconductor structure 10 according to an embodiment of the present invention. FIG. 4 is a schematic energy band diagram of a heterojunction structure provided by an embodiment of the present invention. Please refer to FIG. 1 , and when necessary, in conjunction with FIG. 4 , the semiconductor structure 10 includes a first structural layer 1 and a second structural layer 2 . Wherein, the material of the first structural layer 1 is diamond, and the material of the second structural layer 2 is AlN. The first structural layer 1 and the second structural layer 2 form a heterojunction structure.
金刚石具有独特的物理和化学特性，比如金刚石具有极低化学反应性使其可用于高腐蚀性环境。金刚石的室温热导率为10W/cm*K-20W/cm*K，是目前已知材料中极高甚至最高的比铜、硅高很多可达到铜、硅等的数倍。另一方面，在低温下，它又具有最低的热导率之一。金刚石在室温下为电绝缘体，电阻率高达106ohm-cm。金刚石的机械性能同样也较优，它的硬度比较大，约为100GPa，比碳化硅、立方氮化硼、硅等的硬度大很多。同样，金刚石的杨氏模量非常高，能够达到1000GPa以上,是硅或氮化硅的数倍。此外，金刚石的干摩擦系数在0.05到0.15之间，与聚四氟乙烯的值相似，比碳化硅的磨损率低上千倍。更进一步的，金刚石还是一种宽禁带半导体材料，其禁带宽度约为5.5eV。Diamond has unique physical and chemical properties, such as diamond's extremely low chemical reactivity, which allows it to be used in highly corrosive environments. The room temperature thermal conductivity of diamond is 10W/cm*K-20W/cm*K, which is extremely high or even the highest among currently known materials. It is much higher than copper and silicon, and can reach several times that of copper, silicon, etc. On the other hand, it has one of the lowest thermal conductivities at low temperatures. Diamond is an electrical insulator at room temperature, with a resistivity as high as 106ohm-cm. The mechanical properties of diamond are also superior. Its hardness is relatively large, about 100GPa, which is much harder than silicon carbide, cubic boron nitride, silicon, etc. Similarly, the Young's modulus of diamond is very high, reaching more than 1000GPa, which is several times that of silicon or silicon nitride. In addition, the dry friction coefficient of diamond is between 0.05 and 0.15, which is similar to the value of polytetrafluoroethylene, and the wear rate is thousands of times lower than that of silicon carbide. Furthermore, diamond is also a wide bandgap semiconductor material with a bandgap width of approximately 5.5eV.
金刚石可采用高压高温(HPHT)方法形成。比如，该方法所形成的金刚石常为立方体结构、八面体结构及二者的聚形。金刚石还也可以采用化学气相沉积(CVD)法形成，比如等离子体增强型化学气相沉积法(PECVD-Plasma Enhanced Chemical Vapor Deposition)和微波等离子体化学气相沉积法(MPCVD–Microwave Plasma Chemical VaporDeposition)等。Diamond can be formed using the High Pressure High Temperature (HPHT) method. For example, the diamond formed by this method often has a cubic structure, an octahedral structure, or a combination of the two. Diamond can also be formed using chemical vapor deposition (CVD) methods, such as plasma enhanced chemical vapor deposition (PECVD-Plasma Enhanced Chemical Vapor Deposition) and microwave plasma chemical vapor deposition (MPCVD-Microwave Plasma Chemical Vapor Deposition).
氮化铝(AlN)是新型III-V族半导体材料，在III-V族化合物半导体中具有最大禁带宽度及直接带隙。AlN的禁带宽度约为6.2eV。也具有优良的压电性能，同时氮化铝(AlN)具有热导率高、电阻率高、击穿场强大、介电系数小等优异特性。Aluminum nitride (AlN) is a new III-V semiconductor material that has the largest bandgap and direct band gap among III-V compound semiconductors. The bandgap width of AlN is approximately 6.2eV. It also has excellent piezoelectric properties. At the same time, aluminum nitride (AlN) has excellent properties such as high thermal conductivity, high resistivity, strong breakdown field, and small dielectric coefficient.
本申请中采用金刚石作为第一结构层1。该第一结构层1可以直接作为衬底层。也即第一结构层可以同时作为衬底层。如上所说，金刚石具有较好的物理、化学性能、机械性能等，金刚石可以直接用作衬底层。如图1所示的半导体结构10中，所述第一结构层1为衬底层，AlN生长在第一结构层1的表面作为第二结构层2。Diamond is used as the first structural layer 1 in this application. The first structural layer 1 can directly serve as a substrate layer. That is, the first structural layer can simultaneously serve as the substrate layer. As mentioned above, diamond has good physical, chemical properties, mechanical properties, etc., and diamond can be directly used as a substrate layer. In the semiconductor structure 10 shown in FIG. 1 , the first structural layer 1 is a substrate layer, and AlN is grown on the surface of the first structural layer 1 as the second structural layer 2 .
该实施例中，所述第一结构层1作为沟道层，所述第二结构层2作为势垒层。由于金刚石的优异性能，该金刚石材料形成的第一结构层1作为沟道层，由于金刚石材料具有较大的禁带宽度，其击穿电压高，并且金刚石材料导热系数高，可以承受较大的输出功率。In this embodiment, the first structural layer 1 serves as a channel layer, and the second structural layer 2 serves as a barrier layer. Due to the excellent properties of diamond, the first structural layer 1 formed by the diamond material serves as the channel layer. Since the diamond material has a large bandgap width, its breakdown voltage is high, and the diamond material has a high thermal conductivity and can withstand large Output Power.
根据上述金刚石以及AlN的优异性能，这里金刚石材料形成的第一结构层1作为沟道层，AlN材料形成的第二结构层作为势垒层，所形成的异质结结构，相对于其它不同结构层形成的异质结结构(比如AlxGa(1-x)N(其中x取值范围为0～1)作为沟道层，AlN作为势垒层所形成的异质结结构等)，在具有很高禁带宽度的同时，该异质结结构具有更高的电子迁移率、更高的电子浓度、更高的击穿电压，以及更高的热导率。According to the excellent properties of diamond and AlN mentioned above, the first structural layer 1 formed of diamond material serves as the channel layer, and the second structural layer formed of AlN material serves as the barrier layer. The heterojunction structure formed is, compared to other different structures, The heterojunction structure formed by layers (such as the heterojunction structure formed by AlxGa(1-x)N (where x ranges from 0 to 1) as the channel layer and AlN as the barrier layer) has many advantages in While having a high band gap, the heterojunction structure has higher electron mobility, higher electron concentration, higher breakdown voltage, and higher thermal conductivity.
可以理解的是，该实施例中，金刚石的第一结构层1可以同时作为衬底层和沟道层，使得半导体结构整体的结构膜层得到简化。该实施例中，所述第一结构层1的厚度为100μm-300μm。所述第二结构层2的厚度为3nm-30nm。所述第一结构层1和所述第二结构层2的具体厚度可以根据具体情况进行设置。It can be understood that in this embodiment, the first structural layer 1 of diamond can serve as the substrate layer and the channel layer at the same time, so that the structural film layer of the entire semiconductor structure is simplified. In this embodiment, the thickness of the first structural layer 1 is 100 μm-300 μm. The thickness of the second structural layer 2 is 3nm-30nm. The specific thicknesses of the first structural layer 1 and the second structural layer 2 can be set according to specific circumstances.
如图4所示，图4中Ec为导带底所处的能级，Ev为价带顶所处的能级，△Ec为AlN材料与金刚石(Diamond)材料由于禁带宽度不同而形成导带底的带阶差，EF为处于平衡态时金刚石材料中的费米能级。如图4所示，所述第二结构层2(即AlN)的禁带宽度大于所述第一结构层1(即金刚石)的禁带宽度，第二结构层2与第一结构层1的导带底存在带阶差，带阶差使得导带底能带弯曲，从而使第一结构层1与第二结构层2的界面处形成二维势阱，二维势阱将电子限制在其中，使得电子在二维势阱形成二维电子气(2DEG，如图4中的阴影区域)。也即本申请实施例提供的异质结结构，即使不对第二结构层2进行离子掺杂，其也能得到较高的二维电子气的面密度，能够很好解决AlN由于难于掺杂而导致其在半导体结构中应用受限的问题。As shown in Figure 4, Ec in Figure 4 is the energy level at the bottom of the conduction band, Ev is the energy level at the top of the valence band, △Ec is the conduction formed by the different bandgap widths of AlN materials and diamond materials. The band step difference at the bottom of the band, EF is the Fermi level in the diamond material at equilibrium. As shown in Figure 4, the bandgap width of the second structural layer 2 (i.e. AlN) is greater than the bandgap width of the first structural layer 1 (i.e. diamond). The gap between the second structural layer 2 and the first structural layer 1 is There is a band step difference at the bottom of the conduction band. The band step difference causes the energy band at the bottom of the conduction band to bend, thereby forming a two-dimensional potential well at the interface between the first structural layer 1 and the second structural layer 2. The two-dimensional potential well confines the electrons therein. , causing the electrons to form a two-dimensional electron gas (2DEG, as shown in the shaded area in Figure 4) in the two-dimensional potential well. That is to say, the heterojunction structure provided by the embodiments of the present application can obtain a higher surface density of two-dimensional electron gas even if the second structural layer 2 is not ion doped, and can well solve the problem of AlN being difficult to dope. problems that limit its application in semiconductor structures.
所述半导体结构还可包括帽层3，用以保护第二结构层2。帽层3设于(也即生长于)所述第二结构层2背离所述第一结构层1的表面。The semiconductor structure may further include a cap layer 3 to protect the second structural layer 2 . The cap layer 3 is provided on (that is, grown on) the surface of the second structural layer 2 facing away from the first structural layer 1 .
可以理解的是，该帽层3可以覆盖所述第二结构层2背离所述第一结构层1的部分或全部表面。It can be understood that the cap layer 3 can cover part or all of the surface of the second structural layer 2 facing away from the first structural layer 1 .
该帽层3的材料可以为GaN，以下也以帽层3的材料为GaN为例进行说明。当然，也可以为其他材料(如氮化硅)等材料。The material of the cap layer 3 may be GaN, and the following description will also take the example of the material of the cap layer 3 being GaN. Of course, it can also be other materials (such as silicon nitride).
图2为本发明的一实施例提供的另一种半导体结构20的剖视图。请参照图2所示，相较于上述图1所示的半导体结构10，该半导体结构20除了包括第一结构层1、第二结构层2及帽层3外，还包括衬底(也即一衬底层)4，所述衬底4位于所述第一结构层1背离所述第二结构层2的一侧表面。FIG. 2 is a cross-sectional view of another semiconductor structure 20 according to an embodiment of the present invention. Please refer to FIG. 2 . Compared with the semiconductor structure 10 shown in FIG. 1 , in addition to the first structural layer 1 , the second structural layer 2 and the cap layer 3 , the semiconductor structure 20 also includes a substrate (i.e. A substrate layer) 4, the substrate 4 is located on a side surface of the first structural layer 1 facing away from the second structural layer 2.
衬底4的材料可以是硅(包括SOI)、碳化硅、蓝宝石等。The material of the substrate 4 may be silicon (including SOI), silicon carbide, sapphire, etc.
该实施例中，所述第一结构层1的厚度为0.2um-5um。In this embodiment, the thickness of the first structural layer 1 is 0.2um-5um.
所述第二结构层2的厚度为3nm-30nm。其中，所述第一结构层1和所述第二结构层2的具体厚度可以根据具体情况进行设置。The thickness of the second structural layer 2 is 3nm-30nm. The specific thicknesses of the first structural layer 1 and the second structural layer 2 can be set according to specific circumstances.
图3为本发明的一实施例提供的又一种半导体结构30的剖视图。请参照图3所示，相较于半导体结构20，半导体结构30除了包括第一结构层1、第二结构层2、帽层3及衬底4外，还包括缓冲层5。缓冲层5位于衬底4和第一结构层1之间。FIG. 3 is a cross-sectional view of yet another semiconductor structure 30 according to an embodiment of the present invention. Please refer to FIG. 3 . Compared with the semiconductor structure 20 , the semiconductor structure 30 includes a buffer layer 5 in addition to the first structural layer 1 , the second structural layer 2 , the cap layer 3 and the substrate 4 . The buffer layer 5 is located between the substrate 4 and the first structural layer 1 .
由于衬底4的材料与第一结构层1的材料具有不同的晶格常数和热膨胀系数，晶格常数的不同会引起衬底4与第一结构层1之间的晶格失配，导致发生位错缺陷；同时晶格失配也会使得膜层产生应力并引起膜层翘曲和龟裂等问题，以及衬底4的材料与第一结构层1的材料二者热膨胀系数不同，半导体结构30制备过程中，容易引起膜内产生残余应力等原因，通过设置缓冲层5，可消除或减少衬底4和第一结构层1由于晶格常数不同和热膨胀系数不同而引起的膜层位错、翘曲和龟裂等缺陷，有助于提升半导体结构的性能。Since the material of the substrate 4 and the material of the first structural layer 1 have different lattice constants and thermal expansion coefficients, the difference in lattice constants will cause lattice mismatch between the substrate 4 and the first structural layer 1, leading to Dislocation defects; at the same time, lattice mismatch will also cause stress in the film layer and cause problems such as warping and cracking of the film layer, and the material of the substrate 4 and the material of the first structural layer 1 have different thermal expansion coefficients, and the semiconductor structure During the preparation process of 30, it is easy to cause residual stress in the film and other reasons. By setting the buffer layer 5, the film layer dislocations caused by the different lattice constants and thermal expansion coefficients of the substrate 4 and the first structural layer 1 can be eliminated or reduced. Defects such as warping and cracking can help improve the performance of semiconductor structures.
本发明另提供一种半导体器件，其可包括如前所述的任一种半导体结构，以及及位于所述异质结结构至少部分膜层背离所述衬底一侧的电极结构。The present invention also provides a semiconductor device, which may include any semiconductor structure as described above, and an electrode structure located on at least part of the film layer of the heterojunction structure on a side facing away from the substrate.
请结合图5至图14所示，对所述半导体器件进行描述，其中，图5至图11以及图14分别为不同的半导体器件。图12和图13为不同半导体器件的俯视图。Please describe the semiconductor device with reference to FIGS. 5 to 14 , where FIGS. 5 to 11 and FIG. 14 are different semiconductor devices respectively. Figures 12 and 13 are top views of different semiconductor devices.
请参照图5所示，在一些实施例中，半导体器件100包括上述的半导体结构1、2、3或者类似的半导体结构，以及电极结构。所述电极结构位于所述异质结结构至少部分膜层背离所述衬底4的一侧。Referring to FIG. 5 , in some embodiments, the semiconductor device 100 includes the above-mentioned semiconductor structures 1, 2, 3 or similar semiconductor structures, and electrode structures. The electrode structure is located on a side of at least part of the film layer of the heterojunction structure facing away from the substrate 4 .
该半导体器件100中，所述电极结构包括阴极72和阳极71。其中，对于所述半导体结构中设有帽层3的，所述帽层3覆盖所述第二结构层2，所述阳极71和所述阴极72位于所述帽层3背离所述第一结构层1的表面，与帽层3接触。In the semiconductor device 100, the electrode structure includes a cathode 72 and an anode 71. Wherein, for the cap layer 3 provided in the semiconductor structure, the cap layer 3 covers the second structural layer 2, and the anode 71 and the cathode 72 are located on the cap layer 3 away from the first structure. The surface of layer 1 is in contact with cap layer 3.
阴极72一般由几种金属或其它导电材料的组合通过高温退火形成合金以减小电阻。这些金属可包括Ti，Al，Ni，Pt，Au或其它，可以是一种金属或多种金属的组合，通常可通过金属蒸镀逐层沉淀到氮化铝外延层或氮化镓感帽层上。例如，阴极为多种金属的组合的，可以有2-6层金属层组合，比如阴极72可以由4层金属层组成，分别是Ti，Al，Ti，Au，厚度范围分别为2-25nm，30-300nm，20-100nm，50-500nm。比如，可以分别选用Ti 25nm，Al 50nm，Ti100nm，Au 250nm，总厚度为450nm。阴极72也可以是其他组合和厚度。退火工艺在RTA(快速热退火炉)中进行，温度一般介于700-900℃,通常为800℃左右。在氩气或氮气环境中进行，时间为30秒-90秒，目的是形成欧姆接触以减小电阻。Cathode 72 is typically made from a combination of several metals or other conductive materials alloyed by high temperature annealing to reduce electrical resistance. These metals can include Ti, Al, Ni, Pt, Au or others, and can be one metal or a combination of multiple metals. They can usually be deposited layer by layer through metal evaporation to the aluminum nitride epitaxial layer or the gallium nitride sensing cap layer. superior. For example, the cathode is a combination of multiple metals, and may have a combination of 2-6 metal layers. For example, the cathode 72 may be composed of 4 metal layers, namely Ti, Al, Ti, and Au, with thicknesses ranging from 2-25 nm. 30-300nm, 20-100nm, 50-500nm. For example, you can choose Ti 25nm, Al 50nm, Ti100nm, and Au 250nm respectively, with a total thickness of 450nm. Other combinations and thicknesses of cathode 72 are possible. The annealing process is carried out in an RTA (rapid thermal annealing furnace), and the temperature is generally between 700-900°C, usually around 800°C. It is carried out in an argon or nitrogen environment and the time is 30 seconds to 90 seconds. The purpose is to form ohmic contact to reduce resistance.
阴极72的截面(垂直于半导体结构厚度方向上的截面)形状可以是圆形、方型、长方行、椭圆型或其他形状，比如图12所示。阴极的截面的径向尺寸可以是10um–500um,这里不作具体限定。The cross-sectional shape of the cathode 72 (the cross-section perpendicular to the thickness direction of the semiconductor structure) may be circular, square, rectangular, elliptical or other shapes, such as shown in FIG. 12 . The radial size of the cross-section of the cathode can be 10um-500um, and there is no specific limit here.
阳极71一般选用功函数高的金属或导电材料形成，如Pt，Ni，Au，Ti，其功函数分别为5.65eV，5.15eV，5.1eV，4.33eV。目的是与第二结构层2的AlN或帽层的GaN等形成肖特基接触。该实施例中，与帽层形成肖特基接触。阳极71可以由一层金属组成，也可以由多层金属组成，比如2-4层金属组成，如可以选用Pt/Au或Ni/Au，厚度范围为10nm-50nm及50nm-250nm。其制作方法通常是通过金属蒸镀或溅射逐层沉淀到氮化铝外延层上。The anode 71 is generally made of metal or conductive material with high work function, such as Pt, Ni, Au, and Ti, whose work functions are 5.65eV, 5.15eV, 5.1eV, and 4.33eV respectively. The purpose is to form Schottky contact with AlN of the second structural layer 2 or GaN of the cap layer. In this embodiment, a Schottky contact is formed with the cap layer. The anode 71 can be composed of one layer of metal or multiple layers of metal, such as 2-4 layers of metal. For example, Pt/Au or Ni/Au can be selected, and the thickness range is 10nm-50nm and 50nm-250nm. The manufacturing method is usually to deposit layer by layer onto the aluminum nitride epitaxial layer through metal evaporation or sputtering.
类似的，阳极71的截面(垂直于半导体结构厚度方向上的截面)形状可以是圆形、方型、长方行、椭圆型或其他形状，比如图12所示。阳极的径向大小可以是10um–500um，这里不作具体限定。Similarly, the cross-section (the cross-section perpendicular to the thickness direction of the semiconductor structure) of the anode 71 may be circular, square, rectangular, elliptical or other shapes, such as shown in FIG. 12 . The radial size of the anode can be 10um-500um, and there is no specific limit here.
可以理解的是，阳极71和阴极72完全间隔开外，还可以采用类似图13所示的一个被另一个环绕的方式设置。比如，阴极72的截面(垂直于半导体结构厚度方向上的截面)形状呈环状(比如圆形)，阳极71位于阴极72内部，并与阴极72间隔开。该阳极71的截面(垂直于半导体结构厚度方向上的截面)形状可以为圆形。当然，阳极和阴极二者的形状也可以采用其它形状。It can be understood that, in addition to being completely separated from each other, the anode 71 and the cathode 72 can also be arranged in a manner similar to that shown in FIG. 13 with one surrounded by the other. For example, the cross-section of the cathode 72 (the cross-section perpendicular to the thickness direction of the semiconductor structure) is annular (such as a circle), and the anode 71 is located inside the cathode 72 and is spaced apart from the cathode 72 . The cross-section (the cross-section perpendicular to the thickness direction of the semiconductor structure) of the anode 71 may be circular. Of course, other shapes for both the anode and the cathode may also be used.
请参照图6所示，在一些实施例中，所述半导体器件200包括钝化层6。所述钝化层6包覆阴极72、阳极71的侧壁及所述帽层3背离所述第一结构层1的表面。Referring to FIG. 6 , in some embodiments, the semiconductor device 200 includes a passivation layer 6 . The passivation layer 6 covers the sidewalls of the cathode 72 and the anode 71 and the surface of the cap layer 3 facing away from the first structural layer 1 .
钝化层可以是氧化硅、氮化硅或氧化铝。本说明中以氮化硅为例。氮化硅一般通过PECVD(等离子体增强化学气相沉积法)制作，也可以采用其他方法(如ALD，原子层沉积法)的方法制作。厚度为50nm-500nm。The passivation layer can be silicon oxide, silicon nitride or aluminum oxide. In this explanation, silicon nitride is used as an example. Silicon nitride is generally produced by PECVD (Plasma Enhanced Chemical Vapor Deposition), but it can also be produced by other methods (such as ALD, atomic layer deposition). Thickness is 50nm-500nm.
阴极72、阳极71可自钝化层6中暴露部分区域，以与外界进行电连接。一般可将阴极72、阳极71的顶面部分或全部区域自钝化层6中暴露。比如，在一些实施例中，该钝化层6还包覆阴极72、阳极71顶面外围的部分区域，使得二者顶部的中部自钝化层6中暴露出来。The cathode 72 and the anode 71 may expose part of the passivation layer 6 to electrically connect with the outside world. Generally, part or all of the top surfaces of the cathode 72 and the anode 71 can be exposed from the passivation layer 6 . For example, in some embodiments, the passivation layer 6 also covers part of the peripheral areas of the top surfaces of the cathode 72 and the anode 71 , so that the middle portions of the top surfaces of the cathode 72 and the anode 71 are exposed from the passivation layer 6 .
为了改善肖特基(阳极)的性能，可以将阳极71设置在第二结构层2或第一结构层1上。In order to improve Schottky (anode) performance, the anode 71 can be disposed on the second structural layer 2 or the first structural layer 1 .
请参照图7所示，在一些实施例中，该半导体器件300中，所述第二结构层2的部分表面未被所述帽层3覆盖，所述阳极71在未被帽层覆盖的部分与所述第二结构层2的表面直接接触，所述阴极72位于所述帽层3背离所述第一结构层1的表面。Please refer to FIG. 7 . In some embodiments, in the semiconductor device 300 , part of the surface of the second structural layer 2 is not covered by the cap layer 3 , and the anode 71 is in the part not covered by the cap layer 3 . In direct contact with the surface of the second structural layer 2 , the cathode 72 is located on the surface of the cap layer 3 facing away from the first structural layer 1 .
请参照图8所示，在另一些实施例中，该半导体器件400中，所述第二结构层2的部分表面未被所述帽层3覆盖，所述第二结构层2未被所述帽层3覆盖的区域设有第一通孔201，所述阳极71包括第一电极部711和与所述第一电极部711相连的第二电极部712，所述第一电极部711位于所述第一通孔201内且与所述第一结构层1的表面接触，所述第二电极部712位于所述第二结构层2背离所述第一结构层1的表面。所述阴极72位于所述帽层3背离所述第一结构层1的表面。Please refer to FIG. 8 . In other embodiments, in the semiconductor device 400 , part of the surface of the second structural layer 2 is not covered by the cap layer 3 , and the second structural layer 2 is not covered by the cap layer 3 . The area covered by the cap layer 3 is provided with a first through hole 201. The anode 71 includes a first electrode part 711 and a second electrode part 712 connected to the first electrode part 711. The first electrode part 711 is located there. The second electrode part 712 is located in the first through hole 201 and in contact with the surface of the first structural layer 1 . The second electrode part 712 is located on the surface of the second structural layer 2 away from the first structural layer 1 . The cathode 72 is located on the surface of the cap layer 3 facing away from the first structural layer 1 .
请参照图9所示，在一些实施例中，该半导体器件500中，所述帽层包括N型掺杂区和未掺杂区，所述阳极71位于所述未掺杂区背离所述第一结构层1的表面，所述阴极72位于所述N型掺杂区背离所述第一结构层1的表面。Referring to FIG. 9 , in some embodiments, in the semiconductor device 500 , the cap layer includes an N-type doped region and an undoped region, and the anode 71 is located in the undoped region away from the first On the surface of a structural layer 1 , the cathode 72 is located on the surface of the N-type doped region facing away from the first structural layer 1 .
该实施例中，在形成帽层时，先对用于设置阴极72的区域的将GaN帽层分为掺杂和非掺杂两个区域。常用的掺杂元素是硅，形成N型掺杂，掺杂的浓度范围1e17–1e21 cm-2之间。掺杂后进行激活，温度范围为1000℃-1300℃，时间为30s-120s。阴极金属制作在掺杂区域以形成欧姆接触，阳极金属设置在非掺杂区域形成肖特基。In this embodiment, when forming the cap layer, the GaN cap layer is first divided into two regions, doped and non-doped, in the area used to dispose the cathode 72 . The commonly used doping element is silicon, forming N-type doping, and the doping concentration range is between 1e17–1e21 cm-2 . Activation is carried out after doping, the temperature range is 1000℃-1300℃, and the time is 30s-120s. The cathode metal is made in the doped area to form ohmic contact, and the anode metal is placed in the undoped area to form Schottky.
上述各实施例中，阴极72与帽层3形成欧姆接触。In the above embodiments, the cathode 72 and the cap layer 3 form ohmic contact.
如图10所示，在一些实施例中，该半导体器件600中，所述阴极72包括第三电极部721和与所述第三电极部721相连的第四电极部722。As shown in FIG. 10 , in some embodiments of the semiconductor device 600 , the cathode 72 includes a third electrode part 721 and a fourth electrode part 722 connected to the third electrode part 721 .
所述阳极71位于所述帽层3背离所述第一结构层1的表面；所述帽层3设有第二通孔301，所述第三电极部721位于所述第二通孔301内，且与所述第二结构层2背离所述第一结构层1的表面接触，所述第四电极部722位于所述帽层3背离所述第一结构层1的表面。The anode 71 is located on the surface of the cap layer 3 away from the first structural layer 1; the cap layer 3 is provided with a second through hole 301, and the third electrode portion 721 is located in the second through hole 301. , and is in contact with the surface of the second structural layer 2 facing away from the first structural layer 1 , and the fourth electrode portion 722 is located on the surface of the cap layer 3 facing away from the first structural layer 1 .
该实施例中，将阴极72制作在所述第二结构层2表面而形成欧姆接触。其具体可以先刻蚀GaN帽层，采用低损伤刻蚀工艺，将刻蚀工艺对晶体的损伤最小化；进而再制作欧姆接触，包括金属沉积、退火等步骤，从而形成阴极72。In this embodiment, the cathode 72 is fabricated on the surface of the second structural layer 2 to form an ohmic contact. Specifically, the GaN cap layer can be etched first, using a low-damage etching process to minimize the damage to the crystal caused by the etching process; and then the ohmic contact can be made, including metal deposition, annealing and other steps, to form the cathode 72 .
请参照图11所示，在另一些实施例中，该半导体器件700中，所述阳极71位于所述帽层3背离所述第一结构层1的表面。所述半导体结构设有贯穿所述帽层3及所述第二结构层2的第三通孔302，所述第三电极部721位于所述第三通孔302内，且与所述第一结构层1的表面接触，所述第四电极部722位于所述帽层3背离所述第一结构层1的表面。Please refer to FIG. 11 . In other embodiments, in the semiconductor device 700 , the anode 71 is located on the surface of the cap layer 3 away from the first structural layer 1 . The semiconductor structure is provided with a third through hole 302 penetrating the cap layer 3 and the second structural layer 2. The third electrode portion 721 is located in the third through hole 302 and is connected with the first The surface of the structural layer 1 is in contact, and the fourth electrode portion 722 is located on the surface of the cap layer 3 facing away from the first structural layer 1 .
与半导体器件600不同的是，该实施例中，通孔302及第三电极部721贯穿帽层3及第二结构层2两层结构层。What is different from the semiconductor device 600 is that in this embodiment, the through hole 302 and the third electrode part 721 penetrate through the two structural layers of the cap layer 3 and the second structural layer 2 .
可以理解的是，上述的半导体器件100至700分别可以是发光二极管，肖特基二极管，或场效应晶体管。It can be understood that the above-mentioned semiconductor devices 100 to 700 can respectively be light emitting diodes, Schottky diodes, or field effect transistors.
此外，所述半导体器件还可以为HEMT器件。比如，请参照图14所示，半导体器件800中，所述电极结构包括源极73、栅极75及漏极74；其中，所述半导体结构中未设有帽层的，所述源极73、栅极75及漏极74位于所述第二结构层2背离所述第一结构层1的表面。当然，源极73及漏极74还可穿过第二结构层2而与第一结构层1接触，比如与第一结构层1朝向第二结构层2的表面接触，形成欧姆接触。In addition, the semiconductor device may also be a HEMT device. For example, please refer to FIG. 14. In the semiconductor device 800, the electrode structure includes a source electrode 73, a gate electrode 75 and a drain electrode 74; wherein, if the semiconductor structure is not provided with a cap layer, the source electrode 73 , the gate electrode 75 and the drain electrode 74 are located on the surface of the second structural layer 2 facing away from the first structural layer 1 . Of course, the source electrode 73 and the drain electrode 74 can also pass through the second structural layer 2 and contact the first structural layer 1 , for example, contact the surface of the first structural layer 1 facing the second structural layer 2 to form an ohmic contact.
当然，在其它一些实施例中，对于所述半导体结构中设有帽层3的，所述帽层3覆盖所述第二结构层2的，所述源极73和漏极74可位于所述帽层背离所述第一结构层1的表面，与帽层3接触，也可穿过帽层而与第二结构层2接触，或者穿过帽层3和所述第二结构层2而与所述第一结构层1接触。栅极75可穿过帽层3而与第二结构层2接触。Of course, in some other embodiments, if the cap layer 3 is provided in the semiconductor structure and the cap layer 3 covers the second structural layer 2, the source electrode 73 and the drain electrode 74 may be located on the The surface of the cap layer facing away from the first structural layer 1 is in contact with the cap layer 3 . It can also pass through the cap layer and contact the second structural layer 2 , or it can pass through the cap layer 3 and the second structural layer 2 and be in contact with the second structural layer 2 . The first structural layer 1 contacts. The gate electrode 75 can pass through the cap layer 3 and contact the second structural layer 2 .
源极73和漏极74的制作方法可包括涂胶、对准/曝光、显影、金属沉积、金属剥离(或刻蚀)、去胶、清洗、退火等工艺步骤。源极和漏极一般由几种金属的组合通过高温退火形成合金以减小电阻。这些金属包括Ti，Al，Ni,，Pt，Au或其它，可以是一种金属或多种(比如2种-6种)金属的组合，通常是通过金属蒸镀逐层沉淀到氮化铝外延层(即第二结构层2)上。例如，源极和漏极可以由4层金属层组成，分别是Ti，Al，Ti，Au，这4层金属层的厚度范围分别为：2nm-25nm,30nm-300nm,20nm-100nm,50nm-500nm。比如，可以分别选用Ti 25nm，Al50nm，Ti 100nm，Au 250nm，总厚度为450nm。金属层也可以是其他组合和厚度。退火工艺在RTA(快速热退火炉)中进行，温度一般介于700-900℃，通常为800℃左右。在氩气或氮气环境中进行，时间为30秒-90秒，目的是形成欧姆接触以减小电阻。The manufacturing method of the source electrode 73 and the drain electrode 74 may include process steps such as glue coating, alignment/exposure, development, metal deposition, metal stripping (or etching), glue removal, cleaning, and annealing. The source and drain electrodes are generally made of a combination of several metals and are alloyed by high-temperature annealing to reduce resistance. These metals include Ti, Al, Ni, Pt, Au or others, which can be one metal or a combination of multiple (such as 2 to 6) metals. They are usually deposited layer by layer through metal evaporation to aluminum nitride epitaxy. layer (i.e. second structural layer 2). For example, the source and drain electrodes can be composed of four metal layers, namely Ti, Al, Ti, and Au. The thickness ranges of these four metal layers are: 2nm-25nm, 30nm-300nm, 20nm-100nm, 50nm- 500nm. For example, you can choose Ti 25nm, Al50nm, Ti 100nm, Au 250nm respectively, with a total thickness of 450nm. Other combinations and thicknesses of metal layers are also possible. The annealing process is carried out in an RTA (rapid thermal annealing furnace), and the temperature is generally between 700-900°C, usually around 800°C. It is carried out in an argon or nitrogen environment and the time is 30 seconds to 90 seconds. The purpose is to form ohmic contact to reduce resistance.
栅极75通常是通过金属蒸镀或溅射逐层沉淀到第二结构层2的氮化铝上。栅极75的制作方法包括涂胶、对准/曝光、显影、金属沉积、金属剥离(刻蚀)、去胶、清洗等工艺步骤，这里不作详细描述。图14所示的结构中，栅极75为肖特基，金属电极直接制作在第二结构层2(即势垒层)表面，以与第二结构层2(即势垒层)的氮化铝层形成肖特基接触。栅极75层一般选用功函数高的金属，如Pt，Ni，Au，Ti。其功函数分别为5.65eV,5.15eV,5.1eV,4.33eV。金属层可以由一层金属组成，也可以由2-4层金属组成，比如可以选用Pt/Au或Ni/Au，厚度范围相应为10nm-50nm或50nm-250nm。The gate electrode 75 is usually deposited layer by layer on the aluminum nitride of the second structural layer 2 through metal evaporation or sputtering. The manufacturing method of the gate 75 includes glue coating, alignment/exposure, development, metal deposition, metal stripping (etching), glue removal, cleaning and other process steps, which will not be described in detail here. In the structure shown in Figure 14, the gate 75 is Schottky, and the metal electrode is directly fabricated on the surface of the second structural layer 2 (ie, the barrier layer) to interact with the nitridation of the second structural layer 2 (ie, the barrier layer). The aluminum layer forms a Schottky contact. The gate 75 layer generally uses metals with high work functions, such as Pt, Ni, Au, and Ti. Their work functions are 5.65eV, 5.15eV, 5.1eV, and 4.33eV respectively. The metal layer can be composed of one layer of metal or 2-4 layers of metal. For example, Pt/Au or Ni/Au can be used, and the thickness range is 10nm-50nm or 50nm-250nm.
本发明另提供一种半导体晶圆，其包括多个上所述的半导体器件，多个所述半导体器件阵列排布。比如请参照图15所示，图15所示的半导体晶圆1000，包括多个半导体器件100，多个所述半导体器件100阵列排布。The present invention also provides a semiconductor wafer, which includes a plurality of the above-mentioned semiconductor devices, and a plurality of the semiconductor devices are arranged in an array. For example, please refer to FIG. 15. The semiconductor wafer 1000 shown in FIG. 15 includes a plurality of semiconductor devices 100, and the plurality of semiconductor devices 100 are arranged in an array.
请参照图16，并在必要时结合图1至图3所示，本发明另提供一种半导体结构的制备方法，其包括如下步骤S101和步骤S103：Referring to Figure 16, and when necessary combined with Figures 1 to 3, the present invention also provides a method for preparing a semiconductor structure, which includes the following steps S101 and S103:
在步骤S101中，形成第一结构层；In step S101, a first structural layer is formed;
在步骤S103中，在所述第一结构层表面形成第二结构层；In step S103, a second structural layer is formed on the surface of the first structural layer;
其中，所述第一结构层的材料为金刚石，所述第二结构层的材料为AlN，所述第一结构层和所述第二结构层形成异质结结构。Wherein, the material of the first structural layer is diamond, the material of the second structural layer is AlN, and the first structural layer and the second structural layer form a heterojunction structure.
首先，请结合图17至图19所示，以形成半导体结构10为例进行说明。First, please take the formation of the semiconductor structure 10 as an example for explanation as shown in FIGS. 17 to 19 .
如图17所示，在步骤S101中，形成第一结构层1。As shown in Figure 17, in step S101, the first structural layer 1 is formed.
在一些实施例中，采用高压高温(HPHT)方法形成第一结构层1。In some embodiments, a high-pressure, high-temperature (HPHT) method is used to form the first structural layer 1 .
在另一些实施例中，采用化学气相沉积(CVD)方法形成第一结构层1。比如PECVD法或MPCVD法。In other embodiments, a chemical vapor deposition (CVD) method is used to form the first structural layer 1 . Such as PECVD method or MPCVD method.
如图18所示，在步骤S103中，在所述第一结构层1表面形成第二结构层2。As shown in FIG. 18 , in step S103 , a second structural layer 2 is formed on the surface of the first structural layer 1 .
第二结构层2的厚度范围是3nm-30nm。The thickness of the second structural layer 2 ranges from 3 nm to 30 nm.
第二结构层2的制作可以有多种方法，常用的方法是金属有机化合物化学气相沉积法(MOCVD-Metal Organic Chemical Vapor Deposition)。一般三甲基铝(TMAl，C3H9Al)和氨气(NH3)分别作为铝源和氮源，氢气作为载气。可以通过调节反应炉的压力、温度、气体的流量，生长高质量的单晶氮化铝薄膜。The second structural layer 2 can be produced by a variety of methods, and a commonly used method is metal organic chemical vapor deposition (MOCVD-Metal Organic Chemical Vapor Deposition). Generally, trimethylaluminum (TMAl, C3H9Al) and ammonia (NH3) are used as the aluminum source and nitrogen source respectively, and hydrogen is used as the carrier gas. High-quality single crystal aluminum nitride films can be grown by adjusting the pressure, temperature, and gas flow of the reactor.
第二结构层2的制作，也可以采用分子束外延法(MBE)或等离子体诱导分子束(PIMBE)，使用用于Al的常规渗出池，以及射频等离子体源产生氮自由基。从而才金刚石表面生长高质量的单晶AlN薄膜。The second structural layer 2 can also be produced by molecular beam epitaxy (MBE) or plasma induced molecular beam (PIMBE), using a conventional infiltration cell for Al and a radio frequency plasma source to generate nitrogen radicals. As a result, a high-quality single-crystal AlN film is grown on the diamond surface.
在一些实施例中，在步骤S103形成第二结构层之后，所述方法包括如下步骤S105：In some embodiments, after forming the second structural layer in step S103, the method includes the following step S105:
在步骤S105中，在所述第二结构层背离所述第一结构层的表面形成帽层。In step S105, a cap layer is formed on the surface of the second structural layer facing away from the first structural layer.
帽层3可以是氮化镓或氮化硅。帽层3也可以是低Al组分的AlGaN。Al组分低于0.2的AlGaN。帽层3的厚度范围为3nm-20nm。Cap layer 3 may be gallium nitride or silicon nitride. The cap layer 3 may also be AlGaN with low Al composition. AlGaN with an Al composition lower than 0.2. The thickness of the cap layer 3 ranges from 3 nm to 20 nm.
帽层3的制作可以有多种方法，常用的方法是金属有机化合物化学气相沉积法(MOCVD-Metal Organic Chemical Vapor Deposition)。一般用三甲基镓(TMGa，C3H9Ga)和氨气(NH3)分别作为镓源和氮源，氢气作为载气。可以通过调节反应炉的压力、温度、气体的流量，生长高质量的单晶氮化镓薄膜。The cap layer 3 can be produced by a variety of methods, and a commonly used method is metal organic chemical vapor deposition (MOCVD-Metal Organic Chemical Vapor Deposition). Generally, trimethylgallium (TMGa, C3H9Ga) and ammonia (NH3) are used as the gallium source and nitrogen source respectively, and hydrogen is used as the carrier gas. High-quality single crystal gallium nitride films can be grown by adjusting the pressure, temperature, and gas flow of the reactor.
需要说明的是，该实施例中，第一结构层1作为衬底。It should be noted that in this embodiment, the first structural layer 1 serves as the substrate.
请结合图2所示，在另一些实施例中，对于第一结构层1不做衬底的，在形成第一结构层之前，所述方法包括如下步骤S1001：Please refer to FIG. 2 . In other embodiments, if the first structural layer 1 is not used as a substrate, before forming the first structural layer, the method includes the following steps S1001:
在步骤S1001中，提供衬底4；In step S1001, substrate 4 is provided;
步骤S101中所述形成第一结构层1，包括：Forming the first structural layer 1 as described in step S101 includes:
在所述衬底4之上形成第一结构层1。A first structural layer 1 is formed on the substrate 4 .
通过优化第一结构层1的制备工艺变量(包括反应气体压力和浓度、衬底温度和样品台等)，可以优化第一结构层1(即金刚石)石生长质量并增加其生长速率。发明人经过研究发现，在制作的第一结构层1厚度为0.2um-5um。较优地，可采用MPCVD方法，工艺条件为：功率1KW-10KW，压力5kPa-200kPa，气体比例1-5％(N2/CH4),温度在1000℃–1500℃。By optimizing the preparation process variables of the first structural layer 1 (including reaction gas pressure and concentration, substrate temperature, sample stage, etc.), the stone growth quality of the first structural layer 1 (i.e., diamond) can be optimized and its growth rate increased. The inventor found through research that the thickness of the first structural layer 1 being produced is 0.2um-5um. Preferably, the MPCVD method can be used, and the process conditions are: power 1KW-10KW, pressure 5kPa-200kPa, gas ratio 1-5% (N2/CH4), and temperature 1000℃-1500℃.
在形成第一结构层1时，衬底4优选可以安装在钼基板支架上，以确保温度均匀，以使得形成的第一结构层1不同区域的厚度较为一致。When forming the first structural layer 1, the substrate 4 can preferably be mounted on a molybdenum substrate support to ensure uniform temperature, so that the thickness of different areas of the formed first structural layer 1 is relatively consistent.
对于具有衬底4的，在提供衬底4之后，所述方法可选择地包括：For those with substrate 4, after providing substrate 4, the method optionally includes:
对所述衬底4表面进行抛光及清洗处理；Polish and clean the surface of the substrate 4;
所述在所述衬底4之上形成第一结构层1包括：The forming the first structural layer 1 on the substrate 4 includes:
在经抛光及清洗处理后的衬底4表面形成第一结构层1。The first structural layer 1 is formed on the surface of the polished and cleaned substrate 4 .
这里抛光的方法包括机械抛光，热化学抛光，电火花抛光，激光抛光，离子束抛光等。The polishing methods here include mechanical polishing, thermochemical polishing, electric discharge polishing, laser polishing, ion beam polishing, etc.
这里清洗可以用丙酮或其他溶液进行超声波清洗。Ultrasonic cleaning can be done with acetone or other solutions.
由于衬底4的材料与第一结构层1的材料具有不同的晶格常数和热膨胀系数，晶格常数的不同会引起衬底4与第一结构层1之间的晶格失配，导致发生位错缺陷；同时晶格失配也会使得膜层产生应力并引起膜层翘曲和龟裂等问题，以及衬底4的材料与第一结构层1的材料二者热膨胀系数不同，半导体结构30制备过程中，容易引起膜内产生残余应力等原因，具体可通过设置缓冲层5，可消除或减少衬底4和第一结构层1由于晶格常数不同和热膨胀系数不同而引起的膜层位错、翘曲和龟裂等缺陷，有助于提升半导体结构的性能。Since the material of the substrate 4 and the material of the first structural layer 1 have different lattice constants and thermal expansion coefficients, the difference in lattice constants will cause lattice mismatch between the substrate 4 and the first structural layer 1, leading to Dislocation defects; at the same time, lattice mismatch will also cause stress in the film layer and cause problems such as warping and cracking of the film layer, and the material of the substrate 4 and the material of the first structural layer 1 have different thermal expansion coefficients, and the semiconductor structure 30 During the preparation process, it is easy to cause residual stress in the film. Specifically, by setting the buffer layer 5, the film layer stress caused by the different lattice constants and thermal expansion coefficients of the substrate 4 and the first structural layer 1 can be eliminated or reduced. Defects such as dislocations, warps and cracks help improve the performance of semiconductor structures.
请结合图3所示，对于具有衬底4的，还可在衬底4和第一结构层1之间设置缓冲层5。As shown in FIG. 3 , for a device with a substrate 4 , a buffer layer 5 can also be provided between the substrate 4 and the first structural layer 1 .
相应地，在提供衬底4之后，形成第一外延层1之前，所述方法还可包括：Correspondingly, after providing the substrate 4 and before forming the first epitaxial layer 1 , the method may further include:
在所述衬底4之上形成缓冲层5。A buffer layer 5 is formed on the substrate 4 .
在本申请中，所述结构实施例与方法实施例在不冲突的情况下，可以互为补充。In this application, the structural embodiments and method embodiments may complement each other unless they conflict.
本领域技术人员可以理解附图只是一个优选实施例的示意图，附图中的模块或流程并不一定是实施本发明所必须的。以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。Those skilled in the art can understand that the accompanying drawing is only a schematic diagram of a preferred embodiment, and the modules or processes in the accompanying drawing are not necessarily necessary for implementing the present invention. The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the present invention. are covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310801556.XACN116845093A (en) | 2023-06-30 | 2023-06-30 | Semiconductor structure and preparation method thereof, semiconductor device and semiconductor wafer |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310801556.XACN116845093A (en) | 2023-06-30 | 2023-06-30 | Semiconductor structure and preparation method thereof, semiconductor device and semiconductor wafer |
| Publication Number | Publication Date |
|---|---|
| CN116845093Atrue CN116845093A (en) | 2023-10-03 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310801556.XAPendingCN116845093A (en) | 2023-06-30 | 2023-06-30 | Semiconductor structure and preparation method thereof, semiconductor device and semiconductor wafer |
| Country | Link |
|---|---|
| CN (1) | CN116845093A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119855166A (en)* | 2024-12-31 | 2025-04-18 | 武汉大学 | Diamond diode based on polarized interface two-dimensional electron gas effect and preparation method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119855166A (en)* | 2024-12-31 | 2025-04-18 | 武汉大学 | Diamond diode based on polarized interface two-dimensional electron gas effect and preparation method thereof |
| Publication | Publication Date | Title |
|---|---|---|
| US11699748B2 (en) | Normally-off HEMT transistor with selective generation of 2DEG channel, and manufacturing method thereof | |
| TWI767741B (en) | Electronic power devices integrated with an engineered substrate | |
| CN110249432B (en) | Semiconductor devices for power | |
| US7023010B2 (en) | Si/C superlattice useful for semiconductor devices | |
| KR102592686B1 (en) | Method and system for forming doped regions by diffusion in gallium nitride material | |
| US12087855B2 (en) | Vertical UMOSFET device with high channel mobility and preparation method thereof | |
| CN107978642B (en) | GaN-based heterojunction diode and preparation method thereof | |
| CN115708221A (en) | Semiconductor device, manufacturing method thereof, packaging structure and electronic equipment | |
| KR20190133232A (en) | Vertical Gallium Nitride Schottky Diodes | |
| CN112018177B (en) | Full-vertical Si-based GaN UMOSFET power device and preparation method thereof | |
| TW201709512A (en) | Semiconductor cell | |
| TWI726004B (en) | Diamond electronic components | |
| CN112204752B (en) | Semiconductor device and method for manufacturing the same | |
| CN116845093A (en) | Semiconductor structure and preparation method thereof, semiconductor device and semiconductor wafer | |
| CN116884976B (en) | Semiconductor device and method for manufacturing the same, and semiconductor wafer | |
| CN113594044B (en) | Semiconductor device and preparation method thereof | |
| CN210073863U (en) | Enhanced type heterogeneous metal gate AlGaN/GaN MOS-HEMT device | |
| WO2022032588A1 (en) | N-face polarity gan-based device and composite substrate thereof, and manufacturing method for composite substrate | |
| CN106783997A (en) | A kind of high mobility transistor and preparation method thereof | |
| CN117199124A (en) | Epitaxial structure of power device, preparation method of epitaxial structure and power device | |
| TW202406146A (en) | High electron mobility transistor and method for fabricating the same | |
| CN114823923A (en) | Schottky diode based on n-type gallium oxide-p-type diamond and preparation method thereof | |
| US20250031424A1 (en) | Semiconductor device and fabricating method thereof, and semiconductor wafer | |
| CN112219283A (en) | Semiconductor device and method for manufacturing the same | |
| CN115472688B (en) | High electron mobility transistor resistant to single event effect and preparation method thereof |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |