技术领域Technical field
本发明涉及显示技术领域，尤其涉及一种显示面板和显示装置。The present invention relates to the field of display technology, and in particular, to a display panel and a display device.
背景技术Background technique
目前由显示驱动芯片向显示面板提供信号来驱动显示，其内部的模块也容易受到外界杂讯干扰或者受静电影响导致逻辑电路混乱输出异常信号，而显示面板接收异常信号会导致显示异常。At present, the display driver chip provides signals to the display panel to drive the display. The internal modules are also susceptible to external noise interference or static electricity, causing the logic circuit to be confused and output abnormal signals. The display panel receiving abnormal signals will cause display abnormalities.
发明内容Contents of the invention
本发明实施例提供一种显示面板和显示装置，以解决现有技术中显示面板接收异常信号导致显示异常的问题。Embodiments of the present invention provide a display panel and a display device to solve the problem in the prior art that the display panel receives abnormal signals resulting in abnormal display.
第一方面，本发明实施例提供一种显示面板，显示面板包括：In a first aspect, an embodiment of the present invention provides a display panel, which includes:
第一驱动电路和第二驱动电路，第一驱动电路和第二驱动电路分别包括多个级联的移位寄存器；第一驱动电路和第二驱动电路中一者为发光驱动电路、另一者为扫描驱动电路；The first drive circuit and the second drive circuit respectively include a plurality of cascaded shift registers; one of the first drive circuit and the second drive circuit is a light-emitting drive circuit, and the other is a light-emitting drive circuit. For the scan driver circuit;
第一端子和第二端子，第一端子用于传输第一起始信号，第二端子用于传输第二起始信号；第一起始信号为第一驱动电路的驱动信号，第二起始信号为第二驱动电路的驱动信号；The first terminal and the second terminal, the first terminal is used to transmit the first start signal, and the second terminal is used to transmit the second start signal; the first start signal is the drive signal of the first drive circuit, and the second start signal is The driving signal of the second driving circuit;
复位电路，复位电路的第一输入端与第一端子耦接，复位电路的第二输入端与第二端子耦接，复位电路的输出端与第一驱动电路的起始信号接收端耦接；复位电路用于在第一起始信号和第二起始信号的电平配合异常时将第一起始信号进行复位并输出。Reset circuit, the first input end of the reset circuit is coupled to the first terminal, the second input end of the reset circuit is coupled to the second terminal, and the output end of the reset circuit is coupled to the starting signal receiving end of the first driving circuit; The reset circuit is used to reset and output the first start signal when the level matching of the first start signal and the second start signal is abnormal.
第二方面，基于同一发明构思，本发明实施例还提供一种显示装置，包括本发明任意实施例提供的显示面板。In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, including a display panel provided by any embodiment of the present invention.
本发明实施例提供的显示面板和显示装置，具有如下有益效果：显示面板中设置有复位电路，复位电路的两个输入端分别连接第一端子和第二端子、输出端连接第一驱动电路的起始信号接收端，复位电路用于在第一起始信号和第二起始信号的电平配合异常时将第一起始信号进行复位并输出给第一驱动电路的起始信号接收端。利用复位电路对第一起始信号进行复位，能够保证第一驱动电路接收的第一起始信号和第二驱动电路接收的第二起始信号相互匹配，从而对像素电路进行正常驱动，避免显示异常。The display panel and display device provided by the embodiment of the present invention have the following beneficial effects: the display panel is provided with a reset circuit, the two input terminals of the reset circuit are connected to the first terminal and the second terminal respectively, and the output terminal is connected to the first driving circuit. The starting signal receiving end, the reset circuit is used to reset the first starting signal and output it to the starting signal receiving end of the first driving circuit when the levels of the first starting signal and the second starting signal are abnormally matched. Using the reset circuit to reset the first start signal can ensure that the first start signal received by the first drive circuit and the second start signal received by the second drive circuit match each other, thereby driving the pixel circuit normally and avoiding display abnormalities.
附图说明Description of the drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description These are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without exerting any creative effort.
图1为本发明实施例提供的一种显示面板示意图；Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;
图2为本发明实施例提供的一种像素电路示意图；Figure 2 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention;
图3为图2实施例提供的像素电路的时序图；Figure 3 is a timing diagram of the pixel circuit provided by the embodiment of Figure 2;
图4为第一起始信号和第二起始信号匹配的一种示意图；Figure 4 is a schematic diagram of matching between the first start signal and the second start signal;
图5为本发明实施例提供的一种复位电路结构示意图；Figure 5 is a schematic structural diagram of a reset circuit provided by an embodiment of the present invention;
图6为本发明实施例提供的一种复位电路结构示意图；Figure 6 is a schematic structural diagram of a reset circuit provided by an embodiment of the present invention;
图7为本发明实施例提供的另一种显示面板简化示意图；Figure 7 is a simplified schematic diagram of another display panel provided by an embodiment of the present invention;
图8为经滤波电路作用前后第一起始信号的波形示意图；Figure 8 is a schematic diagram of the waveforms of the first starting signal before and after the filter circuit;
图9为本发明实施例提供的一种滤波电路示意图；Figure 9 is a schematic diagram of a filter circuit provided by an embodiment of the present invention;
图10为本发明实施例提供的显示装置示意图。FIG. 10 is a schematic diagram of a display device according to an embodiment of the present invention.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.
在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。The terminology used in the embodiments of the present invention is only for the purpose of describing specific embodiments and is not intended to limit the present invention. As used in this embodiment and the appended claims, the singular forms "a," "the" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.
现有技术中显示驱动芯片的集成度较高，并不能对所有信号都设置抗静电保护元件。另外，由于客户整机要求，柔性电路板的布局空间有限，也没有增加抗静电保护元件的空间。而显示驱动芯片受到静电干扰导致内部电路逻辑混乱输出的发光控制信号或者扫描信号出现异常时，会导致显示异常。In the existing technology, display driver chips have a high degree of integration and cannot be equipped with anti-static protection components for all signals. In addition, due to the customer's complete machine requirements, the layout space of the flexible circuit board is limited, and there is no space to add anti-static protection components. When the display driver chip is disturbed by static electricity, causing the internal circuit logic to be confused, and the output light-emitting control signal or scanning signal is abnormal, it will cause display abnormalities.
为了解决现有技术存在的问题，本发明实施例提供一种显示面板，在显示面板中设置复位电路，复位电路与信号端子耦接，利用复位电路对异常信号进行复位，将异常信号恢复成正常信号后输出给驱动电路，以避免显示面板显示异常。In order to solve the problems existing in the prior art, embodiments of the present invention provide a display panel. A reset circuit is provided in the display panel. The reset circuit is coupled to the signal terminal. The reset circuit is used to reset abnormal signals and restore the abnormal signals to normal. The signal is then output to the driving circuit to avoid abnormal display on the display panel.
图1为本发明实施例提供的一种显示面板示意图，如图1所示，显示面板包括显示区AA和非显示区NA，显示区AA包括多个子像素sp，子像素sp包括发光器件和像素电路，发光器件为有机发光器件或者无机发光器件，非显示区NA设置有第一驱动电路10和第二驱动电路20，第一驱动电路10和第二驱动电路20分别包括多个级联的移位寄存器，移位寄存器可以为现有技术中任意一种。第一驱动电路10中第一级移位寄存器的输入端接收第一起始信号后第一驱动电路10中多级移位寄存器顺次输出使能信号。第二驱动电路20中第一级移位寄存器的输入端接收第二起始信号后第二驱动电路20中多级移位寄存器顺次输出使能信号。第一驱动电路10和第二驱动电路20中一者为发光驱动电路、另一者为扫描驱动电路；像素电路可以为现有技术中任意一种，扫描驱动电路中的移位寄存器为像素电路提供扫描信号，发光驱动电路中的移位寄存器为像素电路提供发光控制信号。Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention. As shown in Figure 1, the display panel includes a display area AA and a non-display area NA. The display area AA includes a plurality of sub-pixels sp. The sub-pixel sp includes a light-emitting device and a pixel. circuit, the light-emitting device is an organic light-emitting device or an inorganic light-emitting device. The non-display area NA is provided with a first driving circuit 10 and a second driving circuit 20. The first driving circuit 10 and the second driving circuit 20 respectively include a plurality of cascaded shifters. The bit register and the shift register can be any of the existing technologies. After the input terminal of the first-stage shift register in the first driving circuit 10 receives the first start signal, the multi-stage shift registers in the first driving circuit 10 sequentially output enable signals. After the input terminal of the first-stage shift register in the second driving circuit 20 receives the second start signal, the multi-stage shift registers in the second driving circuit 20 sequentially output enable signals. One of the first driving circuit 10 and the second driving circuit 20 is a light-emitting driving circuit and the other is a scanning driving circuit; the pixel circuit can be any of the existing technologies, and the shift register in the scanning driving circuit is a pixel circuit Scanning signals are provided, and the shift register in the light-emitting driving circuit provides light-emitting control signals for the pixel circuit.
图1中仅以第一驱动电路10和第二驱动电路20位于显示区AA的同一侧进行示意。在另一些实施方式中，第一驱动电路10和第二驱动电路20分别位于显示区AA的两侧。在另一些实施方式中，显示面板包括两个第一驱动电路10和两个第二驱动电路20，两个第一驱动电路10分别位于显示区AA的两侧，两个第二驱动电路20分别位于显示区AA的两侧。In FIG. 1 , it is only illustrated that the first driving circuit 10 and the second driving circuit 20 are located on the same side of the display area AA. In other embodiments, the first driving circuit 10 and the second driving circuit 20 are respectively located on both sides of the display area AA. In other embodiments, the display panel includes two first driving circuits 10 and two second driving circuits 20 . The two first driving circuits 10 are located on both sides of the display area AA. The two second driving circuits 20 are respectively located on both sides of the display area AA. Located on both sides of display area AA.
本发明实施例中像素电路可以为aTbC结构，a、b为正整数，T表示晶体管，C表示电容。以a＝7、b＝1，即7T1C结构的像素电路为例。图2为本发明实施例提供的一种像素电路示意图，图3为图2实施例提供的像素电路的时序图。如图2所示，像素电路包括驱动晶体管Tm、栅极复位晶体管M1、电极复位晶体管M2、数据写入晶体管M3、阈值补偿晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6、以及存储电容Cst。其中，栅极复位晶体管M1的第一极接收复位信号Ref，栅极复位晶体管M1的第二极耦接驱动晶体管Tm的栅极，栅极复位晶体管M1的栅极接收第一扫描信号S1。数据写入晶体管M3的第一极接收数据信号Vdata，数据写入晶体管M3的第二极耦接驱动晶体管Tm的第一极，阈值补偿晶体管M4串联在驱动晶体管Tm的栅极和第二极之间，数据写入晶体管M3的栅极和阈值补偿晶体管M4的栅极均接收第二扫描信号S2。驱动晶体管Tm串联在第一发光控制晶体管M5和第二发光控制晶体管M6之间，第一发光控制晶体管M5的栅极和第二发光控制晶体管M6的栅极均接收发光控制信号E。另外，存储电容Cst的第一极板和第一发光控制晶体管M5的第一极接收正极电源信号Pvdd，第二发光控制晶体管M6的第二极耦接发光器件PD的第一电极，发光器件PD的第二电极接收负极电源信号Pvee。电极复位晶体管M2的第一极接收复位信号Ref，电极复位晶体管M2的第二极耦接发光器件PD的第一电极，电极复位晶体管M2的栅极接收第一扫描信号S1，或者电极复位晶体管M2的栅极接收第二扫描信号S2。In the embodiment of the present invention, the pixel circuit may have aTbC structure, a and b are positive integers, T represents a transistor, and C represents a capacitor. Take a=7, b=1, that is, a pixel circuit with a 7T1C structure as an example. FIG. 2 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention, and FIG. 3 is a timing diagram of the pixel circuit provided by the embodiment of FIG. 2 . As shown in FIG. 2 , the pixel circuit includes a driving transistor Tm, a gate reset transistor M1, an electrode reset transistor M2, a data writing transistor M3, a threshold compensation transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, and Storage capacitor Cst. The first electrode of the gate reset transistor M1 receives the reset signal Ref, the second electrode of the gate reset transistor M1 is coupled to the gate of the driving transistor Tm, and the gate of the gate reset transistor M1 receives the first scan signal S1. The first pole of the data writing transistor M3 receives the data signal Vdata, the second pole of the data writing transistor M3 is coupled to the first pole of the driving transistor Tm, and the threshold compensation transistor M4 is connected in series between the gate and the second pole of the driving transistor Tm. During this time, both the gate electrode of the data writing transistor M3 and the gate electrode of the threshold compensation transistor M4 receive the second scanning signal S2. The driving transistor Tm is connected in series between the first light-emitting control transistor M5 and the second light-emitting control transistor M6. The gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 both receive the light-emitting control signal E. In addition, the first plate of the storage capacitor Cst and the first electrode of the first light-emitting control transistor M5 receive the positive power supply signal Pvdd, and the second electrode of the second light-emitting control transistor M6 is coupled to the first electrode of the light-emitting device PD. The light-emitting device PD The second electrode receives the negative power signal Pvee. The first electrode of the electrode reset transistor M2 receives the reset signal Ref, the second electrode of the electrode reset transistor M2 is coupled to the first electrode of the light emitting device PD, and the gate electrode of the electrode reset transistor M2 receives the first scan signal S1, or the electrode reset transistor M2 The gate receives the second scan signal S2.
结合图3示意的时序图来理解图2中像素电路的工作原理。像素电路的工作周期包括复位阶段t1、数据写入阶段t2和发光阶段t3。在复位阶段t1对第一节点N1进行复位，在数据写入阶段t2将数据电压写入到第一节点N1，在发光阶段t3驱动晶体管Tm在第一节点N1的电位控制下产生驱动电流并提供给发光器件PD。其中，第一扫描信号S1和第二扫描信号S2由扫描驱动电路的相邻两级移位寄存器提供，发光控制信号E由发光驱动电路提供。Combined with the schematic timing diagram in Figure 3, we can understand the working principle of the pixel circuit in Figure 2. The working cycle of the pixel circuit includes a reset phase t1, a data writing phase t2 and a light emitting phase t3. In the reset phase t1, the first node N1 is reset. In the data writing phase t2, the data voltage is written to the first node N1. In the light-emitting phase t3, the driving transistor Tm generates a driving current under the potential control of the first node N1 and provides to the light-emitting device PD. The first scanning signal S1 and the second scanning signal S2 are provided by adjacent two-stage shift registers of the scanning driving circuit, and the light-emitting control signal E is provided by the light-emitting driving circuit.
如图1所示，显示面板还包括第一端子31、第二端子32和复位电路40，第一端子31、第二端子32和复位电路40位于非显示区NA。第一端子31用于传输第一起始信号，第二端子32用于传输第二起始信号；第一起始信号为第一驱动电路10的驱动信号，第二起始信号为第二驱动电路20的驱动信号。其中，第一起始信号和第二起始信号均由显示驱动芯片提供。显示面板的非显示区NA还包括多个未示出的端子，显示面板上的端子与显示驱动芯片耦接。在一些实施方式中，显示驱动芯片直接绑定在显示面板的非显示区NA，显示驱动芯片将信号输出给端子，通过端子向显示面板中的线路提供信号，以驱动显示面板进行显示。在另一些实施方式中，柔性电路板与显示面板上的端子绑定连接，显示驱动芯片固定在柔性电路板上，显示驱动芯片通过柔性电路板上的线路向端子输出信号。As shown in FIG. 1 , the display panel also includes a first terminal 31 , a second terminal 32 and a reset circuit 40 . The first terminal 31 , the second terminal 32 and the reset circuit 40 are located in the non-display area NA. The first terminal 31 is used to transmit the first start signal, and the second terminal 32 is used to transmit the second start signal; the first start signal is the drive signal of the first drive circuit 10 , and the second start signal is the second drive circuit 20 drive signal. Wherein, the first start signal and the second start signal are both provided by the display driver chip. The non-display area NA of the display panel also includes a plurality of not-shown terminals, and the terminals on the display panel are coupled to the display driver chip. In some embodiments, the display driver chip is directly bound to the non-display area NA of the display panel. The display driver chip outputs signals to terminals and provides signals to circuits in the display panel through the terminals to drive the display panel to display. In other embodiments, the flexible circuit board is bound and connected to the terminals on the display panel, the display driver chip is fixed on the flexible circuit board, and the display driver chip outputs signals to the terminals through lines on the flexible circuit board.
复位电路40的第一输入端与第一端子31耦接，复位电路40的第二输入端与第二端子32耦接，复位电路40的输出端与第一驱动电路10的起始信号接收端耦接；复位电路40用于在第一起始信号和第二起始信号的电平配合异常时将第一起始信号进行复位并输出。第二端子32还与第二驱动电路20的起始信号接收端耦接。第一驱动电路10中第一级移位寄存器的输入端即为起始信号接收端，同样的，第二驱动电路20中第一级移位寄存器的输入端即为起始信号接收端。The first input terminal of the reset circuit 40 is coupled to the first terminal 31 , the second input terminal of the reset circuit 40 is coupled to the second terminal 32 , and the output terminal of the reset circuit 40 is coupled to the start signal receiving terminal of the first driving circuit 10 Coupling; the reset circuit 40 is used to reset and output the first start signal when the levels of the first start signal and the second start signal match abnormally. The second terminal 32 is also coupled to the start signal receiving end of the second driving circuit 20 . The input terminal of the first-stage shift register in the first driving circuit 10 is the start signal receiving terminal. Similarly, the input terminal of the first-stage shift register in the second driving circuit 20 is the starting signal receiving terminal.
第一起始信号和第二起始信号由显示驱动芯片提供，显示驱动芯片经由第一端子31和第二端子32将第一起始信号和第二起始信号提供给显示面板中的电路线路。而显示驱动芯片的内部模块在受到静电影响时会导致逻辑电路混乱输出异常的起始信号，比如当第一起始信号出现异常时，会由于第一起始信号和第二起始信号的电平配合异常而最终导致显示异常。The first start signal and the second start signal are provided by the display driver chip, which provides the first start signal and the second start signal to the circuit lines in the display panel via the first terminal 31 and the second terminal 32 . When the internal module of the display driver chip is affected by static electricity, it will cause the logic circuit to be confused and output an abnormal start signal. For example, when the first start signal is abnormal, the levels of the first start signal and the second start signal will not match. Abnormal and ultimately lead to abnormal display.
本发明实施例提供的显示面板中设置有复位电路40，复位电路40的两个输入端分别连接第一端子31和第二端子32、输出端连接第一驱动电路10的起始信号接收端，复位电路40用于在第一起始信号和第二起始信号的电平配合异常时将第一起始信号进行复位并输出给第一驱动电路10的起始信号接收端。利用复位电路40对第一起始信号进行复位，能够保证第一驱动电路10接收的第一起始信号和第二驱动电路20接收的第二起始信号相互匹配，从而对像素电路进行正常驱动，避免显示异常。The display panel provided by the embodiment of the present invention is provided with a reset circuit 40. The two input terminals of the reset circuit 40 are connected to the first terminal 31 and the second terminal 32 respectively, and the output terminal is connected to the start signal receiving terminal of the first driving circuit 10. The reset circuit 40 is used to reset the first start signal and output it to the start signal receiving end of the first driving circuit 10 when the level matching of the first start signal and the second start signal is abnormal. Using the reset circuit 40 to reset the first start signal can ensure that the first start signal received by the first drive circuit 10 and the second start signal received by the second drive circuit 20 match each other, thereby driving the pixel circuit normally and avoiding the problem of Display Error.
根据上述图3的像素电路工作时序图，可以确定扫描驱动电路和发光驱动电路的起始信号的匹配时序图。以第一起始信号STV1为驱动发光驱动电路的起始信号、第二起始信号STV2为驱动扫描驱动电路的起始信号为例，图4为第一起始信号和第二起始信号匹配的一种示意图。如图4所示，第一起始信号STV1和第二起始信号STV2的配合情况包括：在同一时刻第一起始信号STV1为高电平、第二起始信号STV2为低电平，第一起始信号STV1为高电平、第二起始信号STV2为高电平，第一起始信号STV1为低电平、第二起始信号STV2为高电平，共三种情况。也就是说，在同一时刻第一起始信号STV1为低电平、第二起始信号STV2为低电平时，第一起始信号STV1和第二起始信号STV2的电平配合异常，会导致显示异常。According to the above-mentioned pixel circuit operation timing diagram in FIG. 3, the matching timing diagram of the start signals of the scanning driving circuit and the light-emitting driving circuit can be determined. Taking the first start signal STV1 as the start signal for driving the light-emitting drive circuit and the second start signal STV2 as the start signal for driving the scanning drive circuit as an example, Figure 4 shows a match between the first start signal and the second start signal. A schematic diagram. As shown in Figure 4, the cooperation between the first start signal STV1 and the second start signal STV2 includes: at the same time, the first start signal STV1 is high level, the second start signal STV2 is low level, and the first start signal STV2 is low level. The signal STV1 is high level, the second start signal STV2 is high level, the first start signal STV1 is low level, and the second start signal STV2 is high level, there are three situations in total. That is to say, when the first start signal STV1 is low level and the second start signal STV2 is low level at the same time, the levels of the first start signal STV1 and the second start signal STV2 are abnormally matched, which will lead to abnormal display. .
在一些实施方式中，如图4所示，第一起始信号STV1和第二起始信号STV2分别由高电平信号和低电平信号组成。其中，复位电路40用于在同一时段内第一起始信号STV1和第二起始信号STV2均为低电平信号时、将第一起始信号STV1复位为高电平信号并输出。图4实施例中以第一起始信号STV1为驱动发光驱动电路的起始信号、第二起始信号STV2为驱动扫描驱动电路的起始信号为例，则第一驱动电路10为发光驱动电路、第二驱动电路20为扫描驱动电路，则复位电路40用于对发光驱动电路的起始信号的异常电位进行复位，以保证发光驱动电路的起始信号的电平能够与扫描驱动电路的起始信号的电平正常配合，从而确保对像素电路进行正常驱动，避免显示异常。In some implementations, as shown in FIG. 4 , the first start signal STV1 and the second start signal STV2 are composed of a high-level signal and a low-level signal respectively. The reset circuit 40 is used to reset the first start signal STV1 to a high-level signal and output it when both the first start signal STV1 and the second start signal STV2 are low-level signals in the same period. In the embodiment of FIG. 4 , taking the first start signal STV1 as the start signal for driving the light-emitting driving circuit and the second start signal STV2 as the starting signal for driving the scanning driving circuit as an example, the first driving circuit 10 is a light-emitting driving circuit. The second drive circuit 20 is a scan drive circuit, and the reset circuit 40 is used to reset the abnormal potential of the start signal of the light-emitting drive circuit to ensure that the level of the start signal of the light-emitting drive circuit can be consistent with the start signal of the scan drive circuit. The signal levels must match normally to ensure normal driving of the pixel circuit and avoid display abnormalities.
在另一些实施方式中，第一起始信号STV1为驱动扫描驱动电路的起始信号、第二起始信号STV2为驱动发光驱动电路的起始信号，则第一驱动电路10为扫描驱动电路、第二驱动电路20为发光驱动电路，复位电路40用于对扫描驱动电路的起始信号的异常电位进行复位，以保证扫描驱动电路的起始信号的电平能够与发光驱动电路的起始信号的电平正常配合，从而确保对像素电路进行正常驱动，避免显示异常。In other embodiments, the first start signal STV1 is a start signal for driving the scan driving circuit, and the second start signal STV2 is a start signal for driving the light-emitting driving circuit. Then the first driving circuit 10 is a scanning driving circuit, and the second starting signal STV2 is a starting signal for driving the light-emitting driving circuit. The second drive circuit 20 is a light-emitting drive circuit, and the reset circuit 40 is used to reset the abnormal potential of the start signal of the scan drive circuit to ensure that the level of the start signal of the scan drive circuit can be consistent with the level of the start signal of the light-emitting drive circuit. The levels are properly matched to ensure normal driving of the pixel circuit and avoid display abnormalities.
在一些实施方式中，图5为本发明实施例提供的一种复位电路结构示意图，图5中示意出了复位电路40的第一输入端IN1和第二输入端IN2、以及输出端OUT，第一输入端IN1接收第一起始信号，第二输入端IN2接收第二起始信号。如图5所示，复位电路40包括判定模块41和复位模块42，复位模块42的控制端与判定模块41的输出端耦接。判定模块41用于对接收的第一起始信号和第二起始信号的电平配合情况进行判定，当判定为异常时向复位模块42发送复位控制信号；结合图4示意的第一起始信号STV1和第二起始信号STV2的电平匹配示意图来理解，判定模块41用于在接收的第一起始信号STV1和第二起始信号STV2在同一时段内均为低电平时判定为异常、并向复位模块42发送复位控制信号。复位模块42在复位控制信号的控制下将复位后的第一起始信号STV1提供给复位电路40的输出端OUT。其中，复位模块42将第一起始信号STV1由低电平复位为高电平后提供给复位电路40的输出端OUT。该实施方式中设置有判定模块41和复位模块42，以实现将第一起始信号STV1复位为能够与第二起始信号STV2相匹配的电平信号，以保证第一驱动电路的起始信号的电平能够与第二驱动电路的起始信号的电平正常配合，从而确保对像素电路进行正常驱动，避免显示异常。In some embodiments, FIG. 5 is a schematic structural diagram of a reset circuit provided by an embodiment of the present invention. FIG. 5 illustrates the first input terminal IN1 and the second input terminal IN2 of the reset circuit 40, as well as the output terminal OUT. An input terminal IN1 receives the first start signal, and a second input terminal IN2 receives the second start signal. As shown in FIG. 5 , the reset circuit 40 includes a determination module 41 and a reset module 42 . The control end of the reset module 42 is coupled to the output end of the determination module 41 . The determination module 41 is used to determine the level coordination of the received first start signal and the second start signal, and when it is determined to be abnormal, send a reset control signal to the reset module 42; combined with the first start signal STV1 illustrated in Figure 4 It can be understood from the schematic diagram of level matching with the second start signal STV2 that the determination module 41 is used to determine that it is abnormal when the received first start signal STV1 and the second start signal STV2 are both low level in the same period, and to The reset module 42 sends a reset control signal. The reset module 42 provides the reset first start signal STV1 to the output terminal OUT of the reset circuit 40 under the control of the reset control signal. The reset module 42 resets the first start signal STV1 from low level to high level and then provides it to the output terminal OUT of the reset circuit 40 . In this embodiment, a determination module 41 and a reset module 42 are provided to reset the first start signal STV1 to a level signal that can match the second start signal STV2 to ensure that the start signal of the first driving circuit The level can normally match the level of the start signal of the second driving circuit, thereby ensuring normal driving of the pixel circuit and avoiding display abnormalities.
如图5所示，判定模块41包括或门411，或门411用于在接收的第一起始信号STV1和第二起始信号STV2在同一时段内均为低电平信号时判定为异常、并向复位模块42的控制端输出复位控制信号，复位控制信号为低电平信号。或门411的第一输入端连接复位电路40的第一输入端IN1、接收第一起始信号，或门411的第二输入端连接复位电路40的第二输入端IN2、接收第二起始信号。当或门411的第一输入端和第二输入端中至少一个接收高电平时，其输出端输出高电平；当或门411的所有输入端都接收低电平时，其输出端输出低电平。该实施方式中利用或门411对第一起始信号和第二起始信号的电平配合异常情况进行判定，当第一起始信号和第二起始信号均为低电平时向复位模块42的控制端输出低电平的复位控制信号、以控制复位模块42对第一起始信号进行复位。As shown in Figure 5, the determination module 41 includes an OR gate 411. The OR gate 411 is used to determine that it is abnormal when the received first start signal STV1 and the second start signal STV2 are both low-level signals in the same period. A reset control signal is output to the control terminal of the reset module 42, and the reset control signal is a low level signal. The first input terminal of the OR gate 411 is connected to the first input terminal IN1 of the reset circuit 40 and receives the first start signal. The second input terminal of the OR gate 411 is connected to the second input terminal IN2 of the reset circuit 40 and receives the second start signal. . When at least one of the first input terminal and the second input terminal of the OR gate 411 receives a high level, its output terminal outputs a high level; when all input terminals of the OR gate 411 receive a low level, its output terminal outputs a low level. flat. In this embodiment, the OR gate 411 is used to determine the level matching abnormality of the first start signal and the second start signal. When the first start signal and the second start signal are both low levels, the control of the reset module 42 is reset. The terminal outputs a low-level reset control signal to control the reset module 42 to reset the first start signal.
如图6所示，复位模块42包括反向器421和第一晶体管422；反向器421的输入端与复位电路40的第一输入端耦接，反向器421的输出端与第一晶体管422的第一端耦接；第一晶体管422的控制端与判定模块41的输出端耦接，第一晶体管422的第二端与复位电路40的输出端耦接；反向器421用于将第一起始信号STV1的相位进行反转并提供给第一晶体管422的第一端，第一晶体管422用于在复位控制信号的控制下将其第一端和第二端导通。该实施方式中，复位模块42包括反向器421和第一晶体管422，复位模块42的结构简单。当第一起始信号和第二起始信号均为低电平时，复位模块42的控制端输出低电平的复位控制信号，第一晶体管422为p型晶体管，第一晶体管422在低电平的控制下开启。当第一起始信号为低电平时，反向器421将低电平信号转换成高电平信号，并提供给第一晶体管422的第一端，当第一晶体管422开启后，将高电平的第一起始信号提供给复位电路40的输出端OUT，由此实现复位电路40将低电平的第一起始信号复位成高电平的第一起始信号，以使得第一起始信号和第二起始信号的电平配合正常。As shown in Figure 6, the reset module 42 includes an inverter 421 and a first transistor 422; the input end of the inverter 421 is coupled to the first input end of the reset circuit 40, and the output end of the inverter 421 is coupled to the first transistor. The first end of 422 is coupled; the control end of the first transistor 422 is coupled to the output end of the determination module 41, and the second end of the first transistor 422 is coupled to the output end of the reset circuit 40; the inverter 421 is used to The phase of the first start signal STV1 is reversed and provided to the first terminal of the first transistor 422. The first transistor 422 is used to conduct the first terminal and the second terminal thereof under the control of the reset control signal. In this embodiment, the reset module 42 includes an inverter 421 and a first transistor 422, and the reset module 42 has a simple structure. When the first start signal and the second start signal are both low level, the control terminal of the reset module 42 outputs a low level reset control signal. The first transistor 422 is a p-type transistor. Turn on under control. When the first start signal is low level, the inverter 421 converts the low level signal into a high level signal and provides it to the first terminal of the first transistor 422. When the first transistor 422 is turned on, the inverter 421 converts the low level signal into a high level signal. The first start signal is provided to the output terminal OUT of the reset circuit 40, thereby realizing the reset circuit 40 to reset the low-level first start signal to the high-level first start signal, so that the first start signal and the second The level of the start signal matches normally.
在一些实施方式中，图6为本发明实施例提供的一种复位电路结构示意图，如图6所示，复位电路40还包括非复位模块43，非复位模块43的控制端与判定模块41的输出端耦接；判定模块41还用于对接收的第一起始信号STV1和第二起始信号STV2在同一时段内的电平配合情况进行判定，当判定为正常时向非复位模块43发送非复位控制信号；非复位模块43在非复位控制信号的控制下将接收的第一起始信号STV1直接提供给复位电路40的输出端OUT。结合图4示意的第一起始信号STV1和第二起始信号STV2的电平匹配示意图来理解，判定模块41用于在接收的第一起始信号STV1和第二起始信号STV2在同一时段内均为高电平、或者一者为高电平另一者为低电平时判定为正常，并向非复位模块43发送非复位控制信号。非复位模块43不改变第一起始信号STV1的相位，而是将第一起始信号STV1直接输出。也就是当第一起始信号STV1和第二起始信号STV2的电平匹配正常时，复位电路40可以将接收的第一起始信号STV1直接输出。In some embodiments, Figure 6 is a schematic structural diagram of a reset circuit provided by an embodiment of the present invention. As shown in Figure 6, the reset circuit 40 also includes a non-reset module 43. The control end of the non-reset module 43 and the determination module 41 The output end is coupled; the determination module 41 is also used to determine the level coordination of the received first start signal STV1 and the second start signal STV2 in the same period, and when it is determined to be normal, send a non-reset module 43 to the non-reset module 43. Reset control signal; the non-reset module 43 directly provides the received first start signal STV1 to the output terminal OUT of the reset circuit 40 under the control of the non-reset control signal. It can be understood in conjunction with the level matching diagram of the first start signal STV1 and the second start signal STV2 shown in FIG. 4 that the determination module 41 is used to ensure that the received first start signal STV1 and the second start signal STV2 are evenly matched within the same period. is high level, or one is high level and the other is low level, it is determined to be normal, and a non-reset control signal is sent to the non-reset module 43 . The non-reset module 43 does not change the phase of the first start signal STV1, but directly outputs the first start signal STV1. That is, when the levels of the first start signal STV1 and the second start signal STV2 match normally, the reset circuit 40 can directly output the received first start signal STV1.
如图6所示，判定模块41包括或门411，或门411用于在接收的第一起始信号STV1和第二起始信号STV2在同一时段内均为高电平信号或者一者为高电平信号、另一者为低电平信号时判定为正常，并向非复位模块43的控制端输出非复位控制信号，非复位控制信号为高电平信号。该实施方式中利用或门411对第一起始信号STV1和第二起始信号STV2的电平配合正常情况进行判定，当第一起始信号STV1和第二起始信号STV2电平配合正常时向非复位模块43的控制端输出高电平的非复位控制信号、以利用非复位模块43将第一起始信号STV1直接输出给复位电路40的输出端OUT。As shown in FIG. 6 , the determination module 41 includes an OR gate 411 . The OR gate 411 is used when the received first start signal STV1 and the second start signal STV2 are both high-level signals or one of them is high-level within the same period. When a flat signal and the other is a low-level signal, it is determined to be normal, and a non-reset control signal is output to the control end of the non-reset module 43, and the non-reset control signal is a high-level signal. In this embodiment, the OR gate 411 is used to determine whether the level coordination of the first start signal STV1 and the second start signal STV2 is normal. The control terminal of the reset module 43 outputs a high-level non-reset control signal, so that the non-reset module 43 directly outputs the first start signal STV1 to the output terminal OUT of the reset circuit 40 .
如图6所示，非复位模块43包括第二晶体管431，第二晶体管431的控制端与判定模块41的输出端耦接，第二晶体管431的第一端与复位电路40的第一输入端耦接，第二晶体管431的第二端与复位电路40的输出端耦接；第二晶体管431用于在非复位控制信号的控制下将其第一端和第二端导通。第二晶体管431为n型晶体管。非复位模块43中第二晶体管431仅起到开关的作用，结构简单。当判定模块41判定第一起始信号STV1和第二起始信号STV2电平配合正常时向非复位模块43的控制端输出高电平信号，第二晶体管431在高电平信号的控制下开启，将复位电路40的第一输入端IN1和输出端OUT导通，也就是利用非复位模块43将第一起始信号STV1直接输出给复位电路40的输出端OUT。As shown in FIG. 6 , the non-reset module 43 includes a second transistor 431 . The control end of the second transistor 431 is coupled to the output end of the determination module 41 . The first end of the second transistor 431 is coupled to the first input end of the reset circuit 40 . coupled, the second terminal of the second transistor 431 is coupled with the output terminal of the reset circuit 40; the second transistor 431 is used to conduct its first terminal and the second terminal under the control of the non-reset control signal. The second transistor 431 is an n-type transistor. The second transistor 431 in the non-reset module 43 only functions as a switch and has a simple structure. When the determination module 41 determines that the levels of the first start signal STV1 and the second start signal STV2 are in normal coordination, it outputs a high-level signal to the control terminal of the non-reset module 43, and the second transistor 431 is turned on under the control of the high-level signal. The first input terminal IN1 and the output terminal OUT of the reset circuit 40 are connected, that is, the non-reset module 43 is used to directly output the first start signal STV1 to the output terminal OUT of the reset circuit 40 .
在一些实施方式中，图7为本发明实施例提供的另一种显示面板简化示意图，图7中仅示意出了显示面板中的部分结构以及连接关系。如图7所示，显示面板还包括滤波电路50，滤波电路50连接于第一端子31和复位电路40的第一输入端之间，滤波电路50用于对第一起始信号STV1的幅值进行修正。滤波电路50对正常幅值内的第一起始信号STV1不起作用。本发明实施例中设置有滤波电路50，在复位电路40接收第一起始信号STV1之前，首先对第一起始信号STV1的电压幅值异常情况进行修正，然后再经复位电路40对第一起始信号STV1的电平进行复位，滤波电路50的设置能够使得第一驱动电路10接收的第一起始信号STV1的电压幅值符合要求，以保证第一驱动电路10接收的第一起始信号和第二驱动电路20接收的第二起始信号相互匹配，从而对像素电路进行正常驱动，避免显示异常。In some embodiments, FIG. 7 is a simplified schematic diagram of another display panel provided by an embodiment of the present invention. FIG. 7 only illustrates part of the structure and connection relationships of the display panel. As shown in Figure 7, the display panel also includes a filter circuit 50. The filter circuit 50 is connected between the first terminal 31 and the first input end of the reset circuit 40. The filter circuit 50 is used to adjust the amplitude of the first start signal STV1. Correction. The filter circuit 50 has no effect on the first start signal STV1 within normal amplitude. In the embodiment of the present invention, a filter circuit 50 is provided. Before the reset circuit 40 receives the first start signal STV1, the abnormal voltage amplitude of the first start signal STV1 is first corrected, and then the first start signal is corrected through the reset circuit 40. The level of STV1 is reset, and the setting of the filter circuit 50 can make the voltage amplitude of the first start signal STV1 received by the first drive circuit 10 meet the requirements, so as to ensure that the first start signal and the second drive signal received by the first drive circuit 10 The second start signals received by the circuit 20 match each other, thereby driving the pixel circuit normally and avoiding display abnormalities.
在一种实施例中，以第一起始信号为扫描驱动电路所需的起始信号为例，扫描驱动电路中移位寄存器输出的低电平信号会控制像素电路工作在发光阶段，而如果第一起始信号的高电平信号时段中叠加了低电平的杂波，则有可能使得移位寄存器在本应输出高电平的时刻输出的低电平而导致像素电路中发光控制晶体管(如图2中第一发光控制晶体管M5和第二发光控制晶体管M6)异常开启。In one embodiment, taking the first start signal as the start signal required by the scan drive circuit as an example, the low-level signal output by the shift register in the scan drive circuit will control the pixel circuit to operate in the light-emitting phase, and if the first If low-level noise is superimposed in the high-level signal period of a start signal, it may cause the shift register to output a low level at the moment when it should output a high level, causing the light-emitting control transistor in the pixel circuit (such as In Figure 2, the first light emission control transistor M5 and the second light emission control transistor M6) are turned on abnormally.
图8为经滤波电路作用前后第一起始信号的波形示意图。如图8所示，STV1-1为滤波电路50接收的第一起始信号，STV1-2为经滤波电路50作用后输出的第一起始信号。受静电干扰影响显示驱动芯片提供给第一端子的第一起始信号STV1-1中叠加了正弦波杂波，经过滤波电路50作用后能够将第一起始信号STV1-1的杂波中电压偏低的部分滤掉，由此能够避免扫描驱动电路中移位寄存器输出异常的低电平信号导致发光控制晶体管异常开启。Figure 8 is a schematic diagram of the waveforms of the first starting signal before and after being filtered by the filter circuit. As shown in FIG. 8 , STV1-1 is the first start signal received by the filter circuit 50, and STV1-2 is the first start signal output by the filter circuit 50. Affected by electrostatic interference, the first start signal STV1-1 provided by the display driver chip to the first terminal is superimposed with sine wave clutter. After the action of the filter circuit 50, the voltage in the clutter of the first start signal STV1-1 is lowered. This can prevent the shift register in the scan driving circuit from outputting abnormal low-level signals, causing the light-emitting control transistor to turn on abnormally.
在一些实施方式中，图9为本发明实施例提供的一种滤波电路示意图，如图9所示，滤波电路50包括比较器51、限流电阻52和双向瞬态二极管53；比较器51的第一输入端与第一端子31耦接，比较器51的第二输入端接地，比较器51的输出端耦接限流电阻52的第一端；限流电阻52的第二端和双向瞬态二极管53的第一端耦接复位电路40的第一输入端，双向瞬态二极管53的第二端接地。该实施方式提供的滤波电路50结构简单，容易制作且占用空间较小，滤波电路50能够对第一起始信号STV1的幅值进行修正、并且对正常幅值内的第一起始信号STV1不起作用。In some embodiments, Figure 9 is a schematic diagram of a filter circuit provided by an embodiment of the present invention. As shown in Figure 9, the filter circuit 50 includes a comparator 51, a current limiting resistor 52 and a bidirectional transient diode 53; The first input terminal is coupled to the first terminal 31, the second input terminal of the comparator 51 is grounded, the output terminal of the comparator 51 is coupled to the first terminal of the current limiting resistor 52; the second terminal of the current limiting resistor 52 and the bidirectional instantaneous The first terminal of the bidirectional transient diode 53 is coupled to the first input terminal of the reset circuit 40, and the second terminal of the bidirectional transient diode 53 is grounded. The filter circuit 50 provided by this embodiment has a simple structure, is easy to manufacture and takes up less space. The filter circuit 50 can correct the amplitude of the first start signal STV1 and has no effect on the first start signal STV1 within the normal amplitude. .
基于同一发明构思，本发明实施例还提供一种显示装置，图10为本发明实施例提供的显示装置示意图，如图10所示，显示装置包括本发明任一实施例提供的显示面板100。对于显示面板100的结构在上述实施例中已经说明，在此不再赘述。本发明实施例提供的显示装置例如可以是手机、电脑、平板、电视等电子设备。Based on the same inventive concept, an embodiment of the present invention also provides a display device. FIG. 10 is a schematic diagram of a display device provided by an embodiment of the present invention. As shown in FIG. 10 , the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be described again here. The display device provided by the embodiment of the present invention may be, for example, a mobile phone, a computer, a tablet, a television, and other electronic devices.
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明保护的范围之内。The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that it can still be used Modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310803109.8ACN116844446A (en) | 2023-06-30 | 2023-06-30 | Display panels and display devices |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310803109.8ACN116844446A (en) | 2023-06-30 | 2023-06-30 | Display panels and display devices |
| Publication Number | Publication Date |
|---|---|
| CN116844446Atrue CN116844446A (en) | 2023-10-03 |
| Application Number | Title | Priority Date | Filing Date |
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| CN202310803109.8APendingCN116844446A (en) | 2023-06-30 | 2023-06-30 | Display panels and display devices |
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| CN (1) | CN116844446A (en) |
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| CN114158282A (en)* | 2020-07-08 | 2022-03-08 | 京东方科技集团股份有限公司 | Display substrate, method for manufacturing the same, and display panel |
| CN113178159A (en)* | 2021-04-23 | 2021-07-27 | 京东方科技集团股份有限公司 | Initial signal providing module, method and splicing display device |
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