技术领域Technical field
本发明属于实时性技术领域，涉及一种实时性领域的多优先级硬件定时器。The invention belongs to the field of real-time technology and relates to a multi-priority hardware timer in the field of real-time.
背景技术Background technique
实时系统中通常存在多个具有不同优先级和执行周期的任务。若要保证系统的实时性和可靠性，就必须进行严格的任务调度和控制。在这种情况下，定时器是一个非常重要的工具，它可以定时触发一些行为，如周期性任务和延迟等待等。传统的定时器主要分为软件定时器和硬件定时器。There are usually multiple tasks with different priorities and execution cycles in real-time systems. To ensure the real-time and reliability of the system, strict task scheduling and control must be carried out. In this case, the timer is a very important tool, which can trigger some behaviors at regular intervals, such as periodic tasks and delayed waiting. Traditional timers are mainly divided into software timers and hardware timers.
传统的软件定时器通常是基于软件实现的，其实现方式一般如下：定义一个全局变量timer_counter，表示定时器计数器，用于记录系统启动以来经过的时间，初始值为0。定义一个定时器处理函数timer_isr，用于处理定时器中断。该函数将根据定时器的设定，在定时器到达设定时间时触发中断。定义一个定时器初始化函数timer_init，用于初始化定时器相关的参数。该函数需要设置定时器的计数模式、计数速率、定时时间等参数，以及关联定时器处理函数timer_isr。在系统初始化时，调用定时器初始化函数timer_init进行初始化。在系统运行时，定时器计数器timer_counter将持续不断地累加。当定时器计数器达到设定的定时时间时，定时器中断被触发，执行定时器处理函数timer_isr。在定时器处理函数timer_isr中，根据具体的需求进行相关处理。例如，可以将定时器中断视为一个事件，通知相关的任务进行处理。Traditional software timers are usually implemented based on software. The implementation method is generally as follows: define a global variable timer_counter, which represents a timer counter and is used to record the elapsed time since the system started. The initial value is 0. Define a timer processing function timer_isr to handle timer interrupts. This function will trigger an interrupt when the timer reaches the set time according to the timer setting. Define a timer initialization function timer_init, which is used to initialize timer-related parameters. This function needs to set the counting mode, counting rate, timing time and other parameters of the timer, as well as the associated timer processing function timer_isr. During system initialization, the timer initialization function timer_init is called for initialization. When the system is running, the timer counter timer_counter will continue to accumulate. When the timer counter reaches the set timing time, the timer interrupt is triggered and the timer processing function timer_isr is executed. In the timer processing function timer_isr, relevant processing is performed according to specific needs. For example, a timer interrupt can be regarded as an event that notifies related tasks to process.
传统软件定时器存在以下问题：传统定时器的精度受到系统时钟精度和操作系统调度延迟等因素的影响，无法满足实时系统对高精度计时的需求。通常是使用链表和数组等数据结构来管理定时器，这种方式需要遍历所有定时器来查找和处理，效率较低。通常是用户态的，如果定时器处理函数有问题，可能会导致系统崩溃或出现安全漏洞。通常只支持固定的触发方式和计时模式，无法灵活地扩展和定制。通常只能支持单一优先级，无法区分不同任务的定时器的优先级，因而会造成以下问题：低优先级任务的定时器中断会对高优先级任务的执行造成干扰，影响高优先级任务的响应时间。优先级反转，低优先级先于高优先级响应，在调度层面看相当于低优先级任务抢占了高优先级任务，影响调度性能以及实时性。Traditional software timers have the following problems: The accuracy of traditional timers is affected by factors such as system clock accuracy and operating system scheduling delays, and cannot meet the needs of real-time systems for high-precision timing. Usually, data structures such as linked lists and arrays are used to manage timers. This method requires traversing all timers to find and process them, which is inefficient. Usually in user mode, if there is a problem with the timer processing function, it may cause a system crash or security vulnerability. Usually only supports fixed triggering methods and timing modes, and cannot be flexibly expanded and customized. Usually only a single priority level can be supported, and the priorities of timers of different tasks cannot be distinguished, which will cause the following problems: timer interrupts of low-priority tasks will interfere with the execution of high-priority tasks, affecting the execution of high-priority tasks. Response time. Priority inversion, low priority responds before high priority, which is equivalent to low priority tasks preempting high priority tasks at the scheduling level, affecting scheduling performance and real-time performance.
传统的硬件定时器通常由一个或多个计数器、一个或多个比较器和一个或多个中断控制器组成，其实现方式如下：定义一个或多个计数器寄存器，用于计数。计数器通常是一个定长的二进制计数器，当计数器溢出时，将产生一个中断。定义一个或多个比较器寄存器，用于设定定时器的触发时间。当计数器的值等于比较器的值时，将产生一个中断。定义一个中断控制器，用于控制定时器中断的触发和处理。中断控制器可以接收来自计数器和比较器的中断信号，并将中断信号转发给处理器。在系统初始化时，配置定时器的计数模式、计数速率、比较器的设定值等参数。在系统运行时，定时器的计数器将持续不断地累加，当计数器的值等于比较器的设定值时，定时器中断将被触发。在定时器中断处理函数中，根据具体的需求进行相关处理。例如，可以将定时器中断视为一个事件，通知相关的任务进行处理。A traditional hardware timer usually consists of one or more counters, one or more comparators and one or more interrupt controllers. Its implementation is as follows: Define one or more counter registers for counting. The counter is usually a fixed-length binary counter. When the counter overflows, an interrupt will be generated. Define one or more comparator registers to set the trigger time of the timer. When the counter value equals the comparator value, an interrupt is generated. Define an interrupt controller to control the triggering and processing of timer interrupts. The interrupt controller can receive interrupt signals from counters and comparators and forward the interrupt signals to the processor. During system initialization, configure the timer's counting mode, counting rate, comparator setting value and other parameters. When the system is running, the timer counter will continue to accumulate. When the counter value is equal to the set value of the comparator, the timer interrupt will be triggered. In the timer interrupt processing function, perform relevant processing according to specific needs. For example, a timer interrupt can be regarded as an event that notifies related tasks to process.
传统硬件定时器存在以下问题：传统的硬件定时器通常只能支持单一优先级，无法进行多优先级调度和管理，也无法区分不同任务的定时器。这使得它难以用于复杂的多任务处理系统。传统的硬件定时器通常需要在初始化时设定定时器的触发时间，一旦设定，就无法在运行时动态调整。这使得它难以应对动态的系统需求。Traditional hardware timers have the following problems: Traditional hardware timers can usually only support a single priority, cannot perform multi-priority scheduling and management, and cannot distinguish timers for different tasks. This makes it difficult to use in complex multitasking systems. Traditional hardware timers usually need to set the trigger time of the timer during initialization. Once set, it cannot be dynamically adjusted at runtime. This makes it difficult to cope with dynamic system requirements.
发明内容Contents of the invention
为解决上述技术问题，本发明的目的是提供一种实时性领域的多优先级硬件定时器，能够支持多任务和多优先级，能够区分不同任务，支持多种计时模式和触发方式，能够满足不同实时任务的需求。In order to solve the above technical problems, the purpose of the present invention is to provide a multi-priority hardware timer in the real-time field, which can support multiple tasks and multiple priorities, can distinguish different tasks, support multiple timing modes and triggering methods, and can meet the needs of requirements of different real-time tasks.
本发明提供一种实时性领域的多优先级硬件定时器，包括相互连接的定时器单元和优先级控制单元；The invention provides a multi-priority hardware timer in the real-time field, including a timer unit and a priority control unit connected to each other;
所述定时器单元包括：计时模块以及与所述计时模块连接的多个比对寄存器；计时模块和每个比对寄存器构成一个硬件定时器，计时模块在被优先级控制单元使能后以特定的频率进行计数，当计时模块中的值大于或等于比对寄存器的值时，相应的比对寄存器便会产生定时中断信号；The timer unit includes: a timing module and a plurality of comparison registers connected to the timing module; the timing module and each comparison register constitute a hardware timer, and the timing module is configured in a specific manner after being enabled by the priority control unit. The frequency is counted. When the value in the timing module is greater than or equal to the value of the comparison register, the corresponding comparison register will generate a timing interrupt signal;
所述优先级控制单元包括：中断仲裁模块、低优先级屏蔽寄存器、计时使能寄存器、定时器ID寄存器和多个优先级配置寄存器；所述低优先级屏蔽寄存器分别与多个比对寄存器、多个优先级配置寄存器以及中断仲裁模块连接；The priority control unit includes: an interrupt arbitration module, a low-priority mask register, a timing enable register, a timer ID register, and multiple priority configuration registers; the low-priority mask register is connected to multiple comparison registers, Multiple priority configuration registers and interrupt arbitration module connections;
所述计时器使能寄存器用于对计时模块进行使能；所述优先级配置寄存器用于根据处理器的指令对相应的比对寄存器进行优先级的配置；所述低优先级屏蔽寄存器用于对低优先级的硬件定时器的中断信号进行屏蔽；所述中断仲裁模块用于对硬件定时器的中断信号进行仲裁，经过中断仲裁后将定时器ID寄存器内容更新为优先级最高的硬件定时器的ID号，并将该硬件定时器的中断信号转发给处理器。The timer enable register is used to enable the timing module; the priority configuration register is used to configure the priority of the corresponding comparison register according to the instructions of the processor; the low priority mask register is used to Mask the interrupt signal of the low-priority hardware timer; the interrupt arbitration module is used to arbitrate the interrupt signal of the hardware timer, and after the interrupt arbitration, the content of the timer ID register is updated to the hardware timer with the highest priority ID number, and forwards the interrupt signal of the hardware timer to the processor.
进一步的，当在执行高优先级任务时，处理器将低优先级屏蔽寄存器更新为该高优先级任务的优先级，所有低于该优先级的定时中断信号都将被屏蔽。Further, when executing a high-priority task, the processor updates the low-priority mask register to the priority of the high-priority task, and all scheduled interrupt signals lower than the priority will be masked.
进一步的，处理器为低优先级屏蔽寄存器、计时使能寄存器、定时器ID寄存器、优先级配置寄存器以及比对寄存器分配相应的访问地址；其中优先级配置寄存器和比对寄存器按顺序进行编址，硬件定时器的ID号从0开始进行分配；Further, the processor allocates corresponding access addresses to the low-priority mask register, timing enable register, timer ID register, priority configuration register and comparison register; the priority configuration register and comparison register are addressed in order , the ID number of the hardware timer is allocated starting from 0;
所述处理器通过内存映射输入输出的方式根据分配的访问地址对多优先级硬件定时器的所有寄存器进行读写。The processor reads and writes all registers of the multi-priority hardware timer according to the allocated access address through memory mapping input and output.
进一步的，处理器通过写入与硬件定时器对应的优先级配置寄存器来将该硬件定时器配置为不同的优先级，并且在运行时动态调整硬件定时器的优先级；优先级配置寄存器的最高位用于记录所对应的硬件定时器当前是否空闲，其余位用于记录对应的硬件定时器的优先级；如果硬件定时器空闲，那么该硬件定时器产生的中断信号也会被低优先级屏蔽寄存器屏蔽。Further, the processor configures the hardware timer to different priorities by writing to the priority configuration register corresponding to the hardware timer, and dynamically adjusts the priority of the hardware timer during runtime; the highest priority configuration register Bits are used to record whether the corresponding hardware timer is currently idle, and the remaining bits are used to record the priority of the corresponding hardware timer; if the hardware timer is idle, the interrupt signal generated by the hardware timer will also be masked by the low priority. Register mask.
进一步的，定时器ID寄存器中存储的硬件定时器的ID号会被处理器读取，用于判定该硬件定时器的定时中断属于哪个任务。Further, the ID number of the hardware timer stored in the timer ID register will be read by the processor to determine which task the scheduled interrupt of the hardware timer belongs to.
进一步的，当某个任务需要申请一个硬件定时器时，首先按照ID号的顺序读取第一个硬件定时器所对应的优先级配置寄存器的值，并根据该优先级配置寄存器的值的最高位是否为0来判断所对应的硬件定时器是否空闲；如果空闲，则分配成功，修改该优先级配置寄存器的最高位为1，同时将该硬件定时器的优先级一同写入优先级配置寄存器；如果不空闲，则访问下一个硬件定时器所对应的优先级配置寄存器再次进行判断。Furthermore, when a task needs to apply for a hardware timer, it first reads the value of the priority configuration register corresponding to the first hardware timer in the order of the ID number, and based on the highest value of the priority configuration register Whether the bit is 0 to determine whether the corresponding hardware timer is idle; if it is idle, the allocation is successful, modify the highest bit of the priority configuration register to 1, and write the priority of the hardware timer into the priority configuration register. ; If it is not idle, access the priority configuration register corresponding to the next hardware timer and make another judgment.
进一步的，所述计时模块和每个比对寄存器通过内存映射输入输出的方式进行读写。Further, the timing module and each comparison register are read and written through memory mapping input and output.
本发明的一种实时性领域的多优先级硬件定时器，至少具有以下A multi-priority hardware timer in the real-time field of the present invention has at least the following features:
有益效果：Beneficial effects:
1.与软件定时器相比，本发明的多优先级硬件定时器具有高精度的特点，可以根据需求，对定时器的计时精度进行配置，上限仅受处理器的时序及硬件晶振的最高频率的限制。1. Compared with software timers, the multi-priority hardware timer of the present invention has the characteristics of high accuracy. The timing accuracy of the timer can be configured according to needs. The upper limit is only affected by the timing of the processor and the highest frequency of the hardware crystal oscillator. limits.
2.无需对定时器进行查找和处理。定时器将直接由硬件进行管理，大大提高了定时器的处理效率。2. There is no need to search and process the timer. The timer will be managed directly by the hardware, which greatly improves the processing efficiency of the timer.
3.支持多任务和多优先级，可以区分定时器单元中不同任务的硬件定时器，也可以根据任务的不同需求进行优先级的配置，更加灵活适应各种任务的要求。同时将硬件定时器按照优先级进行分类和管理，不同优先级的硬件定时器可以独立触发，并且中断仲裁模块可以通过判断优先级来决定是否响应对应的硬件定时器中断，进而决定是否执行调度算法进行调度和处理。避免了低优先级任务对高优先级任务的干扰，也避免了可能出现的系统响应缓慢甚至出现死锁等问题，大大提高了系统的实时性和可靠性。3. Supports multi-tasking and multi-priority. The hardware timers of different tasks in the timer unit can be distinguished, and the priority can also be configured according to the different needs of the tasks, making it more flexible to adapt to the requirements of various tasks. At the same time, hardware timers are classified and managed according to priority. Hardware timers of different priorities can be triggered independently, and the interrupt arbitration module can decide whether to respond to the corresponding hardware timer interrupt by judging the priority, and then decide whether to execute the scheduling algorithm. for scheduling and processing. It avoids the interference of low-priority tasks on high-priority tasks and avoids possible problems such as slow system response or even deadlock, which greatly improves the real-time and reliability of the system.
4.软件层面的处理函数，是在操作系统的内核上实现的，既提高了定时器的处理效率，也保证了系统的安全性。4. The processing functions at the software level are implemented on the kernel of the operating system, which not only improves the processing efficiency of the timer, but also ensures the security of the system.
5.具有灵活的配置和扩展方式，硬件方面通过类似加速器的实现方式，具有灵活且可扩展的特性，用户可以根据自己的需求进行定制化的配置和调整，甚至增加新的功能；软件方面则更为灵活，用户既可以对该定时器直接进行使用，也可以基于这些定时器，进行封装，设计新的定时器库，充分发挥该定时器的特性。5. It has flexible configuration and expansion methods. In terms of hardware, it has flexible and scalable features through an accelerator-like implementation. Users can customize configurations and adjustments according to their own needs, and even add new functions; in terms of software, It is more flexible. Users can either use the timer directly, or encapsulate and design a new timer library based on these timers to give full play to the characteristics of the timer.
6.可动态对定时器的时间以及优先级进行调整，避免了传统的硬件定时器在这方面存在的问题。6. The time and priority of the timer can be dynamically adjusted, avoiding the problems of traditional hardware timers in this regard.
7.计时使能寄存器的设计，使得实际进行多任务配置和执行时更加符合理论研究时的假设条件，即从时间轴上来看，真正做到了多个任务同时释放执行。7. The design of the timing enable register makes the actual multi-task configuration and execution more consistent with the assumptions in theoretical research, that is, from a timeline perspective, multiple tasks can be released for execution at the same time.
8.软件定时器需要占用CPU资源来进行计时操作，而本发明的多优先级硬件定时器由硬件控制，不需要占用CPU资源，可以让CPU专注于其他任务的执行。8. Software timers need to occupy CPU resources to perform timing operations, but the multi-priority hardware timer of the present invention is controlled by hardware and does not need to occupy CPU resources, allowing the CPU to focus on the execution of other tasks.
9.本发明的多优先级硬件定时器由硬件控制，不受软件的影响，可以实现更高的实时性，能够更精确地执行计时任务。9. The multi-priority hardware timer of the present invention is controlled by hardware and is not affected by software. It can achieve higher real-time performance and can perform timing tasks more accurately.
10.本发明的多优先级硬件定时器可以更好地利用系统资源，将高优先级任务与低优先级任务进行有效区分，减少了低优先级任务对高优先级任务的干扰，提高了高优先级任务的响应速度。10. The multi-priority hardware timer of the present invention can make better use of system resources, effectively distinguish high-priority tasks from low-priority tasks, reduce the interference of low-priority tasks on high-priority tasks, and improve high-priority tasks. Response speed of priority tasks.
附图说明Description of the drawings
图1是本发明的一种实时性领域的多优先级硬件定时器的结构框图；Figure 1 is a structural block diagram of a multi-priority hardware timer in the real-time field of the present invention;
图2是本发明的优先级控制单元的结构框图。Figure 2 is a structural block diagram of the priority control unit of the present invention.
具体实施方式Detailed ways
如图1和2所示，本发明的一种实时性领域的多优先级硬件定时器，包括相互连接的定时器单元和优先级控制单元。所述定时器单元包括：计时模块以及与所述计时模块连接的多个比对寄存器；计时模块和每个比对寄存器构成一个硬件定时器，计时模块在被优先级控制单元使能后以特定的频率进行计数，当计时模块中的值大于或等于比对寄存器的值时，相应的比对寄存器便会产生定时中断信号。As shown in Figures 1 and 2, a multi-priority hardware timer in the real-time field of the present invention includes an interconnected timer unit and a priority control unit. The timer unit includes: a timing module and a plurality of comparison registers connected to the timing module; the timing module and each comparison register constitute a hardware timer, and the timing module is configured in a specific manner after being enabled by the priority control unit. The frequency is counted. When the value in the timing module is greater than or equal to the value of the comparison register, the corresponding comparison register will generate a timing interrupt signal.
所述优先级控制单元包括：中断仲裁模块、低优先级屏蔽寄存器、计时使能寄存器、定时器ID寄存器和多个优先级配置寄存器；所述低优先级屏蔽寄存器分别与多个比对寄存器、多个优先级配置寄存器以及中断仲裁模块连接。所述计时器使能寄存器用于对计时模块进行使能；所述优先级配置寄存器用于根据处理器的指令对相应的比对寄存器进行优先级的配置；所述低优先级屏蔽寄存器用于对低优先级的硬件定时器的中断信号进行屏蔽；所述中断仲裁模块用于对硬件定时器的中断信号进行仲裁，经过中断仲裁后将定时器ID寄存器内容更新为优先级最高的硬件定时器的ID号，并将该硬件定时器的中断信号转发给处理器。The priority control unit includes: an interrupt arbitration module, a low-priority mask register, a timing enable register, a timer ID register, and multiple priority configuration registers; the low-priority mask register is connected to multiple comparison registers, Multiple priority configuration registers and interrupt arbitration module connections. The timer enable register is used to enable the timing module; the priority configuration register is used to configure the priority of the corresponding comparison register according to the instructions of the processor; the low priority mask register is used to Mask the interrupt signal of the low-priority hardware timer; the interrupt arbitration module is used to arbitrate the interrupt signal of the hardware timer, and after the interrupt arbitration, the content of the timer ID register is updated to the hardware timer with the highest priority ID number, and forwards the interrupt signal of the hardware timer to the processor.
具体实施时，所述计时模块和每个比对寄存器通过内存映射输入输出的方式进行读写。During specific implementation, the timing module and each comparison register are read and written through memory mapping input and output.
具体实施时，当在执行高优先级任务时，处理器将低优先级屏蔽寄存器更新为该高优先级任务的优先级，所有低于该优先级的定时中断信号都将被屏蔽。During specific implementation, when executing a high-priority task, the processor updates the low-priority mask register to the priority of the high-priority task, and all scheduled interrupt signals lower than this priority will be masked.
具体实施时，处理器为低优先级屏蔽寄存器、计时使能寄存器、定时器ID寄存器、优先级配置寄存器以及比对寄存器分配相应的访问地址；其中优先级配置寄存器和比对寄存器按顺序进行编址，硬件定时器的ID号从0开始进行分配；所述处理器通过内存映射输入输出的方式根据分配的访问地址对多优先级硬件定时器的所有寄存器进行读写。During specific implementation, the processor allocates corresponding access addresses to the low-priority mask register, timing enable register, timer ID register, priority configuration register and comparison register; the priority configuration register and comparison register are programmed in order. Address, the ID number of the hardware timer is allocated starting from 0; the processor reads and writes all registers of the multi-priority hardware timer according to the allocated access address through memory mapping input and output.
具体实施时，处理器通过写入与硬件定时器对应的优先级配置寄存器来将该硬件定时器配置为不同的优先级，并且在运行时动态调整硬件定时器的优先级；优先级配置寄存器的最高位用于记录所对应的硬件定时器当前是否空闲，其余位用于记录对应的硬件定时器的优先级；如果硬件定时器空闲，那么该硬件定时器产生的中断信号也会被低优先级屏蔽寄存器屏蔽。During specific implementation, the processor configures the hardware timer to different priorities by writing to the priority configuration register corresponding to the hardware timer, and dynamically adjusts the priority of the hardware timer during runtime; the priority configuration register The highest bit is used to record whether the corresponding hardware timer is currently idle, and the remaining bits are used to record the priority of the corresponding hardware timer; if the hardware timer is idle, the interrupt signal generated by the hardware timer will also be assigned a low priority. Mask register mask.
具体实施时，定时器ID寄存器中存储的硬件定时器的ID号会被处理器读取，用于判定该硬件定时器的定时中断属于哪个任务。During specific implementation, the ID number of the hardware timer stored in the timer ID register will be read by the processor to determine which task the scheduled interrupt of the hardware timer belongs to.
实施例Example
当某个任务需要申请一个硬件定时器时，首先按照ID号的顺序读取第一个硬件定时器所对应的优先级配置寄存器的值，并根据该优先级配置寄存器的值的最高位是否为0来判断所对应的硬件定时器是否空闲；如果空闲，则分配成功，修改该优先级配置寄存器的最高位为1，同时将该硬件定时器的优先级一同写入优先级配置寄存器；如果不空闲，则访问下一个硬件定时器所对应的优先级配置寄存器再次进行判断。When a task needs to apply for a hardware timer, it first reads the value of the priority configuration register corresponding to the first hardware timer in the order of ID number, and based on whether the highest bit of the value of the priority configuration register is 0 to determine whether the corresponding hardware timer is idle; if it is idle, the allocation is successful, modify the highest bit of the priority configuration register to 1, and write the priority of the hardware timer into the priority configuration register; if not If it is idle, access the priority configuration register corresponding to the next hardware timer to make another judgment.
任务申请到一个定时器后，可以通过读取当前计时模块中的计数值，根据自己的定时需求，计算并配置相应的比对寄存器。例如：计时模块的计数频率为a(Hz)，当前计时器模块的计数值为x，而该任务需要计时b(s)，那么将x+a×b的值写入相应的比对寄存器即可。After a task applies for a timer, it can calculate and configure the corresponding comparison register according to its own timing requirements by reading the count value in the current timing module. For example: the counting frequency of the timing module is a (Hz), the current counting value of the timer module is x, and the task needs to time b (s), then write the value of x+a×b to the corresponding comparison register, that is Can.
当同一时间段内定时器单元产生多个中断信号时，低优先级屏蔽寄存器首先将优先级低于其优先级的硬件定时器发出的中断信号屏蔽掉，其余的中断信号进入优先级控制单元进行仲裁，选出优先级最高的中断信号发送给处理器，并将定时器ID寄存器内容更新为优先级最高的硬件定时器的ID号。处理器读取定时器ID寄存器中存储的ID号，判定该硬件定时器的定时中断属于哪个任务，并执行该任务。When the timer unit generates multiple interrupt signals in the same time period, the low-priority mask register first masks the interrupt signals sent by the hardware timer with a priority lower than its priority, and the remaining interrupt signals enter the priority control unit for processing. Arbitrate, select the interrupt signal with the highest priority and send it to the processor, and update the content of the timer ID register to the ID number of the hardware timer with the highest priority. The processor reads the ID number stored in the timer ID register, determines which task the hardware timer's scheduled interrupt belongs to, and executes the task.
具体实施时，任务如果要注销一个定时器的话，只需要将对应的优先级配置寄存器的最高位配置为0。During specific implementation, if a task wants to cancel a timer, it only needs to configure the highest bit of the corresponding priority configuration register to 0.
具体实施时，在任务执行开始时，可以将低优先级屏蔽寄存器配置为该任务的优先级，来将所有低优先级的定时器中断进行屏蔽，这样既避免了低优先级的定时器中断对当前任务的干扰，也避免了出现优先级反转的情况。During specific implementation, at the beginning of task execution, the low-priority mask register can be configured with the priority of the task to mask all low-priority timer interrupts, thus avoiding the need for low-priority timer interrupts to Interference from current tasks also avoids priority reversal.
具体实施时，若运行过程中需要对任务的优先级进行调整，那么可以对所分配的硬件定时器的优先级配置寄存器进行修改。During specific implementation, if the priority of the task needs to be adjusted during operation, the priority configuration register of the assigned hardware timer can be modified.
具体实施时，若运行过程中需要对定时器时间进行调整，那么可以对所分配的硬件定时器的比对寄存器进行修改。During specific implementation, if the timer time needs to be adjusted during operation, the comparison register of the allocated hardware timer can be modified.
具体实施时，一些理论研究工作存在多个周期性任务同时释放执行的需求，但实际上的硬件定时器是一直在进行计时的，这便会导致各个任务释放执行的时间并不是相同的，但通过计时使能寄存器，可以做到所有任务创建完成后再开启计时，那么便能满足多个任务同时释放执行的需求，为相关理论研究消除了多个任务同时释放执行时存在的误差。并且计时使能寄存器的设计使用户对定时器的运用变得更为灵活。During specific implementation, some theoretical research work requires multiple periodic tasks to be released and executed at the same time. However, in fact, the hardware timer is always timing, which will cause the release and execution time of each task to be different. However, Through the timing enable register, timing can be turned on after all tasks are created, so that the need for multiple tasks to be released for execution at the same time can be met, and errors that exist when multiple tasks are released for execution at the same time can be eliminated for related theoretical research. And the design of the timing enable register makes the user's use of the timer more flexible.
本发明的一种实时性领域的多优先级硬件定时器主要由定时器单元和优先级控制单元构成，定时器单元用来进行定时，优先级控制单元用来实现定时器单元中计时模块的使能、优先级的配置、硬件定时器的分配以及低优先级硬件定时器的中断信号的屏蔽等功能。A multi-priority hardware timer in the real-time field of the present invention is mainly composed of a timer unit and a priority control unit. The timer unit is used for timing, and the priority control unit is used to realize the use of the timing module in the timer unit. Functions such as function, priority configuration, hardware timer allocation, and low-priority hardware timer interrupt signal shielding.
本发明的一种实时性领域的多优先级硬件定时器中的寄存器可通过内存映射输入输出(Memory-mapped I/O，MMIO)的方式进行读写，也可以通过自定义指令的方式进行控制。The registers in the multi-priority hardware timer in the real-time field of the present invention can be read and written through memory-mapped input and output (Memory-mapped I/O, MMIO), and can also be controlled through custom instructions. .
本发明的计时使能寄存器的设计，可以使用户对定时器的运用变得更为灵活，且能满足一些研究工作的需求。The design of the timing enable register of the present invention can make the user's use of the timer more flexible and can meet the needs of some research work.
本发明的低优先级屏蔽寄存器的设计，可以实现对低优先级硬件定时器的中断信号的屏蔽，这样既避免了低优先级的硬件定时器的中断信号对当前任务的干扰，也避免了出现优先级反转的情况。The design of the low-priority shield register of the present invention can realize the shielding of the interrupt signal of the low-priority hardware timer, which not only avoids the interference of the interrupt signal of the low-priority hardware timer on the current task, but also avoids the occurrence of Priority inversion case.
本发明的优先级配置寄存器的设计，可以用来对硬件定时器的优先级进行配置，同时优先级配置寄存器的最高位作为硬件定时器的空闲标志位，可以将空闲标志修改操作与优先级分配操作合并为一个操作进行执行。The design of the priority configuration register of the present invention can be used to configure the priority of the hardware timer. At the same time, the highest bit of the priority configuration register is used as the idle flag bit of the hardware timer, and the idle flag modification operation and priority allocation can be Operations are combined into one operation for execution.
本发明的定时器ID寄存器的设计，实现了对不同硬件定时器的中断的区分，中断处理程序通过读取该寄存器，便可得知该硬件定时器的中断属于哪个任务。这种设计既降低了硬件接口的复杂度，也使得整个中断处理流程更加简洁直观。The design of the timer ID register of the present invention realizes the distinction between interrupts of different hardware timers. By reading this register, the interrupt handler can know which task the interrupt of the hardware timer belongs to. This design not only reduces the complexity of the hardware interface, but also makes the entire interrupt processing process more concise and intuitive.
本发明的多优先级硬件定时器每次产生的操作都会基于当前各寄存器的配置进行。得益这种实现逻辑，定时器的优先级和时间均可在运行时进行动态调整。Each operation generated by the multi-priority hardware timer of the present invention will be performed based on the current configuration of each register. Thanks to this implementation logic, the timer's priority and time can be dynamically adjusted at runtime.
以上所述仅为本发明的较佳实施例，并不用以限制本发明的思想，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above are only preferred embodiments of the present invention and are not intended to limit the idea of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.
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| CN202310798367.1ACN116841617A (en) | 2023-07-03 | 2023-07-03 | A multi-priority hardware timer in real-time field |
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