Detailed Description
Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
The term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean that a exists alone, while a and B exist together, and B exists alone. The term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, e.g., including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C. The terms "first" and "second" herein mean a plurality of similar technical terms and distinguishes them, and does not limit the meaning of the order, or only two, for example, a first feature and a second feature, which means that there are two types/classes of features, the first feature may be one or more, and the second feature may be one or more.
In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be appreciated by one skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
As a logic necessity of breaking through classical physical limits as chip size, quantum computing has gained great attention as a marker technology in the latter molar age. Today quantum computing is very fast in development, either from the application level, the algorithm level, or the hardware level. Notably, the implementation of quantum algorithms and applications is highly dependent on the development and advancement of quantum hardware. On quantum hardware implementation, quantum computing has various technical schemes, such as superconducting quantum circuits, ion traps, optical quantum systems, and the like. Superconducting quantum circuits are considered to be one of the most promising technological routes at present, benefiting from good scalability and mature semiconductor manufacturing processes. In recent years, with development of superconducting quantum computing technology schemes and micro-nano processing technologies, the number of quantum bits integrated on a superconducting quantum chip is increased, and the chip structure is also enriched and comprehensive.
In practical applications, there are many factors for measuring performance of a quantum chip (such as a superconducting quantum chip), and connectivity is one of the key indexes. Here, connectivity refers to the degree of connectivity between one qubit and the remaining other qubits in a quantum chip (such as a superconducting quantum chip). Taking a superconducting quantum chip as an example, unlike ion trap quantum computation, superconducting qubits can only be coupled with adjacent superconducting qubits in a superconducting quantum circuit. With this limitation, two superconducting qubit gates are also limited to implementations between adjacent superconducting qubits. However, in practice, coupling between non-adjacent superconducting qubits is required in order to achieve quantum gate operation between any two superconducting qubits. Based on this, mapping an algorithm-level quantum circuit (i.e., a logic quantum circuit) to a physical-level quantum circuit satisfying physical limitations of a superconducting quantum chip becomes an important subject. Although this mapping solves the problem to some extent, it comes at the cost of requiring the additional introduction of a large number of two-bit quantum gates (e.g., two superconducting quantum bit gates), undoubtedly greatly reducing the efficiency and accuracy of the computation.
Therefore, finding a configuration of a qubit with high connectivity and further obtaining a quantum chip with high connectivity becomes a very important subject.
Based on this, the present disclosure proposes a specific configuration of a quantum chip to achieve strong communication between qubits.
Fig. 1 is a schematic structural diagram of a qubit in a quantum chip according to an embodiment of the present disclosure, and as shown in fig. 1, the quantum chip includes:
At least one qubit;
Further, the configuration of the qubit includes:
A first metal plate 111 located in a first plane, wherein the first metal plate is V-shaped;
the second metal polar plate 112 is positioned on the first plane, wherein the second metal polar plate is in a three-fork shape;
A connection assembly 113 between the first metal plate and the second metal plate for coupling the first metal plate and the second metal plate.
It should be noted here that the first metal plate and the second metal plate are two metal plates in the same plane, not an integrated structure, thus providing configuration support for forming floating qubits.
Further, it is noted that the first metal plate is asymmetric to the second metal plate, in other words, the configuration of the qubit is an asymmetric structure.
As such, the disclosed approach presents significant advantages in connectivity over designs common to the industry. Moreover, the quantum chip has good expansibility and high integration level, and the advantages of the quantum chip in the scheme of the disclosure can be further highlighted especially when the number of the quantum bits is expanded in a large scale. Furthermore, the configuration of the qubit (or the configuration of the weighing sub-chip) benefiting from the scheme of the disclosure is expected to realize stronger chip performance, and therefore, the configuration of the quantum chip of the scheme of the disclosure has important guiding significance and value for the development of the quantum chip.
In a specific example of the disclosed aspects, the quantum chip is a superconducting quantum chip.
It should be noted that, the superconducting quantum chip according to the present disclosure refers to a quantum chip made of a superconducting material. For example, the components used in the superconducting quantum chip are all made of superconducting materials. Further, the qubits in the superconducting quantum chip are superconducting qubits. Therefore, configuration support is provided for the performance research of the superconducting quantum chip and the superconducting quantum chip for realizing stronger chip performance.
In a specific example, the following process flow may be adopted to obtain the configuration of the qubit in the quantum chip, as shown in fig. 2, and the manufacturing method of the quantum chip includes:
Forming a base material layer, for example, using sapphire as a base material;
forming a metal layer, such as a superconducting metal layer, on the base material layer;
etching process is carried out, at least partial area in the metal layer is etched, and at least partial area in the substrate material layer is exposed, so that the configuration of the qubit is formed;
the connection assembly described above is disposed in at least a partial region of the configuration of the qubit to couple the first metal plate and the second metal plate comprised by the configuration of the qubit.
Thus, a quantum chip according to the scheme of the present disclosure is obtained. Moreover, the quantum chip has good expansibility and high integration level, and the advantages of the quantum chip in the scheme of the disclosure can be further highlighted especially when the number of the quantum bits is expanded in a large scale. Furthermore, the configuration of the qubit (or the configuration of the weighing sub-chip) benefiting from the scheme of the disclosure is expected to realize stronger chip performance, and therefore, the configuration of the quantum chip of the scheme of the disclosure has important guiding significance and value for the development of the quantum chip.
It will be appreciated that the above process flow is an exemplary process flow of a quantum chip containing one qubit, and in practical applications, a plurality of qubits having the above configuration may be formed in one process flow, which is not limited in the present disclosure.
In a specific example of the present disclosure, the bottom of the "V" shape of the first metal plate and the bottom of the three-fork shape of the second metal plate are arranged at intervals, so that two branches of the "V" shape and three branches of the three-fork shape extend in different directions. For example, as shown in fig. 1, two branches of the "V" shape extend toward two different directions associated with the first direction, and three branches of the three-fork shape extend toward three different directions associated with the second direction, so that coupling with other qubits by using different branches, for example, coupling with other qubits by using five branches, forms a two-dimensional compact structure, and lays a configuration foundation for realizing high connectivity.
Here, it is noted that the qubits coupled by the different branches are different.
Further, in one example, the connection assembly is disposed in a spaced region of the "V" shaped bottom of the first metal plate and the bottom of the tri-fork shape of the second metal plate. Thus, configuration support is provided for the formation of floating type qubits.
Further, in an example, the area where at least one of the connection component, the first metal plate, and the second metal plate is located is a non-grounded area. For example, in a specific example, as shown in fig. 1, the areas where the connection component, the first metal electrode plate and the second metal electrode plate are all non-grounded areas, so that configuration support is provided for forming floating type qubits.
Further, in a specific example, the qubit is a floating-type qubit. The floating type qubit refers to a connection component coupling two metal plates (i.e., a first metal plate and a second metal plate) that is not directly grounded. Therefore, as the connecting component is not grounded, the floating type quantum bit is less influenced by fluctuation of charges, the robustness to the environment is better, the design of a quantum chip of a three-dimensional flip-chip (3D flip-chip) is facilitated, and a configuration foundation is provided for the design of the quantum chip with stronger performance.
In a specific example of the disclosed solution, the connection component is a superconducting quantum interference device. Further, in an example, the superconducting quantum interference device includes two or more josephson junctions. For example, in a specific example, the superconducting quantum interference device comprises two josephson junctions in parallel. In this way, a convenient-to-implement configuration of qubits is provided to promote the utility of the disclosed schemes. Meanwhile, the energy level of the quantum bit is conveniently nonlinear by utilizing the superconducting quantum interference device.
Further, in an example, two or more josephson junctions are placed in two lines in parallel, and the number of josephson junctions contained in each of the two lines is the same or different. That is, a plurality of Josephson junctions are disposed in two different lines, and the two lines are connected in parallel, so that a Josephson junction ring may be formed, where it should be noted that each line is provided with at least one Josephson junction, and the number of Josephson junctions disposed in different lines may be the same or different, and the present disclosure is not limited thereto. In this way, the energy level of the qubit is conveniently nonlinear by using the superconducting quantum interference device.
In a specific example of the disclosed scheme, the configuration of the qubit further satisfies at least one of the following conditions:
the first condition is that the included angle between the two branches of the V-shaped branch is a first angle, wherein the first angle is an acute angle;
The second condition is that the included angle of two adjacent branches in the three branches of the three branches is a second angle, wherein the second angle is an acute angle;
And in the third condition, a first branch of the two branches of the V shape is adjacent to a second branch of the three branches, and an included angle between the adjacent first branch and second branch is a third angle, wherein the third angle is an obtuse angle, an acute angle or a right angle.
It is understood that in practical applications, the configuration of the qubit may satisfy one of the above conditions, or two of the above three conditions, or all three conditions, which is not limited by the present disclosure.
In this way, the scheme provides a specific configuration scheme of the quantum bit, thus providing configuration reference for realizing a quantum chip with stronger performance, and the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional secret-laid structure, and further lays a configuration foundation for realizing high connectivity.
Further, in a specific example, for the second condition, the second angles formed by any adjacent two branches of the three-branch type are the same or different. As shown in FIG. 1, the two second angles may be denoted as a second angle-1 and a second angle-2, respectively, where the second angle-1 and the second angle-2 are the same or different.
Further, in a specific example, the first angle and the second angle are the same. For example, in one example, the second angles formed by any two adjacent branches of the three branches are the same, for example, the second angle-1 and the second angle-2 shown in fig. 1 are the same, and further, the second angle and the first angle are the same, that is, the second angle-1, the second angle-2 and the first angle are the same. In addition, the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional closely-paved structure, and further lays a configuration foundation for realizing high connectivity.
Further, in a specific example, the first angle is about 60 degrees. Therefore, configuration support is provided for forming a two-dimensional closely-laid structure, and a configuration foundation is laid for further realizing high connectivity.
In some embodiments, the first angle is 54 degrees, or in other embodiments, the first angle is 66 degrees, or in still other embodiments, the first angle is 60 degrees.
Further, in a specific example, the second angle is about 60 degrees. Therefore, configuration support is provided for forming a two-dimensional closely-laid structure, and a configuration foundation is laid for further realizing high connectivity.
In some embodiments, the second angle is 54 degrees, or in other embodiments, the second angle is 66 degrees, or in still other embodiments, the second angle is 60 degrees.
Further, in a specific example, the third angle is about 90 degrees. Therefore, configuration support is provided for forming a two-dimensional closely-laid structure, and a configuration foundation is laid for further realizing high connectivity.
In some embodiments, the third angle is 81 degrees, or in other embodiments, the third angle is 99 degrees, or in still other embodiments, the third angle is 90 degrees.
In a specific example of the present disclosure, the first metal plate is surrounded by a first etching region, where the first etching region is formed by etching away at least a portion of a metal layer used to form the first metal plate, for example, as shown in fig. 2, the first etching region surrounds the bottom of the first metal plate 111 and surrounds two branches of the first metal plate 111 to expose at least a portion of the base material.
And/or, in a specific example of the present disclosure, the second metal plate is surrounded by a second etching region, where the second etching region is formed after etching away at least a part of a metal layer used to form the second metal plate. For example, as shown in fig. 2, the second etched region surrounds the bottom of the second metal plate 112 and three branches of the second metal plate 112 to expose at least a partial region of the base material.
Further, in a specific example, at least part of the first etching region located at the bottom of the "V" shape of the first metal plate and at least part of the second etching region located at the bottom of the "three-fork" shape of the second metal plate overlap at least partially to form a spacing region at the bottom of the "V" shape of the first metal plate and at the bottom of the "three-fork" shape of the second metal plate, and further, the connection component is located in the spacing region, that is, in the at least partially overlapping region, to couple the first metal plate and the second metal plate which are arranged at intervals.
In this way, the scheme of the present disclosure further refines the configuration structure of the qubit, and thus, provides configuration support for forming floating-type qubits.
In a specific example of the scheme of the present disclosure, as shown in fig. 3 (a), the dimensions of each part in the "V" shape satisfy at least one of the following conditions:
Condition four, the height of the first of the two branches of the "V" is about 250 microns;
condition five, the width of the bottom of the "V" shape is about 135 microns;
condition six, the width of at least a portion of the etched region of the first etched region surrounding the first of the two branches of the "V" shape is from about 12 microns to about 15 microns.
For condition four, in some specific examples, the height of the first of the two branches of the "V" is 225 microns, or in other specific examples, the height of the first of the two branches of the "V" is 275 microns, or in still other specific examples, the height of the first of the two branches of the "V" is 250 microns.
For condition five, in some specific examples, the width of the bottom of the "V" shape is 121.5 microns, or in other specific examples, the width of the bottom of the "V" shape is 148.5 microns, or in still other specific examples, the width of the bottom of the "V" shape is 135 microns.
For condition six, the width of at least a portion of the etched region of the first etched region surrounding the first of the two branches of the "V" shape is about 12 microns. Or in other specific examples, at least a portion of the first etched region around the first of the two branches of the "V" shape has a width of about 15 microns. Or in still other specific examples, at least a portion of the first etched region around the first of the two branches of the "V" shape has a width of about 13 microns.
Further, in a specific example, as shown in fig. 3 (a), a portion of the first etched region surrounding the first branch of the "V" shape has a width of about 15 micrometers in the first longitudinal direction, or at least a portion of the first etched region surrounding the first branch of the "V" shape has a width of about 12 micrometers in the first lateral direction. In addition, the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional closely-paved structure, and further lays a configuration foundation for realizing high connectivity.
In some embodiments, the width in the first longitudinal direction of the partially etched region surrounding the first leg of the "V" shape is 13.5 microns, or in other embodiments, the width in the first longitudinal direction of the partially etched region surrounding the first leg of the "V" shape is 16.5 microns, or in still other embodiments, the width in the first longitudinal direction of the partially etched region surrounding the first leg of the "V" shape is 15 microns;
further, in some embodiments, at least a portion of the first etched region surrounding the first leg of the "V" shape has a width in the first lateral direction of 10.8 microns, in other embodiments, at least a portion of the first etched region surrounding the first leg of the "V" shape has a width in the first lateral direction of 13.2 microns, or in still other embodiments, at least a portion of the first etched region surrounding the first leg of the "V" shape has a width in the first lateral direction of 12 microns.
It will be appreciated that in practical applications, the dimensions of each portion of the "V" may meet one of the above conditions, or two of the above three conditions, or all three conditions, and the present disclosure is not limited in this regard.
In this way, the scheme provides a specific configuration scheme of the quantum bit, thus providing configuration reference for realizing a quantum chip with stronger performance, and the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional secret-laid structure, and further lays a configuration foundation for realizing high connectivity.
Further, in a specific example, the "V" shape is a symmetrical pattern. For example, the structure is an axisymmetric graph, as shown in fig. 3 (a), and is symmetric along a symmetry axis A-A', so that a structure reference is provided for realizing a quantum chip with stronger performance, and the structure scheme disclosed by the scheme of the disclosure has good expansibility, is convenient for forming a two-dimensional closely-laid structure, and further lays a structure foundation for realizing high connectivity.
In a specific example of the scheme of the present disclosure, as shown in fig. 3 (b), the dimensions of each part in the three-way type satisfy at least one of the following conditions:
condition seven, the height of the second of the three branches of the three-pronged type is about 245 microns;
condition eight the width of the base of the three-pronged form is about 160 microns;
Condition nine the width of at least a portion of the second etched region surrounding a second branch of the three branches of the tri-branch type is from about 12 microns to about 15 microns.
For condition seven, in some embodiments, the height of the second of the three branches of the tri-fork is 220.5 microns, or in other embodiments, the height of the second of the three branches of the tri-fork is 269.5 microns, or in still other embodiments, the height of the second of the three branches of the tri-fork is 245 microns.
For condition eight, in some embodiments, the width of the base of the bifurcation is 144 microns, or in other embodiments, the width of the base of the bifurcation is 176 microns, or in still other embodiments, the width of the base of the bifurcation is 160 microns.
For condition nine, the width of at least a portion of the second etched region surrounding a second branch of the three branches of the tri-branch type is about 12 microns. Or in other specific examples, at least a portion of the second etched region surrounding a second of the three branches of the tri-branch pattern has a width of about 15 microns. Or in still other specific examples, at least a portion of the second etched region surrounding a second of the three branches of the tri-branch type has a width of about 13 microns.
It will be appreciated that in practical applications, the dimensions of each portion in the bifurcation type may meet one of the above conditions, or two of the above three conditions, or all three conditions, and the present disclosure is not limited thereto.
In this way, the scheme provides a specific configuration scheme of the quantum bit, thus providing configuration reference for realizing a quantum chip with stronger performance, and the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional secret-laid structure, and further lays a configuration foundation for realizing high connectivity.
Further, in a specific example, the bifurcation type is a symmetrical pattern. For example, in an axisymmetric pattern, as shown in fig. 3 (B), it is symmetric along the symmetry axis B-B'. In addition, the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional closely-paved structure, and further lays a configuration foundation for realizing high connectivity.
Further, in a specific example, as shown in fig. 3 (b), at least a portion of the second etching region surrounding the second branch of the triple-fork type has a width of about 15 micrometers in the second longitudinal direction, or at least a portion of the second etching region surrounding the second branch of the triple-fork type has a width of about 12 micrometers in the second lateral direction. In addition, the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional closely-paved structure, and further lays a configuration foundation for realizing high connectivity.
In some embodiments, the width in the second longitudinal direction of the at least partially etched region surrounding the second branch of the tri-fork type in the second etched region is 13.5 microns, or in other embodiments, the width in the second longitudinal direction of the at least partially etched region surrounding the second branch of the tri-fork type in the second etched region is 16.5 microns, or in still other embodiments, the width in the second longitudinal direction of the at least partially etched region surrounding the second branch of the tri-fork type in the second etched region is 15 microns;
Further, in some embodiments, the width in the second lateral direction of the at least partially etched region surrounding the second branch of the tri-branch type in the second etched region is 10.8 microns, or in other embodiments, the width in the second lateral direction of the at least partially etched region surrounding the second branch of the tri-branch type in the second etched region is 13.2 microns, or in still other embodiments, the width in the second lateral direction of the at least partially etched region surrounding the second branch of the tri-branch type in the second etched region is 12 microns.
In a specific example of the present disclosure, as shown in fig. 3 (c), the configuration of the qubit further satisfies at least one of the following conditions:
Condition ten, the qubit height is about 619 microns;
the first metal plate has a "V" shaped bottom spaced about 15 microns from the bottom of the second metal plate in a bifurcated shape.
For condition ten, in some embodiments, the height of the qubit is 557.1 microns, or in other embodiments, the height of the qubit is 680.9 microns, or in still other embodiments, the height of the qubit is 619 microns.
For condition eleven, in some specific examples, the "V" shaped bottom of the first metal plate is spaced 13.5 microns from the bottom of the bifurcation of the second metal plate, or in other specific examples, the "V" shaped bottom of the first metal plate is spaced 16.5 microns from the bottom of the bifurcation of the second metal plate, or in still other specific examples, the "V" shaped bottom of the first metal plate is spaced 15 microns from the bottom of the bifurcation of the second metal plate.
It is understood that in practical applications, the configuration of the qubit may satisfy one of the above conditions, or both conditions, and the present disclosure is not limited thereto.
As shown in fig. 3 (c), in a specific example, the effective length in the first etching region from the start point to the inflection point in the first branch direction is about 240 micrometers. Such as 216 microns in effective length in the first etched region from the start point to the inflection point in some specific examples, 240 microns in effective length in the first etched region from the start point to the inflection point in the first branch direction, or 246 microns in effective length in the first etched region from the start point to the inflection point in some specific examples.
Further, in another specific example, an effective length in the second branch direction from the start point to the inflection point in the second etching region is about 240 micrometers. Such as 216 microns in the second branch direction from the start point to the inflection point in some specific examples, or 240 microns in the second branch direction from the start point to the inflection point in some specific examples, or 246 microns in the second branch direction from the start point to the inflection point in some specific examples.
In this way, the scheme provides a specific configuration scheme of the quantum bit, thus providing configuration reference for realizing a quantum chip with stronger performance, and the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional secret-laid structure, and further lays a configuration foundation for realizing high connectivity.
In a specific example of the scheme of the disclosure, when the quantum chip includes two or more than two qubits, two adjacent qubits are coupled through branches of the qubits, wherein the branches of the qubits are any one of two branches of a V shape and three branches of a three-way shape. In addition, the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional closely-paved structure, and further lays a configuration foundation for realizing high connectivity.
Further, in a specific example, the number of other qubits coupled to the qubit neighbor is 5 or less. It will be appreciated that since a qubit has five branches, the qubit is coupled to different other qubit neighbors through at most five branches, i.e. the same qubit is coupled to at most five qubits in close proximity. In addition, the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional closely-paved structure, and further lays a configuration foundation for realizing high connectivity.
Further, in a specific example, the spacing between branches for coupling two qubit neighbors is 5-20 microns.
In some embodiments, the spacing between branches for coupling two qubit neighbors is 5 microns, or in other embodiments, the spacing between branches for coupling two qubit neighbors is 10 microns, or in still other embodiments, the spacing between branches for coupling two qubit neighbors is 15 microns, or in still other embodiments, the spacing between branches for coupling two qubit neighbors is 20 microns.
For example, as shown in fig. 4 and 5, the spacing between two qubit neighbor coupled branches is made 10 microns.
In addition, the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional closely-paved structure, and further lays a configuration foundation for realizing high connectivity.
Further, in a specific example, in a case that other qubits coupled to the qubit neighbor are 2 or more, the qubit located in the middle can be used as a coupling device for regulating the coupling strength between two qubits coupled by the coupling device. As shown in fig. 5, the qubit Q2 is coupled to the qubit Q1 and the qubit Q3 by its own different branches, and the qubit Q2 corresponds to the intermediate qubit, and at this time, the qubit Q2 may be used as a coupling device, and further, the coupling strength between the coupled qubit Q1 and the qubit Q3 is regulated by the qubit Q2. In addition, the configuration scheme disclosed by the scheme has good expansibility, is convenient for forming a two-dimensional closely-paved structure, and further lays a configuration foundation for realizing high connectivity.
In a specific example of the scheme of the disclosure, when the quantum chip includes five or more than five quantum bits, the five or more than five quantum bits can form a two-dimensional compact unit on the first plane, as shown in fig. 6, the five quantum bits form a two-dimensional compact unit on the first plane, and further, a pattern surrounded by branches of the quantum bits in the two-dimensional compact unit includes a quadrangle and a triangle.
In this way, the scheme of the disclosure provides a specific expansion mode, the expansion mode is simple and convenient, a two-dimensional close-spread structure is formed conveniently, the whole space of the quantum chip is fully utilized, and when the number of equivalent sub bits is expanded in a large scale, the advantage of the expansion mode is more remarkable. Therefore, a configuration reference is provided for realizing the quantum chip with stronger performance, and a configuration foundation is further laid for realizing high connectivity.
In addition, because the space between the quantum bits in the two-dimensional closely-spaced units is larger, enough design space is provided for the follow-up, for example, convenience is provided for wiring of the follow-up adding read lines, measurement and control lines and the like. With the benefit of this, quantum chips based on the disclosed schemes are expected to achieve stronger performance and larger scale.
Further, in a specific example, the quadrangle is square, and/or the triangle is a regular triangle. Therefore, a configuration reference is provided for realizing the quantum chip with stronger performance, and a configuration foundation is further laid for realizing high connectivity.
Further, in a specific example, the quantum chip can form a two-dimensional paving structure meeting two-dimensional paving conditions, wherein the two-dimensional paving structure comprises at least one two-dimensional paving unit. Therefore, a configuration reference is provided for realizing the quantum chip with stronger performance, and a configuration foundation is further laid for realizing high connectivity.
Here, in a specific example, the two-dimensional paving condition includes that an integer multiple of one inner angle degree of the regular polygon is 360 degrees.
Further, in a specific example, the maximum connectivity of the two-dimensional structure formed by the quantum chip is smaller than 0.57, and the maximum connectivity represents the connectivity of the quantum chip under the condition that the number of quantum bits of the quantum chip is infinite.
Thus, the scheme of the present disclosure employs a special construction of qubits, and the topology of the mathematical abstraction thereof proves to have strong connectivity. The method is beneficial to strong connectivity, and lays a configuration foundation for further developing the high-performance quantum chip.
In a specific example of the solution of the present disclosure, the quantum chip further includes:
one end of the control wire is used for being connected with a control port of the quantum bit, and the other end of the quantum bit control wire is used for being connected with the first pin so as to be connected with an external control system through the first pin;
And/or the number of the groups of groups,
And one end of the reading line is used for being connected with a reading port of the quantum bit, and the quantum bit reading line is used for being connected with the second pin so as to be connected with an external control system through the second pin.
In this way, the space between the quantum bits in the quantum chip is larger, so that enough wiring space is provided, and the crosstalk problem caused by the control line approach is effectively avoided.
The scheme of the disclosure also provides a quantum computer, which at least comprises the quantum chip and an external control system connected with the quantum chip. Therefore, the average cost of two quantum bits in any two quantum bits in the quantum chip of the quantum computer can be effectively reduced.
In summary, the scheme of the disclosure provides a configuration of quantum bits with good expansibility and superior performance, and simultaneously provides a quantum chip based on the quantum bit expansion, and the connectivity of the quantum chip is high. Because the coupling strength between two adjacent quantum bits in the scheme is stronger, the scheme can effectively reduce the average cost of two quantum bits of any two quantum bits in the quantum chip, and thus, a configuration foundation is laid for further developing the high-performance quantum chip.
In addition, the space between the quantum bits in the quantum chip is larger, so that enough design space is provided for the follow-up, for example, convenience is provided for wiring such as the follow-up adding of reading lines, measurement and control lines and the like. With the benefit of this, quantum chips based on the disclosed schemes are expected to achieve stronger performance and larger scale.
The structure of the superconducting quantum chip is provided, the structure of the quantum bit is good in expansibility, a two-dimensional close-packed structure (for example, a two-dimensional close-packed network) can be formed, and the superconducting quantum chip obtained based on the configuration of the quantum bit provided by the scheme of the disclosure is high in connectivity and excellent in performance.
It should be noted that, the superconducting quantum chip according to the present disclosure refers to a quantum chip made of a superconducting material. For example, the components used in the superconducting quantum chip are all made of superconducting materials. Further, the qubits in the superconducting quantum chip are superconducting qubits.
The scheme of the present disclosure is described in detail below in two parts, a first part introducing a specific configuration of a novel qubit and showing configuration characteristics of the qubit, and a second part describing performance parameters of the configuration of the novel qubit, such as coupling strength between the qubits, connectivity of a topology structure obtained based on the configuration of the qubit, and the like.
Configuration of the first part, qubit
In an example, as shown in fig. 2, sapphire is used as a substrate material, a layer of superconducting metal layer is formed on the substrate material, and after a part of the area in the superconducting metal layer is etched, a configuration of a qubit as shown in fig. 2 is formed, where the configuration of the qubit at least includes three parts, respectively:
The first portion, the metal plate region, includes a first metal plate 111 in the shape of a "V" and a second metal plate 112 in the shape of an inverted "3" (or "triad"). Here, the first metal plate 111 and the second metal plate 112 are both located on a first plane. Further, in some specific examples, the bottom of the "V" shape of the first metal plate and the bottom of the "three-way" shape of the second metal plate are arranged at intervals, so that two branches of the "V" shape and three branches of the "three-way" shape extend in different directions, for example, two branches of the "V" shape extend in two different directions associated with the first direction respectively, and three branches of the "three-way" shape extend in three different directions associated with the second direction respectively, so that coupling with other qubits by using different branches, for example, coupling with other qubits by using five branches, is facilitated, and a two-dimensional close-packed structure is formed. Here, it is noted that the qubits coupled by the different branches are different.
And a second portion, an etched region surrounding the metal plate region, the etched region being formed after etching away the superconducting metal layer to expose at least a portion of the region in the base material. For convenience of description, the etched region is divided into two parts, wherein the first part is called a first etched region, and the second part is called a second etched region, wherein the first etched region is formed by etching away at least part of the region in the superconducting metal layer for forming the first metal plate 111, and then at least part of the substrate material is exposed after etching away at least part of the region in the superconducting metal layer to form a "V" shape, and the second etched region is formed by etching away at least part of the region in the superconducting metal layer for forming the second metal plate 112, and then at least part of the substrate material is exposed after etching away at least part of the region in the superconducting metal layer to form a three-fork shape.
Further, the etched region (i.e., the first etched region and the second etched region) surrounds the first metal plate 111 and the second metal plate 112, for example, the first etched region surrounds the bottom of the first metal plate 111 and surrounds two branches of the first metal plate 111, the second etched region surrounds the bottom of the second metal plate 112 and surrounds three branches of the second metal plate 112, and at least part of the etched region and the second etched region have at least part of the etched region, for example, at least part of the etched region in the first etched region and at the bottom of the "V" shape of the first metal plate and at least part of the etched region in the second etched region and at the bottom of the three branch shape of the second metal plate overlap, so that a spacer region is formed between the bottom of the "V" shape of the first metal plate and the bottom of the three branch shape of the second metal plate to provide configuration support for forming floating float-type qubits.
And a third portion, a connection region, overlapping at least a portion of the etched region, for coupling the first metal plate 111 and the second metal plate 112, for example, a connection member 113 is disposed in a space region between a bottom of the "V" shape of the first metal plate 111 and a bottom of the inverted "3" shape of the second metal plate 112, for example, a superconducting quantum interference device (Superconducting Quantum INTERFERENCE DEVICE, SQUID) 113 is disposed for coupling the first metal plate 111 and the second metal plate 112, so as to facilitate non-linearization of an energy level of the qubit.
In a specific example, the superconducting quantum interference device 113 includes a plurality (two or more) of josephson junctions, further, a plurality of josephson junctions are disposed in two different lines, and the two lines are connected in parallel, where a josephson junction ring may be formed, where it is to be noted that each line is provided with at least one josephson junction, and the number of josephson junctions disposed in different lines may be the same or different, which is not a limitation of the present disclosure. For example, in one example, the connection region is provided with two josephson junctions in parallel, through which the first metal plate 111 and the second metal plate 112, which are arranged at intervals, are coupled.
In addition, it may be noted that the superconducting metal layer other than the qubit configuration is a ground metal, in other words, other regions of the superconducting metal layer other than the qubit configuration are used for ground.
It is noted that in this example the qubit is a floating-type qubit, where the floating-type qubit refers to a connection component coupling two metal plates, such as SQUID, that is not directly grounded. In this way, the floating type quantum bit is less affected by fluctuation of charges because the connecting component is not grounded, the robustness to the environment is better, the design of a quantum chip of a three-dimensional flip-chip (3D flip-chip) is facilitated, the structural expansion and research and development of the superconducting quantum chip which is required to meet the following requirements are facilitated, and meanwhile, the floating type quantum bit has great benefits on wiring, slow-release crosstalk and the like in the superconducting quantum chip. Here, the superconducting quantum chip needs to meet the requirement that the distance between adjacent qubits in the superconducting quantum chip is far and long because the superconducting quantum chip contains a coupler.
Here, it should be noted that, with the superconducting quantum chip obtained by using the qubit according to the scheme of the present disclosure, since the effective interval between two neighboring qubits can be relatively far, wiring is more utilized, thereby providing configuration support for effective sustained-release crosstalk. Moreover, since the effective spacing between two qubits of a neighbor can be relatively far, configuration support is also provided for meeting the requirement that the coupling strength between two qubits of a neighbor be as great as possible and that between two qubits of a next neighbor be as small as possible.
In one example, as shown in fig. 1 or fig. 3 (a), the included angle between the two branches of the "V" shape in the first metal plate 111 is a first angle, where the first angle is an acute angle, for example, in a specific example, the first angle is about 60 degrees. Further, in some embodiments, the first angle is 54 degrees, or in other embodiments, the first angle is 60 degrees, or in still other embodiments, the first angle is 66 degrees.
Further, in an example, the first metal plate 111 is in a symmetrical pattern, for example, in an axisymmetrical pattern, and as shown in fig. 3 (a), the first metal plate 111 is symmetrical along a symmetry axis A-A'.
Further, in another example, as shown in fig. 1 or fig. 3 (b), the included angle of two adjacent branches of the three branches of the second metal plate 112 is a second angle, where the second angle is an acute angle, for example, in a specific example, the second angle is about 60 degrees. Further, in some embodiments, the second angle is 54 degrees, or in other embodiments, the second angle is 60 degrees, or in still other embodiments, the second angle is 66 degrees.
Here, it should be noted that the second angle formed by any two adjacent branches of the three branches of the second metal plate 112, for example, the second angle-1 and the second angle-2 may have the same degree or different degrees, which the present disclosure is not limited to. For example, in some embodiments, the second angle-1 and the second angle-2 are the same, and further, in some embodiments, the second angle-1 and the second angle-2 are each 60 degrees.
Further, in one example, the second metal plate 112 is in a symmetrical pattern, such as an axisymmetrical pattern, and as shown in FIG. 3 (B), the second metal plate 112 is symmetrical along an axis of symmetry B-B'.
Further, in a specific example, the first angle, the second angle-1 and the second angle-2 are the same, for example, 60 degrees.
Further, in another example, as shown in fig. 1, a first branch (e.g., denoted as b1) of the two branches of the "V" shape is adjacent to a second branch (e.g., denoted as b2) of the three branches of the three-branch shape, and an included angle between the adjacent first branch and second branch is a third angle, which is an obtuse angle, an acute angle, or a right angle.
Further, in a specific example, the third angle is about 90 degrees. For example, in some embodiments, the third angle is 99 degrees, or in other embodiments, the third angle is 90 degrees, or in still other embodiments, the third angle is 81 degrees.
It should be noted that the third angle formed by any adjacent first and second branches may or may not be the same. For example, as shown in FIG. 1, the two branches denoted by "V" are a first branch b11 and a first branch b12, respectively, and the three branches denoted by "three" are a second branch b21, respectively, The second branch b22 and the second branch b23, in which the first branch b11 is adjacent to the second branch b21 and the angle between the adjacent first branch b11 and the adjacent second branch b21 is the third angle, and correspondingly, the angle between the adjacent first branch b12 and the adjacent second branch b23 and the angle between the adjacent first branch b12 and the adjacent second branch b23 is the third angle, wherein, for convenience of distinguishing, the third angle formed by the adjacent first branch b11 and the adjacent second branch b21 is the third angle-11, and the third angle formed by the adjacent first branch b12 and the adjacent second branch b23 is the third angle-23, and in which the third angle-11 and the third angle-23 may be the same or different, the scheme of the disclosure is not limited thereto.
Further, in an example, the third angles 11 are the same as the third angles 23, e.g., all 90 degrees.
In a specific example, as shown in fig. 3 (a), the dimensions of the "V" shaped portions in the configuration of the qubit need to meet at least one of the following:
The height of a first branch (e.g., first branch b11, or first branch b12) of the two branches of the "V" shape of the qubit is about 250 microns;
the bottom width of the "V" shape of the qubit is about 135 microns;
The width of the etched region around the first branch of the "V" shape of the qubit is about 12 microns to about 15 microns, for example, the height (also referred to as the width) of the etched region around the first branch of the "V" shape of the qubit in the first longitudinal direction is about 15 microns, and the width of the etched region around the first branch of the "V" shape of the qubit in the first lateral direction is about 12 microns.
Here, it should be noted that the dimensions of the different first branches may be the same or different, which is not particularly limited by the present disclosure.
In another specific example, as shown in fig. 3 (b), the size of each part of the triplet in the configuration of the qubit needs to satisfy at least one of the following:
The second branch (e.g., second branch b21, or second branch b22, or second branch b23) of the three branches of the triplet of qubits has a height of about 245 microns;
The bottom width of the triplet of qubits is about 160 microns;
The width of the etched region of the second branch of the triplet around the qubit is about 12 microns to about 15 microns, for example, the height (also referred to as width) of the etched region of the second branch of the triplet around the qubit in the second longitudinal direction is about 15 microns, and the width of the etched region of the second branch of the triplet around the qubit in the second lateral direction is about 12 microns.
In yet another specific example, as shown in fig. 3 (c), the configuration of the qubit also satisfies at least one of the following conditions:
the height of the qubit is about 619 microns;
the first metal plate has a "V" shaped bottom spaced about 15 microns from the bottom of the tri-fork of the second metal plate;
the effective length in the first etched region in the first branch direction from the start point to the inflection point is about 240 microns.
Further, in a specific example, the qubit has a height of 619 microns, and further, the first metal plate has a "V" shaped bottom spaced 15 microns from the bottom of the second metal plate in a bifurcated shape. Further, a length from the start point to the inflection point in the direction in which the first branch is located in the first etching region is about 240 μm.
It should be noted that the term "about" is used in conjunction with a numerical value to mean that the value is within ten percent (10%) of the recited numerical value, i.e., within plus or minus ten percent of the recited numerical value.
It can be understood that the specific dimensions described above are merely examples, and in practical applications, the specific dimensions can be adjusted according to practical requirements, in other words, the core of the present disclosure is mainly to provide a configuration of qubits, and the selection of the substrate material and the adjustment of the specific dimensions can be set according to practical situations.
Further, expanding is carried out by taking the configuration of the quantum bit shown in fig. 1 as a unit to obtain a two-dimensional paving unit shown in fig. 6, and the two-dimensional paving unit comprises 5 quantum bits as shown in fig. 6, wherein each quantum bit can form neighbor coupling with other quantum bits through own branches in the expanding process, and it can be understood that the quantum bit has five branches, so that the number of other quantum bits which are neighbor coupled with the quantum bit is 5.
Further, the effective spacing between two qubits of the two-dimensional tiling cell that are neighbor coupled is 5-20 microns, for example, as shown in fig. 4 or 5, for spacing between two branches of two qubits that are neighbor coupled by 5-20 microns. Such as in some embodiments 5 microns apart between the two branches in the two-dimensional tiling cell that are used to couple the two qubits close together, or in other embodiments 15 microns apart between the two branches in the two-dimensional tiling cell that are used to couple the two qubits close together, or in still other embodiments 20 microns apart between the two branches in the two-dimensional tiling cell that are used to couple the two qubits close together.
Note that, the neighbor coupling in the scheme of the present disclosure refers to coupling between adjacent quantum devices, for example, as shown in fig. 5, the coupling between the quantum bit Q1 and the quantum bit Q2 is adjacent two quantum bits, and in this case, the coupling between the quantum bit Q1 and the quantum bit Q2 is neighbor coupling, and in the same manner, the coupling between the quantum bit Q2 and the quantum bit Q3 is adjacent two quantum bits, and in this case, the coupling between the quantum bit Q2 and the quantum bit Q3 is also neighbor coupling.
Here, the qubit Q1 and the qubit Q3 are two non-adjacent qubits, and in this case, the qubit Q1 and the qubit Q3 may be referred to as sub-neighbor coupling.
It should be noted that, in the design process of the superconducting quantum chip, the larger the coupling strength between the adjacent coupled quantum bits is, the better, so that the quantum gate with higher fidelity is convenient to realize, and meanwhile, the quantum gate is convenient to realize faster, for example, in the scene of realizing the double-quantum-bit gate based on two adjacent quantum bits, if the coupling strength between the two adjacent quantum bits is stronger, the double-quantum-bit gate with higher fidelity can be realized, and meanwhile, the double-quantum-bit gate can also be realized faster. And the smaller the coupling strength of the next-neighbor coupling is, the better, so that the crosstalk caused by the next-neighbor coupling is reduced.
Further, in an example, the pattern enclosed by the branches of the middle qubit (e.g., 6 branches of the three qubits) of the two-dimensional tiling unit includes:
Quadrangles, such as those enclosed by 8 branches in four qubits;
Triangles, e.g., triangles surrounded by 6 branches of three qubits.
Further, in a specific example, the quadrilateral may be square, e.g., 536 x 536 square microns in area).
Or in another specific example, the triangle may be a regular triangle.
In this way, other quantum devices in the superconducting quantum chip, such as quantum devices necessary for designing the superconducting quantum chip, such as a reading cavity and a filter, can be flexibly placed.
Further, in a specific example, as shown in fig. 7 (a), based on the two-dimensional compact units, expansion is performed on a two-dimensional plane, such as a first plane where the first metal plate and the second metal plate are located, so as to obtain a superconducting quantum chip including a plurality of two-dimensional compact units. At this time, the superconducting quantum chip may be referred to as having a two-dimensional packed structure satisfying the two-dimensional packed condition.
It should be noted that, the two-dimensional structure may also be represented by a topology diagram shown in fig. 7 (b), that is, fig. 7 (b) is a topology diagram of fig. 7 (a), where in the topology diagram, a dot represents a qubit in fig. 7 (a), and an edge represents a coupling relationship between two adjacent qubits.
Therefore, the configuration of the qubit in the scheme of the disclosure is beneficial to realizing the scale expansion of the qubit, and has strong flexibility, for example, in practical application, a coupling device (such as a coupler and a qubit) for realizing the coupling function can be inserted between two adjacent qubits, so as to realize the design of the quantum chip structure of Q-C-Q.
It should be noted that, in a specific example, the configuration of the inserted coupling device is also the configuration of the qubit described above, and at this time, it may be understood that, in a case where other qubits coupled with the qubit neighbor are 2 or more, the qubit located in the middle may be used as the coupling device to regulate the coupling strength between two qubits coupled by the coupling device, and as shown in fig. 5, the qubit Q2 may be used as the coupling device.
Second part, performance analysis
Basic parameters of (one) qubits
In this example, the following parameters were fixed, for example, sapphire was used as the base material, the relative dielectric constant was set to 10, and the dimensions (length×width×height) of the base material were 2mm×2mm×0.4mm before performance analysis described below was performed. As shown in fig. 8, the configuration of the qubit includes parameters specifically:
the first angle, the second angle-1 and the second angle-2 are 60 degrees;
the third angle-11 and the third angle-23 are 90 degrees;
The "V" shape is an axisymmetric structure, and each of the two branches of the "V" shape, for example, the first branch b11 and the first branch b12 have a height of 250 micrometers;
The bottom width of the "V" shape is 135 microns;
The etched areas around the "V" -shaped branches (e.g., first branch b11 and first branch b12), each have a height of 15 microns in the first longitudinal direction;
The width in the first lateral direction of the etched region around the "V" -shaped branches (e.g., first branch b11 and first branch b12) is 12 microns;
The height of each of the three branches of the tri-branch type (e.g., second branch b21, or second branch b22, or second branch b23) is 245 microns;
the width of the bottom of the three branches is 160 micrometers
The height of the qubit is 619 microns;
the spacing between the bottom of the "V" shape and the bottom of the "tri-fork" shape was 15 microns.
(1) Non-harmonicity of qubits
Electromagnetic simulation was performed on the qubit shown in fig. 8, resulting in a non-harmonic intensity of 220MHz for the qubit.
Here, the non-harmonic intensity of the qubit refers to the difference between two energy differences, where one of the two energy differences is the difference between the ground state energy of the qubit and the first excited state energy and the other of the two energy differences is the difference between the first excited state energy and the second excited state energy. Typically, the non-harmonic intensity of the qubit is between 200-300 MHz.
In addition, the capacitance of the qubit is related to the distance between the metal plate of the qubit and the grounded metal plate, e.g., the closer the distance, the greater the capacitance. Further, the capacitance of the qubit can be controlled by adjusting the geometric parameters of the qubit, so that the control of the non-harmonic intensity of the qubit is realized.
Further, the non-harmonic intensity of the qubit is recorded as α, and the non-harmonic intensity α of the qubit can be expressed by the following formula:
Here, e denotes a unit monad charge amount, h denotes a planck constant, C12 denotes a mutual capacitance between the first metal plate 111 and the second metal plate 112, C1g denotes a mutual capacitance between the first metal plate 111 and ground (ground), and C2g denotes a mutual capacitance between the second metal plate 112 and ground.
(2) Frequency of qubits
The frequency of the qubit can be adjusted by adjusting the current of the Z line, for example, the magnetic flux of the SQUID passing through the qubit is controlled by applying the current to the Z line, so that the frequency of the qubit is regulated, and the frequency of the qubit is generally 4-8GHz.
(II) coupling Strength
Double qubit gates are the necessary basis for achieving quantum computation. The quantum operation of implementing the double-quantum bit gate needs to be based on the coupling of two quantum bits, for example, the double-quantum bit gate is implemented by performing quantum operation on two adjacent quantum bits, and at this time, the operation time of implementing the quantum operation of the double-quantum bit gate can be determined by the coupling strength between the two adjacent quantum bits.
This example is given byThe gate is taken as an example to realize double quantum bitsThe quantum operation time of the gate isHere, g represents a bit for realizing the double quantum bitCoupling strength between two qubits of a gate. Here, the geometric parameters of each of the two qubits of the neighbor coupling are as shown in fig. 8, the base material is sapphire, the relative dielectric constant is 10, and the effective interval between the adjacent qubits is set to 10 μm, and at this time, electromagnetic simulation is performed on the two qubits of the neighbor coupling, so that the coupling strength g between the two qubits is 14.3MHz.
Further, taking the coupling strength g between two qubits as 14.3MHz as an example, the double-qubit is calculatedThe operating time t of the door, i.e. executing oneThe gate operating time t is 8.7ns. Thus, the coupling strength between the two quantum bits formed by the novel quantum bit configuration is stronger, and the two quantum bit gates with higher fidelity and faster can be realized.
Further, as shown in fig. 5, the geometric parameters of each of the two qubits of the sub-neighbor coupling are as shown in fig. 8, and the effective interval between the adjacent qubits is set to 10 μm, and at this time, the sub-neighbor coupling strength between the qubit Q1 and the qubit Q3 is 0.165MHz, which means that the sub-neighbor coupling strength is small. Therefore, based on the configuration of the qubit, the superconducting quantum chip with more excellent performance is convenient to design.
(III) connectivity
In this example, a two-dimensional compact structure as shown in fig. 9 (a) and 9 (b) can be obtained based on the two-dimensional compact unit, the two-dimensional compact structure corresponding to fig. 9 (a) is a twisted square topological structure and can be denoted as s= { S1,S2,S3,..the }, wherein the specific structure shown in fig. 9 (a) is a structure of S4, and further, the two-dimensional compact structure corresponding to fig. 9 (b) is a 45 ° twisted square topological structure and can be denoted as x= { X1,X2,X3,..the specific structure shown in fig. 9 (b) is a structure of X3.
Compared with a quantum chip common in the industry, for example, a one-dimensional chain superconducting quantum chip shown in fig. 10 (a), a 54-quantum-bit quantum chip shown in fig. 10 (b), an 80-quantum-bit quantum chip shown in fig. 10 (c), and a 127-quantum-bit quantum chip shown in fig. 10 (d), the quantum chip obtained based on the quantum chip obtained by the scheme of the present disclosure has significant advantages in planar connectivity, as shown in the following table 1:
TABLE 1
Compared results of the superconducting quantum chip obtained based on the quantum bit according to the scheme of the present disclosure and the existing superconducting quantum chip in planar configuration connectivity are shown in the following table 2:
TABLE 2
It can be seen from the table above that the connectivity of the scheme of the present disclosure is far superior to other schemes except slightly inferior to regular triangle-shaped close-packed networks arranged in regular hexagons.
It should be noted that each qubit in the regular triangle-shaped dense-laid network may be adjacent to at most 6 qubits, while the qubits in the scheme of the present disclosure may be adjacent to at most 5 qubits, and since the reduction of the number of adjacent qubits may reduce the crosstalk between the qubits, the scheme of the present disclosure can improve the fidelity of the quantum gate operation compared to the existing regular triangle-shaped dense-laid network, and thus, is sufficient to compromise the minor disadvantage of connectivity.
In summary, the scheme of the disclosure provides a configuration of qubits with good expansibility and superior performance, and simultaneously provides a superconducting quantum chip obtained based on the expansion of the qubits, and as the coupling strength between two adjacent qubits in the superconducting quantum chip is stronger, the average cost of any two qubits in the superconducting quantum chip as two qubit gates can be effectively reduced. Moreover, the connectivity of the superconducting quantum chip is high.
In addition, the space between the quantum bits in the superconducting quantum chip is larger, so that enough design space is provided for the follow-up, for example, convenience is provided for wiring of the follow-up reading cavity, the measurement and control line and the like. With the benefit of this, superconducting quantum chips based on the disclosed schemes are expected to achieve stronger performance and larger scale.
The specific features are summarized as follows:
1. the connectivity is high. The scheme adopts a special pentagonal structure, and the topology structure of mathematical abstraction of the scheme is proved to have strong connectivity. The method is beneficial to the strong connectivity, and hopefully further develops the high-performance quantum chip. Further analysis finds that the connectivity is superior to most of the design schemes existing in the industry;
2. The expansibility is good. The scheme of the disclosure makes full use of the whole space of the chip in the process of tiling the quantum chip. When the number of the qubits is expanded in a large scale, the advantages of the qubits are further highlighted;
3. The design of the reading cavity and the measurement and control line is more convenient. The design of the scheme of the present disclosure has very large spacing between the centers of bits. This facilitates the design of the reading chamber and the measurement and control line. In addition, since the interval between bits is large, it can prevent the occurrence of the problem of mutual crosstalk. This makes the structure very suitable for use in applications requiring high precision reading and control;
4. The secondary neighbor coupling strength is low. The interval between the quantum bits of the scheme is large, so that the coupling strength between the next adjacent quantum bits is low. This minimizes unwanted parasitic coupling.
The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions, improvements, etc. that are within the principles of the present disclosure are intended to be included within the scope of the present disclosure.