技术领域technical field
本公开的实施例涉及一种用于处理器的验证方法、系统、设备以及存储介质。Embodiments of the present disclosure relate to a verification method, system, device and storage medium for a processor.
背景技术Background technique
处理器作为一个运算及逻辑控制的特化单元，会将常用的计算或逻辑控制提炼打包为单一指令，用户基于特定处理器平台进行程序开发时，可以直接使用这些指令达成特定目标，而无需关注硬件实现，由这些指令构成的组合称之为指令集。As a specialized unit of calculation and logic control, the processor will refine and package common calculation or logic control into a single instruction. When users develop programs based on a specific processor platform, they can directly use these instructions to achieve specific goals without paying attention to Hardware implementation, the combination of these instructions is called an instruction set.
随着技术的发展，软件对处理器的运算需求越来越高，一些常用算法在软件层面的实现已经无法满足对速度的要求，需要转化成硬件实现才能提速。由此，将这些算法提炼成指令并增加到指令集成了处理器演进的一个方向。With the development of technology, the computing requirements of software for processors are getting higher and higher. The implementation of some commonly used algorithms at the software level can no longer meet the requirements for speed, and they need to be transformed into hardware implementations to speed up. Thus, refining these algorithms into instructions and adding to instructions integrates one direction of processor evolution.
目前存在一些属于复杂指令集运算系列的指令集架构，并且随着对应架构处理器的不断发展，复杂指令集中的指令也在不断增加，复杂指令集中包括的指令可按照不同类型进行划分，比如分为包括通用指令、系统指令和高级矢量扩展指令或对高级矢量扩展指令进行拓展的扩展指令等。对于这些复杂指令集，充分验证以及通过有效的方法进行快速验证变得十分必要。At present, there are some instruction set architectures belonging to the complex instruction set operation series, and with the continuous development of corresponding architecture processors, the instructions in the complex instruction set are also increasing. The instructions included in the complex instruction set can be divided according to different types, such as classification These include general-purpose instructions, system instructions, and advanced vector extension instructions or extended instructions that extend advanced vector extension instructions. For these complex instruction sets, sufficient verification and fast verification through effective methods become very necessary.
发明内容Contents of the invention
本公开至少一实施例提供了一种用于处理器的验证方法，包括：获取用于访存操作的页面转换表；获取至少一个生成指令项，其中，所述至少一个生成指令项包括由掩码寄存器中的数值确定的操作掩码以及用于所述访存操作的至少一个指令属性项；基于所述至少一个生成指令项，获取第一访存指令；获取用于所述第一访存指令的指令注入页表需求，其中，所述指令注入页表需求包括对所述第一访存指令注入页表错误或者对所述第一访存指令不注入页表错误；基于所述指令注入页表需求和所述第一访存指令获取第二目标指令，其中，所述第二目标指令用于验证访问所述页表转换表是否异常。At least one embodiment of the present disclosure provides a verification method for a processor, including: obtaining a page conversion table for a memory access operation; obtaining at least one generation instruction item, wherein the at least one generation instruction item includes The operation mask determined by the value in the code register and at least one instruction attribute item used for the memory access operation; based on the at least one generated instruction item, obtain the first memory access instruction; obtain the instruction for the first memory access An instruction injection page table requirement of the instruction, wherein the instruction injection page table requirement includes injecting a page table error into the first memory access instruction or not injecting a page table error into the first memory access instruction; based on the instruction injection The page table requirement and the first memory access instruction acquire a second target instruction, wherein the second target instruction is used to verify whether accessing the page table conversion table is abnormal.
例如，本公开至少一实施例提供的一种验证方法还包括：初始化所述掩码寄存器，以确定所述掩码寄存器中的数值。For example, a verification method provided by at least one embodiment of the present disclosure further includes: initializing the mask register to determine a value in the mask register.
例如，在本公开至少一实施例提供的一种验证方法中，初始化所述掩码寄存器，包括：获取第一随机变量，通过数据存入掩码寄存器指令使用所述第一随机变量对所述掩码寄存器进行初始化。For example, in a verification method provided by at least one embodiment of the present disclosure, initializing the mask register includes: obtaining a first random variable, and using the first random variable to Mask registers are initialized.
例如，在本公开至少一实施例提供的一种验证方法中，获取用于访存操作的页面转换表，包括：创建多个第一页表，使得所述多个第一页表的部分作为保留地址空间，以获取用于所述访存操作的所述页面转换表，其中，所述保留地址空间配置为被指向访问时而产生页表异常。For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining a page translation table for a memory fetch operation includes: creating a plurality of first page tables, so that parts of the plurality of first page tables are used as An address space is reserved to obtain the page translation table used for the memory fetch operation, wherein the reserved address space is configured to generate a page table exception when being pointed to for access.
例如，在本公开至少一实施例提供的一种验证方法中，所述至少一个指令属性项包括以下的至少一种：访存操作的指令类型、访存的源操作数、访存的目的操作数、访存范围大小、访存基址、访存地址偏移、访存变址、访问元素的颗粒度。For example, in a verification method provided by at least one embodiment of the present disclosure, the at least one instruction attribute item includes at least one of the following: instruction type of memory access operation, source operand of memory access, destination operation of memory access Number, memory access range size, memory access base address, memory access address offset, memory access index, and the granularity of access elements.
例如，在本公开至少一实施例提供的一种验证方法中，基于所述至少一个生成指令项，获取第一访存指令，包括：利用随机化函数对所述至少一个生成指令项进行随机，获取所述第一访存指令。For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining a first memory access instruction based on the at least one generated instruction item includes: using a randomization function to randomize the at least one generated instruction item, Acquire the first memory access instruction.
例如，在本公开至少一实施例提供的一种验证方法中，获取用于所述第一访存指令的指令注入页表需求，包括：获取第二随机变量，并基于所述第二随机变量使得随机地对所述第一访存指令注入页表错误或者不注入页表错误。For example, in a verification method provided by at least one embodiment of the present disclosure, obtaining the instruction injection page table requirement for the first memory access instruction includes: obtaining a second random variable, and based on the second random variable The first memory access instruction is randomly injected with a page table error or not injected with a page table error.
例如，本公开至少一实施例提供的一种验证方法还包括：基于所述第一访存指令中的所述访存范围大小以及所述访问元素的颗粒度，获取所述掩码寄存器的有效位信号，其中，所述掩码寄存器的有效位信号用于确定所述第一访存指令是否支持异常抑制。For example, a verification method provided by at least one embodiment of the present disclosure further includes: based on the size of the memory access range in the first memory access instruction and the granularity of the access elements, obtaining the valid A bit signal, wherein the effective bit signal of the mask register is used to determine whether the first memory access instruction supports exception suppression.
例如，在本公开至少一实施例提供的一种验证方法中，基于所述指令注入页表需求和所述第一访存指令获取第二目标指令，包括：响应于所述指令注入页表需求为对所述第一访存指令不注入页表错误，获取正常的所述第二目标指令；或者，响应于所述指令注入页表需求为对所述第一访存指令注入页表错误，获取异常的所述第二目标指令。For example, in a verification method provided by at least one embodiment of the present disclosure, acquiring a second target instruction based on the instruction injection page table requirement and the first memory access instruction includes: responding to the instruction injection page table requirement In order not to inject a page table error into the first memory access instruction, obtain the normal second target instruction; or, in response to the instruction injection page table requirement, inject a page table error into the first memory access instruction, The second target instruction for the exception is fetched.
例如，在本公开至少一实施例提供的一种验证方法中，响应于所述指令注入页表需求为对所述第一访存指令注入页表错误，获取异常的所述第二目标指令，包括：响应于所述指令注入页表需求为对所述第一访存指令注入页表错误，调整所述访存地址偏移和/或所述访存基址，指向所述页面转换表中的保留地址空间，其中，所述保留地址空间配置为被指向访问时产生页表异常；基于所述掩码寄存器的有效位信号，获取页表异常影响结果；响应于所述页表异常影响结果为不影响，获取异常的所述第二目标指令；或者，响应于所述页表异常影响结果为影响，获取所述页表异常预处理子程序并且获取异常的所述第二目标指令。For example, in a verification method provided by at least one embodiment of the present disclosure, in response to the instruction injection page table requirement is to inject a page table error into the first memory access instruction, and obtain the abnormal second target instruction, Including: responding to the instruction injection page table requirement to inject a page table error into the first memory access instruction, adjusting the memory access address offset and/or the memory access base address, pointing to the page translation table The reserved address space, wherein, the reserved address space is configured to generate a page table exception when being pointed to and accessed; based on the valid bit signal of the mask register, obtain a page table abnormal impact result; respond to the page table abnormal impact result If it is not affected, obtain the abnormal second target instruction; or, in response to the page table abnormality affecting result being affected, obtain the page table exception preprocessing subroutine and obtain the abnormal second target instruction.
本公开至少一实施例提供了一种用于处理器的验证系统，包括：页面转换表获取模块，被配置为获取用于访存操作的页面转换表；生成指令项获取模块，被配置为获取至少一个生成指令项，其中，所述至少一个生成指令项包括由掩码寄存器中的数值确定的操作掩码以及用于所述访存操作的至少一个指令属性项；第一指令获取模块，被配置为基于所述至少一个生成指令项获取第一访存指令；指令注入页表需求获取模块，被配置为获取用于所述第一访存指令的指令注入页表需求，其中，所述指令注入页表需求包括对所述第一访存指令注入页表错误或者对所述第一访存指令不注入页表错误；第二指令获取模块，被配置为基于所述指令注入页表需求和所述第一访存指令获取第二目标指令，其中，所述第二目标指令用于验证访问所述页表转换表是否异常。At least one embodiment of the present disclosure provides a verification system for a processor, including: a page translation table acquisition module configured to acquire a page translation table for a memory access operation; a generation instruction item acquisition module configured to acquire At least one generating instruction item, wherein the at least one generating instruction item includes an operation mask determined by the value in the mask register and at least one instruction attribute item for the memory access operation; the first instruction acquisition module is Configured to obtain a first memory access instruction based on the at least one generated instruction item; the instruction injection page table requirement acquisition module is configured to obtain an instruction injection page table requirement for the first memory access instruction, wherein the instruction Injecting a page table requirement includes injecting a page table error into the first memory access instruction or not injecting a page table error into the first memory access instruction; the second instruction acquisition module is configured to inject a page table requirement based on the instruction and The first memory access instruction obtains a second target instruction, wherein the second target instruction is used to verify whether access to the page table conversion table is abnormal.
本公开至少一实施例提供了一种电子设备，包括：处理器和存储器，其中，所述存储器上存储有计算机程序，所述计算机程序被所述处理器执行时，实现如上文任一项所述的验证方法。At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the above-mentioned the verification method described above.
本公开至少一实施例提供了一种计算机可读存储介质，其中，所述存储介质内存储有计算机程序，所述计算机程序被处理器执行时，实现如上述任一示例中所述的验证方法。At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, the verification method described in any of the above examples is implemented .
附图说明Description of drawings
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present disclosure. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本公开一些实施例提供的用于处理器的验证方法的流程图；FIG. 1 is a flowchart of a verification method for a processor provided by some embodiments of the present disclosure;
图2为本公开一些实施例提供的步骤S52的流程图；FIG. 2 is a flowchart of step S52 provided by some embodiments of the present disclosure;
图3为本公开一些实施例提供的用于处理器的验证方法中的随机生成指令的方法的流程图；FIG. 3 is a flowchart of a method for randomly generating instructions in a verification method for a processor provided by some embodiments of the present disclosure;
图4为本公开一些实施例提供的生成测试激励源文件的原理示意图；FIG. 4 is a schematic diagram of the principle of generating test stimulus source files provided by some embodiments of the present disclosure;
图5为本公开一些实施例提供的一种验证系统的框图；Fig. 5 is a block diagram of a verification system provided by some embodiments of the present disclosure;
图6为本公开一些实施例提供的一种电子设备的框图。Fig. 6 is a block diagram of an electronic device provided by some embodiments of the present disclosure.
具体实施方式Detailed ways
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.
除非另有定义，本公开实施例使用的所有术语(包括技术和科学术语)具有与本公开所属领域的普通技术人员共同理解的相同含义。还应当理解，诸如在通常字典里定义的那些术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非本公开实施例明确地这样定义。Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in idealized or extremely formalized meanings, unless the disclosure Embodiments are expressly defined as such.
本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。本公开实施例中使用了流程图用来说明根据本公开实施例的方法的步骤。应当理解的是，前面或后面的步骤不一定按照顺序来精确的进行。相反，可以按照倒序或同时处理各种步骤。同时，也可以将其他操作添加到这些过程中，或从这些过程移除某一步或数步。"First", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "a", "an" or "the" also do not denote a limitation of quantity, but mean that there is at least one. Likewise, "comprising" or "comprises" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, and do not exclude other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. In the embodiment of the present disclosure, a flow chart is used to illustrate the steps of the method according to the embodiment of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily have to be performed in a precise order. Instead, various steps may be processed in reverse order or concurrently. At the same time, other operations can be added to these procedures, or a step or steps can be removed from these procedures.
目前，一些对一系列原有指令集进行扩展的指令(如AVX-512指令，对应下文所述的设定高级向量扩展指令，在本文中可用高级向量扩展指令这个简化描述)可包括相应的基础指令、指数与倒数指令、冲突指令、预取指令以及新加的单指令多数据流(SIMD)扩展指令(例如512bitSIMD扩展指令)。At present, some instructions that extend a series of original instruction sets (such as AVX-512 instructions, corresponding to the set advanced vector extension instructions described below, the simplified description of advanced vector extension instructions can be used in this paper) can include the corresponding basic instructions, exponent and reciprocal instructions, conflicting instructions, prefetch instructions, and newly added single instruction multiple data (SIMD) extension instructions (such as 512bit SIMD extension instructions).
本公开的发明人发现，该指令(如上文所述的设定高级向量扩展指令)还可引入例如以下几点架构上的改进：(1)支持512bit位宽向量和单指令多数据流的寄存器集合；(2)64位模式下支持16个新的512bit的SIMD寄存器；(3)支持8个新的操作掩码寄存器(OpmaskRegisters，k0-k7)，主要用于条件执行和对目的操作数的有效整合；(4)引入新的指令编码前缀(EVEXPrefix)，将操作数位宽扩展至512bit。The inventors of the present disclosure have found that this instruction (as described above to set the advanced vector extension instruction) can also introduce, for example, the following architectural improvements: (1) registers that support 512bit bit-wide vectors and SIMD Set; (2) Support 16 new 512bit SIMD registers in 64-bit mode; (3) Support 8 new operation mask registers (OpmaskRegisters, k0-k7), mainly used for conditional execution and destination operands Effective integration; (4) Introducing a new instruction encoding prefix (EVEXPrefix) to expand the operand bit width to 512bit.
页表转换是一些架构中提出的一种由操作系统软件维护和管理的将虚拟地址转换为物理地址的方法，能够提高内存访问安全性。一般地，页表转换机制可使操作系统软件能够为每个进程或者程序开辟独立的地址空间。该机制思想是操作系统维护一个从虚拟地址到物理地址的页表转换表。例如，以一种架构的64bit模式下的4-Kbyte大小的物理地址页表转换为例，64bit的虚拟地址被划分为6个不同的域，其中的4个域作为索引用于不同级别的物理地址查找，例如6个不同的域中的一个域(比如Bits11:0)作为4-Kbyte物理页表的访存偏移地址，至于其他五个域的作用这里不做赘述。Page table translation is a method proposed in some architectures and maintained and managed by operating system software to convert virtual addresses into physical addresses, which can improve memory access security. Generally, the page table conversion mechanism can enable the operating system software to open up an independent address space for each process or program. The idea of this mechanism is that the operating system maintains a page table translation table from virtual address to physical address. For example, taking a 4-Kbyte physical address page table conversion in 64bit mode of an architecture as an example, the 64bit virtual address is divided into 6 different domains, and 4 of them are used as indexes for different levels of physical addresses. Address lookup, for example, one of the six different fields (such as Bits11:0) is used as the memory access offset address of the 4-Kbyte physical page table, and the functions of the other five fields will not be described here.
页表错误是一种发生在内存访问时产生的场景。例如，页表错误这种异常产生的一般原因是由于从虚拟地址到物理地址的页表映射未创建或程序需要访问的权限和目前存在的页表属性不一致等。本公开的发明人发现，页表错误产生的主要原因包括以下几点：第一，需要访问的内存单元的页表在页面转换表中不存在；第二，处理器试图从不具有可执行权限的页表中读取指令；第三，内存访问时遇到页表保护检查失败；第四，页表转换表中的保留位为1。A page table fault is a scenario that occurs during memory access. For example, the general reason for the abnormality of page table error is that the page table mapping from virtual address to physical address is not created or the permission that the program needs to access is inconsistent with the currently existing page table attributes. The inventors of the present disclosure found that the main causes of page table errors include the following points: first, the page table of the memory unit that needs to be accessed does not exist in the page translation table; second, the processor tries to never have executable permission Third, the page table protection check fails during memory access; fourth, the reserved bit in the page table conversion table is 1.
本公开的发明人还发现，在正常的情况下，如果一条指令中源操作数或目的操作数包含内存访问，并且需要访问的内存单元的地址存在页表错误，比如页表未创建，内存访问单元会产生一个页表错误信号给微码(Ucode)，微码根据中断向量表进入对应的异常/预处理子程序，完成例如对异常/中断的处理。指令(例如上文所述的高级向量扩展指令)由于引入了操作掩码，使得一个源操作数或目的操作数包含内存访问的指令可能不会真正的发送内存访问请求，从而使得在操作掩码是0的情况下，即使源操作数或目的操作数的内存访问地址存在页表错误的时候，访存单元不会产生页表异常的错误返回给微码，从而不需要进入异常预处理子程序进行处理。操作掩码是指令的一个属性。例如，对于VPANDNQZMM0{k1},ZMM1,[mem]，Opmask寄存器k1[7:0]是有效的操作掩码，操作掩码寄存器k1中的每个bit控制内存访问单元中的每8个字节是否会被真正访问。对于上述指令，如果k1[7:0]＝0，即使访问的内存页表不存在，加载(Load)或存储(Store)内存访问单元也不会产生一个页表错误信号给微码，从而微码不会进入页表错误处理的中断子程序。如果k1[7:0]＝1，表示需要从内存起始地址读8个字节的数据元，加载单元或存储单元就会向内存发起真正的访问请求，则会产生页表异常，加载单元或存储单元会将该异常错误信息发送给微码，微码进行进一步的处理。当然，此仅仅为示例性，并不为本申请的限制。The inventors of the present disclosure also found that under normal circumstances, if the source operand or the destination operand in an instruction contains memory access, and the address of the memory unit to be accessed has a page table error, such as the page table is not created, the memory access The unit will generate a page table error signal to the microcode (Ucode), and the microcode enters the corresponding exception/preprocessing subroutine according to the interrupt vector table to complete, for example, the processing of the exception/interrupt. Instructions (such as the advanced vector extension instructions mentioned above) introduce an operation mask, so that a source operand or destination operand contains a memory access instruction that may not actually send a memory access request, so that the operation mask In the case of 0, even if there is a page table error in the memory access address of the source operand or the destination operand, the memory access unit will not generate a page table exception error and return it to the microcode, so there is no need to enter the exception preprocessing subroutine to process. The operation mask is an attribute of the instruction. For example, for VPANDNQZMM0{k1},ZMM1,[mem], the Opmask register k1[7:0] is an effective operation mask, and each bit in the operation mask register k1 controls every 8 bytes in the memory access unit Will it be actually accessed. For the above instructions, if k1[7:0]=0, even if the accessed memory page table does not exist, the load (Load) or store (Store) memory access unit will not generate a page table error signal to the microcode, so that the microcode The code does not enter the interrupt subroutine for page table fault handling. If k1[7:0]=1, it means that 8 bytes of data elements need to be read from the starting address of the memory, the load unit or the storage unit will initiate a real access request to the memory, and a page table exception will be generated, and the load unit Or the storage unit will send the abnormal error information to the microcode, and the microcode will perform further processing. Of course, this is only an example, not a limitation of the present application.
内核集簇(CoreCluster)顶级(top级)的验证测试激励是基于指令序列的汇编程序。本公开的发明人又发现，由于指令集十分复杂，所以测试的空间十分巨大，同时top级别的验证平台侧重系统级别的功能验证，需要关注内核在遇到某些指令异常或中断时功能是否正确。如此，若要进行充分验证必须要通过有效的方法进行快速验证，尽快收敛，所以，在大规模集成电路验证中随机指令的产生方法就显得尤为重要，测试激励的随机性直接决定了验证场景的覆盖是否全面。The verification test stimulus of the core cluster (CoreCluster) top level (top level) is an assembler based on instruction sequences. The inventors of the present disclosure also found that because the instruction set is very complex, the space for testing is huge. At the same time, the top-level verification platform focuses on system-level functional verification, and it is necessary to pay attention to whether the kernel functions correctly when encountering certain instruction exceptions or interruptions. . In this way, in order to conduct sufficient verification, effective methods must be used to quickly verify and converge as soon as possible. Therefore, the method of generating random instructions in large-scale integrated circuit verification is particularly important. The randomness of test incentives directly determines the verification scene. Whether the coverage is comprehensive.
本公开至少一实施例提供了一种用于处理器的验证方法，包括：获取用于访存操作的页面转换表；获取至少一个生成指令项，至少一个生成指令项包括由掩码寄存器中的数值确定的操作掩码以及用于访存操作的至少一个指令属性项；基于至少一个生成指令项，获取第一访存指令；获取用于第一访存指令的指令注入页表需求，指令注入页表需求包括对第一访存指令注入页表错误或者对第一访存指令不注入页表错误；基于指令注入页表需求和第一访存指令获取第二目标指令，第二目标指令用于验证访问页表转换表是否异常。At least one embodiment of the present disclosure provides a verification method for a processor, including: obtaining a page conversion table for a memory access operation; obtaining at least one generating instruction item, at least one generating instruction item including the An operation mask determined by a numerical value and at least one instruction attribute item used for a memory access operation; based on at least one generated instruction item, obtaining a first memory access instruction; obtaining an instruction injection page table requirement for the first memory access instruction, and instruction injection The page table requirement includes injecting a page table error into the first memory access instruction or not injecting a page table error into the first memory access instruction; obtaining the second target instruction based on the instruction injection page table requirement and the first memory access instruction, and using the second target instruction It is used to verify whether the access to the page table conversion table is abnormal.
本公开上述实施例的验证方法可实现对访存指令中包括操作掩码属性发生页表异常场景的验证，能够使测试激励(也可称之为验证激励)变的非常丰富，不断扩充验证空间。例如，在本公开的至少一实施例中，验证方法还能结合操作掩码和异常抑制的特性，实现对访存指令(例如包括但不限于高级向量扩展指令)中具有操作掩码以及不同异常抑制属性发生页表异常场景的全面验证，通过不同场景组合可测出一些意想不到的设计缺陷。本公开的实施例的验证方法也适用除了上述访存指令以外的一些不支持操作掩码和异常抑制的其他访存指令的页表错误注入的场景。本公开的实施例还能够与其它的测试序列生成的指令片段随机组合，针对处理器的验证生成更复杂，更全面的测试激励。本公开的实施例能够非常简单、方便的扩展至多线程，可以为单核多线程以及多核多线程提供测试激励。The verification method of the above-mentioned embodiments of the present disclosure can realize the verification of the page table abnormal scene including the operation mask attribute in the memory access instruction, and can make the test incentives (also called verification incentives) very rich, and continuously expand the verification space . For example, in at least one embodiment of the present disclosure, the verification method can also combine the characteristics of operation mask and exception suppression to realize the operation mask and different exceptions in memory access instructions (including but not limited to advanced vector extension instructions). Comprehensive verification of page table exception scenarios where the suppression attribute occurs, and some unexpected design flaws can be detected by combining different scenarios. The verification method of the embodiments of the present disclosure is also applicable to the scene of page table fault injection of some memory access instructions other than the above memory access instructions that do not support operation mask and exception suppression. The embodiments of the present disclosure can also be randomly combined with instruction fragments generated by other test sequences to generate more complex and comprehensive test stimuli for processor verification. The embodiments of the present disclosure can be extended to multithreading very simply and conveniently, and can provide test incentives for single-core multithreading and multi-core multithreading.
图1为本公开一些实施例提供的用于处理器的验证方法的流程图。Fig. 1 is a flowchart of a verification method for a processor provided by some embodiments of the present disclosure.
例如，如图1所示，本公开至少一实施例提供的用于处理器的验证方法包括步骤S1至步骤S5。For example, as shown in FIG. 1 , the verification method for a processor provided by at least one embodiment of the present disclosure includes steps S1 to S5.
步骤S1、获取用于访存操作的页面转换表。Step S1, obtaining a page conversion table used for a memory fetch operation.
步骤S2、获取至少一个生成指令项，其中，至少一个生成指令项包括由掩码寄存器中的数值确定的操作掩码以及用于访存操作的至少一个指令属性项。Step S2. Obtain at least one generating instruction item, wherein the at least one generating instruction item includes an operation mask determined by a value in the mask register and at least one instruction attribute item for a memory fetch operation.
步骤S3、基于至少一个生成指令项，获取第一访存指令。Step S3, based on at least one generated instruction item, acquire a first memory access instruction.
步骤S4、获取用于第一访存指令的指令注入页表需求，其中，指令注入页表需求包括对第一访存指令注入页表错误或者对第一访存指令不注入页表错误。Step S4. Obtain instruction injection page table requirements for the first memory access instruction, wherein the instruction injection page table requirements include injecting page table errors into the first memory access instruction or not injecting page table errors into the first memory access instruction.
步骤S5、基于指令注入页表需求和第一访存指令获取第二目标指令，其中，第二目标指令用于验证访问页表转换表是否异常。Step S5, acquiring a second target instruction based on the instruction injection page table requirement and the first memory access instruction, wherein the second target instruction is used to verify whether the access page table conversion table is abnormal.
本公开上述实施例的验证方法在实现访存指令对页表(即页表转换表)访问异常的验证时，能够实现对访存指令中包括操作掩码属性发生页表异常场景的验证，可使测试激励变的非常丰富，不断扩充验证空间。The verification method of the above-mentioned embodiments of the present disclosure can realize the verification of the scene where the operation mask attribute in the memory access instruction includes the operation mask attribute and the page table exception occurs when the memory access instruction verifies the access exception to the page table (ie, the page table conversion table). The test incentives are very rich, and the verification space is continuously expanded.
本公开一些实施例的验证方法还能结合操作掩码和异常抑制的特性，实现对访存指令中具有操作掩码以及不同异常抑制属性发生页表异常场景的全面验证，通过不同场景组合可测出一些意想不到的设计缺陷。The verification method of some embodiments of the present disclosure can also combine the characteristics of operation mask and exception suppression to realize comprehensive verification of page table exception scenarios with operation masks and different exception suppression attributes in memory access instructions, which can be tested by combining different scenarios Some unexpected design flaws.
本公开上述实施例的验证方法也适用除了上述访存指令以外的一些不支持操作掩码和异常抑制的访存指令的页表错误注入的场景，验证全面。The verification method in the above embodiments of the present disclosure is also applicable to the scene of page table fault injection of some memory access instructions other than the above memory access instructions that do not support operation mask and exception suppression, and the verification is comprehensive.
本公开上述实施例能够实现与其它的测试序列生成的指令片段随机组合，针对处理器的验证生成更复杂，更全面的测试激励。The above-mentioned embodiments of the present disclosure can be randomly combined with instruction fragments generated by other test sequences to generate more complex and comprehensive test incentives for processor verification.
本公开上述实施例能够非常简单、方便的扩展至多线程，可以为单核多线程以及多核多线程提供测试激励。The above embodiments of the present disclosure can be extended to multi-thread very simply and conveniently, and can provide test incentives for single-core multi-thread and multi-core multi-thread.
目前采用验证方法学是处理器验证的趋势之一，通用验证方法学(UniversalVerificationMethodology，简称UVM)是其中的典型代表。UVM是以SystemVerilog类为主的通用验证方法学，利用它的可重用组件，能够构建具有标准化层次结构和接口的功能验证环境，即UVM验证环境。UVM验证环境规定了UVM中的基本类(即可重用组件)。验证人员可以在基本类的基础上扩展自己需要的类，然后用UVM标准的通信语句将各个类的通信接口连接起来。如此，本公开的实施例可通过随机测试生成模块(RandomTest Generate，RTG)来实现生成随机访存指令(例如AVX-512访存指令)并随机注入页表错误的测试激励(例如内核集簇top测试激励)生成过程。该随机测试生成模块是基于SystemVerilog语言和UVM验证方法搭建的随机指令生成环境。需要说明的是，由于此并非为本公开的实施例需要描述的重点，这里不再赘述。At present, the adoption of verification methodology is one of the trends of processor verification, and Universal Verification Methodology (Universal Verification Methodology, UVM for short) is a typical representative thereof. UVM is a general verification methodology based on the SystemVerilog class. Using its reusable components, it is possible to build a functional verification environment with a standardized hierarchy and interface, that is, a UVM verification environment. The UVM verification environment specifies the basic classes (ie, reusable components) in UVM. Verifiers can extend the classes they need on the basis of the basic classes, and then use UVM standard communication statements to connect the communication interfaces of each class. In this way, the embodiments of the present disclosure can generate random memory access instructions (such as AVX-512 memory memory instructions) and randomly inject test incentives for page table errors (such as kernel cluster top test stimulus) generation process. The random test generation module is a random instruction generation environment based on SystemVerilog language and UVM verification method. It should be noted that since this is not the focus of the description of the embodiments of the present disclosure, it will not be repeated here.
在一些示例中，本公开的实施例的第一访存指令和/或第二目标指令是一种包含内存访问操作的指令，由此可以实现页表访问异常的场景的验证。In some examples, the first memory access instruction and/or the second target instruction in the embodiments of the present disclosure is an instruction including a memory access operation, so that the verification of the page table access exception scenario can be realized.
本公开的实施例的第一访存指令和/或第二目标指令可以是AVX-512访存指令。需要说明的是，下文的实施例主要是以第一访存指令和/或第二目标指令为AVX-512访存指令为例进行说明，但是本公开的实施例并不仅限于此，这里不再穷举和赘述。The first memory fetch instruction and/or the second target instruction in the embodiment of the present disclosure may be an AVX-512 memory fetch instruction. It should be noted that the following embodiments are mainly described by taking the first memory access instruction and/or the second target instruction as an AVX-512 memory access instruction as an example, but the embodiments of the present disclosure are not limited thereto, and will not be described here again. Exhaustive and redundant.
在一些示例中，本公开的实施例的验证方法还包括以下过程或步骤T1：初始化掩码寄存器，以确定掩码寄存器(也可称操作掩码寄存器)中的数值。In some examples, the verification method of the embodiment of the present disclosure further includes the following process or step T1: initializing a mask register to determine a value in the mask register (also called an operation mask register).
本公开的实施例能够通过SystemVerilog增加一定的约束来控制掩码寄存器所初始化的值，从而构建出对应的场景，使得本公开的实施例的测试激励变的非常丰富，验证也会更加全面。The embodiment of the present disclosure can control the initialized value of the mask register by adding certain constraints in SystemVerilog, so as to construct a corresponding scene, so that the test stimulus of the embodiment of the present disclosure becomes very rich, and the verification will be more comprehensive.
在一些示例中，对于步骤T1，初始化掩码寄存器以确定掩码寄存器中的数值包括以下过程或步骤T11：获取第一随机变量，通过数据存入掩码寄存器指令使用第一随机变量对掩码寄存器进行初始化。In some examples, for step T1, initializing the mask register to determine the value in the mask register includes the following process or step T11: obtaining a first random variable, using the first random variable to the mask by storing data into the mask register instruction Registers are initialized.
例如，在步骤T11中，第一随机变量可以是64bit的变量。当然，此仅仅为示例性的，并不为本公开的实施例的限制。For example, in step T11, the first random variable may be a 64-bit variable. Certainly, this is only exemplary, and is not a limitation of the embodiments of the present disclosure.
例如，在步骤T11中，第一随机变量可以是一个立即数，也可以是内存当中的数据，当然，此仅仅为示例性的，本公开的实施例对此不作限制，这里不再穷举和赘述。For example, in step T11, the first random variable may be an immediate value, or data in the memory. Of course, this is only exemplary, and the embodiments of the present disclosure do not limit this, and no exhaustive examples and repeat.
例如，对于步骤T11，本公开的实施例可以在SystemVerilog中将一个变量定义为bit[63:0]var1，即该var1是一个64bit的变量，再调用SystemVerilog中的随机函数接口，这样可以对变量var1进行随机。如此，var1成为一个随机生成的64bit的变量，即对应上述的64bit的第一随机变量。当然，此仅仅为示例性的，并不为本公开的实施例的限制。For example, for step T11, the embodiment of the present disclosure can define a variable as bit[63:0]var1 in SystemVerilog, that is, the var1 is a 64bit variable, and then call the random function interface in SystemVerilog, so that the variable var1 is randomized. In this way, var1 becomes a randomly generated 64-bit variable, which corresponds to the above-mentioned 64-bit first random variable. Certainly, this is only exemplary, and is not a limitation of the embodiments of the present disclosure.
例如，在步骤T11中，数据存入掩码寄存器指令可以是KMOVW或KMOVB或KMOVQ或KMOVD指令，这些指令是设定高级向量扩展指令集中支持的可将掩码寄存器作为目的地址的指令，由此实现将一个立即数或者内存当中的数据加载到掩码寄存器中。当然，此仅仅为示例性的，并不为本公开的实施例的限制。For example, in step T11, the instruction for storing data into the mask register may be KMOVW or KMOVB or KMOVQ or KMOVD instructions, these instructions are instructions that can use the mask register as the destination address supported by the advanced vector extension instruction set, thus The implementation loads an immediate value or data in memory into the mask register. Certainly, this is only exemplary, and is not a limitation of the embodiments of the present disclosure.
在一些示例中，上述步骤T1可以在步骤S1之前，也可以在步骤S1之后或者步骤T1与步骤S1同时进行，本公开的实施例对此不作限制，其可以根据实际情况进行自由调整，这里不再赘述。In some examples, the above step T1 may be performed before step S1, or after step S1, or step T1 and step S1 at the same time, the embodiments of the present disclosure are not limited to this, it can be freely adjusted according to the actual situation, not here Let me repeat.
在一些示例中，对于步骤S1，获取用于访存操作的页面转换表包括以下过程或步骤S11：创建多个第一页表，使得多个第一页表的部分作为保留地址空间，以获取用于访存操作的页面转换表，该保留地址空间配置为被指向访问时而产生页表异常。In some examples, for step S1, obtaining a page translation table for a memory fetch operation includes the following process or step S11: creating a plurality of first page tables, so that part of the plurality of first page tables is used as a reserved address space to obtain A page translation table for memory fetch operations, the reserved address space is configured to cause a page table exception when accessed.
在一些示例中，在步骤S11中，多个第一页表可以是多个不同属性的页表。例如，创建的多个第一页表可以是虚拟地址映射为物理地址的连续的四个4K-byte的页表(例如每一个虚拟地址映射为物理地址需要经过4个页表转换)，并且当这四个4K-byte的页表中的最后一个4K-byte的页表中的presentbit属性为0(presentbit＝1表示存在，presentbit＝0表示不存在)，则该最后一个4K-byte的页表即是保留地址空间。由此，若内存访问中的虚拟地址指向的是最后一个4K-byte的页表，就会产生因页表不存在而导致的页表异常。In some examples, in step S11, the multiple first page tables may be multiple page tables with different attributes. For example, the plurality of first page tables created may be four consecutive 4K-byte page tables in which virtual addresses are mapped to physical addresses (for example, each virtual address is mapped to a physical address and needs to go through 4 page table conversions), and when The presentbit attribute in the last 4K-byte page table of the four 4K-byte page tables is 0 (presentbit=1 indicates existence, presentbit=0 indicates non-existence), then the last 4K-byte page table That is, the address space is reserved. Therefore, if the virtual address in the memory access points to the last 4K-byte page table, a page table exception will occur due to the non-existence of the page table.
本公开一些实施例的生成指令项是作为一条指令的基本要素，生成指令项可确定出基于随机测试生成模块根据随机约束生成的具体指令。The generated instruction item in some embodiments of the present disclosure is a basic element of an instruction, and the generated instruction item can determine the specific instruction generated by the random test generation module according to random constraints.
在一些示例中，在步骤S2中，指令属性项包括以下的至少一种：访存操作的指令类型、访存的源操作数、访存的目的操作数、访存范围大小、访存基址、访存地址偏移、访存变址、访问元素的颗粒度。In some examples, in step S2, the instruction attribute item includes at least one of the following: the instruction type of the memory access operation, the source operand of the memory access, the destination operand of the memory access, the size of the memory access range, and the base address of the memory access , access address offset, access index, granularity of access elements.
在一些示例中，对于步骤S3，基于至少一个生成指令项获取第一访存指令包括以下过程或步骤：利用随机化函数对至少一个生成指令项进行随机，获取第一访存指令。如此，本公开的实施例能够实现指令产生随机访存并随机注入页表错误的测试用例的生成，从而实现页表转换表访问是否异常的验证。In some examples, for step S3, obtaining the first memory access instruction based on the at least one generated instruction item includes the following process or steps: using a randomization function to randomize the at least one generated instruction item to obtain the first memory access instruction. In this way, the embodiments of the present disclosure can realize the generation of test cases in which instructions generate random memory access and randomly inject page table errors, so as to verify whether the access to the page table conversion table is abnormal.
在一些示例中，随机化函数是SystemVerilog的随机约束randomize()函数。当然，此仅仅为示例性的，并不为本公开的实施例的限制。In some examples, the randomization function is SystemVerilog's random constrained randomize() function. Certainly, this is only exemplary, and is not a limitation of the embodiments of the present disclosure.
在一些示例中，对于步骤S4，获取用于第一访存指令的指令注入页表需求包括以下过程或步骤：获取第二随机变量，并基于第二随机变量使得随机地对第一访存指令注入页表错误或者不注入页表错误。In some examples, for step S4, obtaining the instruction injection page table requirements for the first memory access instruction includes the following process or steps: obtaining a second random variable, and making the first memory access instruction randomly based on the second random variable Inject page table faults or not inject page table faults.
本公开的实施例通过随机地确定是否对访存指令注入页表错误可以增加测试场景的复杂性，覆盖到更多的随机测试场景。The embodiment of the present disclosure can increase the complexity of the test scenario by randomly determining whether to inject a page table fault into the memory access instruction, covering more random test scenarios.
在一些示例中，本公开的实施例可以基于一个第二随机变量，在每次生成一条访存指令时控制该第二随机变量的随机值是否为1(例如设置10％的概率让其值为1)来确定是否对第一访存指令注入页表错误。例如，若第二随机变量的随机值是1，则控制该条访存指令的生成指令项从而用来生成一条会产生页表访问异常的访存指令(即第二目标指令)。当然，此仅仅为示例性的，并不为本公开的实施例的限制。In some examples, the embodiments of the present disclosure may be based on a second random variable, and control whether the random value of the second random variable is 1 each time a memory access instruction is generated (for example, setting a probability of 10% so that its value is 1) to determine whether to inject a page table error into the first memory access instruction. For example, if the random value of the second random variable is 1, the generation instruction item of the memory access instruction is controlled so as to generate a memory access instruction (that is, the second target instruction) that will generate a page table access exception. Certainly, this is only exemplary, and is not a limitation of the embodiments of the present disclosure.
在一些示例中，本公开的实施例的验证方法还包括以下过程或步骤T2：基于第一访存指令中的访存范围大小以及访问元素的颗粒度，获取掩码寄存器的有效位信号，例如，掩码寄存器的有效位信号用于确定第一访存指令是否支持异常抑制(FaultSuppression)。In some examples, the verification method of the embodiment of the present disclosure further includes the following process or step T2: based on the size of the memory access range in the first memory access instruction and the granularity of the elements to be accessed, obtain a valid bit signal of the mask register, for example , the effective bit signal of the mask register is used to determine whether the first memory access instruction supports exception suppression (FaultSuppression).
在一些示例中，在步骤T2中，对于支持异常抑制的访存指令，在掩码寄存器的有效位信号中对应bit是1的内存颗粒，被认为是真正的被读取并且用于指令计算。In some examples, in step T2, for a memory access instruction that supports exception suppression, memory particles whose corresponding bit is 1 in the effective bit signal of the mask register are considered to be actually read and used for instruction calculation.
本公开一些实施例的验证方法能够结合操作掩码和异常抑制的特性，实现对访存指令中具有操作掩码以及不同异常抑制属性发生页表异常场景的全面验证，通过不同场景组合可测出一些意想不到的设计缺陷。The verification method in some embodiments of the present disclosure can combine the characteristics of operation mask and exception suppression to realize comprehensive verification of page table exception scenarios with operation masks and different exception suppression attributes in memory access instructions, which can be detected by combining different scenarios Some unexpected design flaws.
例如，对于步骤S5，在一些示例中，基于指令注入页表需求和第一访存指令获取第二目标指令包括以下过程或步骤S51：响应于指令注入页表需求为对第一访存指令不注入页表错误，获取正常的第二目标指令。For example, for step S5, in some examples, obtaining the second target instruction based on the instruction injection page table requirement and the first memory access instruction includes the following process or step S51: responding to the instruction injection page table requirement is not for the first memory access instruction Injects page table faults, fetches normal second target instructions.
例如，对于步骤S5，在另一些示例中，基于指令注入页表需求和第一访存指令获取第二目标指令包括以下过程或步骤S52：响应于指令注入页表需求为对第一访存指令注入页表错误，获取异常的第二目标指令。For example, for step S5, in some other examples, obtaining the second target instruction based on the instruction injection page table requirement and the first memory access instruction includes the following process or step S52: responding to the instruction injection page table requirement for the first memory access instruction Inject a page table fault, get the exception's second target instruction.
图2为本公开一些实施例提供的步骤S52的流程图。Fig. 2 is a flowchart of step S52 provided by some embodiments of the present disclosure.
例如，如图2所示，验证方法中的步骤S52包括步骤S521至步骤S523。For example, as shown in FIG. 2, step S52 in the verification method includes step S521 to step S523.
步骤S521、响应于指令注入页表需求为对第一访存指令注入页表错误，调整访存地址偏移和/或访存基址，指向页面转换表中的保留地址空间，其中，保留地址空间配置为被指向访问时产生页表异常。Step S521: In response to the instruction injection page table requirement, in order to inject a page table error into the first memory access instruction, adjust the memory access address offset and/or the memory access base address to point to the reserved address space in the page translation table, wherein the reserved address A page table exception is generated when the space is configured to be accessed.
步骤S522、基于掩码寄存器的有效位信号，获取页表异常影响结果。Step S522 , based on the valid bit signal of the mask register, obtain the page table exception impact result.
步骤S523、响应于页表异常影响结果为不影响，获取异常的第二目标指令；或者，响应于页表异常影响结果为影响，获取页表异常预处理子程序并且获取异常的第二目标指令。Step S523, in response to the result of the abnormal impact of the page table being no impact, acquire the second target instruction of the exception; or, in response to the impact of the abnormal impact of the page table, acquire the page table exception preprocessing subroutine and acquire the second target instruction of the exception .
在一些示例中，在第一访存指令产生了页表异常错误，若指令程序中没有对异常做特殊处理，则程序无法继续执行该第一访存指令后面的其它指令流。由此，本公开的实施例能够结合指令操作数中操作掩码寄存器以及访存指令是否支持异常抑制来注入页表错误，判断是否会产生实际的页表错误的异常，并且实现对页表错误预处理的子程序，使得本公开的实施例可以通过异常预处理子程序完成对异常的处理并返回到产生异常的访存指令(即一条异常的第二目标指令)之后继续执行后面的指令序列(即对应随机生成的第一访存指令)，从而可以解决程序测试效率受影响的问题。In some examples, a page table exception error occurs in the first memory access instruction. If the exception is not specially handled in the instruction program, the program cannot continue to execute other instruction streams following the first memory access instruction. Therefore, the embodiments of the present disclosure can inject page table errors in combination with the operation mask register in the instruction operand and whether the memory access instruction supports exception suppression, determine whether an actual page table error exception will occur, and realize page table error detection. The preprocessing subroutine, so that the embodiments of the present disclosure can complete the exception processing through the exception preprocessing subroutine and return to the memory access instruction that generated the exception (that is, an abnormal second target instruction) and continue to execute the following instruction sequence (that is, corresponding to the randomly generated first memory access instruction), so as to solve the problem that the efficiency of program testing is affected.
在一些示例中，本公开的实施例的验证方法还包括以下过程或步骤T3：对获取的第二目标指令进行计数，判断获取的第二目标指令的数目是否小于期望生成的随机指令总数：若是，则重复上述步骤继续获取另外的第二目标指令，直至获取的第二目标指令的数目达到期望生成的随机指令总数；若否，则对应生成完整的测试激励源文件。In some examples, the verification method of the embodiment of the present disclosure further includes the following process or step T3: count the acquired second target instructions, and determine whether the number of acquired second target instructions is less than the total number of random instructions expected to be generated: if , then repeat the above steps and continue to obtain another second target instruction until the number of acquired second target instructions reaches the total number of random instructions expected to be generated; if not, correspondingly generate a complete test stimulus source file.
需要说明的是，本公开的实施例对期望生成的随机指令总数的具体数目不作限制，这可根据实际情况进行自由调整，此处不再穷举和赘述。It should be noted that the embodiments of the present disclosure do not limit the specific number of the total number of random instructions that are expected to be generated, which can be freely adjusted according to actual conditions, and will not be exhaustive and repeated here.
图3为本公开一些实施例提供的用于处理器的验证方法中的随机生成指令的方法的流程图。FIG. 3 is a flowchart of a method for randomly generating instructions in a processor verification method provided by some embodiments of the present disclosure.
例如，如图3所示，用于处理器的验证方法中的随机生成指令的方法包括步骤P1至步骤P11。For example, as shown in FIG. 3 , the method for randomly generating instructions in the verification method for a processor includes steps P1 to P11.
步骤P1、获取至少一个生成指令项，生成指令项包括由掩码寄存器中的数值确定的操作掩码以及用于访存操作的至少一个指令属性项。Step P1. Obtain at least one generated instruction item, which includes an operation mask determined by the value in the mask register and at least one instruction attribute item used for a memory access operation.
步骤P2、获取用于访存操作的页面转换表。Step P2, obtaining a page conversion table used for a memory fetch operation.
步骤P3、初始化掩码寄存器，以确定掩码寄存器中的数值。Step P3, initialize the mask register to determine the value in the mask register.
步骤P4、利用随机化函数对至少一个生成指令项进行随机，获取第一访存指令。Step P4, using a randomization function to randomize at least one generated instruction item to obtain a first memory access instruction.
步骤P5、基于第一访存指令中的访存范围大小以及访问元素的颗粒度，获取掩码寄存器的有效位信号，掩码寄存器的有效位信号用于确定第一访存指令是否支持异常抑制。Step P5, based on the size of the memory access range in the first memory access instruction and the granularity of the access elements, obtain the valid bit signal of the mask register, and the valid bit signal of the mask register is used to determine whether the first memory access instruction supports exception suppression .
步骤P6、获取用于第一访存指令的指令注入页表需求，判断指令注入页表需求是否为对第一访存指令进行注入页表错误：若是，即指令注入页表需求为对第一访存指令注入页表错误，则继续执行步骤P7；若否，即指令注入页表需求为对第一访存指令不注入页表错误，则转至步骤P11。Step P6. Obtain the instruction injection page table requirement for the first memory access instruction, and determine whether the instruction injection page table requirement is an injection page table error for the first memory access instruction: if yes, the instruction injection page table requirement is for the first memory access instruction. If the memory access instruction injects a page table error, continue to execute step P7; if not, that is, the instruction injection page table requirement is not to inject a page table error for the first memory access instruction, then go to step P11.
步骤P7、调整访存地址偏移和/或访存基址，指向页面转换表中的保留地址空间，其中，保留地址空间配置为被指向访问时产生页表异常。Step P7, adjusting the memory access address offset and/or the memory access base address to point to the reserved address space in the page translation table, wherein the reserved address space is configured to generate a page table exception when being pointed to and accessed.
步骤P8、基于掩码寄存器的有效位信号获取页表异常影响结果，判断是否产生真正的页表异常：若是，即页表异常影响结果为影响，则继续执行步骤P9；若否，即页表异常影响结果为不影响，则转至步骤P10。Step P8, based on the effective bit signal of the mask register to obtain the result of the abnormal impact of the page table, and judge whether a real page table abnormality occurs: if yes, that is, the result of the abnormal impact of the page table is affected, then continue to perform step P9; if not, the page table If the result of abnormal influence is no influence, go to step P10.
步骤P9、获取页表异常预处理子程序，再继续执行步骤P10。Step P9, obtain the page table exception preprocessing subroutine, and then continue to execute step P10.
步骤P10、获取异常的第二目标指令。Step P10, acquire the abnormal second target instruction.
步骤P11、获取正常的第二目标指令。Step P11, obtaining a normal second target instruction.
在一些示例中，本公开的实施例的第二目标指令为随机访存指令。In some examples, the second target instruction of the embodiments of the present disclosure is a random access instruction.
本公开上述实施例的验证方法可以实现针对指令访存中存在操作掩码的随机注入页表错误的随机测试激励的生成，从而完成对访存指令页表异常的验证。本公开上述实施例的验证方法不仅能够保证验证能够覆盖到随机注入一些指令异常的场景，也能保证处理器在进入处理异常程序之后也可以继续执行测试激励中其它的指令序列。本公开上述实施例不但可以用于处理器访存模块的例如内核集簇top级针对高级向量扩展指令随机注入页表错误测试激励的产生，还可以用于扩展生成其它高级向量扩展指令异常的测试激励的产生。本公开上述实施例生成的随机测试激励指令序列还可以和其它的随机测试激励指令序列混合，构建生成更复杂的汇编程序，从而覆盖到更多的随机测试场景。本公开上述实施例不仅可以能够保证验证能够覆盖到随机注入一些指令异常的场景，还能保证处理器在进入处理异常程序之后也能继续执行测试激励中其它的指令序列，可以避免程序测试效率受影响。The verification method of the above-mentioned embodiments of the present disclosure can realize the generation of random test stimulus for random injection of page table errors with operation masks in instruction memory access, thereby completing the verification of page table exceptions of memory access instructions. The verification method of the above-mentioned embodiments of the present disclosure can not only ensure that the verification can cover scenarios where some instruction exceptions are randomly injected, but also ensure that the processor can continue to execute other instruction sequences in the test stimulus after entering the exception handling program. The above-mentioned embodiments of the present disclosure can not only be used for the generation of test incentives for random injection of page table errors for advanced vector extension instructions at the top level of the core cluster of the processor memory access module, but also can be used for extending and generating abnormal tests for other advanced vector extension instructions generation of incentives. The random test stimulus instruction sequence generated by the above-mentioned embodiments of the present disclosure can also be mixed with other random test stimulus instruction sequences to construct and generate a more complex assembly program, thereby covering more random test scenarios. The above embodiments of the present disclosure can not only ensure that the verification can cover the scene where some instruction exceptions are randomly injected, but also ensure that the processor can continue to execute other instruction sequences in the test stimulus after entering the exception handling program, which can avoid program test efficiency from being affected. Influence.
例如，如图3所示，步骤P1至步骤P11是一次序的随机生成第二目标指令的方法步骤(如图3所示的次序0，比如可以记为seq0)，每一次序均对应生成一个第二目标指令。For example, as shown in Figure 3, step P1 to step P11 are the method steps (order 0 as shown in Figure 3 shown in Figure 3, can be denoted as seq0 for example) of the method step (order 0 shown in Figure 3) of a sequence randomly generating the second target instruction, and each sequence all corresponds to generate a Second target instruction.
例如，如图3所示，本公开的实施例的验证方法还包括：For example, as shown in Figure 3, the verification method of the embodiment of the present disclosure also includes:
步骤P12、对第二目标指令进行计数，并且判断计数得到的指令数目是否小于期望生成的随机指令总数N，N为大于等于1的整数：若是，则跳转至步骤P4并且循环执行上述步骤继续生成下一条第二目标指令，直至生成需要的所有的第二目标指令；若否，则跳转至步骤P13。Step P12, count the second target instructions, and judge whether the number of instructions counted is less than the total number of random instructions N expected to be generated, N is an integer greater than or equal to 1: if so, jump to step P4 and execute the above steps in a loop to continue Generate the next second target instruction until all required second target instructions are generated; if not, go to step P13.
步骤P13、根据获取的N个第二目标指令去生成完整的测试激励源文件。Step P13: Generate a complete test stimulus source file according to the acquired N second target instructions.
在一些示例中，期望生成的随机指令总数N可以由用户进行控制和确定，并且其作为随机生成第二目标指令的方法的循环结束机制的条件。In some examples, the total number N of random instructions expected to be generated can be controlled and determined by the user, and it serves as a condition for the loop-ending mechanism of the method for randomly generating the second target instruction.
图4为本公开一些实施例提供的生成测试激励源文件的原理示意图。Fig. 4 is a schematic diagram of the principle of generating test stimulus source files provided by some embodiments of the present disclosure.
在一些示例中，本公开的实施例通过针对不同测试场景的次序之间随机组合，可以构建更为强大的测试激励，极大地丰富了测试激励的复杂性。In some examples, the embodiments of the present disclosure can construct more powerful test stimuli by randomly combining the orders of different test scenarios, which greatly enriches the complexity of the test stimuli.
例如，如图4所示，本公开的实施例通过针对不同测试场景的次序0、次序1、次序2直至次序N之间的随机组合，可以生成完整的测试激励源文件，这样可极大地丰富测试激励的复杂性，从而能够帮助验证环境发现更多隐藏的设计问题。For example, as shown in FIG. 4 , the embodiment of the present disclosure can generate a complete test stimulus source file by randomly combining order 0, order 1, order 2 and order N for different test scenarios, which can greatly enrich The complexity of test stimuli can help the verification environment find more hidden design problems.
图5为本公开一些实施例提供的一种用于处理器的验证系统的框图。Fig. 5 is a block diagram of a verification system for a processor provided by some embodiments of the present disclosure.
例如，如图5所示，本公开至少一实施例提供的用于处理器的验证系统100包括页面转换表获取模块101、生成指令项获取模块102、第一指令获取模块103、指令注入页表需求获取模块104和第二指令获取模块105。For example, as shown in FIG. 5 , a verification system 100 for a processor provided by at least one embodiment of the present disclosure includes a page conversion table acquisition module 101, a generated instruction item acquisition module 102, a first instruction acquisition module 103, and an instruction injection page table A requirement acquisition module 104 and a second instruction acquisition module 105 .
页面转换表获取模块101被配置为获取用于访存操作的页面转换表。生成指令项获取模块102被配置为获取至少一个生成指令项，生成指令项包括由掩码寄存器中的数值确定的操作掩码以及用于访存操作的至少一个指令属性项。第一指令获取模块103被配置为基于生成指令项获取第一访存指令。指令注入页表需求获取模块104被配置为获取用于第一访存指令的指令注入页表需求，指令注入页表需求包括对第一访存指令注入页表错误或者对第一访存指令不注入页表错误。第二指令获取模块105被配置为基于指令注入页表需求和第一访存指令获取第二目标指令，第二目标指令用于验证访问页表转换表是否异常。The page conversion table obtaining module 101 is configured to obtain a page conversion table used for a memory fetch operation. The generating instruction item acquiring module 102 is configured to acquire at least one generating instruction item, which includes an operation mask determined by a value in a mask register and at least one instruction attribute item for a memory access operation. The first instruction obtaining module 103 is configured to obtain the first memory access instruction based on the generated instruction item. The instruction injection page table requirement obtaining module 104 is configured to obtain the instruction injection page table requirement for the first memory access instruction, where the instruction injection page table requirement includes injecting a page table error into the first memory access instruction or incorrectly injecting the first memory access instruction. Inject page table faults. The second instruction acquisition module 105 is configured to acquire a second target instruction based on the instruction injection page table requirement and the first memory access instruction, and the second target instruction is used to verify whether the access page table translation table is abnormal.
需要注意的是，在本公开的实施例中，该用于处理器的验证系统100可以包括更多或更少的模块，并且各个模块之间的连接关系不受限制，可以根据实际需求而定。各个模块的具体构成方式不受限制。关于用于处理器的验证系统100的技术效果可以参考本公开上述实施例中提供的用于处理器的验证方法的技术效果，这里不再赘述。It should be noted that, in the embodiment of the present disclosure, the verification system 100 for a processor may include more or fewer modules, and the connection relationship between each module is not limited, and may be determined according to actual needs . The specific configuration of each module is not limited. Regarding the technical effects of the verification system 100 for processors, reference may be made to the technical effects of the verification methods for processors provided in the above embodiments of the present disclosure, which will not be repeated here.
以上实施例中的各个模块可被分别配置为执行特定功能的软件、硬件、固件或上述项的任意组合。例如，这些模块可对应于专用的集成电路，也可对应于纯粹的软件代码，还可对应于软件与硬件相结合的模块。Each module in the above embodiments can be respectively configured as software, hardware, firmware or any combination of the above-mentioned items to perform specific functions. For example, these modules may correspond to dedicated integrated circuits, may also correspond to pure software codes, and may also correspond to modules combining software and hardware.
需要说明的是，尽管以上在描述用于处理器的验证系统时将其划分为用于分别执行相应处理的模块，然而，本领域技术人员清楚的是，各模块执行的处理也可以在验证系统不进行任何具体模块划分或者各模块之间并无明确划界的情况下执行。It should be noted that although the verification system for the processor is described above as modules for respectively executing corresponding processing, it is clear to those skilled in the art that the processing performed by each module can also be performed in the verification system Execute without any specific module division or without clear boundaries between modules.
图6为本公开至少一实施例提供的一种电子设备的结构示意图。本公开实施例中的终端设备可以包括但不限于诸如移动电话、笔记本电脑、数字广播接收器、PDA(个人数字助理)、PAD(平板电脑)、PMP(便携式多媒体播放器)、车载终端(例如车载导航终端)等等的移动终端以及诸如数字TV、台式计算机等等的固定终端。图6示出的电子设备仅仅是一个示例，不应对本公开实施例的功能和使用范围带来任何限制。Fig. 6 is a schematic structural diagram of an electronic device provided by at least one embodiment of the present disclosure. The terminal equipment in the embodiment of the present disclosure may include but not limited to such as mobile phone, notebook computer, digital broadcast receiver, PDA (personal digital assistant), PAD (tablet computer), PMP (portable multimedia player), vehicle terminal (such as mobile terminals such as car navigation terminals) and fixed terminals such as digital TVs, desktop computers and the like. The electronic device shown in FIG. 6 is only an example, and should not limit the functions and application scope of the embodiments of the present disclosure.
例如，如图6所示，在一些示例中，电子设备200包括处理装置(例如中央处理器、图形处理器等)201，其可以根据存储在只读存储器(ROM)202中的程序或者从存储装置208加载到随机访问存储器(RAM)203中的程序而执行如上所述的验证方法。在RAM203中，还存储有计算机系统操作所需的各种程序和数据。处理装置201、ROM202以及RAM203通过总线204彼此相连。输入/输出(I/O)接口205也连接至总线204。For example, as shown in FIG. 6 , in some examples, an electronic device 200 includes a processing device (such as a central processing unit, a graphics processing unit, etc.) The device 208 loads the program in the random access memory (RAM) 203 to execute the verification method as described above. Various programs and data necessary for the operation of the computer system are also stored in the RAM 203 . The processing device 201 , ROM 202 and RAM 203 are connected to each other through a bus 204 . An input/output (I/O) interface 205 is also connected to the bus 204 .
例如，以下部件可以连接至I/O接口205：包括例如触摸屏、触摸板、键盘、鼠标、摄像头、麦克风、加速度计、陀螺仪等的输入装置206；包括诸如液晶显示器(LCD)、扬声器、振动器等的输出装置207；包括例如磁带、硬盘等的存储装置208；以及包括诸如LAN卡、调制解调器等的网络接口卡的通信装置209。通信装置209可以允许电子设备200与其他设备进行无线或有线通信以交换数据，经由诸如因特网的网络执行通信处理。驱动器210也根据需要连接至I/O接口205。可拆卸介质211，诸如磁盘、光盘、磁光盘、半导体存储器等等，根据需要安装在驱动器210上，以便于从其上读出的计算机程序根据需要被安装入存储装置209。虽然图6示出了包括各种装置的电子设备200，但是应理解的是，并不要求实施或包括所有示出的装置。可以替代地实施或包括更多或更少的装置。For example, the following components may be connected to I/O interface 205: input devices 206 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; storage device 208 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 209 including a network interface card such as a LAN card, a modem, or the like. The communication means 209 may allow the electronic device 200 to perform wireless or wired communication with other devices to exchange data, perform communication processing via a network such as the Internet. A drive 210 is also connected to the I/O interface 205 as needed. A removable medium 211, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 210 as necessary so that a computer program read therefrom is installed into the storage device 209 as necessary. While FIG. 6 illustrates electronic device 200 including various means, it should be understood that implementing or including all of the illustrated means is not a requirement. Additional or fewer devices may alternatively be implemented or included.
例如，该电子设备200还可以进一步包括外设接口(图中未示出)等。该外设接口可以为各种类型的接口，例如为USB接口、闪电(lighting)接口等。该通信装置209可以通过无线通信来与网络和其他设备进行通信，该网络例如为因特网、内部网和/或诸如蜂窝电话网络之类的无线网络、无线局域网(LAN)和/或城域网(MAN)。无线通信可以使用多种通信标准、协议和技术中的任何一种，包括但不局限于全球移动通信系统(GSM)、增强型数据GSM环境(EDGE)、宽带码分多址(W-CDMA)、码分多址(CDMA)、时分多址(TDMA)、蓝牙、Wi-Fi(例如基于IEEE802.11a、IEEE802.11b、IEEE802.11g和/或IEEE802.11n标准)、基于因特网协议的语音传输(VoIP)、Wi-MAX，用于电子邮件、即时消息传递和/或短消息服务(SMS)的协议，或任何其他合适的通信协议。For example, the electronic device 200 may further include a peripheral interface (not shown in the figure) and the like. The peripheral interface may be various types of interfaces, for example, a USB interface, a lightning (lightning) interface, and the like. The communication means 209 may communicate with a network and other devices by wireless communication, such as the Internet, an intranet and/or a wireless network such as a cellular telephone network, a wireless local area network (LAN) and/or a metropolitan area network ( MAN). Wireless communications can use any of a variety of communications standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA) , Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g. based on IEEE802.11a, IEEE802.11b, IEEE802.11g and/or IEEE802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and/or Short Message Service (SMS), or any other suitable communication protocol.
例如，电子设备可以为手机、平板电脑、笔记本电脑、电子书、游戏机、电视机、数码相框、导航仪等任何设备，也可以为任意的电子设备及硬件的组合，本公开的实施例对此不作限制。For example, an electronic device can be any device such as a mobile phone, a tablet computer, a notebook computer, an e-book, a game console, a TV set, a digital photo frame, a navigator, or any combination of electronic devices and hardware. This is not limited.
例如，根据本公开的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在非暂态计算机可读介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信装置209从网络上被下载和安装，或者从存储装置208被安装，或者从ROM202被安装。在该计算机程序被处理装置201执行时，执行本公开实施例的方法中限定的上述用于处理器的验证功能。For example, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product, which includes a computer program carried on a non-transitory computer readable medium, where the computer program includes program code for executing the method shown in the flowchart. In such an embodiment, the computer program may be downloaded and installed from a network via communication means 209, or from storage means 208, or from ROM 202. When the computer program is executed by the processing device 201, the above-mentioned verification function for the processor defined in the method of the embodiment of the present disclosure is executed.
需要说明的是，本公开上述的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本公开的实施例中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本公开的实施例中，计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读信号介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：电线、光缆、RF(射频)等等，或者上述的任意合适的组合。It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, electrical connections with one or more wires, portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable Programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above. In the embodiments of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the embodiments of the present disclosure, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device . Program code embodied on a computer readable medium may be transmitted by any appropriate medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.
在一些实施方式中，客户端、服务器可以利用诸如HTTP(HyperTextTransferProtocol，超文本传输协议)之类的任何当前已知或未来研发的网络协议进行通信，并且可以与任意形式或介质的数字数据通信(例如，通信网络)互连。通信网络的示例包括局域网(“LAN”)，广域网(“WAN”)，网际网(例如，互联网)以及端对端网络(例如，adhoc端对端网络)，以及任何当前已知或未来研发的网络。In some embodiments, the client and the server can communicate using any currently known or future-developed network protocols such as HTTP (HyperTextTransferProtocol, Hypertext Transfer Protocol), and can communicate with digital data in any form or medium ( For example, communication networks) interconnect. Examples of communication networks include local area networks ("LANs"), wide area networks ("WANs"), internetworks (e.g., the Internet), and peer-to-peer networks (e.g., adhoc peer-to-peer networks), as well as any currently known or future developed network.
上述计算机可读介质可以是上述电子设备中所包含的；也可以是单独存在，而未装配入该电子设备中。The above-mentioned computer-readable medium may be included in the above-mentioned electronic device, or may exist independently without being incorporated into the electronic device.
需要说明的是，本公开的实施例中，电子设备200的具体功能和技术效果可以参考上文中关于用于处理器的验证方法的描述，此处不再赘述。It should be noted that, in the embodiments of the present disclosure, for the specific functions and technical effects of the electronic device 200 , reference may be made to the above description about the verification method for the processor, which will not be repeated here.
有以下几点需要说明：The following points need to be explained:
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。(1) Embodiments of the present disclosure The drawings only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to common designs.
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。(2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。The above description is only a specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be based on the protection scope of the claims.
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| CN117076330A (en)* | 2023-10-12 | 2023-11-17 | 北京开源芯片研究院 | Access verification method, system, electronic equipment and readable storage medium |
| CN119248286A (en)* | 2024-12-03 | 2025-01-03 | 北京麟卓信息科技有限公司 | A cross-memory page difference compatible operation method based on memory access instruction reconstruction |
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| CN117076330A (en)* | 2023-10-12 | 2023-11-17 | 北京开源芯片研究院 | Access verification method, system, electronic equipment and readable storage medium |
| CN117076330B (en)* | 2023-10-12 | 2024-02-02 | 北京开源芯片研究院 | Access verification method, system, electronic equipment and readable storage medium |
| CN119248286A (en)* | 2024-12-03 | 2025-01-03 | 北京麟卓信息科技有限公司 | A cross-memory page difference compatible operation method based on memory access instruction reconstruction |
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