技术领域technical field
本发明涉及微处理器技术领域，尤其涉及一种数字神经形态计算处理器及计算方法。The invention relates to the technical field of microprocessors, in particular to a digital neuromorphic computing processor and a computing method.
背景技术Background technique
目前发展人工智能的研究上分化出两条并行的方向：计算科学导向的人工神经网络和神经科学导向的脉冲神经网络。人工神经网络往往忽略掉神经科学中的底层细节，专注于在实际任务中提高准确率。脉冲从生物学神经元结构中得到启发，探索与大脑运行方式更相近的神经形态计算。近年来两类神经网络的研究开始出现交叉的趋势，包括二者之间的相互借鉴、转换与结合，近年来针对两类神经网络分别已提出了基于FPGA、ASIC和RRAM等新型器件的深度神经网络加速器与神经形态处理器两类专用硬件，然而两类硬件并不能很好地实现兼容。At present, there are two parallel directions in the development of artificial intelligence research: artificial neural network oriented by computing science and spiking neural network oriented by neuroscience. Artificial neural networks tend to ignore the low-level details in neuroscience and focus on improving accuracy in practical tasks. Inspired by the structure of biological neurons, Impulse explores neuromorphic computing that is closer to the way the brain operates. In recent years, the research on the two types of neural networks has begun to show a crossover trend, including the mutual reference, conversion and combination between the two. In recent years, for the two types of neural networks, deep neural networks based on new devices such as FPGA, ASIC and RRAM have been proposed. Network accelerators and neuromorphic processors are two types of dedicated hardware, but the two types of hardware are not well compatible.
现有技术中，采用单一的专用硬件作为通用平台，由于两类网络有明显差别，难以实现对两类网络的兼容，从而导致推理准确率和速度能效等性能下降。In the existing technology, a single dedicated hardware is used as a general platform. Due to the obvious differences between the two types of networks, it is difficult to achieve compatibility with the two types of networks, resulting in a decrease in performance such as inference accuracy and speed and energy efficiency.
发明内容Contents of the invention
本发明提供一种数字神经形态计算处理器及计算方法，用以解决现有技术中无法兼容两种神经网络的缺陷。The invention provides a digital neuromorphic computing processor and computing method, which are used to solve the defect that the two kinds of neural networks cannot be compatible in the prior art.
本发明提供一种数字神经形态计算处理器，包括依次连接的数据包路由模块、数据缓存模块、突触连接存储模块和神经元计算模块；The present invention provides a digital neuromorphic computing processor, comprising a sequentially connected data packet routing module, a data cache module, a synapse connection storage module and a neuron computing module;
所述数据包路由模块，用于获取神经网络输入数据，并将所述神经网络输入数据发送至所述数据缓存模块；The data packet routing module is used to obtain neural network input data, and send the neural network input data to the data cache module;
所述数据缓存模块，用于根据神经网络类型，对所述神经网络输入数据进行解码，以获得待处理数据，所述待处理数据包括脉冲神经网络脉冲信号或者人工神经网络激活值；The data cache module is used to decode the input data of the neural network according to the type of the neural network to obtain data to be processed, the data to be processed includes a pulse signal of a neural network or an activation value of an artificial neural network;
所述突触连接存储模块，用于存储神经网络突触权重值以及神经元参数；The synaptic connection storage module is used to store the synaptic weight value and neuron parameters of the neural network;
所述神经元计算模块，用于根据预先存储的神经网络突触权重值以及神经元参数，对所述待处理数据进行运算，并根据神经网络类型输出运算结果。The neuron calculation module is used to perform calculations on the data to be processed according to the pre-stored neural network synaptic weight values and neuron parameters, and output calculation results according to the type of neural network.
根据本发明提供的一种数字神经形态计算处理器，还包括外围存储接口模块；According to a digital neuromorphic computing processor provided by the present invention, it also includes a peripheral storage interface module;
所述外围存储接口模块，用于获取片外存储数据，并根据所述片外存储数据更新所述突触连接存储模块中的所述神经网络突触权重值和所述神经元参数。The peripheral storage interface module is configured to acquire off-chip storage data, and update the neural network synapse weight value and the neuron parameters in the synapse connection storage module according to the off-chip storage data.
根据本发明提供的一种数字神经形态计算处理器，所述数据包路由模块，还用于将所述运算结果编码为AER协议数据包，所述AER协议数据包包括目标发送地址、目标轴突地址、时间步长信息、脉冲信号或者激活值。According to a digital neuromorphic computing processor provided by the present invention, the data packet routing module is also used to encode the operation result into an AER protocol data packet, and the AER protocol data packet includes a target sending address, a target axon Addresses, time step information, pulse signals, or activation values.
根据本发明提供的一种数字神经形态计算处理器，所述突触连接存储模块由静态随机存取存储器和存储控制器构成；According to a digital neuromorphic computing processor provided by the present invention, the synaptic connection storage module is composed of a static random access memory and a storage controller;
每两个静态随机存取存储器组成乒乓缓存结构，用于存储所述神经网络突触权重值以及所述神经元参数；Every two static random access memories form a ping-pong cache structure for storing the synaptic weight value of the neural network and the neuron parameters;
所述存储控制器，用于调度所述神经网络突触权重值以及所述神经元参数。The storage controller is used for scheduling the synaptic weight values of the neural network and the neuron parameters.
根据本发明提供的一种数字神经形态计算处理器，所述根据神经网络类型，对所述神经网络输入数据进行解码，以获得待处理数据，包括：According to a digital neuromorphic computing processor provided by the present invention, the input data of the neural network is decoded according to the type of the neural network to obtain the data to be processed, including:
当所述神经网络类型为脉冲神经网络，则将所述神经网络输入数据解码为所述脉冲神经网络脉冲信号归分到所属的生物周期，并将所述生物周期对应的神经网络脉冲信号输入至所述神经元计算模块；When the type of the neural network is a pulse neural network, the input data of the neural network is decoded into the pulse signal of the pulse neural network and assigned to the biological cycle to which it belongs, and the neural network pulse signal corresponding to the biological cycle is input to The neuron computing module;
当所述神经网络类型为人工神经网络，则将所述神经网络输入数据解码为所述人工神经网络激活值并输入至所述神经元计算模块。When the neural network type is artificial neural network, the neural network input data is decoded into the artificial neural network activation value and input to the neuron computing module.
根据本发明提供的一种数字神经形态计算处理器，所述神经元计算模块由树形加法器、积分单元和脉冲发射单元构成；According to a digital neuromorphic computing processor provided by the present invention, the neuron computing module is composed of a tree adder, an integrating unit and a pulse emitting unit;
所述树形加法器，用于根据预先存储的神经网络突触权重值以及神经元参数，对所述神经网络输入数据进行加权求和；The tree adder is used to weight and sum the neural network input data according to the pre-stored neural network synaptic weight values and neuron parameters;
所述积分单元，用于将所述树形加法器的计算结果积分到膜电位上，并将积分后的膜电位输出至所述脉冲发射单元；The integration unit is used to integrate the calculation result of the tree adder to the membrane potential, and output the integrated membrane potential to the pulse emission unit;
所述脉冲发射单元，用于根据预先设置的脉冲发放阈值，与积分后的膜电位进行比较，并根据比较结果生成脉冲信号。The pulse emission unit is configured to compare the integrated membrane potential with the preset pulse emission threshold, and generate a pulse signal according to the comparison result.
根据本发明提供的一种数字神经形态计算处理器，所述神经元计算模块还包括泄露单元；According to a digital neuromorphic computing processor provided by the present invention, the neuron computing module further includes a leakage unit;
所述泄露单元，用于对所述膜电位进行泄露操作，所述泄露操作包括正向泄露和反向泄露。The leakage unit is configured to perform a leakage operation on the membrane potential, and the leakage operation includes forward leakage and reverse leakage.
根据本发明提供的一种数字神经形态计算处理器，所述神经元计算模块还包括阈值移位寄存器；According to a digital neuromorphic computing processor provided by the present invention, the neuron computing module further includes a threshold shift register;
所述阈值移位寄存器，用于将经过所述积分单元积分后的膜电位转换成激活值输出。The threshold value shift register is used to convert the membrane potential integrated by the integration unit into an activation value for output.
本发明还提供一种用于神经网络的计算方法，包括：The present invention also provides a calculation method for a neural network, comprising:
获取神经网络输入数据，以确定所述神经网络输入数据的神经网络类型；Acquiring neural network input data to determine the neural network type of the neural network input data;
根据预先存储的神经网络突触权重值以及神经元参数，对输入的待处理数据进行运算，并根据所述神经网络类型输出运算结果；According to the pre-stored neural network synaptic weight value and neuron parameters, the input data to be processed is calculated, and the calculation result is output according to the neural network type;
所述待处理数据是通过对神经网络输入数据解码获得的。The data to be processed is obtained by decoding the input data of the neural network.
根据本发明提供的一种用于神经网络的计算方法，还包括更新所述神经网络突触权重值以及所述神经元参数，具体为：According to a calculation method for a neural network provided by the present invention, it also includes updating the synaptic weight value of the neural network and the neuron parameters, specifically:
获取片外存储数据；Obtain off-chip storage data;
根据所述片外存储数据更新所述神经网络突触权重值和所述神经元参数。Updating the synaptic weight value of the neural network and the neuron parameters according to the off-chip storage data.
本发明还提供一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现如上述任一种所述用于神经网络的计算方法方法。The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and operable on the processor. Network computing method method.
本发明还提供一种非暂态计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现如上述任一种所述用于神经网络的计算方法方法。The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, any one of the above-mentioned computing methods for neural networks can be realized.
本发明提供的一种数字神经形态计算处理器及计算方法，该处理器通过数据包路由模块、数据缓存模块、突触连接存储模块和神经元计算模块，获取神经网络输入数据，以确定神经网络输入数据的神经网络类型，接着，根据预先存储的神经网络突触权重值以及神经元参数，对输入的脉冲神经网络脉冲信号或者人工神经网络激活值进行运算，并根据神经网络类型输出运算结果。现有的基于模型转换方法的计算处理器需要进行模型算法转换，导致出现明显的精度损失。而本发明既可以应用于脉冲神经网络，也可以应用于人工神经网络，并且无需进行模型算法转换，避免了模型转换过程中的精度损失。A digital neuromorphic computing processor and computing method provided by the present invention, the processor obtains input data of a neural network through a data packet routing module, a data cache module, a synaptic connection storage module and a neuron computing module to determine the neural network The neural network type of the input data, and then, according to the pre-stored neural network synaptic weight value and neuron parameters, the input pulse neural network pulse signal or artificial neural network activation value is calculated, and the calculation result is output according to the neural network type. Existing computing processors based on model conversion methods need to perform model algorithm conversion, resulting in significant loss of accuracy. However, the present invention can be applied not only to the pulse neural network, but also to the artificial neural network, and does not need to perform model algorithm conversion, thus avoiding the loss of precision in the process of model conversion.
附图说明Description of drawings
为了更清楚地说明本发明或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the present invention or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are the present invention. For some embodiments of the invention, those skilled in the art can also obtain other drawings based on these drawings without creative effort.
图1是本发明提供的数字神经形态计算处理器装置的结构示意图；Fig. 1 is a schematic structural diagram of a digital neuromorphic computing processor device provided by the present invention;
图2是本发明提供的神经元计算模块的结构示意图；Fig. 2 is a schematic structural diagram of a neuron computing module provided by the present invention;
图3是本发明提供的ReLU激活函数的实现方式示意图；Fig. 3 is a schematic diagram of the implementation of the ReLU activation function provided by the present invention;
图4是本发明提供的权值精度-扇出权衡的流程示意图；Fig. 4 is a schematic flow chart of the weight accuracy-fan-out trade-off provided by the present invention;
图5是本发明提供的扇入-扇出权衡的流程示意图；Fig. 5 is a schematic flow chart of the fan-in-fan-out trade-off provided by the present invention;
图6是本发明提供的用于神经网络的计算方法的流程示意图；Fig. 6 is a schematic flow chart of a calculation method for a neural network provided by the present invention;
图7是本发明提供的电子设备的结构示意图。Fig. 7 is a schematic structural diagram of an electronic device provided by the present invention.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明中的附图，对本发明中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention , but not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
目前发展人工智能的研究上分化出两条并行的方向：计算科学导向的人工神经网络和神经科学导向的脉冲神经网络。人工神经网络往往忽略掉神经科学中的底层细节，专注于在实际任务中提高准确率。脉冲从生物学神经元结构中得到启发，探索与大脑运行方式更相近的神经形态计算。近年来两类神经网络的研究开始出现交叉的趋势，包括二者之间的相互借鉴、转换与结合，近年来针对两类神经网络分别已提出了基于FPGA、ASIC和RRAM等新型器件的深度神经网络加速器与神经形态处理器两类专用硬件，然而两类硬件并不能很好地兼容对方所擅长的网络模型。At present, there are two parallel directions in the development of artificial intelligence research: artificial neural network oriented by computing science and spiking neural network oriented by neuroscience. Artificial neural networks tend to ignore the low-level details in neuroscience and focus on improving accuracy in practical tasks. Inspired by the structure of biological neurons, Impulse explores neuromorphic computing that is closer to the way the brain operates. In recent years, the research on the two types of neural networks has begun to show a crossover trend, including the mutual reference, conversion and combination between the two. In recent years, for the two types of neural networks, deep neural networks based on new devices such as FPGA, ASIC and RRAM have been proposed. Network accelerators and neuromorphic processors are two types of dedicated hardware. However, the two types of hardware are not well compatible with the network models that the other is good at.
为了解决现有技术存在的问题，本发明提供一种数字神经形态计算处理器，包括依次连接的数据包路由模块110、数据缓存模块120、突触连接存储模块130和神经元计算模块140；In order to solve the problems existing in the prior art, the present invention provides a digital neuromorphic computing processor, including a sequentially connected data packet routing module 110, a data cache module 120, a synaptic connection storage module 130, and a neuron computing module 140;
所述数据包路由模块110，用于获取神经网络输入数据，并将所述神经网络输入数据发送至所述数据缓存模块。The data packet routing module 110 is configured to acquire neural network input data, and send the neural network input data to the data cache module.
所述数据缓存模块120，用于根据神经网络类型，对所述神经网络输入数据进行解码，以获得待处理数据。The data cache module 120 is configured to decode the input data of the neural network according to the type of the neural network to obtain data to be processed.
所述突触连接存储模块130，用于存储神经网络突触权重值以及神经元参数。The synaptic connection storage module 130 is used for storing the synaptic weight values of the neural network and neuron parameters.
所述神经元计算模块140，用于根据预先存储的神经网络突触权重值以及神经元参数，对所述待处理数据进行运算，并根据神经网络类型输出运算结果。The neuron calculation module 140 is configured to perform calculations on the data to be processed according to the pre-stored neural network synaptic weight values and neuron parameters, and output calculation results according to the type of neural network.
具体地，参照图1，数据包路由模块110作为该计算处理器的主要通信模块。数据包路由模块110一方面接收东南西北四个方向输入的数据包，另一方面把本地神经元计算模块的输出编码为数据包，并把该数据包发送至对应的地址，实现神经元间的通信。数据包路由模块可以实现片级网络的一对多广播路由，并且通过芯片间的接口互连可以实现片级的网络规模扩展。Specifically, referring to FIG. 1 , the data packet routing module 110 serves as the main communication module of the computing processor. On the one hand, the data packet routing module 110 receives data packets input from the four directions of southeast, northwest, and on the other hand, encodes the output of the local neuron computing module into a data packet, and sends the data packet to the corresponding address to realize the communication between neurons. communication. The data packet routing module can realize one-to-many broadcast routing of the chip-level network, and can realize the scale expansion of the chip-level network through the interface interconnection between chips.
数据缓存模块120用于对数据包路由模块110获取到的神经网络输入数据进行解码。具体地，数据缓存模块120可以根据不同的网络类型对输入数据进行时空解码：在应用脉冲神经网络时，数据缓存模块将脉冲归分到所属的生物周期，并在每一次生物周期计数触发时将所包含的脉冲输入到神经元计算模块；在应用人工神经网络时，数据缓存模块将神经网络输入数据解码为人工神经网络激活值并输入到神经元计算模块。The data cache module 120 is used for decoding the neural network input data acquired by the data packet routing module 110 . Specifically, the data caching module 120 can perform spatiotemporal decoding on the input data according to different network types: when applying the spiking neural network, the data caching module classifies the spiking into the corresponding biological cycle, and when each biological cycle counting is triggered, the The contained pulses are input to the neuron computing module; when the artificial neural network is applied, the data cache module decodes the neural network input data into the artificial neural network activation value and inputs it to the neuron computing module.
突触连接存储模块130，用于存储神经网络突触权重值以及神经元参数。突触连接存储模块是一种用于神经网络芯片中的电路单元，用于实现神经元之间的连接。在神经网络中，神经元之间的连接通常是通过突触实现的。突触连接存储模块实现了高效、可重构的突触连接，从而支持复杂的神经网络计算。The synaptic connection storage module 130 is used for storing the synaptic weight values of the neural network and neuron parameters. The synaptic connection storage module is a circuit unit used in neural network chips to realize the connection between neurons. In neural networks, the connection between neurons is usually achieved through synapses. The synaptic connection storage module enables efficient and reconfigurable synaptic connections to support complex neural network computations.
神经元计算模块140，用于根据预先存储的神经网络突触权重值以及神经元参数，对待处理数据进行运算，并根据神经网络类型输出运算结果。神经元计算模块140作为该计算处理器的主要运算模块，可以通过设置加法器、泄露单元、积分器以及脉冲发射单元的方式实现。具体地，通过加法器实现输入与突触权重的与门输出累加，泄漏单元可以实现随机或确定的正向泄漏和反向泄漏，以实现膜电位向0收敛或发散，而积分模块将加法器的累加结果积分到膜电位上，最后脉冲发射单元根据膜电位与阈值电位的关系进行脉冲输出。The neuron calculation module 140 is configured to perform calculations on the data to be processed according to the pre-stored neural network synaptic weight values and neuron parameters, and output calculation results according to the type of the neural network. The neuron calculation module 140, as the main operation module of the calculation processor, can be realized by setting an adder, a leak unit, an integrator and a pulse emission unit. Specifically, the AND gate output accumulation of the input and the synaptic weight is realized through the adder, and the leakage unit can realize random or deterministic forward leakage and reverse leakage, so as to realize the convergence or divergence of the membrane potential to 0, and the integration module converts the adder The accumulative results are integrated to the membrane potential, and finally the pulse emission unit performs pulse output according to the relationship between the membrane potential and the threshold potential.
通过神经元计算模块140，可以实现脉冲神经网络算法和人工神经网络算法。Through the neuron computing module 140 , the spiking neural network algorithm and the artificial neural network algorithm can be realized.
脉冲神经网络算法如下：The spiking neural network algorithm is as follows:
Vj(t+1)＝Vj(t)+∑xiwij-λjVj (t+1)＝Vj (t)+∑xi wij -λj
其中Vj(t)为神经元j在t时刻的膜电位，wij为突触前神经元i和突触后神经元j的突触连接权值，xi为突触前神经元i的输出，λj为神经元j的线性泄漏。Where Vj (t) is the membrane potential of neuron j at time t, wij is the synaptic connection weight of pre-synaptic neuron i and post-synaptic neuron j, xi is the weight of pre-synaptic neuron i Output, λj is the linear leakage of neuron j.
人工神经网络算法如下：The artificial neural network algorithm is as follows:
yj＝f(∑xiwij+bj)yj ＝f(∑xi wij +bj )
其中yj为激活值输出，xi为激活值输入，wij为权值，bj为偏差值，f(x)为ReLU型激活函数。Among them, yj is the activation value output, xi is the activation value input, wij is the weight value, bj is the deviation value, and f(x) is the ReLU activation function.
本发明提供的一种数字神经形态计算处理器及计算方法，该处理器通过数据包路由模块、数据缓存模块、突触连接存储模块和神经元计算模块，获取神经网络输入数据，以确定神经网络输入数据的神经网络类型，接着，根据预先存储的神经网络突触权重值以及神经元参数，对输入的脉冲神经网络脉冲信号或者人工神经网络激活值进行运算，并根据神经网络类型输出运算结果。现有的基于模型转换方法的计算处理器需要进行模型算法转换，导致出现明显的精度损失。而本发明既可以应用于脉冲神经网络，也可以应用于人工神经网络，并且无需进行模型算法转换，避免了模型转换过程中的精度损失。A digital neuromorphic computing processor and computing method provided by the present invention, the processor obtains input data of a neural network through a data packet routing module, a data cache module, a synaptic connection storage module and a neuron computing module to determine the neural network The neural network type of the input data, and then, according to the pre-stored neural network synaptic weight value and neuron parameters, the input pulse neural network pulse signal or artificial neural network activation value is calculated, and the calculation result is output according to the neural network type. Existing computing processors based on model conversion methods need to perform model algorithm conversion, resulting in significant loss of accuracy. However, the present invention can be applied not only to the pulse neural network, but also to the artificial neural network, and does not need to perform model algorithm conversion, thus avoiding the loss of precision in the process of model conversion.
作为进一步可选的实施例，还包括外围存储接口模块；As a further optional embodiment, a peripheral storage interface module is also included;
所述外围存储接口模块150，用于获取片外存储数据，并根据所述片外存储数据更新所述突触连接存储模块中的所述神经网络突触权重值和所述神经元参数。The peripheral storage interface module 150 is configured to obtain off-chip storage data, and update the neural network synapse weight values and the neuron parameters in the synapse connection storage module according to the off-chip storage data.
外围存储接口模块150负责读取外部存储的DMA，可以配合突触连接存储模块130的乒乓缓存结构，在其中一块片上SRAM读写工作时，向另一块片上SRAM写入数据以更新权值和神经元参数。外围存储接口模块150可以解决片上参数量存储限制的问题，以实现更大的网络结构。The peripheral storage interface module 150 is responsible for reading the DMA stored externally, and can cooperate with the ping-pong cache structure of the synaptic connection storage module 130. When one of the on-chip SRAMs reads and writes, it writes data to the other on-chip SRAM to update the weights and neurons. meta parameters. The peripheral storage interface module 150 can solve the problem of on-chip parameter storage limitation, so as to realize a larger network structure.
作为进一步可选的实施例，所述数据包路由模块，还用于将所述运算结果编码为AER协议数据包，所述AER协议数据包包括目标发送地址、目标轴突地址、时间步长信息、脉冲信号或者激活值。As a further optional embodiment, the data packet routing module is further configured to encode the operation result into an AER protocol data packet, and the AER protocol data packet includes target sending address, target axon address, and time step information , pulse signal or activation value.
AER(Address-Event Representation)协议是一种用于神经元芯片通信的协议，它使用事件驱动的方式来传输信息。在AER协议中，每个神经元都被分配一个唯一的地址，并使用地址来标识神经元发送和接收的事件。AER协议中的数据包通常由两个部分组成：地址和事件类型。The AER (Address-Event Representation) protocol is a protocol for neuron chip communication, which uses an event-driven method to transmit information. In the AER protocol, each neuron is assigned a unique address, and addresses are used to identify the events sent and received by the neuron. A data packet in the AER protocol usually consists of two parts: address and event type.
地址部分包含发送和接收神经元的唯一标识符，通常是一个数字。事件类型部分描述了发生的事件类型，例如脉冲的有或者无。这种事件驱动的通信方式可以使神经元芯片在高速并行计算中进行高效的信息交换。The address part contains the unique identifier of the sending and receiving neuron, usually a number. The Event Type section describes the type of event that occurred, such as the presence or absence of a pulse. This event-driven communication method can enable neuron chips to perform efficient information exchange in high-speed parallel computing.
AER协议的优点之一是可以实现异步通信，即不需要时钟信号来同步发送和接收数据。本实施例通过采用AER协议进行传输可以减少通信延迟，并且使得多个神经元可以同时进行通信，从而提高了神经元芯片的计算效率。One of the advantages of the AER protocol is that it can realize asynchronous communication, that is, no clock signal is required to send and receive data synchronously. In this embodiment, the communication delay can be reduced by using the AER protocol for transmission, and multiple neurons can communicate at the same time, thereby improving the computing efficiency of the neuron chip.
作为进一步可选的实施例，所述突触连接存储模块由静态随机存取存储器和存储控制器构成；As a further optional embodiment, the synaptic connection storage module is composed of a static random access memory and a storage controller;
每两个静态随机存取存储器组成乒乓缓存结构，用于存储所述神经网络突触权重值以及所述神经元参数；Every two static random access memories form a ping-pong cache structure for storing the synaptic weight value of the neural network and the neuron parameters;
所述存储控制器，用于调度所述神经网络突触权重值以及所述神经元参数。The storage controller is used for scheduling the synaptic weight values of the neural network and the neuron parameters.
本实施例中，突触连接存储模块的设计和实现依赖于特定的神经网络算法和芯片架构。具体地，可以通过设置2组1024×1390比特的静态随机存取存储器(SRAM)组成乒乓缓存结构，以存储1024×1152比特的全连接交叉开关矩阵结构的突触连接权重与1024×238比特的神经元参数；再设置存储控制器，以负责调度与读写SRAM参数。In this embodiment, the design and implementation of the synaptic connection storage module depends on specific neural network algorithms and chip architectures. Specifically, a ping-pong cache structure can be formed by setting two groups of 1024×1390-bit static random access memories (SRAMs) to store the synaptic connection weights of the 1024×1152-bit fully connected crossbar matrix structure and the 1024×238-bit Neuron parameters; then set the storage controller to be responsible for scheduling and reading and writing SRAM parameters.
突触连接存储模块是神经网络芯片中非常重要的电路单元之一，它对神经网络的计算性能和能耗有着重要的影响。随着人工智能技术的不断发展，神经网络芯片的需求也在不断增加，突触连接存储模块的设计和实现也在不断优化和改进，为神经网络计算提供了强大的支持。The synaptic connection storage module is one of the very important circuit units in the neural network chip, which has an important impact on the computing performance and energy consumption of the neural network. With the continuous development of artificial intelligence technology, the demand for neural network chips is also increasing, and the design and implementation of synaptic connection storage modules are also continuously optimized and improved, providing strong support for neural network computing.
作为进一步可选的实施例，所述根据神经网络类型，对所述神经网络输入数据进行解码，以获得待处理数据，包括：As a further optional embodiment, the decoding of the neural network input data according to the neural network type to obtain the data to be processed includes:
当所述神经网络类型为脉冲神经网络，则将所述神经网络输入数据解码为所述脉冲神经网络脉冲信号归分到所属的生物周期，并将所述生物周期对应的神经网络脉冲信号输入至所述神经元计算模块；When the type of the neural network is a pulse neural network, the input data of the neural network is decoded into the pulse signal of the pulse neural network and assigned to the biological cycle to which it belongs, and the neural network pulse signal corresponding to the biological cycle is input to The neuron computing module;
当所述神经网络类型为人工神经网络，则将所述神经网络输入数据解码为所述人工神经网络激活值并输入至所述神经元计算模块。When the neural network type is artificial neural network, the neural network input data is decoded into the artificial neural network activation value and input to the neuron calculation module.
本实施例中，当AER数据包传输到神经元电路的接收端时，数据缓存模块可以帮助将这些数据包缓冲和存储到适当的位置。然后，通过数据缓存模块中的解码器等电路对这些数据包进行解码和分析，从而获取神经信号的相关信息。具体地，在不同的神经网络类型中，数据缓存模块可以根据不同的时空解码方式对脉冲进行处理和解码。在应用脉冲神经网络时，数据缓存模块将脉冲归分到所属的生物周期，并在每一次生物周期计数触发时将所包含的脉冲输入到神经元计算模块。这种时空解码方式可以帮助实现对神经元信息传递的模拟和模拟生物神经网络的特征。在应用人工神经网络时，数据缓存模块将1比特的脉冲信号整合为高精度的整数，并输入到神经元计算模块。这种时空解码方式可以帮助实现对人工神经网络的高效计算和精度控制。In this embodiment, when the AER data packets are transmitted to the receiving end of the neuron circuit, the data buffer module can help to buffer and store these data packets in an appropriate location. Then, these data packets are decoded and analyzed by circuits such as a decoder in the data cache module, so as to obtain relevant information of neural signals. Specifically, in different neural network types, the data cache module can process and decode pulses according to different spatio-temporal decoding methods. When applying the spiking neural network, the data cache module classifies the spikes into their biological cycles, and inputs the included spikes to the neuron computing module when each biological cycle count is triggered. This spatio-temporal decoding method can help realize the simulation of neuron information transmission and simulate the characteristics of biological neural networks. When applying the artificial neural network, the data cache module integrates the 1-bit pulse signal into a high-precision integer and inputs it to the neuron calculation module. This space-time decoding method can help realize efficient calculation and precision control of artificial neural networks.
作为进一步可选的实施例，所述神经元计算模块由树形加法器、积分单元和脉冲发射单元构成；As a further optional embodiment, the neuron calculation module is composed of a tree adder, an integration unit and a pulse emission unit;
所述树形加法器，用于根据预先存储的神经网络突触权重值以及神经元参数，对所述神经网络输入数据进行加权求和；The tree adder is used to weight and sum the neural network input data according to the pre-stored neural network synaptic weight values and neuron parameters;
所述积分单元，用于将所述树形加法器的计算结果积分到膜电位上，并将积分后的膜电位输出至所述脉冲发射单元；The integration unit is used to integrate the calculation result of the tree adder to the membrane potential, and output the integrated membrane potential to the pulse emission unit;
所述脉冲发射单元，用于根据预先设置的脉冲发放阈值，与积分后的膜电位进行比较，并根据比较结果生成脉冲信号。The pulse emission unit is configured to compare the integrated membrane potential with the preset pulse emission threshold, and generate a pulse signal according to the comparison result.
参考图2，神经元计算模块是神经元电路中的一个重要部分，用于对脉冲信号进行处理和计算。加法器是神经元计算模块的核心部分，用于将神经元接收到的多个输入脉冲信号相加，得到神经元的总输入电流值。通常，加法器可以通过电流分配器将输入电流进行加权，以实现不同输入信号的权重调节。积分器用于对神经元的总输入电流进行积分，得到神经元的膜电位值。脉冲发射单元用于检测神经元膜电位是否超过了阈值，并在超过阈值时产生一个输出脉冲。通常，脉冲发射单元可以通过比较器来实现神经元膜电位和阈值之间的比较，以决定是否发生脉冲输出。同时，发射单元还可以通过递增器来实现膜电位的重置，以模拟神经元脉冲输出后的电位变化。Referring to Fig. 2, the neuron calculation module is an important part of the neuron circuit, and is used for processing and calculating pulse signals. The adder is the core part of the neuron calculation module, which is used to add multiple input pulse signals received by the neuron to obtain the total input current value of the neuron. Usually, the adder can weight the input current through the current divider to realize the weight adjustment of different input signals. The integrator is used to integrate the total input current of the neuron to obtain the membrane potential value of the neuron. The pulse emission unit is used to detect whether the neuron membrane potential exceeds a threshold, and generates an output pulse when the threshold is exceeded. Usually, the pulse emission unit can realize the comparison between the neuron membrane potential and the threshold value through a comparator, so as to decide whether to generate a pulse output. At the same time, the firing unit can also reset the membrane potential through the stepper, so as to simulate the potential change after the neuron pulse output.
优选地，加法器可以采用稀疏优化加法器树单元(Sparse Optimized Adder TreeCell)，这是一种针对稀疏数据优化的树形加法器单元。在传统的树形加法器中，所有输入位都要参与运算，即使有些位为0。这样会浪费很多计算资源。而稀疏优化加法器树单元则利用输入数据的稀疏性质，在计算时仅考虑非零输入位，从而减少运算次数和功耗消耗。Preferably, the adder may use a sparse optimized adder tree unit (Sparse Optimized Adder TreeCell), which is a tree adder unit optimized for sparse data. In a traditional tree adder, all input bits are involved in the operation, even if some bits are 0. This will waste a lot of computing resources. The sparse optimized adder tree unit takes advantage of the sparse nature of the input data and only considers non-zero input bits during calculation, thereby reducing the number of operations and power consumption.
稀疏优化加法器树单元可以通过两个主要的优化方式实现：部分和计算和动态控制。部分和计算是指将输入数据分为两部分，一部分是稠密的，即大部分输入位为1，另一部分是稀疏的，即只有少数输入位为1。稠密的输入位可以直接计算，而稀疏的输入位可以通过动态控制的方式来减少计算次数。动态控制是指根据输入数据的特点，在计算过程中选择合适的路径来减少计算次数。这种方法可以根据输入数据的变化实时调整计算路径，从而提高运算效率。Sparse-optimized adder tree units can be implemented with two main optimizations: partial sum computation and dynamic control. Partial sum calculation refers to dividing the input data into two parts, one part is dense, that is, most of the input bits are 1, and the other part is sparse, that is, only a few input bits are 1. Dense input bits can be calculated directly, while sparse input bits can be dynamically controlled to reduce the number of calculations. Dynamic control refers to selecting an appropriate path in the calculation process to reduce the number of calculations according to the characteristics of the input data. This method can adjust the calculation path in real time according to the change of the input data, thereby improving the operation efficiency.
作为进一步可选的实施例，所述神经元计算模块还包括泄露单元；As a further optional embodiment, the neuron computing module further includes a leakage unit;
所述泄露单元，用于对所述膜电位进行泄露操作，所述泄露操作包括正向泄露和反向泄露。The leakage unit is configured to perform a leakage operation on the membrane potential, and the leakage operation includes forward leakage and reverse leakage.
参考图2，在本实施例中，泄露单元可以实现随机的或确定的正向泄漏和反向泄漏，可以实现膜电位向0收敛或发散。反映到脉冲神经网络算法中就是泄露单元产生了λj，λj为神经元j的线性泄漏。而反映到人工神经网络算法中就是泄露单元产生了bj，bj为偏差值。Referring to FIG. 2 , in this embodiment, the leakage unit can realize random or deterministic forward leakage and reverse leakage, and can realize the convergence or divergence of the membrane potential to 0. It is reflected in the spiking neural network algorithm that the leakage unit generates λj , and λj is the linear leakage of neuron j. It is reflected in the artificial neural network algorithm that the leakage unit generates bj , and bj is the deviation value.
作为进一步可选的实施例，所述神经元计算模块还包括阈值移位寄存器；As a further optional embodiment, the neuron computing module further includes a threshold shift register;
所述阈值移位寄存器，用于将经过所述积分单元积分后的膜电位转换成激活值输出。The threshold value shift register is used to convert the membrane potential integrated by the integration unit into an activation value for output.
本实施例中，通过设置阈值移位寄存器，可以实现ReLU激活函数。如图3所示，当电路设置为ReLU输出时，膜电位首先与初始阈值比较，如果膜电位超过初始阈值，则发射脉冲并且从膜电位中减去阈值，否则膜电位保持原值；一次比较后，初始阈值向右移1位，再次与右移1位后的膜电位进行比较，如此重复直到达到所设定的精度。如图5右所示，等效的量化输出为：In this embodiment, the ReLU activation function can be realized by setting a threshold shift register. As shown in Figure 3, when the circuit is set to ReLU output, the membrane potential is first compared with the initial threshold, if the membrane potential exceeds the initial threshold, a pulse is emitted and the threshold is subtracted from the membrane potential, otherwise the membrane potential remains the original value; a comparison Afterwards, the initial threshold is shifted to the right by 1 bit, and compared with the membrane potential shifted to the right by 1 bit again, and so on until the set precision is reached. As shown on the right of Figure 5, the equivalent quantized output is:
其中，yi为膜电位的等效量化输出，Vth为初始阈值，V(t)为当前的膜电位。Among them, yi is the equivalent quantitative output of the membrane potential, Vth is the initial threshold, and V(t) is the current membrane potential.
下面对本发明数字神经形态计算处理器的应用场景进行描述。The application scenarios of the digital neuromorphic computing processor of the present invention are described below.
如图4所示，本发明数字神经形态计算处理器可以用于权值精度-扇出权衡方法。As shown in FIG. 4 , the digital neuromorphic computing processor of the present invention can be used in a weight precision-fan-out trade-off method.
本发明采用的全连接交叉开关矩阵结构的突触权值为1比特，但可以通过组合树突来实现高精度权值。如图4，以M＝8为例，举例了在人工神经网络模式下的高精度权值实现方法。每M个子树突分为一组作为一个完整树突，每个子树突的膜电位累加完毕后进行加权再累加在一起得到完整神经元的膜电位，随后再进行神经元的其他运算，因此等效为1个M比特精度树突的膜电位累加，M的最大取值为8，即可以实现1～8比特任意精度的权值。相应地，每M个子树突组合后，电路的总扇出数量会减小到1024/M。图4展示了树突组合实现高精度权值的方法使用在人工神经网络模型的应用中，但这一方法也可以同样使用在脉冲神经网络模型的应用中。树突组合方法不需要实现高位宽的权值运算电路即可支持高精度权值模型，提升了电路的能效和面积效率，是一种灵活的权值精度-扇出权衡方法。The synaptic weight of the fully connected crossbar matrix structure adopted in the present invention is 1 bit, but high-precision weight can be realized by combining dendrites. As shown in FIG. 4 , taking M=8 as an example, the method for realizing high-precision weights in the artificial neural network mode is exemplified. Every M sub-dendrites are divided into a group as a complete dendrite. After the accumulation of the membrane potential of each sub-dendrite is completed, it is weighted and then accumulated together to obtain the membrane potential of the complete neuron, and then other operations of the neuron are performed. Therefore, etc. The effect is the accumulation of the membrane potential of a dendrite with M-bit precision, and the maximum value of M is 8, that is, weights with arbitrary precision of 1-8 bits can be realized. Correspondingly, after every M sub-dendrites are combined, the total fan-out number of the circuit will be reduced to 1024/M. Figure 4 shows that the method of combining dendrites to achieve high-precision weights is used in the application of the artificial neural network model, but this method can also be used in the application of the spiking neural network model. The dendritic combination method does not need to implement a high-bit-width weight operation circuit to support a high-precision weight model, which improves the energy efficiency and area efficiency of the circuit. It is a flexible weight precision-fan-out trade-off method.
如图5所示，本发明数字神经形态计算处理器可以用于扇入-扇出权衡方法。As shown in FIG. 5, the digital neuromorphic computing processor of the present invention can be used in a fan-in-fan-out trade-off method.
本实施例采用1024×1152比特全连接交叉开关矩阵结构突触连接，在常规情况下其最大扇入为1152。在实现更大神经网络时，可以通过组合树突来扩展扇入。如图5，以M＝4、P＝2为例，每M个子树突组合为完整树突后，在此基础上将P个完整树突组合为1个扩展树突，同时数据缓存模块划分输入为P组，每个扩展树突的第i个完整树突包含的子树突会接收来自第i组输入的脉冲数据，累加计算得到膜电位的中间结果，再将P个完整树突的膜电位中间结果累加在一起，得到最终的膜电位数值，再经过神经元的泄漏比较等操作。因此单个扩展树突所接收的扇入可以扩展到P×1152，P的取值范围为1～64，即扇入最大可以扩展到64×1152＝72K。相应地，电路的总扇出数量会减小到1024/(M×P)。图5展示了树突组合实现扇入扩展的方法使用在人工神经网络模型的应用中，但这一方法也可以使用在脉冲神经网络模型的应用中。树突组合方法不需要直接增加全连接交叉开关矩阵结构的轴突输入数目即可支持高扇入的神经网络模型，降低了对电路的面积要求，是一种灵活的扇入-扇出权衡方法。In this embodiment, a 1024×1152-bit fully-connected crossbar matrix structure is used for synaptic connections, and its maximum fan-in is 1152 under normal circumstances. When implementing larger neural networks, fan-in can be extended by combining dendrites. As shown in Figure 5, taking M=4 and P=2 as an example, after every M sub-dendrites are combined into a complete dendrite, on this basis, P complete dendrites are combined into an extended dendrite, and the data cache module is divided The input is P group, and the sub-dendrites contained in the i-th complete dendrite of each extended dendrite will receive the pulse data from the i-th group input, accumulate and calculate the intermediate result of the membrane potential, and then combine the P complete dendrites The intermediate results of the membrane potential are added together to obtain the final membrane potential value, and then undergo operations such as neuron leakage comparison. Therefore, the fan-in received by a single extended dendrite can be extended to P×1152, and the value range of P is 1-64, that is, the fan-in can be extended to a maximum of 64×1152=72K. Accordingly, the total fan-out number of the circuit is reduced to 1024/(M×P). Figure 5 shows that the method of dendrite combination to achieve fan-in expansion is used in the application of the artificial neural network model, but this method can also be used in the application of the spiking neural network model. The dendritic combination method does not need to directly increase the number of axon inputs of the fully connected crossbar matrix structure to support high-fan-in neural network models, which reduces the area requirements of the circuit, and is a flexible fan-in-fan-out trade-off method .
下面对本发明提供的用于神经网络的计算方法进行描述，参考图6，下文描述的用于神经网络的计算方法与上文描述的数字神经形态计算处理器可相互对应参照。The calculation method for the neural network provided by the present invention is described below. Referring to FIG. 6 , the calculation method for the neural network described below and the digital neuromorphic computing processor described above can be referred to in correspondence.
步骤610、获取神经网络输入数据，以确定所述神经网络输入数据的神经网络类型；Step 610, acquiring neural network input data to determine the neural network type of the neural network input data;
步骤620、根据预先存储的神经网络突触权重值以及神经元参数，对输入的待处理数据进行运算，并根据所述神经网络类型输出运算结果；Step 620: Perform calculations on the input data to be processed according to the pre-stored neural network synaptic weight values and neuron parameters, and output calculation results according to the neural network type;
所述对输入的待处理数据是通过对神经网络输入数据解码获得的。The input data to be processed is obtained by decoding the input data of the neural network.
作为一种进一步可选的实施例，还包括获取所述神经网络突触权重值，具体为：As a further optional embodiment, it also includes obtaining the synaptic weight value of the neural network, specifically:
获取片外存储数据；Obtain off-chip storage data;
根据所述片外存储数据更新所述神经网络突触权重值和所述神经元参数。Updating the synaptic weight value of the neural network and the neuron parameters according to the off-chip storage data.
图7示例了一种电子设备的实体结构示意图，如图7所示，该电子设备可以包括：处理器(processor)710、通信接口(Communications Interface)720、存储器(memory)730和通信总线740，其中，处理器710，通信接口720，存储器730通过通信总线740完成相互间的通信。处理器710可以调用存储器730中的逻辑指令，以执行用于神经网络的计算方法，该方法包括：FIG. 7 illustrates a schematic diagram of the physical structure of an electronic device. As shown in FIG. 7, the electronic device may include: a processor (processor) 710, a communication interface (Communications Interface) 720, a memory (memory) 730, and a communication bus 740, Wherein, the processor 710 , the communication interface 720 , and the memory 730 communicate with each other through the communication bus 740 . The processor 710 can invoke the logic instructions in the memory 730 to execute a calculation method for the neural network, the method comprising:
获取神经网络输入数据，以确定所述神经网络输入数据的神经网络类型；Acquiring neural network input data to determine the neural network type of the neural network input data;
根据预先存储的神经网络突触权重值以及神经元参数，对输入的待处理数据进行运算，并根据所述神经网络类型输出运算结果；According to the pre-stored neural network synaptic weight value and neuron parameters, the input data to be processed is calculated, and the calculation result is output according to the neural network type;
所述输入的待处理数据是通过对神经网络输入数据解码获得的。The input data to be processed is obtained by decoding the input data of the neural network.
此外，上述的存储器730中的逻辑指令可以通过软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。In addition, the above-mentioned logic instructions in the memory 730 may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes. .
另一方面，本发明还提供一种计算机程序产品，所述计算机程序产品包括计算机程序，计算机程序可存储在非暂态计算机可读存储介质上，所述计算机程序被处理器执行时，计算机能够执行上述各方法所提供的用于神经网络的计算方法，该方法包括：On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can Carry out the calculation method for neural network provided by above-mentioned each method, this method comprises:
获取神经网络输入数据，以确定所述神经网络输入数据的神经网络类型；Acquiring neural network input data to determine the neural network type of the neural network input data;
根据预先存储的神经网络突触权重值以及神经元参数，对输入的待处理数据进行运算，并根据所述神经网络类型输出运算结果；According to the pre-stored neural network synaptic weight value and neuron parameters, the input data to be processed is calculated, and the calculation result is output according to the neural network type;
所述待处理数据是通过对神经网络输入数据解码获得的。The data to be processed is obtained by decoding the input data of the neural network.
又一方面，本发明还提供一种非暂态计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现以执行上述各方法提供的用于神经网络的计算方法，该方法包括：In yet another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it is implemented to perform the calculation methods for neural networks provided by the above methods, The method includes:
获取神经网络输入数据，以确定所述神经网络输入数据的神经网络类型；Acquiring neural network input data to determine the neural network type of the neural network input data;
根据预先存储的神经网络突触权重值以及神经元参数，对输入的待处理数据进行运算，并根据所述神经网络类型输出运算结果；According to the pre-stored neural network synaptic weight value and neuron parameters, the input data to be processed is calculated, and the calculation result is output according to the neural network type;
所述待处理数据是通过对神经网络输入数据解码获得的。The data to be processed is obtained by decoding the input data of the neural network.
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。The device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，上述技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。Through the above description of the implementations, those skilled in the art can clearly understand that each implementation can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, magnetic discs, optical discs, etc., including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments.
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.
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