High-side driving semiconductor chip and substrate potential processing methodTechnical Field
The present invention relates to a power switch chip and a control method, and more particularly, to a high-side driving semiconductor chip and a substrate potential processing method.
Background
The system configuration principle of the high-side driving semiconductor chip is shown in fig. 1. When the chip is applied to the high side of a circuit, the chip is not provided with a pin which is directly grounded, so that an N-type semiconductor process (ntype) design is generally adopted, an N-type substrate (nsub) is connected with a power supply voltage Vbb with the highest potential, then a P well is formed in the N-type substrate, and the P well is taken as a substrate of other devices, so that isolation among functional modules in the chip is realized.
However, when the P-type semiconductor process (ptype) is adopted, the substrate potential of the P-type substrate (psub) needs to be connected to the lowest potential, otherwise, the forward bias of the substrate diode is easy to form, and the parasitic leakage of the substrate is caused.
Fig. 2 is a schematic diagram of an N-type semiconductor process, in which the substrate bias potential Ve can be any voltage without forming a PN junction forward bias when Vc is connected to the power supply voltage Vbb, so that parasitic leakage of the substrate is not caused.
Referring to fig. 3, in the P-type semiconductor process, it is impossible to connect each non-isolated NMOS device to the power supply voltage Vbb in order to avoid the liner bias, so it is necessary to consider whether the liner bias diode of the P-type substrate to NMOS device is turned on. If the bias diode is turned on, it may cause other parasitic transistors to conduct and leak electricity. For this purpose, measures must be taken to ensure that the P-type substrate is reverse biased against the bias diode in the chip internal functional module.
IN addition, IN fig. 1, when the switch Vin is closed, the IN end is turned on to the ground, and the GATE driving module realizes the output of the charge pump (charge pump) by controlling the on-off of the power MOS transistor. When the chip is not in operation, the GATE pull-down module is in operation, the power MOS tube is cut off, and when the chip is in normal operation, the GATE pull-down module is required to be turned off in order to turn on the power MOS tube. When the IN terminal is at a low level, the P-type substrate needs to be pulled down to be equal to the IN terminal, but the pull-down current must be smaller than the pull-up current of the IN terminal, otherwise, the IN terminal cannot be pulled up, and accordingly the power MOS tube cannot be turned off.
Disclosure of Invention
The invention aims to provide a high-side driving semiconductor chip and a substrate potential processing method, which solve the technical problem that parasitic tubes exist for conducting and leaking electricity in the high-side driving semiconductor chip prepared by the existing P-type semiconductor technology.
The technical scheme provided by the invention is as follows:
The substrate potential processing method of the high-side driving semiconductor chip is characterized IN that when the high-side driving semiconductor chip is prepared by adopting a P-type semiconductor process, a substrate potential bias circuit is added between the IN end of the chip and the GATE end of the GATE driving module, the substrate potential bias circuit achieves the following functions that when a power MOS tube control signal inL is turned off, the substrate potential bias circuit turns off the power MOS tube and provides additional pull-down current so that the potential of the GATE end is approximately equal to the potential of the OUT end, when a power MOS tube control signal inL is turned on, the substrate potential bias circuit enables the power MOS tube to be turned on and simultaneously current flowing into the P-type substrate flows into the IN end so as to clamp the substrate potential to the potential of the IN end.
The substrate potential bias circuit comprises a driving switch module, a current mirror module and a GATE pull-down module; the input end of the driving switch module is connected with the output end of the charge pump and is used for controlling the on-off of the driving current output by the charge pump; the current mirror module comprises a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a second PMOS tube P2; the source electrode of the fifth NMOS tube N5 is connected with the P-type substrate, the drain electrode of the fifth NMOS tube N5 is connected with the IN end, the grid electrode of the third NMOS tube N4 is connected with the grid electrode and the drain electrode of the fourth NMOS tube N4, the grid electrode of the third NMOS tube N3 is connected with the P-type substrate, the grid electrode of the second NMOS tube P2 is connected with the power MOS tube control signal inL1, the source electrode of the second NMOS tube P2 is connected with the bias current bias1, the GATE pull-down module comprises a second NMOS tube N2, a third resistor R3, a fourth resistor R4 and a pull-down resistor R5, one end of the third resistor R3 is connected with the grid electrode of the second NMOS tube N2, one end of the fourth resistor R4 is connected with the drain electrode of the second NMOS tube N2, the source electrode of the second NMOS tube N2 and one end of the OUT end of the fifth resistor are connected with the NMOS output end of the driving the switch module, the third resistor R3, the fourth resistor R4 and the other end of the fifth resistor are connected with the NMOS output end of the MOS tube control module, when the second NMOS tube N2 is connected with the bias current, the MOS tube is turned off, when the GATE electrode of the second NMOS tube N2 is turned off, the GATE electrode of the MOS tube is turned off, the GATE electrode of the MOS transistor is turned off, when the GATE electrode is turned off, the MOS transistor is turned off, and the MOS transistor is turned off and the MOS transistor has the MOS transistor and the MOS transistor has a transistor and the transistor electrode is turned off the transistor and the transistor electrode is a transistor and the electrode is a the electrode and the a the electrode is a the electrode and the a, the current flowing into the P-type substrate flows into the IN terminal through the substrate bias circuit while clamping the substrate potential to the IN terminal potential.
When the second NMOS tube N2 is turned on, the pull-down current of the second NMOS tube N2 is limited by the fourth resistor R4 to control the turn-off speed of the power MOS tube.
The high-side driving semiconductor chip for realizing the first substrate potential processing method comprises a Vbb end, an IN end, an OUT end, a P-type substrate, a charge pump and a GATE driving module, wherein the P-type substrate, the charge pump and the GATE driving module are arranged IN the chip; the GATE driving module comprises a power MOS tube and is characterized by further comprising a substrate potential bias circuit, wherein the substrate potential bias circuit comprises a driving switch module, a current mirror module and a GATE pull-down module, the input end of the driving switch module is connected with an output end of a charge pump and is used for controlling the on-off of a driving current output by the charge pump, the current mirror module comprises a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a second PMOS tube P2, the source electrode of the fifth NMOS tube N5 is connected with a P-type substrate, the drain electrode of the fifth NMOS tube N5 is connected with an IN end, the grid electrode of the fifth NMOS tube N4 is connected with the grid electrode of the third NMOS tube N3 and the drain electrode of the second PMOS tube P2, the drain electrode of the fourth NMOS tube N4 and the source electrode of the third NMOS tube N3 are connected with a P-type substrate, the grid electrode of the second PMOS tube P2 is connected with a power MOS tube control signal inL, the source electrode of the second PMOS tube P2 is connected with a bias current bias1, the GATE pull-down module comprises a second NMOS tube N2, a third NMOS resistor R3, a fourth NMOS resistor R4 and a fifth NMOS tube N2, and a third NMOS tube N2 are connected with the grid electrode of the fourth NMOS tube N4 and the third NMOS tube N3N 2.
The driving switch module specifically comprises a first PMOS tube P1 and a first resistor R1, wherein the grid electrode of the first PMOS tube P1 is connected with a power MOS tube control signal inL through the first resistor R1, the source electrode of the first PMOS tube P1 is connected with the output end of the charge pump, and the drain electrode of the first PMOS tube P1 is connected with one end of a third resistor R3, a fourth resistor R4 and a fifth resistor R5.
The driving switch module can further comprise a first voltage stabilizing tube D1, wherein the positive electrode of the first voltage stabilizing tube D1 is connected with the grid electrode of the first PMOS tube P1, and the negative electrode of the first voltage stabilizing tube D1 is connected with the source electrode of the first PMOS tube P1.
The GATE pull-down module may further include a second voltage regulator D2, where the positive electrode of the second voltage regulator D2 is connected to the GATE of the second NMOS transistor N2, and the negative electrode of the second voltage regulator D2 is connected to the drain of the first PMOS transistor P1.
The invention relates to a substrate potential processing method of a second high-side driving semiconductor chip, which comprises a Vbb end, an IN end, an OUT end, a GND end, a P-type substrate arranged IN the chip, a charge pump and a GATE driving module; the GATE driving module comprises a power MOS tube, and is characterized IN that when a power switch chip is prepared by adopting a P-type semiconductor process, a substrate potential bias circuit is added between the GND end of the high-side driving semiconductor chip and the P-type substrate, and the substrate potential bias circuit is used for realizing the functions that when a power MOS tube control signal inL is turned off, the substrate potential bias circuit turns off the power MOS tube and simultaneously provides additional pull-down current so that the potential of the GATE end of the GATE driving module pair is approximately equal to the potential of the OUT end, and when the power MOS tube control signal inL is turned on, the substrate potential bias circuit enables the power MOS tube to be turned on and simultaneously enables current flowing into the P-type substrate to flow into the IN end, so that the substrate potential is clamped to the potential of the IN end.
The substrate potential bias circuit is a depletion type MOS tube or JFET tube connected in parallel between the GND end and the P-type substrate.
The high-side driving semiconductor chip for realizing the second substrate potential processing method comprises a Vbb end, an IN end, an OUT end, a GND end, a P-type substrate, a charge pump and a GATE driving module, wherein the P-type substrate, the charge pump and the GATE driving module are arranged IN the chip, and the GATE driving module comprises a power MOS tube and is characterized by further comprising a substrate potential bias circuit which is a depletion type MOS tube or a JFET tube connected between the GND end and the P-type substrate IN parallel.
The invention has the beneficial effects that:
The invention adds the substrate potential bias circuit IN the high-side driving semiconductor chip based on the P-type semiconductor process, and introduces bias current into the GATE pull-down module through the current mirror module, so that current flowing into the P-type substrate flows into the IN end through the substrate bias circuit when the IN end is pulled down, namely the power MOS tube is conducted, and meanwhile, the potential of the P-type substrate is clamped to the potential of the IN end, and the potential of the IN end is the lowest at the moment, thereby preventing the conduction of a bias diode of a device and avoiding the conduction and leakage problem of a parasitic tube.
If the high-side driving semiconductor chip is provided with the GND end, the substrate potential bias circuit of the high-side driving semiconductor chip adopts the depletion type MOS tube or the JFET tube which is connected in parallel between the GND end and the P-type substrate so as to pull the potential of the P-type substrate and the potential of the GND end to be approximately equal, and the parasitic leakage problem caused by floating of the potential of the P-type substrate in the chip can be prevented.
Drawings
Fig. 1 is a schematic diagram of a system configuration of a high-side driving semiconductor chip;
FIG. 2 is a schematic diagram of a high-side driving semiconductor chip structure based on an N-type semiconductor process;
FIG. 3 is a schematic diagram of a high-side driving semiconductor chip structure based on a P-type semiconductor process;
FIG. 4 is a schematic diagram of a substrate potential bias circuit of an embodiment 1 of a high-side-drive semiconductor chip based on a P-type semiconductor process of the present invention;
Fig. 5 is a schematic diagram of a substrate potential bias circuit of embodiment 2 of a high-side driving semiconductor chip based on P-type semiconductor process according to the present invention.
Detailed Description
The high-side driving semiconductor chip comprises a VBB end, an IN end and an OUT end which are arranged on the chip, a P-type substrate (psub), a charge pump, a GATE driving module and a substrate potential bias circuit which are arranged IN the chip, wherein the GATE driving module comprises a power MOS tube.
Example 1
Referring to fig. 4, the substrate potential bias circuit includes a driving switch module, a current mirror module, and a GATE pull-down module. The driving switch module comprises a first PMOS tube P1, a first resistor R1 and a first voltage stabilizing tube D1, wherein the grid electrode of the first PMOS tube P1 is connected with a power MOS tube control signal inL1 through the first resistor R1, the source electrode of the first PMOS tube P1 is connected with the output end charge of the charge pump, and the drain electrode of the first PMOS tube P1 is connected with one end of a third resistor R3, a fourth resistor R4 and a fifth resistor. The positive electrode of the first voltage stabilizing tube D1 is connected with the grid electrode of the first PMOS tube P1, the negative electrode of the first voltage stabilizing tube D1 is connected with the source electrode of the first PMOS tube P1, and the driving switch module is used for controlling the on-off of the driving current output by the charge pump. The current mirror module comprises a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a second PMOS tube P2, wherein the source electrode of the fifth NMOS tube N5 is connected with a P-type substrate, the drain electrode of the fifth NMOS tube N5 is connected with an IN end, the grid electrode of the third NMOS tube N4 is connected with the grid electrode and the drain electrode of the second PMOS tube P2, the drain electrode of the fourth NMOS tube N4 is connected with the P-type substrate, the source electrode of the third NMOS tube N3 is connected with the P-type substrate, the grid electrode of the second PMOS tube P2 is connected with a power MOS tube control signal inL, the source electrode of the second NMOS tube P2 is connected with a bias current bias1, the GATE pull-down module comprises a second NMOS tube N2, a third resistor R3, a fourth resistor R4, a pull-down resistor R5 and a second voltage stabilizing tube D2, one end of the third resistor R3 is connected with the grid electrode of the second NMOS tube N2, one end of the fourth resistor R4 is connected with the drain electrode of the second NMOS tube N2, the source electrode of the second NMOS tube N2 and the source electrode of the fifth NMOS tube N3 are connected with the drain electrode of the fifth resistor R3, and the drain electrode of the fourth resistor R4 is connected with the positive electrode of the second PMOS tube P2 and the second resistor P2 is connected with the drain electrode of the fifth resistor P2. The drain electrode of the third NMOS tube N3 is connected with the grid electrode of the second NMOS tube N2.
Working principle:
Referring to fig. 1, when the high-side driving semiconductor chip works normally, the switch Vin is closed, the IN terminal is turned on to be low level, and the charge pump outputs current from the OUT terminal after passing through the first PMOS transistor P1 and the GATE driving module.
The control signal inL is a control signal required by the conduction of the power MOS transistor, when the control signal inL is low, the power MOS transistor is conducted to drive the output end to output, meanwhile, the first PMOS transistor P1 and the second PMOS transistor P2 are conducted, and as the third NMOS transistor N3 and the fourth NMOS transistor N4 form a current mirror, the current flowing on the third NMOS transistor N3 is proportional to the bias current bias1 flowing through the third NMOS transistor N3, the current of the third NMOS transistor N3 pulls down the GATE voltage of the second NMOS transistor N2, so that the second NMOS transistor N2 is cut off, and the pull-down current of the GATE end of the GATE driving module is turned off.
The third resistor R3 provides GATE voltage for the second NMOS tube N2 when the third NMOS tube N3 is cut off, so that the second NMOS tube N2 is conducted to pull down the GATE end, and the power MOS tube is turned off;
the fourth resistor R4 limits the pull-down current of the second NMOS transistor N2 to control the turn-off speed of the power MOS transistor when the second NMOS transistor N2 is turned on.
The fifth resistor R5 provides an additional pull-down current when the GATE terminal is pulled down, and particularly when the GATE terminal is pulled down to the threshold voltage Vth of the second NMOS transistor N2, the pull-down is continued by the fifth resistor R5 so that the GATE terminal and the OUT terminal are approximately equal in potential.
Example 2
As shown in FIG. 5, the modules of the high-side driving semiconductor chip, such as a voltage source, overvoltage protection, current limitation, gate voltage protection, voltage sampling, charge pump potential translation rectifier, inductance demagnetization clamping, logic control, current sampling, output voltage detection, temperature sampling, electrostatic protection, current source and the like, are all connected with the P-type substrate, and the high-side driving semiconductor chip is provided with a GND end which is directly grounded, and a depletion type MOS tube or a JFET tube is connected in parallel between the GND end and the P-type substrate so as to pull the potential of the P-type substrate and the potential of the GND end to be approximately equal, thereby preventing parasitic leakage problem caused by floating of the potential of the P-type substrate in the chip.