技术领域technical field
本发明涉及一种电源开关芯片及控制方法，尤其涉及一种高侧驱动半导体芯片及衬底电位处理方法。The invention relates to a power switch chip and a control method, in particular to a high-side driving semiconductor chip and a substrate potential processing method.
背景技术Background technique
高侧驱动半导体芯片的系统结构原理参见图1。该芯片运用于电路高侧时，芯片没有直接接地的管脚，因此一般都采用N型半导体工艺(ntype)设计，将N型衬底(nsub)接最高电位的电源电压Vbb，然后在N型衬底中做P阱，并将P阱作为其他器件的衬底，以实现芯片中各功能模块之间的隔离。Refer to Figure 1 for the system structure principle of the high-side driver semiconductor chip. When the chip is used on the high side of the circuit, the chip does not have a direct ground pin, so it is generally designed with an N-type semiconductor process (ntype). The N-type substrate (nsub) is connected to the highest potential power supply voltage Vbb, and then the N-type Make a P well in the substrate, and use the P well as the substrate of other devices to realize the isolation between the functional modules in the chip.
但是，采用P型半导体工艺(ptype)设计时，P型衬底(psub)的衬底电位需要接到最低电位，否则容易形成衬底二极管正偏，引起衬底寄生漏电的问题。However, when using a P-type semiconductor process (ptype) design, the substrate potential of the P-type substrate (psub) needs to be connected to the lowest potential, otherwise it is easy to form a forward-biased substrate diode, causing the problem of substrate parasitic leakage.
图2是N型半导体工艺示意图，在Vc接电源电压Vbb的情况下，衬偏电位Ve可以是任意电压，都不会形成PN结正偏，所以不会引起衬底寄生漏电的问题。Figure 2 is a schematic diagram of an N-type semiconductor process. When Vc is connected to the power supply voltage Vbb, the substrate bias potential Ve can be any voltage, and will not form a forward biased PN junction, so the problem of substrate parasitic leakage will not be caused.
参见图3，在P型半导体工艺中，不可能为了避免衬偏而让每个非隔离NMOS器件都接电源电压Vbb，因此就需要考虑P型衬底到NMOS器件的衬偏二极管是否导通。如果该衬偏二极管导通，就有可能导致其他寄生管导通漏电。为此必须采取措施来确保P型衬底对芯片内部功能模块中衬偏二极管形成反偏。Referring to Figure 3, in the P-type semiconductor process, it is impossible to connect each non-isolated NMOS device to the power supply voltage Vbb in order to avoid the back bias, so it is necessary to consider whether the back bias diode from the P-type substrate to the NMOS device is turned on. If the lining bias diode is turned on, it may cause other parasitic tubes to turn on and leak. For this reason, measures must be taken to ensure that the P-type substrate forms a reverse bias to the substrate-biased diodes in the internal functional modules of the chip.
另外，在图1中，开关Vin闭合时，IN端对地导通，则GATE驱动模块通过控制功率MOS管的通断实现电荷泵(charge pump)的输出。芯片不工作时，GATE下拉模块工作，功率MOS管截止；芯片正常工作时，为了开启功率MOS管，需要关掉GATE下拉模块。当IN端为低电平时，需要将P型衬底下拉到与IN端电位相等，但下拉电流必须小于IN端上拉电流，否则会导致IN端无法上拉，相应无法关闭功率MOS管。In addition, in FIG. 1, when the switch Vin is closed, the IN terminal is conducted to the ground, and the GATE drive module realizes the output of the charge pump by controlling the power MOS transistor to be switched on and off. When the chip is not working, the GATE pull-down module is working, and the power MOS tube is cut off; when the chip is working normally, in order to turn on the power MOS tube, the GATE pull-down module needs to be turned off. When the IN terminal is at low level, the P-type substrate needs to be pulled down to the same potential as the IN terminal, but the pull-down current must be smaller than the pull-up current of the IN terminal, otherwise the IN terminal cannot be pulled up, and the power MOS tube cannot be turned off accordingly.
发明内容Contents of the invention
本发明目的是提供一种高侧驱动半导体芯片及衬底电位处理方法，其解决了现有P型半导体工艺制备的高侧驱动半导体芯片存在寄生管导通漏电的技术问题。The object of the present invention is to provide a high-side driving semiconductor chip and a substrate potential processing method, which solves the technical problem of parasitic tube conduction leakage in the high-side driving semiconductor chip prepared by the existing P-type semiconductor process.
本发明提供的技术方案是：The technical scheme provided by the invention is:
本发明第一种高侧驱动半导体芯片的衬底电位处理方法，所述高侧驱动半导体芯片包括Vbb端、IN端和OUT端，以及设置在芯片内的P型衬底、电荷泵、GATE驱动模块；所述GATE驱动模块包括功率MOS管；其特殊之处是，采用P型半导体工艺制备高侧驱动半导体芯片时，在芯片的IN端和GATE驱动模块的GATE端之间增加衬底电位偏置电路；所述衬底电位偏置电路实现以下功能：当功率MOS管控制信号inL1为关断时，衬底电位偏置电路关掉功率MOS管，同时提供额外的下拉电流，使得GATE端电位与OUT端电位近似相等；当功率MOS管控制信号inL1为导通时，衬底电位偏置电路使得功率MOS管导通，同时将流入P型衬底的电流流入IN端，从而将衬底电位箝位至IN端电位。The first substrate potential processing method of the high-side driving semiconductor chip of the present invention, the high-side driving semiconductor chip includes a Vbb terminal, an IN terminal and an OUT terminal, and a P-type substrate, a charge pump, and a GATE driver arranged in the chip module; the GATE drive module includes a power MOS tube; its special feature is that when the high-side drive semiconductor chip is prepared by a P-type semiconductor process, the substrate potential bias is added between the IN end of the chip and the GATE end of the GATE drive module. The substrate potential bias circuit realizes the following functions: when the power MOS tube control signal inL1 is turned off, the substrate potential bias circuit turns off the power MOS tube and provides additional pull-down current to make the GATE terminal potential It is approximately equal to the potential of the OUT terminal; when the power MOS transistor control signal inL1 is turned on, the substrate potential bias circuit makes the power MOS transistor turn on, and at the same time, the current flowing into the P-type substrate flows into the IN terminal, thereby reducing the substrate potential Clamped to the IN terminal potential.
上述衬底电位偏置电路包括驱动开关模块、电流镜模块和GATE下拉模块；所述驱动开关模块输入端接电荷泵输出端，用于控制电荷泵输出驱动电流的通断；所述电流镜模块包括第三NMOS管N3、第四NMOS管N4、第五NMOS管N5、第二PMOS管P2；所述第五NMOS管N5的源极接P型衬底，其漏极接IN端，其栅极接第四NMOS管N4的栅极和漏极、第三NMOS管N3的栅极和第二PMOS管P2的漏极；所述第四NMOS管N4的漏极和第三NMOS管N3的源极接P型衬底；所述第二PMOS管P2的栅极接功率MOS管控制信号inL1，其源极接偏置电流bias1；所述GATE下拉模块包括第二NMOS管N2、第三电阻R3、第四电阻R4、下拉电阻R5；第三电阻R3的一端接第二NMOS管N2的栅极；第四电阻R4的一端接第二NMOS管N2的漏极；所述第二NMOS管N2的源极以及第五电阻的一端接OUT端；所述第三电阻R3、第四电阻R4以及第五电阻的另一端均接驱动开关模块的输出端；所述第三NMOS管N3的漏极接第二NMOS管N2的栅极；当功率MOS管控制信号inL1为关断时，衬底电位偏置电路的GATE下拉模块中的第二NMOS管N2导通，通过下拉GATE从而关掉功率MOS管，OUT端无输出电流；在GATE下拉时，下拉电阻R5提供额外的下拉电流，使得GATE端与OUT端电位近似相等；当功率MOS管控制信号inL1为导通时，第二NMOS管N2截止，从而关掉GATE端的下拉电流，功率MOS管导通，电荷泵从OUT端输出电流；功率MOS管导通时，流入P型衬底的电流通过衬底偏置电路流入IN端，同时将衬底电位箝位至IN端电位。The above-mentioned substrate potential bias circuit includes a drive switch module, a current mirror module and a GATE pull-down module; the input terminal of the drive switch module is connected to the output terminal of the charge pump, and is used to control the on-off of the output drive current of the charge pump; the current mirror module It includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a second PMOS transistor P2; the source of the fifth NMOS transistor N5 is connected to the P-type substrate, its drain is connected to the IN terminal, and its gate connected to the gate and drain of the fourth NMOS transistor N4, the gate of the third NMOS transistor N3 and the drain of the second PMOS transistor P2; the drain of the fourth NMOS transistor N4 and the source of the third NMOS transistor N3 The pole is connected to the P-type substrate; the gate of the second PMOS transistor P2 is connected to the power MOS transistor control signal inL1, and its source is connected to the bias current bias1; the GATE pull-down module includes a second NMOS transistor N2 and a third resistor R3 , the fourth resistor R4, the pull-down resistor R5; one end of the third resistor R3 is connected to the gate of the second NMOS transistor N2; one end of the fourth resistor R4 is connected to the drain of the second NMOS transistor N2; the second NMOS transistor N2 The source and one end of the fifth resistor are connected to the OUT end; the other ends of the third resistor R3, the fourth resistor R4, and the fifth resistor are all connected to the output end of the drive switch module; the drain of the third NMOS transistor N3 is connected to The gate of the second NMOS transistor N2; when the power MOS transistor control signal inL1 is turned off, the second NMOS transistor N2 in the GATE pull-down module of the substrate potential bias circuit is turned on, and the power MOS transistor is turned off by pulling down the GATE , there is no output current at the OUT terminal; when the GATE is pulled down, the pull-down resistor R5 provides an additional pull-down current, so that the potentials of the GATE terminal and the OUT terminal are approximately equal; when the power MOS tube control signal inL1 is turned on, the second NMOS tube N2 is turned off, Therefore, the pull-down current at the GATE terminal is turned off, the power MOS tube is turned on, and the charge pump outputs current from the OUT terminal; when the power MOS tube is turned on, the current flowing into the P-type substrate flows into the IN terminal through the substrate bias circuit, and at the same time, the substrate The potential is clamped to the IN terminal potential.
在第二NMOS管N2导通时，通过第四电阻R4限制第二NMOS管N2的下拉电流来控制功率MOS管的关断速度。When the second NMOS transistor N2 is turned on, the fourth resistor R4 limits the pull-down current of the second NMOS transistor N2 to control the turn-off speed of the power MOS transistor.
本发明实现上述第一种衬底电位处理方法的高侧驱动半导体芯片，包括Vbb端、IN端和OUT端，以及设置在芯片内的P型衬底、电荷泵、GATE驱动模块；所述GATE驱动模块包括功率MOS管；其特殊之处是，还包括衬底电位偏置电路；所述衬底电位偏置电路包括驱动开关模块、电流镜模块和GATE下拉模块；所述驱动开关模块输入端接电荷泵输出端，用于控制电荷泵输出驱动电流的通断；所述电流镜模块包括第三NMOS管N3、第四NMOS管N4、第五NMOS管N5、第二PMOS管P2；所述第五NMOS管N5的源极接P型衬底，其漏极接IN端，其栅极接第四NMOS管N4的栅极和漏极、第三NMOS管N3的栅极和第二PMOS管P2的漏极；所述第四NMOS管N4的漏极和第三NMOS管N3的源极接P型衬底；所述第二PMOS管P2的栅极接功率MOS管控制信号inL1，其源极接偏置电流bias1；所述GATE下拉模块包括第二NMOS管N2、第三电阻R3、第四电阻R4、下拉电阻R5；第三电阻R3的一端接第二NMOS管N2的栅极；第四电阻R4的一端接第二NMOS管N2的漏极；所述第二NMOS管N2的源极以及第五电阻的一端接OUT端；所述第三电阻R3、第四电阻R4以及第五电阻的另一端均接驱动开关模块的输出端；所述第三NMOS管N3的漏极接第二NMOS管N2的栅极。The present invention realizes the high-side driving semiconductor chip of the above-mentioned first substrate potential processing method, including a Vbb terminal, an IN terminal and an OUT terminal, and a P-type substrate, a charge pump, and a GATE drive module arranged in the chip; the GATE The drive module includes a power MOS tube; its special feature is that it also includes a substrate potential bias circuit; the substrate potential bias circuit includes a drive switch module, a current mirror module and a GATE pull-down module; the input terminal of the drive switch module Connected to the output terminal of the charge pump, used to control the on-off of the output drive current of the charge pump; the current mirror module includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a second PMOS transistor P2; the The source of the fifth NMOS transistor N5 is connected to the P-type substrate, its drain is connected to the IN terminal, and its gate is connected to the gate and drain of the fourth NMOS transistor N4, the gate of the third NMOS transistor N3 and the second PMOS transistor The drain of P2; the drain of the fourth NMOS transistor N4 and the source of the third NMOS transistor N3 are connected to the P-type substrate; the gate of the second PMOS transistor P2 is connected to the power MOS transistor control signal inL1, and its source The electrode is connected to the bias current bias1; the GATE pull-down module includes a second NMOS transistor N2, a third resistor R3, a fourth resistor R4, and a pull-down resistor R5; one end of the third resistor R3 is connected to the gate of the second NMOS transistor N2; One end of the four resistors R4 is connected to the drain of the second NMOS transistor N2; the source of the second NMOS transistor N2 and one end of the fifth resistor are connected to the OUT end; the third resistor R3, the fourth resistor R4 and the fifth resistor The other ends of both are connected to the output end of the driving switch module; the drain of the third NMOS transistor N3 is connected to the gate of the second NMOS transistor N2.
上述驱动开关模块具体包括第一PMOS管P1和第一电阻R1；所述第一PMOS管P1的栅极通过第一电阻R1接功率MOS管控制信号inL1，其源极接电荷泵输出端，其漏极接第三电阻R3、第四电阻R4以及第五电阻R5的一端。The above drive switch module specifically includes a first PMOS transistor P1 and a first resistor R1; the gate of the first PMOS transistor P1 is connected to the power MOS transistor control signal inL1 through the first resistor R1, and its source is connected to the output terminal of the charge pump. The drain is connected to one end of the third resistor R3, the fourth resistor R4 and the fifth resistor R5.
上述驱动开关模块还可包括第一稳压管D1；所述第一稳压管D1的正极接第一PMOS管P1的栅极，其负极接第一PMOS管P1的源极。The drive switch module may further include a first voltage regulator transistor D1; the anode of the first voltage regulator transistor D1 is connected to the gate of the first PMOS transistor P1, and its cathode is connected to the source of the first PMOS transistor P1.
上述GATE下拉模块还可包括第二稳压管D2；所述第二稳压管D2的正极接第二NMOS管N2的栅极，其负极接第一PMOS管P1的漏极。The above-mentioned GATE pull-down module may further include a second voltage regulator transistor D2; the anode of the second voltage regulator transistor D2 is connected to the gate of the second NMOS transistor N2, and its cathode is connected to the drain of the first PMOS transistor P1.
本发明第二种高侧驱动半导体芯片的衬底电位处理方法，所述高侧驱动半导体芯片包括Vbb端、IN端、OUT端和GND端，以及设置在芯片内的P型衬底、电荷泵、GATE驱动模块；所述GATE驱动模块包括功率MOS管；其特征在于：采用P型半导体工艺制备电源开关芯片时，在高侧驱动半导体芯片的GND端与P型衬底之间增加衬底电位偏置电路；所述衬底电位偏置电路用于实现以下功能：当功率MOS管控制信号inL1为关断时，衬底电位偏置电路关掉功率MOS管，同时提供额外的下拉电流，使得GATE驱动模块对的GATE端电位与OUT端电位近似相等；当功率MOS管控制信号inL1为导通时，衬底电位偏置电路使得功率MOS管导通，同时将流入P型衬底的电流流入IN端，从而将衬底电位箝位至IN端电位。The second substrate potential processing method of the high-side driving semiconductor chip of the present invention, the high-side driving semiconductor chip includes a Vbb terminal, an IN terminal, an OUT terminal and a GND terminal, and a P-type substrate and a charge pump arranged in the chip . GATE drive module; the GATE drive module includes a power MOS tube; it is characterized in that: when using a P-type semiconductor process to prepare a power switch chip, the substrate potential is increased between the GND end of the high-side drive semiconductor chip and the P-type substrate Bias circuit; the substrate potential bias circuit is used to realize the following functions: when the power MOS tube control signal inL1 is turned off, the substrate potential bias circuit turns off the power MOS tube and provides additional pull-down current, so that The potential of the GATE terminal of the GATE driver module pair is approximately equal to the potential of the OUT terminal; when the power MOS tube control signal inL1 is turned on, the substrate potential bias circuit makes the power MOS tube turn on, and at the same time, the current flowing into the P-type substrate flows into IN terminal, thereby clamping the substrate potential to the IN terminal potential.
上述衬底电位偏置电路为并联在GND端与P型衬底之间的耗尽型MOS管或JFET管。The above-mentioned substrate potential bias circuit is a depletion MOS transistor or a JFET transistor connected in parallel between the GND terminal and the P-type substrate.
本发明实现上述第二种衬底电位处理方法的高侧驱动半导体芯片，包括Vbb端、IN端、OUT端和GND端，以及设置在芯片内的P型衬底、电荷泵、GATE驱动模块；所述GATE驱动模块包括功率MOS管；其特征在于：还包括衬底电位偏置电路；所述衬底电位偏置电路为并联在GND端与P型衬底之间的耗尽型MOS管或JFET管。The present invention realizes the high-side drive semiconductor chip of the second substrate potential processing method, including Vbb terminal, IN terminal, OUT terminal and GND terminal, and a P-type substrate, a charge pump, and a GATE drive module arranged in the chip; The GATE drive module includes a power MOS tube; it is characterized in that: it also includes a substrate potential bias circuit; the substrate potential bias circuit is a depletion-type MOS tube connected in parallel between the GND terminal and the P-type substrate or JFET tube.
本发明的有益效果：Beneficial effects of the present invention:
本发明在基于P型半导体工艺的高侧驱动半导体芯片中增加了衬底电位偏置电路，通过电流镜模块在GATE下拉模块中引入偏置电流，使得在IN端下拉即功率MOS管导通时流入P型衬底的电流通过衬底偏置电路而流入IN端，同时P型衬底电位被箝位至IN端电位，而此时的IN端电位最低，所以可以防止器件的衬偏二极管导通，避免了寄生管导通漏电的问题。In the present invention, a substrate potential bias circuit is added to the high-side drive semiconductor chip based on P-type semiconductor technology, and a bias current is introduced into the GATE pull-down module through the current mirror module, so that when the IN terminal is pulled down, that is, when the power MOS tube is turned on The current flowing into the P-type substrate flows into the IN terminal through the substrate bias circuit, and at the same time, the P-type substrate potential is clamped to the IN terminal potential, and at this time the IN terminal potential is the lowest, so it can prevent the substrate bias diode of the device from conducting Through, avoiding the problem of the conduction leakage of the parasitic tube.
若高侧驱动半导体芯片设置有GND端，本发明在高侧驱动半导体芯片的衬底电位偏置电路则采用在GND端与P型衬底之间并联耗尽型MOS管或JFET管，以便将P型衬底电位与GND端电位拉至近似相等，可以防止芯片内部因P型衬底电位浮空所引起的寄生漏电问题。If the high-side driver semiconductor chip is provided with a GND end, the substrate potential bias circuit of the high-side driver semiconductor chip in the present invention uses a depletion-type MOS tube or a JFET tube connected in parallel between the GND end and the P-type substrate, so that the The potential of the P-type substrate is pulled to be approximately equal to the potential of the GND terminal, which can prevent the parasitic leakage problem caused by the floating potential of the P-type substrate inside the chip.
附图说明Description of drawings
图1是高侧驱动半导体芯片的系统结构原理图；FIG. 1 is a schematic diagram of a system structure of a high-side driving semiconductor chip;
图2是基于N型半导体工艺的高侧驱动半导体芯片结构示意图；2 is a schematic structural diagram of a high-side drive semiconductor chip based on an N-type semiconductor process;
图3是基于P型半导体工艺的高侧驱动半导体芯片结构示意图；3 is a schematic structural diagram of a high-side drive semiconductor chip based on a P-type semiconductor process;
图4是本发明基于P型半导体工艺的高侧驱动半导体芯片实施例1的衬底电位偏置电路示意图；FIG. 4 is a schematic diagram of a substrate potential bias circuit of Embodiment 1 of a high-side driving semiconductor chip based on a P-type semiconductor process in the present invention;
图5本发明基于P型半导体工艺的高侧驱动半导体芯片实施例2的衬底电位偏置电路示意图。FIG. 5 is a schematic diagram of a substrate potential bias circuit of Embodiment 2 of a high-side driving semiconductor chip based on a P-type semiconductor process in the present invention.
具体实施方式Detailed ways
高侧驱动半导体芯片参见图1，包括设置在芯片上的VBB端、IN端和OUT端，以及设置在芯片内的P型衬底(psub)、电荷泵、GATE驱动模块和衬底电位偏置电路；GATE驱动模块包括功率MOS管。Refer to Figure 1 for the high-side drive semiconductor chip, including the VBB terminal, IN terminal and OUT terminal set on the chip, as well as the P-type substrate (psub), charge pump, GATE drive module and substrate potential bias set in the chip circuit; the GATE drive module includes a power MOS tube.
实施例1Example 1
参见图4，衬底电位偏置电路包括驱动开关模块、电流镜模块和GATE下拉模块。驱动开关模块包括第一PMOS管P1、第一电阻R1和第一稳压管D1；第一PMOS管P1的栅极通过第一电阻R1接功率MOS管控制信号inL1，其源极接电荷泵输出端charge，其漏极接第三电阻R3、第四电阻R4以及第五电阻的一端。第一稳压管D1的正极接第一PMOS管P1的栅极，其负极接第一PMOS管P1的源极；驱动开关模块用于控制电荷泵输出驱动电流的通断。电流镜模块包括第三NMOS管N3、第四NMOS管N4、第五NMOS管N5、第二PMOS管P2；第五NMOS管N5的源极接P型衬底，其漏极接IN端，其栅极接第四NMOS管N4的栅极和漏极、第三NMOS管N3的栅极和第二PMOS管P2的漏极；第四NMOS管N4的漏极接P型衬底；第三NMOS管N3的源极接P型衬底；所述第二PMOS管P2的栅极接功率MOS管控制信号inL1，其源极接偏置电流bias1；GATE下拉模块包括第二NMOS管N2、第三电阻R3、第四电阻R4、下拉电阻R5和第二稳压管D2；第三电阻R3的一端接第二NMOS管N2的栅极；第四电阻R4的一端接第二NMOS管N2的漏极；所述第二NMOS管N2的源极以及第五电阻的一端接OUT端；所述第三电阻R3、第四电阻R4以及第五电阻的另一端均接驱动开关模块的输出端；第二稳压管D2的正极接第二NMOS管N2的栅极，其负极接第一PMOS管P1的漏极。第三NMOS管N3的漏极接第二NMOS管N2的栅极。Referring to FIG. 4 , the substrate potential bias circuit includes a drive switch module, a current mirror module and a GATE pull-down module. The drive switch module includes a first PMOS transistor P1, a first resistor R1 and a first voltage regulator transistor D1; the gate of the first PMOS transistor P1 is connected to the power MOS transistor control signal inL1 through the first resistor R1, and its source is connected to the charge pump output terminal charge, the drain of which is connected to one terminal of the third resistor R3, the fourth resistor R4 and the fifth resistor. The anode of the first regulator transistor D1 is connected to the gate of the first PMOS transistor P1, and its cathode is connected to the source of the first PMOS transistor P1; the driving switch module is used to control the on-off of the output driving current of the charge pump. The current mirror module includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a second PMOS transistor P2; the source of the fifth NMOS transistor N5 is connected to the P-type substrate, its drain is connected to the IN terminal, and its The gate is connected to the gate and drain of the fourth NMOS transistor N4, the gate of the third NMOS transistor N3 and the drain of the second PMOS transistor P2; the drain of the fourth NMOS transistor N4 is connected to the P-type substrate; the third NMOS The source of the transistor N3 is connected to the P-type substrate; the gate of the second PMOS transistor P2 is connected to the power MOS transistor control signal inL1, and its source is connected to the bias current bias1; the GATE pull-down module includes the second NMOS transistor N2, the third Resistor R3, fourth resistor R4, pull-down resistor R5 and second regulator tube D2; one end of the third resistor R3 is connected to the gate of the second NMOS transistor N2; one end of the fourth resistor R4 is connected to the drain of the second NMOS transistor N2 The source of the second NMOS transistor N2 and one end of the fifth resistor are connected to the OUT end; the other ends of the third resistor R3, the fourth resistor R4, and the fifth resistor are all connected to the output end of the drive switch module; the second The anode of the Zener transistor D2 is connected to the gate of the second NMOS transistor N2, and the cathode thereof is connected to the drain of the first PMOS transistor P1. The drain of the third NMOS transistor N3 is connected to the gate of the second NMOS transistor N2.
工作原理：working principle:
参见图1，高侧驱动半导体芯片正常工作时，开关Vin闭合，IN端导通变为低电平，电荷泵经第一PMOS管P1和GATE驱动模块后从OUT端输出电流。Referring to Fig. 1, when the high-side driving semiconductor chip is working normally, the switch Vin is closed, the IN terminal is turned on and becomes low level, and the charge pump outputs current from the OUT terminal after passing through the first PMOS transistor P1 and the GATE drive module.
控制信号inL1是功率MOS管导通所需要的控制信号，当控制信号inL1为低时，功率MOS管导通，驱动OUT端输出；同时第一PMOS管P1和第二PMOS管P2导通，由于第三NMOS管N3和第四NMOS管N4构成电流镜，则第三NMOS管N3上流过的电流与流过第三NMOS管N3的偏置电流bias1成比例，则第三NMOS管N3的电流下拉第二NMOS管N2的栅电压，使得第二NMOS管N2截止，关掉GATE驱动模块的GATE端的下拉电流。The control signal inL1 is the control signal required to turn on the power MOS transistor. When the control signal inL1 is low, the power MOS transistor is turned on to drive the output of the OUT terminal; at the same time, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on. The third NMOS transistor N3 and the fourth NMOS transistor N4 constitute a current mirror, the current flowing through the third NMOS transistor N3 is proportional to the bias current bias1 flowing through the third NMOS transistor N3, and the current of the third NMOS transistor N3 is pulled down The gate voltage of the second NMOS transistor N2 turns off the second NMOS transistor N2 and turns off the pull-down current of the GATE terminal of the GATE driving module.
第三电阻R3在第三NMOS管N3截止时给第二NMOS管N2提供栅电压，使第二NMOS管N2导通下拉GATE端，从而关掉功率MOS管；The third resistor R3 provides a gate voltage to the second NMOS transistor N2 when the third NMOS transistor N3 is turned off, so that the second NMOS transistor N2 is turned on and pulls down the GATE terminal, thereby turning off the power MOS transistor;
第四电阻R4在第二NMOS管N2导通时限制第二NMOS管N2的下拉电流来控制功率MOS管的关断速度。The fourth resistor R4 limits the pull-down current of the second NMOS transistor N2 to control the turn-off speed of the power MOS transistor when the second NMOS transistor N2 is turned on.
第五电阻R5在GATE端下拉时提供额外的下拉电流，尤其是在GATE端下拉到第二NMOS管N2的阈值电压Vth时，由第五电阻R5继续下拉使得GATE端与OUT端电位近似相等。The fifth resistor R5 provides additional pull-down current when the GATE terminal is pulled down, especially when the GATE terminal is pulled down to the threshold voltage Vth of the second NMOS transistor N2, the fifth resistor R5 continues to pull down so that the potentials of the GATE terminal and the OUT terminal are approximately equal.
实施例2Example 2
如图5所示，高侧驱动半导体芯片内部的电压源、过压保护、电流限制、栅电压保护、电压采样、电荷泵电位平移整流器、电感退磁箝位、逻辑控制、电流采样、输出电压检测、温度采样、静电防护、电流源等模块均接P型衬底，且该高侧驱动半导体芯片带有直接接地的GND端，在GND端与P型衬底之间并联耗尽型MOS管或JFET管，以便将P型衬底电位与GND端电位拉至近似相等，可以防止芯片内部因P型衬底电位浮空所引起的寄生漏电问题。As shown in Figure 5, the voltage source, overvoltage protection, current limit, gate voltage protection, voltage sampling, charge pump potential translation rectifier, inductance demagnetization clamp, logic control, current sampling, output voltage detection inside the high-side drive semiconductor chip , temperature sampling, electrostatic protection, current source and other modules are all connected to the P-type substrate, and the high-side drive semiconductor chip has a GND terminal directly grounded, and a depletion-type MOS transistor or JFET tube, in order to pull the potential of the P-type substrate to approximately equal to the potential of the GND terminal, which can prevent the parasitic leakage problem caused by the floating of the P-type substrate potential inside the chip.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310371334.9ACN116527030B (en) | 2023-04-07 | 2023-04-07 | High-side driving semiconductor chip and substrate potential processing method |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310371334.9ACN116527030B (en) | 2023-04-07 | 2023-04-07 | High-side driving semiconductor chip and substrate potential processing method |
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| CN116527030Atrue CN116527030A (en) | 2023-08-01 |
| CN116527030B CN116527030B (en) | 2025-02-14 |
| Application Number | Title | Priority Date | Filing Date |
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| CN202310371334.9AActiveCN116527030B (en) | 2023-04-07 | 2023-04-07 | High-side driving semiconductor chip and substrate potential processing method |
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| CN119030504A (en)* | 2024-10-28 | 2024-11-26 | 江苏润石科技有限公司 | An adaptive substrate potential generating circuit and its application |
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| CN119030504A (en)* | 2024-10-28 | 2024-11-26 | 江苏润石科技有限公司 | An adaptive substrate potential generating circuit and its application |
| CN119030504B (en)* | 2024-10-28 | 2025-04-01 | 江苏润石科技有限公司 | An adaptive substrate potential generating circuit and its application |
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