技术领域technical field
本发明涉及一种低压差稳压系统。特别涉及一种可避免输出电压发生严重下冲(undershoot)的低压差稳压系统及其控制方法。The invention relates to a low-drop voltage stabilizing system. In particular, it relates to a low-dropout voltage stabilizing system capable of avoiding severe undershoot of the output voltage and a control method thereof.
背景技术Background technique
随着科技的发展，各式集成电路已被发展出来。然而，许多集成电路的效能仍有改善的空间。With the development of technology, various integrated circuits have been developed. However, there is still room for improvement in the performance of many integrated circuits.
举例而言，在一些相关技术中，低压差稳压器长时间维持在失锁状态。此时，若负载电流提高，则低压差稳压器的输出电压可能会发生严重下冲(undershoot)的问题。另外，在一些相关技术中，当低压差稳压器从轻载模式转为重载模式时，低压差稳压器的输出电压也可能会发生严重下冲的问题。For example, in some related technologies, the LDO voltage regulator remains in an unlocked state for a long time. At this time, if the load current increases, the output voltage of the low dropout regulator may suffer serious undershoot. In addition, in some related technologies, when the low-dropout voltage regulator changes from light-load mode to heavy-load mode, the output voltage of the low-dropout voltage regulator may also have a serious undershoot problem.
发明内容Contents of the invention
本发明的一些实施方式涉及一种低压差稳压系统。低压差稳压系统包括一低压差稳压器。低压差稳压器包括一比较电路、一放大电路、一晶体管、一第一电阻以及一第二电阻。比较电路用于依据一参考电压以及一反馈电压产生一比较电压。放大电路用于依据该比较电压产生一放大电压。晶体管用于接收一输入电压且受该放大电压控制以于一输出端产生一输出电压。第一电阻耦接于一第一节点与一接地端之间。反馈电压产生于第一节点。第二电阻耦接于输出端与第一节点之间。在低压差稳压器的一启动时间点，第二电阻具有一第一电阻值。在输入电压达到一最大电压后，第二电阻具有一第二电阻值。第二电阻值大于第一电阻值。Some embodiments of the present invention relate to a low dropout voltage stabilizing system. The low dropout voltage regulator system includes a low dropout voltage regulator. The low dropout regulator includes a comparator circuit, an amplifying circuit, a transistor, a first resistor and a second resistor. The comparison circuit is used for generating a comparison voltage according to a reference voltage and a feedback voltage. The amplifying circuit is used for generating an amplified voltage according to the comparison voltage. The transistor is used for receiving an input voltage and being controlled by the amplified voltage to generate an output voltage at an output terminal. The first resistor is coupled between a first node and a ground terminal. The feedback voltage is generated at the first node. The second resistor is coupled between the output terminal and the first node. At a start-up time point of the low dropout voltage regulator, the second resistor has a first resistance value. After the input voltage reaches a maximum voltage, the second resistor has a second resistance value. The second resistance value is greater than the first resistance value.
本发明的一些实施方式涉及一种低压差稳压系统。低压差稳压系统包括一低压差稳压器。低压差稳压器包括一比较电路、一放大电路、一晶体管、一第一电阻以及一第二电阻。比较电路用于依据一参考电压以及一反馈电压产生一比较电压。放大电路用于依据该比较电压产生一放大电压。晶体管用于接收一输入电压且受该放大电压控制以于一输出端产生一输出电压。第一电阻耦接于一第一节点与一接地端之间。反馈电压产生于第一节点。第二电阻耦接于输出端与第一节点之间。当低压差稳压器从一轻载模式转为一重载模式时，第二电阻从一第一电阻值转为具有一第二电阻值。第二电阻值小于第一电阻值。Some embodiments of the present invention relate to a low dropout voltage stabilizing system. The low dropout voltage regulator system includes a low dropout voltage regulator. The low dropout regulator includes a comparator circuit, an amplifying circuit, a transistor, a first resistor and a second resistor. The comparison circuit is used for generating a comparison voltage according to a reference voltage and a feedback voltage. The amplifying circuit is used for generating an amplified voltage according to the comparison voltage. The transistor is used for receiving an input voltage and being controlled by the amplified voltage to generate an output voltage at an output terminal. The first resistor is coupled between a first node and a ground terminal. The feedback voltage is generated at the first node. The second resistor is coupled between the output terminal and the first node. When the low dropout regulator changes from a light load mode to a heavy load mode, the second resistor changes from a first resistance value to a second resistance value. The second resistance value is smaller than the first resistance value.
本发明的一些实施方式涉及一种用于一低压差稳压系统的控制方法。控制方法包括以下操作：在一低压差稳压器的一启动时间点，根据一数字控制器控制低压差稳压器的一电阻分压比例具有一第一比例值；以及在低压差稳压器的一输入电压达到一最大电压后，根据数字控制器控制该电阻分压比例转为具有一第二比例值。第二比例值小于第一比例值。Some embodiments of the present invention relate to a control method for a low dropout voltage stabilizing system. The control method includes the following operations: at a start-up time point of a low dropout voltage regulator, a digital controller controls a resistor divider ratio of the low dropout voltage regulator to have a first ratio value; and in the low dropout voltage regulator After an input voltage reaches a maximum voltage, the resistor divider ratio is controlled by a digital controller to have a second ratio value. The second proportional value is smaller than the first proportional value.
综上所述，本发明可避免低压差稳压器的输出电压发生严重下冲的问题，进而提高低压差稳压器的效能。To sum up, the present invention can avoid the serious undershoot of the output voltage of the low dropout voltage regulator, thereby improving the performance of the low dropout voltage regulator.
附图说明Description of drawings
为让本发明的上述和其他目的、特征、优点与实施例能够更明显易懂，对附图说明如下：In order to make the above and other purposes, features, advantages and embodiments of the present invention more obvious and understandable, the accompanying drawings are described as follows:
图1为根据本发明一些实施例示出的一低压差稳压系统的示意图；FIG. 1 is a schematic diagram of a low dropout voltage stabilizing system according to some embodiments of the present invention;
图2为根据本发明一些实施例示出的一低压差稳压器的示意图；2 is a schematic diagram of a low dropout regulator according to some embodiments of the present invention;
图3为根据本发明一些实施例示出的图2中两个电阻的示意图；Fig. 3 is a schematic diagram of two resistors shown in Fig. 2 according to some embodiments of the present invention;
图4为根据本发明一些实施例示出的多个信号的波形图；FIG. 4 is a waveform diagram of multiple signals shown according to some embodiments of the present invention;
图5为根据本发明一些实施例示出的多个信号的波形图；以及5 is a waveform diagram of multiple signals shown according to some embodiments of the present invention; and
图6为根据本发明一些实施例示出的控制方法的流程图。Fig. 6 is a flowchart of a control method according to some embodiments of the present invention.
附图标记说明：Explanation of reference signs:
100-低压差稳压系统 110-低压差稳压器 111-比较电路100-Low dropout regulator system 110-Low dropout regulator 111-Comparison circuit
112-放大电路 120-数字控制器 600-控制方法112-amplification circuit 120-digital controller 600-control method
DS-检测结果信号 M1-晶体管 R1-电阻DS-detection result signal M1-transistor R1-resistance
R2-电阻 β-电阻分压比例 CL-负载电容R2-resistor β-resistor voltage divider ratio CL-load capacitance
CC-补偿电容 VDD-电源电压 VIN-输入电压CC-compensation capacitor VDD-power supply voltage VIN-input voltage
VREF-参考电压 VFB-反馈电压 VM-比较电压VREF-reference voltage VFB-feedback voltage VM-comparison voltage
VG-放大电压 VOUT-输出电压 OUT-输出端VG-amplified voltage VOUT-output voltage OUT-output terminal
GND-接地端 N1、N2-节点 IL-负载电流GND-ground terminal N1, N2-node IL-load current
VL-负载电压 TUNE’[0：6]-反相调 TUNE_V-调整电压 整信号VL-load voltage TUNE’[0:6]-reverse phase adjustment TUNE_V-adjust voltage adjustment signal
RR1、RR2、RR4、RR8、RR16、RR32、RR64-电阻器RR1, RR2, RR4, RR8, RR16, RR32, RR64 - resistors
S1、S2、S4、S8、S16、S32、S64-开关S1, S2, S4, S8, S16, S32, S64-Switches
T1、T2、T3、T4、T5、T6、T7、t1、t2、t3-时间点T1, T2, T3, T4, T5, T6, T7, t1, t2, t3-time points
DT-延迟时间 TUNE[0：6]-调整信号 S610、S620-操作DT-delay time TUNE[0:6]-adjustment signal S610, S620-operation
具体实施方式Detailed ways
在本说明书中所使用的用词“耦接”也可指“电性耦接”，且用词“连接”也可指“电性连接”。“耦接”及“连接”也可指两个或多个元件相互配合或相互互动。The term "coupled" used in this specification may also refer to "electrically coupled", and the term "connected" may also refer to "electrically connected". "Coupled" and "connected" may also mean that two or more elements cooperate or interact with each other.
参考图1。图1为根据本发明一些实施例示出的低压差稳压系统100的示意图。Refer to Figure 1. FIG. 1 is a schematic diagram of a low dropout voltage stabilizing system 100 according to some embodiments of the present invention.
以图1为示例，低压差稳压系统100包括低压差稳压器110以及数字控制器120。数字控制器120耦接低压差稳压器110。Taking FIG. 1 as an example, the low dropout voltage regulator system 100 includes a low dropout voltage regulator 110 and a digital controller 120 . The digital controller 120 is coupled to the low dropout voltage regulator 110 .
参考图2。图2为根据本发明一些实施例示出的低压差稳压器110的示意图。Refer to Figure 2. FIG. 2 is a schematic diagram of a low dropout voltage regulator 110 according to some embodiments of the present invention.
低压差稳压器110的输出端OUT可耦接一负载，且低压差稳压器110可依据输入电压VIN于输出端OUT产生输出电压VOUT，以将输出电压VOUT提供给此负载。当此负载开始运作时，负载电流IL会提高，负载电压VL维持在输出电压VOUT。The output terminal OUT of the low dropout voltage regulator 110 can be coupled to a load, and the low dropout voltage regulator 110 can generate an output voltage VOUT at the output terminal OUT according to the input voltage VIN, so as to provide the output voltage VOUT to the load. When the load starts to operate, the load current IL increases, and the load voltage VL maintains at the output voltage VOUT.
再次参考图1。数字控制器120用于控制低压差稳压器110。在一些实施例中，数字控制器120可检测低压差稳压器110以接收检测结果信号DS，且依据检测结果信号DS设定一调整信号(如图4中的调整信号TUNE[0：6])，并依据调整信号产生反相调整信号TUNE’[0：6]以控制低压差稳压器110。在另一实施例中，数字控制器120直接依据调整信号TUNE[0：6]控制低压差稳压器110。Referring again to FIG. 1 . The digital controller 120 is used to control the low dropout voltage regulator 110 . In some embodiments, the digital controller 120 can detect the LDO 110 to receive the detection result signal DS, and set an adjustment signal according to the detection result signal DS (such as the adjustment signal TUNE[0:6] in FIG. 4 . ), and generate an inverted adjustment signal TUNE′[0:6] according to the adjustment signal to control the low dropout voltage regulator 110 . In another embodiment, the digital controller 120 directly controls the LDO voltage regulator 110 according to the tuning signal TUNE[0:6].
以图2为示例，低压差稳压器110包括比较电路111、放大电路112、晶体管M1、电阻R1、电阻R2、负载电容CL以及补偿电容CC。Taking FIG. 2 as an example, the low dropout voltage regulator 110 includes a comparison circuit 111 , an amplifier circuit 112 , a transistor M1 , a resistor R1 , a resistor R2 , a load capacitor CL and a compensation capacitor CC.
在这个实施例中，晶体管M1是以P型晶体管实现，但本发明不以此为限。在一些其他的实施例中，晶体管M1可改为以N型晶体管实现。在这些其他的实施例中，放大电路112的输出端可耦接一反相器。In this embodiment, the transistor M1 is implemented as a P-type transistor, but the invention is not limited thereto. In some other embodiments, the transistor M1 can be implemented as an N-type transistor instead. In these other embodiments, the output terminal of the amplifying circuit 112 may be coupled to an inverter.
比较电路111依据电源电压VDD(例如：1.8伏特)运作，且与放大电路112耦接于节点N2。比较电路111比较参考电压VREF与反馈电压VFB以于节点N2产生比较电压VM。放大电路112也依据电源电压VDD运作。放大电路112依据比较电压VM产生放大电压VG。晶体管M1的第一端接收输入电压VIN(例如：1.1伏特)，晶体管M1的第二端耦接输出端OUT，且晶体管M1的控制端接收放大电压VG。晶体管M1依据输入电压VIN以及放大电压VG于输出端OUT产生输出电压VOUT。电阻R1耦接于节点N1与接地端GND之间。电阻R2耦接于输出端OUT与节点N1之间。在这个配置下，电阻R1与电阻R2将形成一分压电路。而反馈电压VFB产生于节点N1。The comparison circuit 111 operates according to the power supply voltage VDD (for example: 1.8 volts), and is coupled to the node N2 with the amplifier circuit 112 . The comparison circuit 111 compares the reference voltage VREF and the feedback voltage VFB to generate a comparison voltage VM at the node N2. The amplifier circuit 112 also operates according to the power supply voltage VDD. The amplifying circuit 112 generates an amplified voltage VG according to the comparison voltage VM. A first terminal of the transistor M1 receives an input voltage VIN (eg, 1.1V), a second terminal of the transistor M1 is coupled to an output terminal OUT, and a control terminal of the transistor M1 receives an amplified voltage VG. The transistor M1 generates an output voltage VOUT at the output terminal OUT according to the input voltage VIN and the amplified voltage VG. The resistor R1 is coupled between the node N1 and the ground GND. The resistor R2 is coupled between the output terminal OUT and the node N1. Under this configuration, the resistor R1 and the resistor R2 will form a voltage divider circuit. And the feedback voltage VFB is generated at the node N1.
电阻R1与电阻R2的电阻分压比例如下列公式(1)：The resistor divider ratio between resistor R1 and resistor R2 is shown in the following formula (1):
其中r1为电阻R1的电阻值，r2为电阻R2的电阻值，且β为电阻R1与电阻R2的电阻分压比例。Wherein r1 is the resistance value of the resistor R1, r2 is the resistance value of the resistor R2, and β is a resistance voltage dividing ratio between the resistor R1 and the resistor R2.
反馈电压VFB与输出电压VOUT之间的关系如下列公式(2)：The relationship between the feedback voltage VFB and the output voltage VOUT is as the following formula (2):
另外，以图2为示例，负载电容CL耦接于输出端OUT与接地端GND之间。补偿电容CC则耦接于节点N2与输出端OUT之间。In addition, taking FIG. 2 as an example, the load capacitor CL is coupled between the output terminal OUT and the ground terminal GND. The compensation capacitor CC is coupled between the node N2 and the output terminal OUT.
参考图3。图3为根据本发明一些实施例示出的图2中两个电阻R1-R2的示意图。Refer to Figure 3. FIG. 3 is a schematic diagram of two resistors R1 - R2 shown in FIG. 2 according to some embodiments of the present invention.
以图3为示例，电阻R2包括多个电阻器RR1、RR2、RR4、RR8、RR16、RR32、RR64以及多个开关S1、S2、S4、S8、S16、S32、S64。这些电阻器RR1、RR2、RR4、RR8、RR16、RR32、RR64之间串联耦接。各开关与一对应电阻器并联耦接。举例而言，开关S1与电阻器RR1并联耦接，开关S2与电阻器RR2并联耦接，以此类推。这些开关S1、S2、S4、S8、S16、S32、S64在本实施例中可以N型晶体管实现，且这些开关S1、S2、S4、S8、S16、S32、S64的控制端(例如：晶体管的闸极端)分别接收反相调整信号TUNE’[0]、TUNE’[1]、TUNE’[2]、TUNE’[3]、TUNE’[4]、TUNE’[5]、TUNE’[6]。举例而言，当反相调整信号TUNE’[6]的电位具有逻辑值1时，开关S64为导通。当反相调整信号TUNE’[6]的电位具有逻辑值0时，开关S64为截止。其他反相调整信号与开关具有相似的运作方式，故在此不再赘述。在另一实施例中，这些开关S1、S2、S4、S8、S16、S32、S64的控制端分别接收来自数字控制器120产生的调整信号TUNE[0：6]来导通或截止，而这些开关在本实施例中可以P型晶体管实现。Taking FIG. 3 as an example, the resistor R2 includes a plurality of resistors RR1 , RR2 , RR4 , RR8 , RR16 , RR32 , RR64 and a plurality of switches S1 , S2 , S4 , S8 , S16 , S32 , S64 . These resistors RR1 , RR2 , RR4 , RR8 , RR16 , RR32 , RR64 are coupled in series. Each switch is coupled in parallel with a corresponding resistor. For example, the switch S1 is coupled in parallel with the resistor RR1 , the switch S2 is coupled in parallel with the resistor RR2 , and so on. These switches S1, S2, S4, S8, S16, S32, and S64 can be realized by N-type transistors in this embodiment, and the control terminals of these switches S1, S2, S4, S8, S16, S32, and S64 (for example: Gate terminals) respectively receive the anti-phase adjustment signals TUNE'[0], TUNE'[1], TUNE'[2], TUNE'[3], TUNE'[4], TUNE'[5], TUNE'[6] . For example, when the potential of the inverted adjustment signal TUNE'[6] has a logic value of 1, the switch S64 is turned on. When the potential of the inverted adjustment signal TUNE'[6] has a logic value of 0, the switch S64 is turned off. Other anti-phase adjustment signals and switches have a similar operation mode, so details will not be repeated here. In another embodiment, the control terminals of these switches S1, S2, S4, S8, S16, S32, and S64 respectively receive the adjustment signal TUNE[0:6] generated by the digital controller 120 to turn on or off, and these The switches can be implemented with P-type transistors in this embodiment.
参考图2-图4。图4为根据本发明一些实施例示出的多个信号的波形图。Refer to Figures 2-4. Fig. 4 is a waveform diagram showing multiple signals according to some embodiments of the present invention.
以下将1.1伏特转为1伏特的低压差稳压器为例进行说明。也就是说，输入电压VIN的最大电压为1.1伏特，而输出电压VOUT的最终目标电压为1伏特。然而，本发明不以此实施例为限。The low dropout voltage regulator converting 1.1 volts to 1 volts is described below as an example. That is, the maximum voltage of the input voltage VIN is 1.1 volts, and the final target voltage of the output voltage VOUT is 1 volt. However, the present invention is not limited to this embodiment.
首先，以图4为示例，在时间点T1至时间点T5之间，数字控制器120可将调整电压TUNE_V设定为较小(例如：第一值)。调整电压TUNE_V可对应于调整信号TUNE[0：6]的十进制值。详细内容将在下文段落中进行描述。First, taking FIG. 4 as an example, the digital controller 120 may set the adjustment voltage TUNE_V to a smaller value (for example, a first value) between the time point T1 and the time point T5. The tuning voltage TUNE_V may correspond to the decimal value of the tuning signal TUNE[0:6]. Details will be described in the following paragraphs.
在时间点T1(启动时间点)，低压差稳压器110开始启动且输入电压VIN从0伏特开始上升。此时，由于低压差稳压器110的负反馈稳态尚未建立，因此比较电压VM和放大电压VG的电位具有逻辑值0。另外，由于此时的输入电压VIN还很小，因此输入电压VIN与放大电压VG之间的电压差尚未达到晶体管M1的临界电压。据此，晶体管M1为截止。At time point T1 (start-up time point), the low dropout voltage regulator 110 starts to start and the input voltage VIN starts to rise from 0 volts. At this time, since the negative feedback steady state of the low dropout voltage regulator 110 has not been established, the potentials of the comparison voltage VM and the amplification voltage VG have a logic value of 0. In addition, since the input voltage VIN at this time is still very small, the voltage difference between the input voltage VIN and the amplified voltage VG has not yet reached the critical voltage of the transistor M1. Accordingly, the transistor M1 is turned off.
在时间点T2，由于输入电压VIN与放大电压VG之间的电压差已达到晶体管M1的临界电压，因此晶体管M1转为导通。由于晶体管M1导通，因此输出电压VOUT可依据输入电压VIN而开始上升且输出电压VOUT接近于输入电压VIN。At time point T2, since the voltage difference between the input voltage VIN and the amplified voltage VG has reached the threshold voltage of the transistor M1, the transistor M1 is turned on. Since the transistor M1 is turned on, the output voltage VOUT can start to rise according to the input voltage VIN and the output voltage VOUT is close to the input voltage VIN.
由上述公式(2)可知，当输出电压VOUT依据输入电压VIN开始上升时，反馈电压VFB也会开始上升。From the above formula (2), it can be seen that when the output voltage VOUT starts to rise according to the input voltage VIN, the feedback voltage VFB also starts to rise.
在时间点T3，当反馈电压VFB与参考电压VREF之间的差值小于一阈值时，由比较电路111所输出的比较电压VM会开始上升。由于比较电压VM开始上升，由放大电路112所输出的放大电压VG也会开始上升。在这个实施例中，基于放大电路112的放大增益，放大电压VG的上升斜率大于比较电压VM的上升斜率。由于放大电压VG的电位快速上升至逻辑值1，晶体管M1将被截止使得输出电压VOUT不再上升。At time point T3, when the difference between the feedback voltage VFB and the reference voltage VREF is smaller than a threshold, the comparison voltage VM output by the comparison circuit 111 starts to increase. Since the comparison voltage VM starts to rise, the amplified voltage VG output by the amplifying circuit 112 also starts to rise. In this embodiment, based on the amplification gain of the amplifying circuit 112 , the rising slope of the amplified voltage VG is larger than that of the comparison voltage VM. Since the potential of the amplified voltage VG rises rapidly to a logic value of 1, the transistor M1 is turned off so that the output voltage VOUT does not rise any more.
如前所述，此时调整电压TUNE_V为较小(例如：第一值)，这代表调整信号TUNE[0：6]较小。由于反相调整信号TUNE’[0：6]为调整信号TUNE[0：6]的反相，因此反相调整信号TUNE’[0：6]较大。以图3为示例，当反相调整信号TUNE’[0：6]较大时，电阻R2的电阻值r2会较小(例如：第一电阻值)。基于上述公式(1)可知，当电阻值r2较小，电阻分压比例β会较大。也就是说，调整电压TUNE_V与电阻R2的电阻值r2为正相关，但调整电压TUNE_V与电阻分压比例β为负相关。As mentioned above, the tuning voltage TUNE_V is relatively small (for example, the first value), which means that the tuning signal TUNE[0:6] is relatively small. Since the inverted adjustment signal TUNE'[0:6] is the inverted phase of the adjusted signal TUNE[0:6], the inverted adjustment signal TUNE'[0:6] is relatively large. Taking FIG. 3 as an example, when the inverted adjustment signal TUNE'[0:6] is larger, the resistance value r2 of the resistor R2 will be smaller (for example: the first resistance value). Based on the above formula (1), it can be seen that when the resistance value r2 is small, the resistance voltage dividing ratio β will be large. That is to say, the adjustment voltage TUNE_V is positively correlated with the resistance value r2 of the resistor R2 , but the adjustment voltage TUNE_V is negatively correlated with the resistor divider ratio β.
另外，基于上述公式(2)可知，当低压差稳压器110锁定时(也就是，反馈电压VFB被锁定于一固定值)，电阻分压比例β与输出电压VOUT为负相关。进一步而言，由于调整电压TUNE_V与电阻分压比例β为负相关，因此调整电压TUNE_V与输出电压VOUT的目标电压为正相关。换句话说，当调整电压TUNE_V较小时，输出电压VOUT的目标电压也会较小。如前所述，由于此时调整电压TUNE_V为较小(例如：第一值)，因此此时输出电压VOUT的目标电压(例如：0.9伏特)可低于最终目标电压(例如：1伏特)。In addition, based on the above formula (2), it can be seen that when the low dropout voltage regulator 110 is locked (that is, the feedback voltage VFB is locked at a fixed value), the resistor divider ratio β is negatively correlated with the output voltage VOUT. Further, since the tuning voltage TUNE_V is negatively correlated with the resistor voltage dividing ratio β, the tuning voltage TUNE_V is positively correlated with the target voltage of the output voltage VOUT. In other words, when the tuning voltage TUNE_V is smaller, the target voltage of the output voltage VOUT is also smaller. As mentioned above, since the adjustment voltage TUNE_V is relatively small (eg, the first value), the target voltage (eg, 0.9V) of the output voltage VOUT at this time may be lower than the final target voltage (eg, 1V).
在实际运作过程中，当晶体管M1导通时，输出电压VOUT相较于当下的目标电压可能会发生些微过冲(overshoot)的现象。也就是说，输出电压VOUT实际上会略大于当下的目标电压(例如：0.9伏特)。举例而言，输出电压VOUT可能会过冲至0.95伏特。然而，虽然输出电压VOUT(例如：0.95伏特)略大于当下的目标电压(例如：0.9伏特)，但输出电压VOUT仍低于最终目标电压(例如：1伏特)。In actual operation, when the transistor M1 is turned on, the output voltage VOUT may slightly overshoot compared with the current target voltage. That is to say, the output voltage VOUT will actually be slightly greater than the current target voltage (for example: 0.9 volts). For example, the output voltage VOUT may overshoot to 0.95V. However, although the output voltage VOUT (for example: 0.95V) is slightly greater than the current target voltage (for example: 0.9V), the output voltage VOUT is still lower than the final target voltage (for example: 1V).
接着，如前所述，数字控制器120可检测输入电压VIN是否达到最大电压(例如：1.1伏特)。以图4为示例，在时间点T4，数字控制器120的检测结果信号DS为输入电压VIN达到最大电压(例如：1.1伏特)。Then, as mentioned above, the digital controller 120 can detect whether the input voltage VIN reaches the maximum voltage (for example: 1.1V). Taking FIG. 4 as an example, at the time point T4 , the detection result signal DS of the digital controller 120 is that the input voltage VIN reaches a maximum voltage (for example: 1.1 volts).
接着，经过延迟时间DT后(在时间点T5)，数字控制器120可将调整电压TUNE_V设定为较大(例如：大于第一值的第二值)。也就是说，将电阻R2的电阻值r2调整为较大(例如：大于第一电阻值的第二电阻值)。如前所述，调整电压TUNE_V与输出电压VOUT的目标电压为正相关。也就是说，当调整电压TUNE_V较大时，输出电压VOUT的目标电压会从0.9伏特被拉升至更高的水平以使输出电压VOUT上升至最终目标电压(例如：1伏特)，如时间点T6。如此一来，低压差稳压器110可在未超过最终目标电压(例如：1伏特)的情况下，将输出电压VOUT锁定在最终目标电压(例如：1伏特)，以快速进入锁定状态。Then, after the delay time DT (at time point T5 ), the digital controller 120 can set the tuning voltage TUNE_V to be larger (eg, a second value greater than the first value). That is to say, the resistance value r2 of the resistor R2 is adjusted to be larger (for example: a second resistance value greater than the first resistance value). As mentioned above, the adjustment voltage TUNE_V is positively correlated with the target voltage of the output voltage VOUT. That is to say, when the adjustment voltage TUNE_V is larger, the target voltage of the output voltage VOUT will be pulled up from 0.9 volts to a higher level to make the output voltage VOUT rise to the final target voltage (for example: 1 volt), such as the time point T6. In this way, the LDO voltage regulator 110 can lock the output voltage VOUT at the final target voltage (eg, 1V) without exceeding the final target voltage (eg, 1V), so as to quickly enter the locked state.
在一些相关技术中，低压差稳压器的输出电压会超过最终目标电压且长时间维持在失锁状态。此时，若负载开始运作，则低压差稳压器的输出电压将会发生严重下冲(undershoot)的问题。In some related technologies, the output voltage of the LDO voltage regulator will exceed the final target voltage and remain in an unlocked state for a long time. At this time, if the load starts to operate, the output voltage of the low dropout voltage regulator will have a serious undershoot problem.
相较于上述这些相关技术，在本发明中，数字控制器120先将调整电压TUNE_V设定为较小(电阻R2的电阻值r2为较小)。在输入电压VIN达到最大电压后，再将调整电压TUNE_V设定为较大(电阻R2的电阻值r2为较大)。据此，可避免输出电压OUT超过最终目标电压且使低压差稳压器110快速进入锁定状态。由于低压差稳压器110已快速进入锁定状态，因此即使负载开始运作，输出电压OUT也不会发生严重下冲的问题。Compared with the related technologies mentioned above, in the present invention, the digital controller 120 first sets the adjustment voltage TUNE_V to be smaller (the resistance value r2 of the resistor R2 is smaller). After the input voltage VIN reaches the maximum voltage, the adjustment voltage TUNE_V is set to be larger (the resistance value r2 of the resistor R2 is larger). Accordingly, the output voltage OUT can be prevented from exceeding the final target voltage and the low dropout voltage regulator 110 can be quickly entered into the locked state. Since the low dropout voltage regulator 110 has quickly entered the locked state, even if the load starts to operate, the output voltage OUT will not suffer serious undershoot.
参考图5。图5为根据本发明一些实施例示出的多个信号的波形图。Refer to Figure 5. Fig. 5 is a waveform diagram showing multiple signals according to some embodiments of the present invention.
在一些实施例中，耦接于输出端OUT的负载会在重载状态与轻载状态之间切换。举例而言，当负载电流IL为大电流，代表负载处于重载状态。当负载电流IL为小电流时，代表负载处于轻载状态。In some embodiments, the load coupled to the output terminal OUT is switched between a heavy load state and a light load state. For example, when the load current IL is a large current, it means that the load is in a heavy load state. When the load current IL is a small current, it means that the load is in a light load state.
在时间点t1，负载从重载状态(负载电流IL为大电流)转为轻载状态(负载电流IL为小电流)。At the time point t1, the load changes from a heavy load state (the load current IL is a large current) to a light load state (the load current IL is a small current).
在时间点t1与时间点t2之间，负载处于轻载状态(负载电流IL为小电流)。当负载处于轻载状态时，数字控制器120可将调整电压TUNE_V设定为较大(例如：第三值)。如前所述，调整电压TUNE_V与电阻分压比例β为负相关。另外，基于上述公式(2)可知，电阻分压比例β与反馈电压VFB为正相关。也就是说，当调整电压TUNE_V设定为较大时，电阻分压比例β会较小且反馈电压VFB会较低。Between the time point t1 and the time point t2, the load is in a light load state (the load current IL is a small current). When the load is in a light load state, the digital controller 120 can set the tuning voltage TUNE_V to a larger value (for example, a third value). As mentioned above, the adjustment voltage TUNE_V is negatively correlated with the resistor divider ratio β. In addition, based on the above formula (2), it can be seen that the resistor voltage divider ratio β is positively correlated with the feedback voltage VFB. That is to say, when the tuning voltage TUNE_V is set to be larger, the resistor divider ratio β will be smaller and the feedback voltage VFB will be lower.
在时间点t2，负载从轻载状态(负载电流IL为小电流)转为重载状态(负载电流IL为大电流)。数字控制器120可将调整电压TUNE_V设定为较小(例如：小于第三值的第四值)。At time point t2, the load changes from a light load state (load current IL is a small current) to a heavy load state (load current IL is a large current). The digital controller 120 can set the tuning voltage TUNE_V to be smaller (eg, a fourth value smaller than the third value).
在一些相关技术中，当负载从重载状态转为轻载状态时(对应本发明的时间点t1)，比较电压会上升(如第5图中对应于比较电压VM的虚线)，使得放大电压对应地上升以关闭后端晶体管，进而不再提供电流或提供较小的电流。然而，电位上升的比较电压会需要一段时间恢复至低电位(稳态)。若恢复时间太短，则使得负载在比较电压尚未恢复至低电位(非稳态)的情况下就从轻载状态转为重载状态，这会使得输出电压发生严重下冲(如第5图中对应于输出电压VOUT的虚线)。In some related technologies, when the load changes from the heavy-load state to the light-load state (corresponding to the time point t1 of the present invention), the comparison voltage will rise (as shown in the dotted line corresponding to the comparison voltage VM in Figure 5), so that the amplified voltage Correspondingly rise to turn off the back-end transistor, and then no longer provide current or provide a smaller current. However, it takes a while for the comparative voltage whose potential rises to return to a low potential (steady state). If the recovery time is too short, the load will change from a light load state to a heavy load state before the comparison voltage returns to a low potential (unsteady state), which will cause a serious undershoot of the output voltage (as shown in Figure 5 Corresponding to the dotted line in the output voltage VOUT).
相较于上述这些相关技术，在本发明中，当负载处于轻载状态时，数字控制器120将调整电压TUNE_V设定为较大(电阻R2的电阻值r2较大)，这使得电阻分压比例β较小且使反馈电压VFB较低。由于反馈电压VFB较低，因此由比较电路111所输出的比较电压VM较不易上升。据此，比较电压VM恢复至低电位(稳态)的时间可较短。在这个情况下，当负载切回重载状态时，输出电压VOUT将不会发生严重下冲(如第5图中对应于输出电压VOUT的实线)。Compared with the above-mentioned related technologies, in the present invention, when the load is in a light-load state, the digital controller 120 sets the adjustment voltage TUNE_V to be larger (the resistance value r2 of the resistor R2 is larger), which makes the resistor voltage divider The ratio β is smaller and makes the feedback voltage VFB lower. Since the feedback voltage VFB is relatively low, the comparison voltage VM output by the comparison circuit 111 is less likely to increase. Accordingly, the time for the comparison voltage VM to return to a low level (steady state) can be shorter. In this case, when the load switches back to the heavy load state, the output voltage VOUT will not experience severe undershoot (as shown in Fig. 5 corresponding to the solid line of the output voltage VOUT).
接着，在时间点t3，负载从重载状态(负载电流IL为大电流)转为轻载状态(负载电流IL为小电流)。数字控制器120可将调整电压TUNE_V恢复较大(例如：恢复为第三值)。简单而言，当负载处于轻载状态时，数字控制器120将调整电压TUNE_V设定为较大。当负载处于重载状态时，数字控制器120将调整电压TUNE_V设定为较小。Then, at time point t3, the load changes from the heavy load state (the load current IL is a large current) to the light load state (the load current IL is a small current). The digital controller 120 can restore the adjustment voltage TUNE_V to be larger (for example: restore to a third value). In short, when the load is in a light load state, the digital controller 120 sets the tuning voltage TUNE_V to be larger. When the load is in a heavy load state, the digital controller 120 sets the tuning voltage TUNE_V to be smaller.
基于上述关于图5的描述，在图4中的时间点T5至时间点T7之间，负载处于轻载状态(负载电流IL为小电流)，因此数字控制器120将调整电压TUNE_V设定为较大(例如：大于第一值的第二值)，这使得电阻R2的电阻值r2为较大(例如：第二电阻值)。在时间点T7之后，负载处于重载状态(负载电流IL为大电流)，因此数字控制器120将调整电压TUNE_V设定为较小(例如：小于第二值但大于第一值的第三值)，使得电阻R2的电阻值r2为较小(例如：小于第二电阻值但大于第一电阻值的第三电阻值)。这同样可避免输出电压VOUT发生严重下冲的问题。Based on the above description about FIG. 5 , between the time point T5 and the time point T7 in FIG. large (for example: a second value greater than the first value), which makes the resistance value r2 of the resistor R2 larger (for example: a second resistance value). After the time point T7, the load is in a heavy load state (the load current IL is a large current), so the digital controller 120 sets the adjustment voltage TUNE_V to be smaller (for example: a third value smaller than the second value but larger than the first value ), so that the resistance value r2 of the resistor R2 is small (for example: a third resistance value smaller than the second resistance value but greater than the first resistance value). This also avoids the problem of severe undershoot of the output voltage VOUT.
参考图6。图6是本发明一些实施例的控制方法600的流程图。Refer to Figure 6. FIG. 6 is a flowchart of a control method 600 of some embodiments of the present invention.
在一些实施例中，控制方法600可应用于图1中的低压差稳压系统100，但本发明不以此为限。然而，为了易于了解，将结合图1中的低压差稳压系统100对控制方法600进行描述。In some embodiments, the control method 600 can be applied to the low dropout voltage stabilizing system 100 in FIG. 1 , but the invention is not limited thereto. However, for ease of understanding, the control method 600 will be described in conjunction with the low dropout voltage stabilizing system 100 in FIG. 1 .
以图6为示例，控制方法600包括操作S610以及操作S620。Taking FIG. 6 as an example, the control method 600 includes operation S610 and operation S620.
在操作S610中，在低压差稳压器110的启动时间点(例如：第4图中的时间点T1)，根据数字控制器120控制低压差稳压器110的电阻分压比例β具有第一比例值。如前所述，在时间点T1至时间点T5，数字控制器120可将调整电压TUNE_V设定为较小，且调整电压TUNE_V与电阻分压比例β为负相关。等效而言，此时电阻分压比例β较大。In operation S610, at the startup time point of the low dropout voltage regulator 110 (for example: time point T1 in FIG. scale value. As mentioned above, from time point T1 to time point T5 , the digital controller 120 can set the adjustment voltage TUNE_V to be smaller, and the adjustment voltage TUNE_V is negatively correlated with the resistor voltage dividing ratio β. Equivalently speaking, the resistor voltage division ratio β is relatively large at this time.
在操作S620中，在低压差稳压器110的输入电压VIN达到最大电压(例如：1.1伏特)后，根据数字控制器120控制电阻分压比例β转为具有第二比例值，此第二比例值小于操作S610中的第一比例值。在时间点T5，数字控制器120可将调整电压TUNE_V设定为较大。也就是说，此时电阻分压比例β较小。In operation S620, after the input voltage VIN of the low dropout regulator 110 reaches the maximum voltage (for example: 1.1 volts), the digital controller 120 controls the resistor divider ratio β to have a second ratio value, the second ratio The value is smaller than the first proportional value in operation S610. At time point T5, the digital controller 120 can set the tuning voltage TUNE_V to be larger. That is to say, at this time, the resistor voltage dividing ratio β is relatively small.
综上所述，本发明可避免低压差稳压器的输出电压发生严重下冲的问题，进而提高低压差稳压器的效能。To sum up, the present invention can avoid the serious undershoot of the output voltage of the low dropout voltage regulator, thereby improving the performance of the low dropout voltage regulator.
虽然本发明的实施例如上所述，然而这些实施例并非用来限定本发明，任何本技术领域中具有普通知识的技术人员，在不脱离本发明之精神和范围内，可以进行更动与修饰，因此本发明的保护范围应当根据本发明权利要求书所界定的为准。Although the embodiments of the present invention are as described above, these embodiments are not intended to limit the present invention, and any skilled person in the technical field can make changes and modifications without departing from the spirit and scope of the present invention. , so the protection scope of the present invention should be defined according to the claims of the present invention.
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| CN202210067898.9ACN116520922A (en) | 2022-01-20 | 2022-01-20 | Low dropout voltage stabilizing system and its control method |
| Application Number | Priority Date | Filing Date | Title |
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| CN202210067898.9ACN116520922A (en) | 2022-01-20 | 2022-01-20 | Low dropout voltage stabilizing system and its control method |
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| CN202210067898.9APendingCN116520922A (en) | 2022-01-20 | 2022-01-20 | Low dropout voltage stabilizing system and its control method |
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| CN117270619A (en)* | 2023-11-17 | 2023-12-22 | 苏州贝克微电子股份有限公司 | Circuit structure for improving stability of output voltage |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070018623A1 (en)* | 2005-07-21 | 2007-01-25 | Agere Systems Inc. | Low-dropout regulator with startup overshoot control |
| US20090027110A1 (en)* | 2007-07-25 | 2009-01-29 | Hynix Semiconductor Inc. | High voltage generator |
| US20090302811A1 (en)* | 2008-06-09 | 2009-12-10 | Yotaro Nihei | Voltage regulator |
| US20150061623A1 (en)* | 2013-09-04 | 2015-03-05 | Samsung Electro-Mechanics Co., Ltd. | Voltage regulator of low-drop-output type and operation method of the same |
| US20160062376A1 (en)* | 2014-09-01 | 2016-03-03 | Samsung Electro-Mechanics Co., Ltd. | Low-drop-output type voltage regulator and rf switching control device having the same |
| CN106200731A (en)* | 2015-04-29 | 2016-12-07 | 展讯通信（上海）有限公司 | Multiple power supplies calibration system and method for work thereof |
| US10345840B1 (en)* | 2018-02-07 | 2019-07-09 | Hua Cao | Low dropout regulator (LDO) |
| CN112148055A (en)* | 2020-10-23 | 2020-12-29 | 湖南大学 | Adaptive filtering control circuit applied to multi-voltage output LDO chip |
| US20210021270A1 (en)* | 2017-01-10 | 2021-01-21 | Southern University Of Science And Technology | Low dropout linear voltage regulator |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070018623A1 (en)* | 2005-07-21 | 2007-01-25 | Agere Systems Inc. | Low-dropout regulator with startup overshoot control |
| US20090027110A1 (en)* | 2007-07-25 | 2009-01-29 | Hynix Semiconductor Inc. | High voltage generator |
| US20090302811A1 (en)* | 2008-06-09 | 2009-12-10 | Yotaro Nihei | Voltage regulator |
| US20150061623A1 (en)* | 2013-09-04 | 2015-03-05 | Samsung Electro-Mechanics Co., Ltd. | Voltage regulator of low-drop-output type and operation method of the same |
| US20160062376A1 (en)* | 2014-09-01 | 2016-03-03 | Samsung Electro-Mechanics Co., Ltd. | Low-drop-output type voltage regulator and rf switching control device having the same |
| CN106200731A (en)* | 2015-04-29 | 2016-12-07 | 展讯通信（上海）有限公司 | Multiple power supplies calibration system and method for work thereof |
| US20210021270A1 (en)* | 2017-01-10 | 2021-01-21 | Southern University Of Science And Technology | Low dropout linear voltage regulator |
| US10345840B1 (en)* | 2018-02-07 | 2019-07-09 | Hua Cao | Low dropout regulator (LDO) |
| CN112148055A (en)* | 2020-10-23 | 2020-12-29 | 湖南大学 | Adaptive filtering control circuit applied to multi-voltage output LDO chip |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117270619A (en)* | 2023-11-17 | 2023-12-22 | 苏州贝克微电子股份有限公司 | Circuit structure for improving stability of output voltage |
| CN117270619B (en)* | 2023-11-17 | 2024-02-09 | 苏州贝克微电子股份有限公司 | Circuit structure for improving stability of output voltage |
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