技术领域technical field
本发明属于低功耗电源管理芯片技术领域，涉及一种静态功耗的压差线性稳压器(low dropout regulator简称LDO)电路。The invention belongs to the technical field of low power consumption power management chips, and relates to a static power consumption differential pressure linear regulator (low dropout regulator for short LDO) circuit.
背景技术Background technique
请参阅图1，图1所示为现有技术中的一种低静态功耗的LDO电路示意图。如图1所示，该电路可以包含电路输入端、电路输出端、参考信号、接地端、第一放大器、第二放大器、PMOS管M3和用于输出采样信号的输出采样模块。Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a low static power consumption LDO circuit in the prior art. As shown in FIG. 1 , the circuit may include a circuit input terminal, a circuit output terminal, a reference signal, a ground terminal, a first amplifier, a second amplifier, a PMOS transistor M3 and an output sampling module for outputting sampling signals.
其中，所述第一放大器的一输入端连接参考信号，另一输入端连接输出采样模块的输出端，所述第一放大器的输出端连接第二放大器的输入端，用于根据所述采样信号和参考信号，产生第一控制信号；所述第二放大器的另一输入端连接第一放大器的输出端，输出端连接PMOS管M3的栅极，用于根据所述第一控制信号，产生第二控制信号；所述PMOS管M3的源极连接于输入端，漏极连接输出端，栅极连接第二放大器的输出端，用于根据所述第二控制信号，设置电路输出端的输出电压；所述输出采样模块连接于输出端和接地端之间，输出端连接到第一放大器的一输入端，用于根据该输出电压产生一个与电路输出端的输出电压相关的采样信号。Wherein, one input end of the first amplifier is connected to the reference signal, the other input end is connected to the output end of the output sampling module, the output end of the first amplifier is connected to the input end of the second amplifier, and is used to and the reference signal to generate the first control signal; the other input end of the second amplifier is connected to the output end of the first amplifier, and the output end is connected to the gate of the PMOS transistor M3 for generating the first control signal according to the first control signal. Two control signals; the source of the PMOS transistor M3 is connected to the input terminal, the drain is connected to the output terminal, and the gate is connected to the output terminal of the second amplifier, for setting the output voltage of the circuit output terminal according to the second control signal; The output sampling module is connected between the output terminal and the ground terminal, the output terminal is connected to an input terminal of the first amplifier, and is used for generating a sampling signal related to the output voltage of the circuit output terminal according to the output voltage.
进一步地，所述的第二放大器可以第二放大器包含NMOS管M1和PMOS管M2，所述NMOS管M1的栅极连接第二放大器的输入端，源极接地，漏极接第二放大器的输出端，所述PMOS管M2的栅极连接第二放大器的输出端，源极接输入端，漏极接第二放大器的输出端；PMOS管M2用于根据M3的电流，产生一镜像电流。Further, the second amplifier may include an NMOS transistor M1 and a PMOS transistor M2, the gate of the NMOS transistor M1 is connected to the input terminal of the second amplifier, the source is grounded, and the drain is connected to the output of the second amplifier. The gate of the PMOS transistor M2 is connected to the output terminal of the second amplifier, the source is connected to the input terminal, and the drain is connected to the output terminal of the second amplifier; the PMOS transistor M2 is used to generate a mirror current according to the current of M3.
本领域技术人员清楚，当所述电路的输入电压低于所述电路的预设输出电压时，所述电路的输出电压将随所述电路的输入电压降低而降低，此时采样信号减小，第一控制信号增大，第二控制信号减小，所述PMOS管M3处于线性区而所述电流采样PMOS管M2处于饱和区，此时PMOS管M2的漏极电压低于PMOS管M3的漏极电压，导致PMOS管M2和PMOS管M3电流镜像失配，此时PMOS管M2产生较大的电流，增大静态功耗，即：It is clear to those skilled in the art that when the input voltage of the circuit is lower than the preset output voltage of the circuit, the output voltage of the circuit will decrease as the input voltage of the circuit decreases, and the sampling signal decreases at this time, The first control signal increases, the second control signal decreases, the PMOS transistor M3 is in the linear region and the current sampling PMOS transistor M2 is in the saturation region, at this time the drain voltage of the PMOS transistor M2 is lower than the drain voltage of the PMOS transistor M3 Pole voltage causes the current mirror mismatch between PMOS transistor M2 and PMOS transistor M3. At this time, PMOS transistor M2 generates a large current and increases static power consumption, namely:
其中，IM2为PMOS管M2电流，IM3为PMOS管M3电流，(W/L)M2为PMOS管M2宽长比，(W/L)M3为PMOS管M3宽长比。Wherein, IM2 is the current of the PMOS transistor M2, IM3 is the current of the PMOS transistor M3, (W/L)M2 is the width-to-length ratio of the PMOS transistor M2, and (W/L)M3 is the width-to-length ratio of the PMOS transistor M3.
请查阅图2，图2所示为图1中现有技术静态电流和输入电压的关系图。如他2所示，当输入电压高于预设输出电压时静态功耗很小，即当输入电压小于预设输出电压时随着输入电压减小静态电流先增大到一个峰值然后随输入电压减小而减小。现有技术的主要缺点是当输入电压低于预设电压后，静态电流变为输入电压大于预设值时的数十倍甚至数百倍，导致其静态功耗非常大。Please refer to FIG. 2 . FIG. 2 shows the relationship between quiescent current and input voltage in the prior art in FIG. 1 . As shown in his 2, when the input voltage is higher than the preset output voltage, the static power consumption is very small, that is, when the input voltage is lower than the preset output voltage, as the input voltage decreases, the quiescent current first increases to a peak value and then increases with the input voltage Decrease and decrease. The main disadvantage of the prior art is that when the input voltage is lower than the preset voltage, the quiescent current becomes tens or even hundreds of times of that when the input voltage is higher than the preset value, resulting in a very large static power consumption.
本领域技术人员清楚，静态功耗为静态电流和输入电压的乘积。上述现有技术在输入电压低于预设输出电压时静态功耗猛增的原因是，当输入电压低于预设输出电压时PMOS管M3处于线性区工作状态，电流采样PMOS管M2处于饱和区工作状态，这导致电流采样电路镜像失配。It is clear to those skilled in the art that the static power consumption is the product of the static current and the input voltage. The reason why the static power consumption of the above prior art increases sharply when the input voltage is lower than the preset output voltage is that when the input voltage is lower than the preset output voltage, the PMOS transistor M3 is in the linear region, and the current sampling PMOS transistor M2 is in the saturation region. operating state, which results in a mirror mismatch in the current-sensing circuit.
因此，当输入电压低于预设电压后，如果静态电流变为输入电压大于预设值时的数十倍甚至数百倍的情况，这会导致其静态功耗非常大。Therefore, when the input voltage is lower than the preset voltage, if the quiescent current becomes tens or even hundreds of times of the input voltage higher than the preset value, this will cause a very large static power consumption.
发明内容Contents of the invention
为解决的上述技术问题，本发明提出一种低静态功耗的LDO(低压差线性稳压器)电路，达到降低输入电压小于预设输出电压时的LDO静态功耗的目的。In order to solve the above technical problems, the present invention proposes a low static power consumption LDO (Low Dropout Linear Regulator) circuit to achieve the purpose of reducing the static power consumption of the LDO when the input voltage is less than the preset output voltage.
为实现上述目的，本发明的技术方案如下：To achieve the above object, the technical scheme of the present invention is as follows:
一种低静态功耗LDO的电路，其包括电路输入端、电路输出端和接地端；其特征在于，还包括第一放大器、第二放大器、第三放大器、PMOS管M3和输出采样模块；其中，A circuit of a low static power consumption LDO, which includes a circuit input terminal, a circuit output terminal and a ground terminal; it is characterized in that it also includes a first amplifier, a second amplifier, a third amplifier, a PMOS transistor M3 and an output sampling module; wherein ,
所述输出采样模块产生一个与第一采样信号相关的输出电压；The output sampling module generates an output voltage related to the first sampling signal;
所述第一放大器的一输入端接收第一参考信号，另一输入端连接所述输出采样电路的第一采样信号输出端，所述第一放大器的输出端连接所述第二放大器的NMOS管M1的栅极；用于根据所述第一参考信号和第一采样信号，产生第一控制信号；其中，当所述第一采样信号减小，所述第一控制信号增大；所述第一采样信号增大，所述第一控制信号减小，所述第一参考信号小于所述电路输入端的电压；One input end of the first amplifier receives the first reference signal, the other input end is connected to the first sampling signal output end of the output sampling circuit, and the output end of the first amplifier is connected to the NMOS transistor of the second amplifier The gate of M1; used to generate a first control signal according to the first reference signal and the first sampling signal; wherein, when the first sampling signal decreases, the first control signal increases; the first control signal increases; When the sampling signal increases, the first control signal decreases, and the first reference signal is smaller than the voltage at the input terminal of the circuit;
所述第二放大器，包括NMOS管M1、PMOS管M2、PMOS管M4；所述NMOS管M1的源极连接地，漏极连接PMOS管M3的栅极，栅极连接所述第一放大器的输出端；所述PMOS管M2的源极连接输入端，漏极连接第三放大器的一输入端，栅极连接PMOS管M3的栅极；所述PMOS管M4的源极连接第三放大器的一输入端，漏极连接PMOS管M3的栅极，栅极连接第三放大器的输出端；所述第二放大器用于根据所述第一控制信号产生第二控制信号控制PMOS管M3的导通状态；其中，当所述第一控制信号增大，所述第二控制信号减小；所述第一控制信号减小，所述第二控制信号增大；The second amplifier includes an NMOS transistor M1, a PMOS transistor M2, and a PMOS transistor M4; the source of the NMOS transistor M1 is connected to the ground, the drain is connected to the gate of the PMOS transistor M3, and the gate is connected to the output of the first amplifier. terminal; the source of the PMOS transistor M2 is connected to the input terminal, the drain is connected to an input terminal of the third amplifier, and the gate is connected to the gate of the PMOS transistor M3; the source of the PMOS transistor M4 is connected to an input of the third amplifier terminal, the drain is connected to the gate of the PMOS transistor M3, and the gate is connected to the output terminal of the third amplifier; the second amplifier is used to generate a second control signal to control the conduction state of the PMOS transistor M3 according to the first control signal; Wherein, when the first control signal increases, the second control signal decreases; when the first control signal decreases, the second control signal increases;
所述PMOS管M3的源极连接所述电路输入端，漏极连接所述电路输出端；所述PMOS管M3用于根据所述第二控制信号，设置所述电路输出端的输出电压，当所述第二控制信号增大，所述电路输出端的输出电压减小，所述第二控制信号减小，所述电路输出端的输出电压增加；The source of the PMOS transistor M3 is connected to the input terminal of the circuit, and the drain is connected to the output terminal of the circuit; the PMOS transistor M3 is used to set the output voltage of the output terminal of the circuit according to the second control signal. The second control signal increases, the output voltage at the output end of the circuit decreases, the second control signal decreases, and the output voltage at the output end of the circuit increases;
所述第三放大器的另一输入端连接输出端，所述第三放大器根据输出端的输出电压和所述PMOS管M4的源极电压产生第三控制信号，所述的第三控制信号使得PMOS管M4的源极电压跟随输出端电压变化；The other input terminal of the third amplifier is connected to the output terminal, and the third amplifier generates a third control signal according to the output voltage of the output terminal and the source voltage of the PMOS transistor M4, and the third control signal makes the PMOS transistor M4 The source voltage of M4 changes with the output terminal voltage;
其中，当所述电路输入端电压低于输出端预设电压时，所述电路输出端电压将随所述电路输入端电压的降低而降低，此时，所述第一采样信号减小，第一控制信号增大，第二控制信号减小，所述PMOS管M3处于线性区；所述的第三控制信号使得PMOS管M4的源极电压跟随输出端电压变化且值相同；此时所述PMOS管M2处于线性区，且PMOS管M2的栅极、漏极和源极电压和PMOS管M3栅极、漏极和源极电压分别相等，所述PMOS管M2的电流IM2和所述PMOS管M3的电流IM3为镜像关系，所述的镜像关系为：Wherein, when the voltage at the input terminal of the circuit is lower than the preset voltage at the output terminal, the voltage at the output terminal of the circuit will decrease as the voltage at the input terminal of the circuit decreases. At this time, the first sampling signal decreases, and the second The first control signal increases, the second control signal decreases, and the PMOS transistor M3 is in the linear region; the third control signal makes the source voltage of the PMOS transistor M4 change with the output voltage and have the same value; at this time, the The PMOS transistor M2 is in the linear region, and the gate, drain, and source voltages of the PMOS transistor M2 are equal to the gate, drain, and source voltages of the PMOS transistor M3, respectively, and the current IM2 of the PMOS transistor M2 is equal to the current IM2 of the PMOS transistor M2. The current IM3 of M3 is a mirror image relationship, and the mirror image relationship is:
其中，所述输出端预设电压大于等于所述第一参考信号，IM2为PMOS管M2电流，IM3为PMOS管M3电流，(W/L)M2为PMOS管M2宽长比，(W/L)M3为PMOS管M3宽长比；以使在输入端电压低于输出端预设电压时PMOS管M2电流为：Wherein, the preset voltage at the output terminal is greater than or equal to the first reference signal, IM2 is the current of the PMOS transistor M2, IM3 is the current of the PMOS transistor M3, (W/L)M2 is the width-to-length ratio of the PMOS transistor M2, (W/L ) M3 is the width-to-length ratio of the PMOS transistor M3; so that the current of the PMOS transistor M2 is:
从避免电流镜像失配导致的电路静态功耗增大。Increased static power consumption of the circuit from avoiding current mirror mismatch.
进一步地，所述第一采样信号为电路输出端的输出电压/A，A为不小于1的数；通过所述输出采样电路、第一放大器、第二放大器和PMOS管M3的调节，产生电路输出端的输出电压为：Further, the first sampling signal is the output voltage/A of the circuit output terminal, A is a number not less than 1; through the adjustment of the output sampling circuit, the first amplifier, the second amplifier and the PMOS transistor M3, the circuit output The output voltage at the terminal is:
(第一参考信号+VOS1)*A(1st reference signal+VOS1)*A
其中，所述VOS1为第一放大器的失调电压。Wherein, the VOS1 is the offset voltage of the first amplifier.
进一步地，所述低静态功耗LDO的电路还包括电阻R1，所述电阻R1的一端连接所述电路输入端，另一端连接所述PMOS管M2的源极，用于控制所述PMOS管M2的电流采样比例。Further, the circuit of the low static power consumption LDO further includes a resistor R1, one end of the resistor R1 is connected to the input end of the circuit, and the other end is connected to the source of the PMOS transistor M2 for controlling the PMOS transistor M2 The current sampling ratio of .
从上述技术方案可以看出，本发明提出一种低静态功耗的LDO(低压差线性稳压器)电路，用于解决现有技术在输入电压小于预设输出电压时静态功耗增大的问题。在本发明实施例中，可以实现将输入电压小于预设输出电压时的静态功耗降低至与输入电压大于预设输出电压时的静态功耗相当。It can be seen from the above technical solution that the present invention proposes a low static power consumption LDO (low dropout linear voltage regulator) circuit, which is used to solve the problem of increased static power consumption in the prior art when the input voltage is less than the preset output voltage question. In the embodiment of the present invention, the static power consumption when the input voltage is lower than the preset output voltage can be reduced to be equivalent to the static power consumption when the input voltage is higher than the preset output voltage.
附图说明Description of drawings
图1所示为现有技术的一种低静态功耗的LDO电路示意图Fig. 1 shows a schematic diagram of a low static power consumption LDO circuit in the prior art
图2所示为图1中现有技术静态电流和输入电压的关系图Figure 2 is a graph showing the relationship between quiescent current and input voltage in the prior art in Figure 1
图3所示为本发明实施例中静态功耗的LDO电路的示意图Fig. 3 is the schematic diagram of the LDO circuit of static power consumption in the embodiment of the present invention
图4所示为图3所示实施例中静态电流和输入电压的关系示意图Figure 4 is a schematic diagram of the relationship between quiescent current and input voltage in the embodiment shown in Figure 3
图5所示为本发明静态功耗的LDO电路另一较佳实施例的示意图Fig. 5 shows the schematic diagram of another preferred embodiment of the LDO circuit of static power consumption of the present invention
具体实施方式Detailed ways
下面结合附图3-5对本发明的具体实施方式作进一步的详细说明。The specific embodiment of the present invention will be further described in detail below in conjunction with accompanying drawings 3-5.
实施例1Example 1
请参阅图3，图3所示为本发明实施例中低静态功耗的LDO电路示意图。如图3所示，包括电路可以电路输入端、电路输出端和接地端；其还包括第一放大器、第二放大器、第三放大器、PMOS管M3和输出采样模块，所述输出采样模块产生一个与第一采样信号相关的输出电压。Please refer to FIG. 3 . FIG. 3 is a schematic diagram of an LDO circuit with low static power consumption in an embodiment of the present invention. As shown in Figure 3, the circuit may include a circuit input terminal, a circuit output terminal and a ground terminal; it also includes a first amplifier, a second amplifier, a third amplifier, a PMOS transistor M3 and an output sampling module, and the output sampling module generates a The output voltage associated with the first sampled signal.
在本发明的实施例中，所述第一放大器的一输入端接收第一参考信号，另一输入端连接所述输出采样电路的第一采样信号输出端，所述第一放大器的输出端连接所述第二放大器的NMOS管M1的栅极；用于根据所述第一参考信号和第一采样信号，产生第一控制信号；其中，当所述第一采样信号减小，所述第一控制信号增大；所述第一采样信号增大，所述第一控制信号减小，所述第一参考信号小于所述电路输入端的电压。In an embodiment of the present invention, one input terminal of the first amplifier receives the first reference signal, the other input terminal is connected to the first sampling signal output terminal of the output sampling circuit, and the output terminal of the first amplifier is connected to The gate of the NMOS transistor M1 of the second amplifier; used to generate a first control signal according to the first reference signal and the first sampling signal; wherein, when the first sampling signal decreases, the first The control signal increases; the first sampling signal increases, the first control signal decreases, and the first reference signal is smaller than the voltage at the input terminal of the circuit.
在本发明的实施例中，所述第二放大器可以包括NMOS管M1、PMOS管M2、PMOS管M4；所述NMOS管M1的源极连接地，漏极连接PMOS管M3的栅极，栅极连接所述第一放大器的输出端；所述PMOS管M2的源极连接输入端，漏极连接第三放大器的一输入端，栅极连接PMOS管M3的栅极；所述PMOS管M4的源极连接第三放大器的一输入端，漏极连接PMOS管M3的栅极，栅极连接第三放大器的输出端；所述第二放大器用于根据所述第一控制信号产生第二控制信号控制PMOS管M3的导通状态；其中，当所述第一控制信号增大，所述第二控制信号减小；所述第一控制信号减小，所述第二控制信号增大。In an embodiment of the present invention, the second amplifier may include an NMOS transistor M1, a PMOS transistor M2, and a PMOS transistor M4; the source of the NMOS transistor M1 is connected to the ground, the drain is connected to the gate of the PMOS transistor M3, and the gate Connect the output terminal of the first amplifier; the source of the PMOS transistor M2 is connected to the input terminal, the drain is connected to an input terminal of the third amplifier, and the gate is connected to the gate of the PMOS transistor M3; the source of the PMOS transistor M4 The pole is connected to an input terminal of the third amplifier, the drain is connected to the gate of the PMOS transistor M3, and the gate is connected to the output terminal of the third amplifier; the second amplifier is used to generate a second control signal according to the first control signal to control The conduction state of the PMOS transistor M3; wherein, when the first control signal increases, the second control signal decreases; when the first control signal decreases, the second control signal increases.
所述PMOS管M3的源极连接所述电路输入端，漏极连接所述电路输出端；所述PMOS管M3用于根据所述第二控制信号，设置所述电路输出端的输出电压，当所述第二控制信号增大，所述电路输出端的输出电压减小，所述第二控制信号减小，所述电路输出端的输出电压增加。The source of the PMOS transistor M3 is connected to the input terminal of the circuit, and the drain is connected to the output terminal of the circuit; the PMOS transistor M3 is used to set the output voltage of the output terminal of the circuit according to the second control signal. When the second control signal increases, the output voltage at the output end of the circuit decreases, and when the second control signal decreases, the output voltage at the output end of the circuit increases.
所述第三放大器的另一输入端连接输出端，所述第三放大器根据输出端的输出电压和所述PMOS管M4的源极电压产生第三控制信号，所述的第三控制信号使得PMOS管M4的源极电压跟随输出端电压变化。The other input terminal of the third amplifier is connected to the output terminal, and the third amplifier generates a third control signal according to the output voltage of the output terminal and the source voltage of the PMOS transistor M4, and the third control signal makes the PMOS transistor M4 The source voltage of M4 changes with the output terminal voltage.
其中，当所述电路输入端电压低于输出端预设电压时，所述电路输出端电压将随所述电路输入端电压的降低而降低，此时，所述第一采样信号减小，第一控制信号增大，第二控制信号减小，所述PMOS管M3处于线性区；所述的第三控制信号使得PMOS管M4的源极电压跟随输出端电压变化且值相同；此时所述PMOS管M2处于线性区，且PMOS管M2的栅极、漏极和源极电压和PMOS管M3栅极、漏极和源极电压分别相等，所述PMOS管M2的电流IM2和所述PMOS管M3的电流IM3为镜像关系，所述的镜像关系为：Wherein, when the voltage at the input terminal of the circuit is lower than the preset voltage at the output terminal, the voltage at the output terminal of the circuit will decrease as the voltage at the input terminal of the circuit decreases. At this time, the first sampling signal decreases, and the second The first control signal increases, the second control signal decreases, and the PMOS transistor M3 is in the linear region; the third control signal makes the source voltage of the PMOS transistor M4 change with the output voltage and have the same value; at this time, the The PMOS transistor M2 is in the linear region, and the gate, drain, and source voltages of the PMOS transistor M2 are equal to the gate, drain, and source voltages of the PMOS transistor M3, respectively, and the current IM2 of the PMOS transistor M2 is equal to the current IM2 of the PMOS transistor M2. The current IM3 of M3 is a mirror image relationship, and the mirror image relationship is:
其中，所述输出端预设电压大于等于所述第一参考信号，IM2为PMOS管M2电流，IM3为PMOS管M3电流，(W/L)M2为PMOS管M2宽长比，(W/L)M3为PMOS管M3宽长比；保证在输入端电压低于输出端预设电压时PMOS管M2电流为：Wherein, the preset voltage at the output terminal is greater than or equal to the first reference signal, IM2 is the current of the PMOS transistor M2, IM3 is the current of the PMOS transistor M3, (W/L)M2 is the width-to-length ratio of the PMOS transistor M2, (W/L ) M3 is the width-to-length ratio of the PMOS transistor M3; ensure that the current of the PMOS transistor M2 is as follows when the voltage at the input terminal is lower than the preset voltage at the output terminal:
从避免电流镜像失配导致的电路静态功耗增大。Increased static power consumption of the circuit from avoiding current mirror mismatch.
在本发明的而一些实施例中，所述第一采样信号为电路输出端的输出电压/A，A为不小于1的数；通过所述输出采样电路、第一放大器、第二放大器和PMOS管M3的调节，产生电路输出端的输出电压为：In some embodiments of the present invention, the first sampling signal is the output voltage/A of the circuit output terminal, A is a number not less than 1; through the output sampling circuit, the first amplifier, the second amplifier and the PMOS transistor With the adjustment of M3, the output voltage at the output end of the generating circuit is:
(第一参考信号+VOS1)*A(1st reference signal+VOS1)*A
其中，所述VOS1为第一放大器的失调电压。Wherein, the VOS1 is the offset voltage of the first amplifier.
请参阅图4，图4所示为图3所示实施例中静态电流和输入电压的关系示意图。如图4所示，本发明的静态电流和输入电压的关系图，当输入电压高于预设输出电压时静态功耗很小，当输入电压小于预设输出电压时随着输入电压减小静态电流不会陡增，而是随输入电压减小现有一个轻微的增大，然后随输入电压减小而减小。Please refer to FIG. 4 . FIG. 4 is a schematic diagram showing the relationship between the quiescent current and the input voltage in the embodiment shown in FIG. 3 . As shown in Figure 4, the relationship diagram of the quiescent current and the input voltage of the present invention, when the input voltage is higher than the preset output voltage, the quiescent power consumption is very small, and when the input voltage is lower than the preset output voltage, the quiescent power consumption decreases with the input voltage The current does not increase sharply, but instead has a slight increase as the input voltage decreases, and then decreases as the input voltage decreases.
也就是说，在本发明的实施例中，在输入电压低于预设输出电压时PMOS管M4的源极电压跟随输出变化，保证PMOS管M2和PMOS管M3一样处于线性区，避免当输入电压低于预设输出电压时PMOS管M2和PMOS管M3失配导致的静态电流增大，从而达到降低静态电流的效果，同时PMOS管M3的栅极被拉低，保证输出电压能跟随输入电压变化。That is to say, in the embodiment of the present invention, when the input voltage is lower than the preset output voltage, the source voltage of the PMOS transistor M4 changes with the output, ensuring that the PMOS transistor M2 and the PMOS transistor M3 are in the same linear region, avoiding when the input voltage When the output voltage is lower than the preset output voltage, the quiescent current caused by the mismatch between PMOS transistor M2 and PMOS transistor M3 increases, so as to achieve the effect of reducing the quiescent current. At the same time, the gate of PMOS transistor M3 is pulled down to ensure that the output voltage can follow the input voltage change .
实施例2Example 2
请参阅图5，图5所示为本发明静态功耗的LDO电路另一较佳实施例的示意图。在本发明的实施例中，该静态功耗的LDO电路，除可以包括第一放大器、第二放大器、第三放大器、PMOS管M3和输出采样模块，还可以包括电阻R1，所述电阻R1的一端连接所述电路输入端，另一端连接所述PMOS管M2的源极，用于控制所述PMOS管M2的电流采样比例。Please refer to FIG. 5 . FIG. 5 is a schematic diagram of another preferred embodiment of the static power consumption LDO circuit of the present invention. In an embodiment of the present invention, the LDO circuit for static power consumption may include a resistor R1 in addition to the first amplifier, the second amplifier, the third amplifier, the PMOS transistor M3 and the output sampling module. One end is connected to the input end of the circuit, and the other end is connected to the source of the PMOS transistor M2 for controlling the current sampling ratio of the PMOS transistor M2.
在本发明的实施例中，所述第一放大器的一输入端接收第一参考信号，另一输入端连接所述输出采样电路的第一采样信号输出端，所述第一放大器的输出端连接所述第二放大器的NMOS管M1的栅极；用于根据所述第一参考信号和第一采样信号，产生第一控制信号；其中，当所述第一采样信号减小，所述第一控制信号增大；所述第一采样信号增大，所述第一控制信号减小，所述第一参考信号小于所述电路输入端的电压。In an embodiment of the present invention, one input terminal of the first amplifier receives the first reference signal, the other input terminal is connected to the first sampling signal output terminal of the output sampling circuit, and the output terminal of the first amplifier is connected to The gate of the NMOS transistor M1 of the second amplifier; used to generate a first control signal according to the first reference signal and the first sampling signal; wherein, when the first sampling signal decreases, the first The control signal increases; the first sampling signal increases, the first control signal decreases, and the first reference signal is smaller than the voltage at the input terminal of the circuit.
在本发明的实施例中，所述第二放大器可以包括NMOS管M1、PMOS管M2、PMOS管M4；所述NMOS管M1的源极连接地，漏极连接PMOS管M3的栅极，栅极连接所述第一放大器的输出端；所述PMOS管M2的源极连接输入端，漏极连接第三放大器的一输入端，栅极连接PMOS管M3的栅极；所述PMOS管M4的源极连接第三放大器的一输入端，漏极连接PMOS管M3的栅极，栅极连接第三放大器的输出端；所述第二放大器用于根据所述第一控制信号产生第二控制信号控制PMOS管M3的导通状态；其中，当所述第一控制信号增大，所述第二控制信号减小；所述第一控制信号减小，所述第二控制信号增大。In an embodiment of the present invention, the second amplifier may include an NMOS transistor M1, a PMOS transistor M2, and a PMOS transistor M4; the source of the NMOS transistor M1 is connected to the ground, the drain is connected to the gate of the PMOS transistor M3, and the gate Connect the output terminal of the first amplifier; the source of the PMOS transistor M2 is connected to the input terminal, the drain is connected to an input terminal of the third amplifier, and the gate is connected to the gate of the PMOS transistor M3; the source of the PMOS transistor M4 The pole is connected to an input terminal of the third amplifier, the drain is connected to the gate of the PMOS transistor M3, and the gate is connected to the output terminal of the third amplifier; the second amplifier is used to generate a second control signal according to the first control signal to control The conduction state of the PMOS transistor M3; wherein, when the first control signal increases, the second control signal decreases; when the first control signal decreases, the second control signal increases.
所述PMOS管M3的源极连接所述电路输入端，漏极连接所述电路输出端；所述PMOS管M3用于根据所述第二控制信号，设置所述电路输出端的输出电压，当所述第二控制信号增大，所述电路输出端的输出电压减小，所述第二控制信号减小，所述电路输出端的输出电压增加。The source of the PMOS transistor M3 is connected to the input terminal of the circuit, and the drain is connected to the output terminal of the circuit; the PMOS transistor M3 is used to set the output voltage of the output terminal of the circuit according to the second control signal. When the second control signal increases, the output voltage at the output end of the circuit decreases, and when the second control signal decreases, the output voltage at the output end of the circuit increases.
所述第三放大器的另一输入端连接输出端，所述第三放大器根据输出端的输出电压和所述PMOS管M4的源极电压产生第三控制信号，所述的第三控制信号使得PMOS管M4的源极电压跟随输出端电压变化。The other input terminal of the third amplifier is connected to the output terminal, and the third amplifier generates a third control signal according to the output voltage of the output terminal and the source voltage of the PMOS transistor M4, and the third control signal makes the PMOS transistor M4 The source voltage of M4 changes with the output terminal voltage.
其中，当所述电路输入端电压低于输出端预设电压时，所述电路输出端电压将随所述电路输入端电压的降低而降低，此时，所述第一采样信号减小，第一控制信号增大，第二控制信号减小，所述PMOS管M3处于线性区；所述的第三控制信号使得PMOS管M4的源极电压跟随输出端电压变化且值相同；此时所述PMOS管M2处于线性区，且PMOS管M2的栅极、漏极和源极电压和PMOS管M3栅极、漏极和源极电压分别相等，所述PMOS管M2的电流IM2和所述PMOS管M3的电流IM3为镜像关系，所述的镜像关系为：Wherein, when the voltage at the input terminal of the circuit is lower than the preset voltage at the output terminal, the voltage at the output terminal of the circuit will decrease as the voltage at the input terminal of the circuit decreases. At this time, the first sampling signal decreases, and the second The first control signal increases, the second control signal decreases, and the PMOS transistor M3 is in the linear region; the third control signal makes the source voltage of the PMOS transistor M4 change with the output voltage and have the same value; at this time, the The PMOS transistor M2 is in the linear region, and the gate, drain, and source voltages of the PMOS transistor M2 are equal to the gate, drain, and source voltages of the PMOS transistor M3, respectively, and the current IM2 of the PMOS transistor M2 is equal to the current IM2 of the PMOS transistor M2. The current IM3 of M3 is a mirror image relationship, and the mirror image relationship is:
其中，所述输出端预设电压大于等于所述第一参考信号，IM2为PMOS管M2电流，IM3为PMOS管M3电流，(W/L)M2为PMOS管M2宽长比，(W/L)M3为PMOS管M3宽长比；保证在输入端电压低于输出端预设电压时PMOS管M2电流为：Wherein, the preset voltage at the output terminal is greater than or equal to the first reference signal, IM2 is the current of the PMOS transistor M2, IM3 is the current of the PMOS transistor M3, (W/L)M2 is the width-to-length ratio of the PMOS transistor M2, (W/L ) M3 is the width-to-length ratio of the PMOS transistor M3; ensure that the current of the PMOS transistor M2 is as follows when the voltage at the input terminal is lower than the preset voltage at the output terminal:
从避免电流镜像失配导致的电路静态功耗增大。Increased static power consumption of the circuit from avoiding current mirror mismatch.
在本发明的而一些实施例中，所述第一采样信号为电路输出端的输出电压/A，A为不小于1的数；通过所述输出采样电路、第一放大器、第二放大器和PMOS管M3的调节，产生电路输出端的输出电压为：In some embodiments of the present invention, the first sampling signal is the output voltage/A of the circuit output terminal, A is a number not less than 1; through the output sampling circuit, the first amplifier, the second amplifier and the PMOS transistor With the adjustment of M3, the output voltage at the output end of the generating circuit is:
(第一参考信号+VOS1)*A(1st reference signal+VOS1)*A
其中，所述VOS1为第一放大器的失调电压。Wherein, the VOS1 is the offset voltage of the first amplifier.
以上所述的仅为本发明的优选实施例，所述实施例并非用以限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。The above are only preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention, so all equivalent structural changes made by using the description and accompanying drawings of the present invention should be included in the same way Within the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310458394.4ACN116501119A (en) | 2023-04-25 | 2023-04-25 | LDO circuit with static power consumption |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310458394.4ACN116501119A (en) | 2023-04-25 | 2023-04-25 | LDO circuit with static power consumption |
| Publication Number | Publication Date |
|---|---|
| CN116501119Atrue CN116501119A (en) | 2023-07-28 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310458394.4APendingCN116501119A (en) | 2023-04-25 | 2023-04-25 | LDO circuit with static power consumption |
| Country | Link |
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| CN (1) | CN116501119A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117590887A (en)* | 2023-11-24 | 2024-02-23 | 上海维安半导体有限公司 | A circuit for reducing static power consumption in voltage drop state |
| CN119200735A (en)* | 2024-11-26 | 2024-12-27 | 上海裕芯电子科技有限公司 | A LDO circuit and method for improving output overcharge |
| CN119210429A (en)* | 2024-11-29 | 2024-12-27 | 上海裕芯电子科技有限公司 | An LDO circuit and method for preventing overcharging of residual power hot-swap output under no-load |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120223688A1 (en)* | 2011-03-01 | 2012-09-06 | Analog Devices, Inc. | High power supply rejection ratio (psrr) and low dropout regulator |
| CN102707753A (en)* | 2011-03-25 | 2012-10-03 | 精工电子有限公司 | Voltage regulator |
| CN109669501A (en)* | 2017-10-13 | 2019-04-23 | 艾普凌科有限公司 | Voltage regulator |
| CN114879810A (en)* | 2022-04-26 | 2022-08-09 | 思瑞浦微电子科技（苏州）股份有限公司 | Low dropout regulator, current control method and chip |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120223688A1 (en)* | 2011-03-01 | 2012-09-06 | Analog Devices, Inc. | High power supply rejection ratio (psrr) and low dropout regulator |
| CN102707753A (en)* | 2011-03-25 | 2012-10-03 | 精工电子有限公司 | Voltage regulator |
| CN109669501A (en)* | 2017-10-13 | 2019-04-23 | 艾普凌科有限公司 | Voltage regulator |
| CN114879810A (en)* | 2022-04-26 | 2022-08-09 | 思瑞浦微电子科技（苏州）股份有限公司 | Low dropout regulator, current control method and chip |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117590887A (en)* | 2023-11-24 | 2024-02-23 | 上海维安半导体有限公司 | A circuit for reducing static power consumption in voltage drop state |
| CN119200735A (en)* | 2024-11-26 | 2024-12-27 | 上海裕芯电子科技有限公司 | A LDO circuit and method for improving output overcharge |
| CN119200735B (en)* | 2024-11-26 | 2025-03-21 | 上海裕芯电子科技有限公司 | A LDO circuit and method for improving output overcharge |
| CN119210429A (en)* | 2024-11-29 | 2024-12-27 | 上海裕芯电子科技有限公司 | An LDO circuit and method for preventing overcharging of residual power hot-swap output under no-load |
| CN119210429B (en)* | 2024-11-29 | 2025-03-21 | 上海裕芯电子科技有限公司 | An LDO circuit and method for preventing overcharging of residual power hot-swap output under no-load |
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