CN116312332A - Pixel circuit, driving method thereof and display device - Google Patents
Pixel circuit, driving method thereof and display deviceDownload PDFInfo
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
Description
Translated fromChinese技术领域technical field
本发明涉及显示技术领域，尤其涉及一种像素电路及其驱动方法和显示装置。The present invention relates to the field of display technology, in particular to a pixel circuit, a driving method thereof, and a display device.
背景技术Background technique
随着显示技术的发展，用户对显示质量的要求也越来越高。With the development of display technology, users have higher and higher requirements for display quality.
显示装置在工作时，会有不同的工作模式，不同工作模式下的刷新频率不同。例如显示装置在显示静态图片和显示动态画面时，刷新频率是不同的。当显示画面不同时，需要切换刷新频率，但是在切换刷新频率时，存在显示效果不佳的问题。When the display device is working, it has different working modes, and the refresh frequency in different working modes is different. For example, when the display device displays static pictures and dynamic pictures, the refresh frequency is different. When the display screens are different, the refresh rate needs to be switched, but when the refresh rate is switched, there is a problem that the display effect is not good.
发明内容Contents of the invention
本发明提供了一种像素电路及其驱动方法和显示装置，以解决显示装置在切换刷新频率时显示效果不佳的问题。The invention provides a pixel circuit, its driving method and a display device to solve the problem of poor display effect when the display device switches the refresh frequency.
根据本发明的一方面，提供了一种像素电路，驱动模块、数据写入模块、补偿模块、漏电抑制模块、第一初始化模块、发光模块和偏置模块；According to one aspect of the present invention, there is provided a pixel circuit, a driving module, a data writing module, a compensation module, a leakage suppression module, a first initialization module, a light emitting module and a bias module;
数据写入模块用于在数据写入阶段向驱动模块的控制端写入数据电压；The data writing module is used to write data voltage to the control terminal of the driving module during the data writing phase;
补偿模块的第一端与驱动模块的第二端连接，补偿模块的第二端与漏电抑制模块的第一端连接，漏电抑制模块的第二端与驱动模块的控制端连接，补偿模块用于在数据写入阶段对驱动模块的阈值电压进行补偿；The first terminal of the compensation module is connected to the second terminal of the driving module, the second terminal of the compensation module is connected to the first terminal of the leakage suppression module, the second terminal of the leakage suppression module is connected to the control terminal of the driving module, and the compensation module is used for Compensate the threshold voltage of the driving module during the data writing phase;
第一初始化模块与漏电抑制模块的第一端连接，第一初始化模块用于在第一初始化阶段对驱动模块的控制端、第一端和第二端的电位进行初始化，漏电抑制模块用于抑制驱动模块控制端的漏电；The first initialization module is connected to the first terminal of the leakage suppression module, the first initialization module is used to initialize the potentials of the control terminal, the first terminal and the second terminal of the driving module in the first initialization stage, and the leakage suppression module is used to suppress the driving Leakage at the control terminal of the module;
偏置模块与驱动模块的第一端或第二端连接，偏置模块用于在发光模块每次发光之前的电压偏置阶段对驱动模块的第一端和第二端的电位进行电压偏置。The bias module is connected with the first terminal or the second terminal of the driving module, and the bias module is used for voltage biasing the potentials of the first terminal and the second terminal of the driving module in the voltage bias stage before each light emitting module emits light.
驱动模块和发光模块连接于第一电源线和第二电源线之间，驱动模块用于在发光阶段驱动发光模块发光；The driving module and the light emitting module are connected between the first power line and the second power line, and the driving module is used to drive the light emitting module to emit light during the light emitting stage;
可选地，还包括发光控制模块，发光控制模块包括第一发光控制单元和第二发光控制单元；Optionally, a light emission control module is also included, the light emission control module includes a first light emission control unit and a second light emission control unit;
第一发光控制单元的控制端与第一发光控制信号线连接，第一发光控制单元串联在第一电源线和驱动模块的第一端之间；第二发光控制单元的控制端与第二发光控制信号线连接，第二发光控制单元串联在驱动模块的第二端和发光模块的第一端之间，发光模块的第二端与第二电源线连接；The control end of the first light emission control unit is connected to the first light emission control signal line, and the first light emission control unit is connected in series between the first power line and the first end of the driving module; the control end of the second light emission control unit is connected to the second light emission control unit. The control signal line is connected, the second light emitting control unit is connected in series between the second end of the driving module and the first end of the light emitting module, and the second end of the light emitting module is connected to the second power line;
优选地，发光控制模块包括的晶体管的沟道类型与补偿模块包括的晶体管的沟道类型不同。Preferably, the channel type of the transistor included in the lighting control module is different from that of the transistor included in the compensation module.
可选地，显示周期包括写入帧和保持帧，偏置模块的第一端接入偏置电压，偏置模块的第二端与驱动模块的第一端或第二端连接，偏置模块用于在写入帧内的电压偏置阶段响应自身控制端的第一扫描信号导通，将偏置电压写入至驱动模块的第一端或第二端，以及在保持帧内的电压偏置阶段响应自身控制端的第一扫描信号导通，将偏置电压再次写入至驱动模块的第一端或第二端；Optionally, the display period includes a write frame and a hold frame, the first terminal of the bias module is connected to a bias voltage, the second terminal of the bias module is connected to the first terminal or the second terminal of the drive module, and the bias module It is used to respond to the first scan signal conduction of its own control terminal in the phase of voltage bias writing in the frame, write the bias voltage to the first terminal or the second terminal of the driving module, and maintain the voltage bias in the frame Responding to the conduction of the first scanning signal of its own control terminal, the bias voltage is written into the first terminal or the second terminal of the driving module again;
优选地，第一扫描信号在写入帧内的有效时长与在保持帧内的有效时长不同；Preferably, the effective duration of the first scanning signal in the writing frame is different from the effective duration in the maintaining frame;
优选地，第一发光控制信号线上传输的第一发光控制信号在写入帧内的有效时长与在保持帧内的有效时长不同，第二发光控制信号线上传输的第二发光控制信号在写入帧内的有效时长与在保持帧内的有效时长不同；Preferably, the effective duration of the first light emission control signal transmitted on the first light emission control signal line in the write frame is different from the effective time duration in the hold frame, and the second light emission control signal transmitted on the second light emission control signal line is in the The valid duration in the write frame is different from the valid duration in the hold frame;
优选地，偏置电压在写入帧内的电压值与在保持帧内的电压值不同。Preferably, the voltage value of the bias voltage in the writing frame is different from that in the holding frame.
可选地，第一初始化模块的控制端接入第二扫描信号，第一初始化模块用于在写入帧的第一初始化阶段将第一初始化电压传输至驱动模块的控制端，以及在写入帧的第二初始化阶段将第一初始化信号线上的第一初始化电压传输至发光模块的第一端；Optionally, the control terminal of the first initialization module is connected to the second scanning signal, and the first initialization module is used to transmit the first initialization voltage to the control terminal of the drive module during the first initialization phase of the writing frame, and to transmit the first initialization voltage to the control terminal of the driving module during the writing In the second initialization stage of the frame, the first initialization voltage on the first initialization signal line is transmitted to the first terminal of the light emitting module;
第一初始化模块还用于在保持帧的第二初始化阶段将第一初始化信号线上的第一初始化电压再次传输至发光模块的第一端；The first initialization module is also used to retransmit the first initialization voltage on the first initialization signal line to the first terminal of the light emitting module during the second initialization phase of the holding frame;
优选地，补偿模块的控制端与第一发光控制信号线连接；Preferably, the control terminal of the compensation module is connected to the first lighting control signal line;
优选地，补偿模块包括的晶体管为金属氧化物晶体管；Preferably, the transistors included in the compensation module are metal oxide transistors;
优选地，第二扫描信号在写入帧内的有效时长与在保持帧内的有效时长不同；Preferably, the effective duration of the second scanning signal in the write frame is different from the effective duration in the hold frame;
优选地，第一初始化电压在写入帧内的电压值与在保持帧内的电压值不同。Preferably, the voltage value of the first initialization voltage in the writing frame is different from the voltage value in the maintaining frame.
可选地，还包括第二初始化模块，第二初始化模块的第一端与第二初始化信号线连接，第二初始化模块的第二端与发光模块的第一端连接，第二初始化模块的控制端接入第一扫描信号，第一初始化模块用于在第一初始化阶段将第一初始化信号线上的第一初始化电压传输至驱动模块的控制端，第二初始化模块用于在第二初始化阶段将第二初始化信号线上的第二初始化电压传输至发光模块的第一端；Optionally, it also includes a second initialization module, the first end of the second initialization module is connected to the second initialization signal line, the second end of the second initialization module is connected to the first end of the light emitting module, and the control of the second initialization module The terminal is connected to the first scan signal, the first initialization module is used to transmit the first initialization voltage on the first initialization signal line to the control terminal of the drive module in the first initialization stage, and the second initialization module is used to transmit the first initialization voltage on the first initialization signal line to the control terminal of the drive module in the second initialization stage transmitting the second initialization voltage on the second initialization signal line to the first end of the light emitting module;
优选地，第一发光控制信号线复用为第二发光控制信号线。Preferably, the first light emission control signal line is multiplexed as the second light emission control signal line.
可选地，漏电抑制模块的控制端接入第三扫描信号，漏电抑制模块响应第三扫描信号在写入帧内的电压写入阶段导通，以及在保持帧内保持关断；Optionally, the control terminal of the leakage suppression module is connected to the third scanning signal, and the leakage suppression module is turned on during the voltage writing phase in the writing frame in response to the third scanning signal, and kept off in the holding frame;
其中，漏电抑制模块包括的晶体管为金属氧化物晶体管。Wherein, the transistors included in the leakage suppression module are metal oxide transistors.
可选地，还包括第一存储模块，第一存储模块的第一端与第一电源线连接，第一存储模块的第二端与驱动模块的控制端连接，第一存储模块用于存储驱动模块的控制端的电压；Optionally, it also includes a first storage module, the first end of the first storage module is connected to the first power line, the second end of the first storage module is connected to the control end of the drive module, and the first storage module is used for storing the drive The voltage of the control terminal of the module;
优选地，还包括第二存储模块，数据写入模块的第一端与数据线连接，数据写入模块的第二端与驱动模块的第一端连接，数据写入模块的控制端接入第四扫描信号，第二存储模块的第一端与第一电源线连接，第二存储模块的第二端与驱动模块的第一端连接。Preferably, it also includes a second storage module, the first end of the data writing module is connected to the data line, the second end of the data writing module is connected to the first end of the driving module, and the control end of the data writing module is connected to the second storage module. For four scan signals, the first end of the second storage module is connected to the first power line, and the second end of the second storage module is connected to the first end of the drive module.
根据本发明的另一方面，提供了一种像素电路的驱动方法，像素电路包括驱动模块、数据写入模块、补偿模块、漏电抑制模块、第一初始化模块、发光模块和偏置模块，补偿模块和漏电抑制模块连接于驱动模块的第二端和控制端之间，第一初始化模块与漏电抑制模块的第一端连接，偏置模块与驱动模块的第一端或第二端连接，驱动模块和发光模块连接于第一电源线和第二电源线之间；According to another aspect of the present invention, a driving method of a pixel circuit is provided, the pixel circuit includes a driving module, a data writing module, a compensation module, a leakage suppression module, a first initialization module, a light emitting module and a bias module, and the compensation module The leakage suppression module is connected between the second terminal and the control terminal of the driving module, the first initialization module is connected to the first terminal of the leakage suppression module, the bias module is connected to the first terminal or the second terminal of the driving module, and the driving module and the light emitting module is connected between the first power line and the second power line;
像素电路的驱动方法包括：The driving method of the pixel circuit includes:
在第一初始化阶段，控制第一初始化模块对驱动模块的控制端、第一端和第二端的电位进行初始化；In the first initialization stage, the first initialization module is controlled to initialize the potentials of the control terminal, the first terminal and the second terminal of the driving module;
在数据写入阶段，控制数据写入模块向驱动模块的控制端写入数据电压，以及控制补偿模块对驱动模块的阈值电压进行补偿；In the data writing stage, the data writing module is controlled to write data voltage to the control terminal of the driving module, and the compensation module is controlled to compensate the threshold voltage of the driving module;
在电压偏置阶段，控制偏置模块对驱动模块的第一端和第二端进行电压偏置；In the voltage bias stage, the control bias module performs voltage bias on the first terminal and the second terminal of the driving module;
在发光阶段，控制驱动模块驱动发光模块发光。In the light emitting stage, the driving module is controlled to drive the light emitting module to emit light.
可选地，一显示周期包括写入帧和保持帧，其中，写入帧包括第一初始化阶段、数据写入阶段、电压偏置阶段和发光阶段，保持帧包括电压偏置阶段和发光阶段；Optionally, a display period includes a writing frame and a holding frame, wherein the writing frame includes a first initialization phase, a data writing phase, a voltage bias phase, and a light-emitting phase, and the holding frame includes a voltage bias phase and a light-emitting phase;
像素电路还包括第一发光控制单元和第二发光控制单元，第一发光控制单元串联在第一电源线和驱动模块的第一端之间，第二发光控制单元串联在驱动模块的第二端和发光模块的第一端之间，发光模块的第二端与第二电源线连接，第一初始化模块的第一端与第一初始化信号线连接，第一初始化模块的第二端与漏电抑制模块的第一端连接；The pixel circuit also includes a first light emission control unit and a second light emission control unit, the first light emission control unit is connected in series between the first power line and the first end of the drive module, and the second light emission control unit is connected in series with the second end of the drive module Between the first end of the light emitting module and the first end of the light emitting module, the second end of the light emitting module is connected to the second power line, the first end of the first initialization module is connected to the first initialization signal line, and the second end of the first initialization module is connected to the leakage suppression the first end of the module is connected;
写入帧还包括第二初始化阶段，第二初始化阶段介于第一初始化阶段之前；The writing frame also includes a second initialization phase, the second initialization phase being prior to the first initialization phase;
在写入帧的第二初始化阶段，控制第一初始化模块将第一初始化信号线上的第一初始化电压传输至发光模块的第一端；In the second initialization phase of writing the frame, the first initialization module is controlled to transmit the first initialization voltage on the first initialization signal line to the first terminal of the light emitting module;
在写入帧的第一初始化阶段，控制第一初始化模块将第一初始化电压传输至驱动模块的控制端和第二端；In the first initialization phase of writing the frame, the first initialization module is controlled to transmit the first initialization voltage to the control terminal and the second terminal of the driving module;
优选地，保持帧还包括第二初始化阶段，在保持帧内，第二初始化阶段位于电压偏置阶段之前；Preferably, the hold frame further includes a second initialization stage, and within the hold frame, the second initialization stage is located before the voltage bias stage;
优选地，像素电路还包括第一存储模块和第二存储模块，第一存储模块与驱动模块的控制端连接，第二存储模块与驱动模块的第一端连接，数据写入模块与驱动模块的第一端连接；写入帧还包括亚阈值补偿阶段，亚阈值补偿阶段介于写入帧的数据写入阶段和电压偏置阶段之间；Preferably, the pixel circuit further includes a first storage module and a second storage module, the first storage module is connected to the control terminal of the drive module, the second storage module is connected to the first terminal of the drive module, and the data writing module is connected to the drive module The first end is connected; the writing frame also includes a sub-threshold compensation stage, and the sub-threshold compensation stage is between the data writing stage and the voltage bias stage of the writing frame;
在亚阈值补偿阶段，控制第二存储模块上存储的数据电压经导通的漏电抑制模块和补偿模块写入至驱动模块的控制端。In the sub-threshold compensation stage, the data voltage stored on the second storage module is controlled to be written into the control terminal of the driving module through the leakage suppression module and the compensation module that are turned on.
根据本发明的另一方面，提供了一种显示装置，该显示装置包括本发明任意实施例所提供的像素电路。According to another aspect of the present invention, a display device is provided, and the display device includes the pixel circuit provided by any embodiment of the present invention.
本发明实施例的技术方案，通过设置偏置模块，偏置模块与驱动模块的第一端或第二端连接，偏置模块在发光模块每次发光之前的电压偏置阶段对驱动模块的第一端和第二端的电位进行重置，使得不同刷新频率下的驱动模块的第一端的电位相同，第二端的电位也相同，从而使得不同刷新频率下的驱动模块有相同的偏置状态，有利于改善驱动模块的瞬态特性，进而使得在进行刷新频率切换时发光模块的发光亮度不会突变，有利于保证切频前后亮度的一致性，改善切频闪烁的问题。且通过设置在驱动模块控制端和补偿模块之间的漏电抑制模块，能够减少驱动模块控制端的漏电路径，使得驱动模块控制端仅存在一条漏电路径，有利于减小漏电流，从而能够稳定驱动模块控制端的电位，进而提高显示效果。In the technical solution of the embodiment of the present invention, by setting up a bias module, the bias module is connected to the first terminal or the second terminal of the driving module, and the bias module controls the first terminal of the driving module in the voltage bias stage before the light-emitting module emits light each time. The potentials of one end and the second end are reset, so that the potentials of the first end of the driving modules at different refresh frequencies are the same, and the potentials of the second end are also the same, so that the driving modules at different refresh frequencies have the same bias state, It is beneficial to improve the transient characteristics of the driving module, so that the luminance of the light-emitting module will not change suddenly when the refresh frequency is switched, which is beneficial to ensure the consistency of brightness before and after frequency switching, and improve the problem of frequency switching flicker. Moreover, the leakage suppression module arranged between the control terminal of the driving module and the compensation module can reduce the leakage path of the control terminal of the driving module, so that there is only one leakage path at the control terminal of the driving module, which is beneficial to reduce the leakage current, thereby stabilizing the driving module Control the potential of the terminal, thereby improving the display effect.
应当理解，本部分所描述的内容并非旨在标识本发明的实施例的关键或重要特征，也不用于限制本发明的范围。本发明的其它特征将通过以下的说明书而变得容易理解。It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will be easily understood from the following description.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.
图1为本发明实施例提供的一种像素电路的结构示意图；FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;
图2为本发明实施例提供的另一种像素电路的结构示意图；FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;
图3为本发明实施例提供的另一种像素电路的结构示意图；FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;
图4为本发明实施例提供的一种像素电路的驱动时序波形图；FIG. 4 is a driving timing waveform diagram of a pixel circuit provided by an embodiment of the present invention;
图5为本发明实施例提供的另一种像素电路的结构示意图；FIG. 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;
图6为本发明实施例提供的另一种像素电路的结构示意图；FIG. 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;
图7为本发明实施例提供的另一种像素电路的驱动时序波形图；FIG. 7 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present invention;
图8为本发明实施例提供的另一种像素电路的驱动时序波形图；FIG. 8 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present invention;
图9为本发明实施例提供的另一种像素电路的驱动时序波形图；FIG. 9 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present invention;
图10为本发明实施例提供的另一种像素电路的结构示意图；FIG. 10 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;
图11为本发明实施例提供的另一种像素电路的驱动时序波形图；FIG. 11 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present invention;
图12为本发明实施例提供的一种像素电路的驱动方法的流程图；FIG. 12 is a flow chart of a method for driving a pixel circuit provided by an embodiment of the present invention;
图13为本发明实施例提供的一种像素电路在写入帧的驱动方法的流程图；FIG. 13 is a flowchart of a method for driving a pixel circuit in writing a frame according to an embodiment of the present invention;
图14为本发明实施例提供的一种像素电路在保持帧的驱动方法的流程图；FIG. 14 is a flow chart of a method for driving a pixel circuit while maintaining a frame provided by an embodiment of the present invention;
图15为本发明实施例提供的一种显示装置的结构示意图。FIG. 15 is a schematic structural diagram of a display device provided by an embodiment of the present invention.
具体实施方式Detailed ways
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。It should be noted that the terms "first" and "second" in the description and claims of the present invention and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.
图1为本发明实施例提供的一种像素电路的结构示意图，参考图1，该像素电路包括：驱动模块110、数据写入模块120、补偿模块130、漏电抑制模块140、第一初始化模块150、发光模块160和偏置模块170；数据写入模块120用于在数据写入阶段向驱动模块110的控制端G写入数据电压Vdata；补偿模块130的第一端与驱动模块110的第二端连接，补偿模块130的第二端与漏电抑制模块140的第一端连接，漏电抑制模块140的第二端与驱动模块110的控制端G连接，补偿模块130用于在数据写入阶段对驱动模块110的阈值电压进行补偿；第一初始化模块150与漏电抑制模块140的第一端连接，第一初始化模块150用于在第一初始化阶段对驱动模块110的控制端G、第一端S和第二端D的电位进行初始化，漏电抑制模块140用于抑制驱动模块110控制端的漏电；偏置模块170与驱动模块110的第一端S或第二端D连接，偏置模块170用于在发光模块160每次发光之前的电压偏置阶段对驱动模块110的第一端S和第二端D的电位进行电压偏置；驱动模块110和发光模块160连接于第一电源线L1和第二电源线L2之间，驱动模块110用于在发光阶段驱动发光模块160发光。FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. Referring to FIG. 1 , the pixel circuit includes: a driving
具体地，第一电源线L1用于传输第一电源电压VDD，第二电源线L2用于传输第二电源电压VSS，驱动模块110和发光模块160连接在第一电源线L1和第二电源线L2之间，驱动模块110用于在第一电源线L1和第二电源线L2之间的连接路径导通时，根据其控制端G和第一端的电压驱动发光模块160在显示周期内的发光阶段发光。其中，可在该连接路径上设置发光控制模块180，以保证发光可靠性。Specifically, the first power line L1 is used to transmit the first power supply voltage VDD, the second power line L2 is used to transmit the second power supply voltage VSS, and the
其中，像素电路可以工作在不同刷新频率下，不同刷新频率下，像素电路对应的显示周期不同。驱动模块110包括驱动晶体管，数据电压写入需要通过驱动晶体管，但是由于显示周期不同，使得不同刷新频率下的驱动晶体管的特性存在差异，导致在刷新频率切换时出现闪烁现象，造成显示质量较差。Wherein, the pixel circuit can work at different refresh rates, and the display periods corresponding to the pixel circuits are different at different refresh rates. The
在本实施例中，在发光模块160每次发光之前设置电压偏置阶段，通过设置偏置模块170，在电压偏置阶段将偏置电压VEH写入至驱动模块110的第一端S或第二端D，实现对驱动模块110的第一端S和第二端D的电位的重置效果，进而使得驱动模块110在不同刷新频率具有相同的偏置状态，有利于改善驱动模块110的瞬态特性。In this embodiment, a voltage bias phase is set before the light-emitting
其中，图1中示意性示出了偏置模块170与驱动模块110的第二端电连接的情况。以图1所示像素电路为例，该像素电路的工作过程如下：Wherein, FIG. 1 schematically shows the situation that the
在第一初始化阶段，第一初始化模块150、补偿模块130和漏电抑制模块140导通，第一初始化模块150将第一初始化电压Vref1分别传输至驱动模块110的控制端G和第二端D，由于驱动模块110处于导通状态，第二端D的第一初始化电压Vref1也能够通过驱动模块110传输至自身的第一端S，从而实现驱动模块110控制端G、第一端S和第二端D的电位同时复位至相同或相近的电压，有利于改善残影。In the first initialization stage, the
此外，由于漏电抑制模块140的存在，使得驱动模块110控制端G仅存在一条漏电路径(通过漏电抑制模块140进行漏电)，有利于减小驱动模块110控制端G的漏电。In addition, due to the existence of the
在数据写入阶段，数据写入模块120、补偿模块130和漏电抑制模块140导通，数据写入模块120将数据电压Vdata写入至驱动模块110的控制端G，补偿模块130对驱动模块110的阈值电压进行补偿。这里，数据电压Vdata可以由数据线提供。In the data writing stage, the
在电压偏置阶段，偏置模块170导通，数据写入模块120、漏电抑制模块140关断，偏置模块170将偏置电压VEH传输至驱动模块110的第二端D，并通过驱动模块110将偏置电压VEH写入到驱动模块110的第一端S。In the voltage bias phase, the
当然，在其他实施例中，偏置模块170也可以与驱动模块110的第一端S连接，则在电压偏置阶段，偏置模块170将偏置电压VEH传输至驱动模块110的第一端S，并通过驱动模块110将偏置电压VEH写入到驱动模块110的第二端D。Of course, in other embodiments, the
在发光阶段，发光控制模块180导通，驱动模块110根据其控制端G和第一端S的电压产生驱动电流，驱动发光模块160发光。In the light-emitting stage, the light-emitting
本发明实施例提供的像素电路，通过设置偏置模块，偏置模块与驱动模块的第一端或第二端连接，偏置模块在发光模块每次发光之前的电压偏置阶段对驱动模块的第一端和第二端的电位进行重置，使得不同刷新频率下的驱动模块的第一端的电位相同，第二端的电位也相同，从而使得不同刷新频率下的驱动模块有相同的偏置状态，有利于改善驱动模块的瞬态特性，进而使得在进行刷新频率切换时发光模块的发光亮度不会突变，有利于保证切频前后亮度的一致性，改善切频闪烁的问题。且通过设置在驱动模块控制端和补偿模块之间的漏电抑制模块，能够减少驱动模块控制端的漏电路径，使得驱动模块控制端仅存在一条漏电路径，有利于减小漏电流，从而能够稳定驱动模块控制端的电位，进而提高显示效果。In the pixel circuit provided by the embodiment of the present invention, a bias module is provided, and the bias module is connected to the first end or the second end of the driving module. The potentials of the first terminal and the second terminal are reset, so that the potentials of the first terminal of the driving modules at different refresh frequencies are the same, and the potentials of the second terminal are also the same, so that the driving modules at different refresh frequencies have the same bias state , which is beneficial to improve the transient characteristics of the driving module, so that the light-emitting brightness of the light-emitting module will not change suddenly when the refresh frequency is switched, which is conducive to ensuring the consistency of brightness before and after frequency switching, and improving the problem of frequency switching flicker. Moreover, the leakage suppression module arranged between the control terminal of the driving module and the compensation module can reduce the leakage path of the control terminal of the driving module, so that there is only one leakage path at the control terminal of the driving module, which is beneficial to reduce the leakage current, thereby stabilizing the driving module Control the potential of the terminal, thereby improving the display effect.
可选地，继续参考图1，偏置电压VEH的大小可以根据实际调屏效果进行设定。其中，为保证驱动模块110在电压偏置阶段可以导通，使得偏置电压VEH可以从驱动模块110的第二端传输到驱动模块110的第一端，可以对偏置电压VEH的大小进行设定。例如，驱动模块110包括P型驱动晶体管，则设定偏置电压VEH大于数据电压Vdata，且偏置电压VEH与数据电压Vdata之间差值的绝对值大于该驱动晶体管的阈值电压的绝对值，以保证驱动模块110能够在电压偏置阶段导通。又例如，驱动模块110包括N型驱动晶体管，则设定偏置电压VEH小于数据电压Vdata，且偏置电压VEH与数据电压Vdata之间差值的绝对值大于该驱动晶体管的阈值电压的绝对值，以保证驱动模块110能够在电压偏置阶段导通。Optionally, continuing to refer to FIG. 1 , the magnitude of the bias voltage VEH can be set according to the actual screen adjustment effect. Wherein, in order to ensure that the
图2为本发明实施例提供的另一种像素电路的结构示意图，参考图2，在上述技术方案的基础上，可选地，像素电路还包括发光控制模块180，发光控制模块180包括第一发光控制单元181和第二发光控制单元182；其中，第一发光控制单元181的控制端与第一发光控制信号线连接，第一发光控制单元181串联在第一电源线L1和驱动模块110的第一端S之间；第二发光控制单元182的控制端与第二发光控制信号线连接，第二发光控制单元182串联在驱动模块110的第二端D和发光模块160的第一端之间，发光模块160的第二端与第二电源线L2连接。Fig. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Referring to Fig. 2, on the basis of the above technical solution, optionally, the pixel circuit further includes a light
其中，第一发光控制信号线可传输第一发光控制信号EM1，第二发光控制信号线可传输第二发光控制信号EM2，通过采用不同的发光控制信号控制第一发光控制单元181和第二发光控制单元182，可以灵活设置其他模块的控制信号，以达到节省信号线数量的目的。Wherein, the first light emission control signal line can transmit the first light emission control signal EM1, and the second light emission control signal line can transmit the second light emission control signal EM2, and the first light
示例性地，发光控制模块180包括的晶体管的沟道类型与补偿模块130包括的晶体管的沟道类型不同，也即第一发光控制单元181和第二发光控制单元182包括的晶体管的沟道类型相同，但与补偿模块130包括的晶体管的沟道类型不同，因此，补偿模块130可以由第一发光控制信号EM1控制。Exemplarily, the channel type of the transistor included in the light
可选地，第一初始化模块150还用于在显示周期内的第二初始化阶段，将第一初始化电压Vref1经导通的补偿模块130和第二发光控制单元182传输至发光模块160的第一端，以对发光模块160第一端的电位进行初始化。其中，第二初始化阶段可位于第一初始化阶段之前。图3为本发明实施例提供的另一种像素电路的结构示意图，参考图3，补偿模块130的控制端与补偿控制信号线连接，补偿控制信号线用于传输补偿控制信号S0。第一存储模块190与驱动模块110的控制端G连接，用于存储其控制端G的电压。Optionally, the
其中，图3可对应图2所示像素电路的具体器件化的结构示意图，驱动模块110包括第一晶体管M1，数据写入模块120包括第二晶体管M2，漏电抑制模块140包括第三晶体管T3，补偿模块130包括第四晶体管M4，偏置模块170包括第五晶体管M5，第一初始化模块150包括第六晶体管M6，第一发光控制单元181包括第七晶体管M7，第二发光控制单元182包括第八晶体管M8，发光模块160包括发光二极管D1，第一存储模块190包括第一电容C1。在本实施例中，发光二极管D1可以为有机发光器件，也可以为无机发光器件。Wherein, FIG. 3 may correspond to a schematic structural diagram of a specific device of the pixel circuit shown in FIG. 2 , the
可选地，漏电抑制模块140包括的第三晶体管M3为为N型晶体管，其他晶体管为P型晶体管。第三晶体管M3可以为金属氧化物晶体管，金属氧化物晶体管具有较小的漏电流，因此，在发光阶段，能够保持驱动模块110控制端G的电压，有利于提高显示均一性。Optionally, the third transistor M3 included in the
图4为本发明实施例提供的一种像素电路的驱动时序波形图，可适用于图3所示像素电路，参考图3和图4，该像素电路的工作过程至少包括第二初始化阶段T1、第一初始化阶段T2、数据写入阶段T3、电压偏置阶段T5和发光阶段T6。Fig. 4 is a driving timing waveform diagram of a pixel circuit provided by an embodiment of the present invention, which is applicable to the pixel circuit shown in Fig. 3. Referring to Fig. 3 and Fig. 4, the working process of the pixel circuit includes at least the second initialization phase T1, A first initialization phase T2, a data writing phase T3, a voltage biasing phase T5 and a light emitting phase T6.
在第二初始化阶段T1，第一发光控制信号线上传输的第一发光控制信号EM1为高电平，第二发光控制信号线上传输的第二发光控制信号EM2为低电平，第一扫描信号线上传输的第一扫描信号S1为高电平，第二扫描信号线上传输的第二扫描信号S2为低电平，第三扫描信号线上传输的第三扫描信号S3为低电平，第四扫描信号线上传输的第四扫描信号S4为高电平，补偿控制信号线上传输的补偿控制信号S0为低电平。因此，第四晶体管M4、第六晶体管M6和第八晶体管M8导通，第一初始化电压Vref1经第六晶体管M6、第四晶体管M4和第八晶体管M8传输至发光二极管D1的第一极(阳极)，实现对发光二极管D1阳极电位的初始化。In the second initialization phase T1, the first light emission control signal EM1 transmitted on the first light emission control signal line is at high level, the second light emission control signal EM2 transmitted on the second light emission control signal line is at low level, and the first scan The first scanning signal S1 transmitted on the signal line is at high level, the second scanning signal S2 transmitted on the second scanning signal line is at low level, and the third scanning signal S3 transmitted on the third scanning signal line is at low level , the fourth scanning signal S4 transmitted on the fourth scanning signal line is at high level, and the compensation control signal S0 transmitted on the compensation control signal line is at low level. Therefore, the fourth transistor M4, the sixth transistor M6 and the eighth transistor M8 are turned on, and the first initialization voltage Vref1 is transmitted to the first pole (anode electrode) of the light emitting diode D1 through the sixth transistor M6, the fourth transistor M4 and the eighth transistor M8. ), realize the initialization of the anode potential of the light-emitting diode D1.
在第一初始化阶段T2，第一发光控制信号线上传输的第一发光控制信号EM1为高电平，第二发光控制信号线上传输的第二发光控制信号EM2为高电平，第一扫描信号线上传输的第一扫描信号S1为高电平，第二扫描信号线上传输的第二扫描信号S2为低电平，第三扫描信号线上传输的第三扫描信号S3为高电平，第四扫描信号线上传输的第四扫描信号S4为高电平，补偿控制信号线上传输的补偿控制信号S0为低电平。因此，第三晶体管M3、第四晶体管M4和第六晶体管M6导通，第一初始化电压Vref1经第六晶体管M6和第三晶体管M3写入至第一晶体管M1的栅极，实现对第一晶体管M1栅极电位的初始化。同时，第一初始化电压Vref1还通过第六晶体管M6和第四晶体管M4写入到第一晶体管M1的第二极，并通过第一晶体管M1传输至自身的第一极，实现对第一晶体管M1第一极和第二极电位的初始化，此时，第一晶体管M1有电流流过，有利于改善残影，进一步提高显示效果。In the first initialization phase T2, the first light emission control signal EM1 transmitted on the first light emission control signal line is at a high level, the second light emission control signal EM2 transmitted on the second light emission control signal line is at a high level, and the first scan The first scanning signal S1 transmitted on the signal line is high level, the second scanning signal S2 transmitted on the second scanning signal line is low level, and the third scanning signal S3 transmitted on the third scanning signal line is high level , the fourth scanning signal S4 transmitted on the fourth scanning signal line is at high level, and the compensation control signal S0 transmitted on the compensation control signal line is at low level. Therefore, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on, and the first initialization voltage Vref1 is written into the gate of the first transistor M1 through the sixth transistor M6 and the third transistor M3, so that the first transistor M1 Initialization of M1 gate potential. At the same time, the first initialization voltage Vref1 is also written into the second pole of the first transistor M1 through the sixth transistor M6 and the fourth transistor M4, and is transmitted to the first pole of itself through the first transistor M1, so as to implement the first transistor M1 Initialization of the potentials of the first pole and the second pole, at this time, the first transistor M1 has a current flowing, which is beneficial to improve afterimage and further improve the display effect.
在数据写入阶段T3，第一发光控制信号线上传输的第一发光控制信号EM1为高电平，第二发光控制信号线上传输的第二发光控制信号EM2为高电平，第一扫描信号线上传输的第一扫描信号S1为高电平，第二扫描信号线上传输的第二扫描信号S2为高电平，第三扫描信号线上传输的第三扫描信号S3为高电平，第四扫描信号线上传输的第四扫描信号S4为低电平，补偿控制信号线上传输的补偿控制信号S0为低电平。因此，第二晶体管M2、第三晶体管M3和第四晶体管M4导通，数据电压Vdata经第二晶体管M2、第一晶体管M1、第四晶体管M4和第三晶体管M3写入至第一晶体管M1的栅极，实现第一晶体管M1的数据写入以及阈值补偿。In the data writing phase T3, the first light emission control signal EM1 transmitted on the first light emission control signal line is high level, the second light emission control signal EM2 transmitted on the second light emission control signal line is high level, and the first scan The first scanning signal S1 transmitted on the signal line is high level, the second scanning signal S2 transmitted on the second scanning signal line is high level, and the third scanning signal S3 transmitted on the third scanning signal line is high level , the fourth scanning signal S4 transmitted on the fourth scanning signal line is low level, and the compensation control signal S0 transmitted on the compensation control signal line is low level. Therefore, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on, and the data voltage Vdata is written into the first transistor M1 via the second transistor M2, the first transistor M1, the fourth transistor M4, and the third transistor M3. The gate implements data writing and threshold compensation of the first transistor M1.
在电压偏置阶段T5，第一发光控制信号线上传输的第一发光控制信号EM1为高电平，第二发光控制信号线上传输的第二发光控制信号EM2为高电平，第一扫描信号线上传输的第一扫描信号S1为低电平，第二扫描信号线上传输的第二扫描信号S2为高电平，第三扫描信号线上传输的第三扫描信号S3为低电平，第四扫描信号线上传输的第四扫描信号S4为高电平，补偿控制信号线上传输的补偿控制信号S0为低电平。因此，第四晶体管M4和第五晶体管M5导通，偏置电压VEH经第五晶体管M5写入至第一晶体管M1的第二极，并通过第一晶体管M1传输至自身的第一极，实现对第一晶体管M1的第一极和第二极电位的重置。其中，第一晶体管M1的第一极可以为源极、第二极可以为漏极。在其他实施例中，第一极也可以为漏极，第二极可以为源极。In the voltage bias phase T5, the first light emission control signal EM1 transmitted on the first light emission control signal line is at a high level, the second light emission control signal EM2 transmitted on the second light emission control signal line is at a high level, and the first scan The first scanning signal S1 transmitted on the signal line is low level, the second scanning signal S2 transmitted on the second scanning signal line is high level, and the third scanning signal S3 transmitted on the third scanning signal line is low level , the fourth scanning signal S4 transmitted on the fourth scanning signal line is at high level, and the compensation control signal S0 transmitted on the compensation control signal line is at low level. Therefore, the fourth transistor M4 and the fifth transistor M5 are turned on, the bias voltage VEH is written into the second pole of the first transistor M1 through the fifth transistor M5, and transmitted to the first pole of itself through the first transistor M1, realizing Resetting the potentials of the first pole and the second pole of the first transistor M1. Wherein, the first pole of the first transistor M1 may be a source, and the second pole may be a drain. In other embodiments, the first pole may also be a drain, and the second pole may be a source.
可选地，在电压偏置阶段T5，第四晶体管M4也可以响应高电平的补偿控制信号S0关断。Optionally, in the voltage bias phase T5, the fourth transistor M4 may also be turned off in response to the high level compensation control signal S0.
在发光阶段T6，第一发光控制信号线上传输的第一发光控制信号EM1为低电平，第二发光控制信号线上传输的第二发光控制信号EM2为低电平，第一扫描信号线上传输的第一扫描信号S1为高电平，第二扫描信号线上传输的第二扫描信号S2为高电平，第三扫描信号线上传输的第三扫描信号S3为低电平，第四扫描信号线上传输的第四扫描信号S4为高电平，补偿控制信号线上传输的补偿控制信号S0为高电平。因此，第七晶体管M7和第八晶体管M8导通，第一晶体管M1生产成驱动电流，驱动发光二极管D1发光。In the light-emitting phase T6, the first light-emitting control signal EM1 transmitted on the first light-emitting control signal line is at low level, the second light-emitting control signal EM2 transmitted on the second light-emitting control signal line is at low level, and the first scanning signal line The first scanning signal S1 transmitted on the upper line is at a high level, the second scanning signal S2 transmitted on the second scanning signal line is at a high level, the third scanning signal S3 transmitted on the third scanning signal line is at a low level, and the second scanning signal S2 transmitted on the second scanning signal line is at a low level. The fourth scan signal S4 transmitted on the four-scan signal line is at high level, and the compensation control signal S0 transmitted on the compensation control signal line is at high level. Therefore, the seventh transistor M7 and the eighth transistor M8 are turned on, and the first transistor M1 generates a driving current to drive the LED D1 to emit light.
图5为本发明实施例提供的另一种像素电路的结构示意图，参考图5，可选地，补偿模块130的控制端与第一发光控制信号线连接，第四晶体管M4为金属氧化物晶体管。图5所示像素电路的工作过程可参考对图4所示像素电路的相关描述，在此不再赘述。FIG. 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Referring to FIG. 5 , optionally, the control terminal of the
图6为本发明实施例提供的另一种像素电路的结构示意图，参考图6，在上述各技术方案的基础上，可选地，像素电路还包括第二存储模块210，数据写入模块120的第一端与数据线连接，数据写入模块120的第二端与驱动模块110的第一端S连接，数据写入模块120的控制端接入第四扫描信号S4，第二存储模块210的第一端与第一电源线L1连接，第二存储模块210的第二端与驱动模块110的第一端S连接。其中，第二存储模块210可以包括第二电容。FIG. 6 is a schematic structural diagram of another pixel circuit provided by the embodiment of the present invention. Referring to FIG. The first terminal of the
图7为本发明实施例提供的另一种像素电路的驱动时序波形图，参考图7，本实施例提供的像素电路的工作过程还包括亚阈值补偿阶段T4，亚阈值补偿阶段T4介于数据写入阶段T3和电压偏置阶段T5之间。FIG. 7 is a driving timing waveform diagram of another pixel circuit provided by the embodiment of the present invention. Referring to FIG. 7 , the working process of the pixel circuit provided by this embodiment also includes a sub-threshold compensation stage T4, and the sub-threshold compensation stage T4 is between the data between the writing phase T3 and the voltage biasing phase T5.
在亚阈值补偿阶段T4，第一发光控制信号线上传输的第一发光控制信号EM1为高电平，第二发光控制信号线上传输的第二发光控制信号EM2为高电平，第一扫描信号线上传输的第一扫描信号S1为高电平，第二扫描信号线上传输的第二扫描信号S2为高电平，第三扫描信号线上传输的第三扫描信号S3为高电平，第四扫描信号线上传输的第四扫描信号S4为高电平。因此，第三晶体管M3和第四晶体管M4导通，在数据写入阶段T3存储在第二电容C2上的数据电压Vdata继续通过微弱打开的第一晶体管M1向第一电容C1充电，以微调第一晶体管M1栅极的电压，使得数据电压Vdata能够充分写入至第一晶体管M1栅极。同时能够补偿第一晶体管M1的亚阈值摆幅，从而可以减小因第一晶体管M1亚阈值摆幅不同带来的驱动电流不一致的现象，可进一步提高显示均一性。In the sub-threshold compensation stage T4, the first light emission control signal EM1 transmitted on the first light emission control signal line is at high level, the second light emission control signal EM2 transmitted on the second light emission control signal line is at high level, and the first scan The first scanning signal S1 transmitted on the signal line is high level, the second scanning signal S2 transmitted on the second scanning signal line is high level, and the third scanning signal S3 transmitted on the third scanning signal line is high level , the fourth scanning signal S4 transmitted on the fourth scanning signal line is at a high level. Therefore, the third transistor M3 and the fourth transistor M4 are turned on, and the data voltage Vdata stored on the second capacitor C2 in the data writing phase T3 continues to charge the first capacitor C1 through the weakly turned on first transistor M1, so as to fine-tune the second capacitor C1. The gate voltage of a transistor M1 enables the data voltage Vdata to be fully written into the gate of the first transistor M1. At the same time, the subthreshold swing of the first transistor M1 can be compensated, thereby reducing the inconsistency of the driving current caused by the different subthreshold swings of the first transistor M1, and further improving display uniformity.
在本实施例中，可以通过调节第三扫描信号S3的导通时间和第二电容C2的容值来调节补偿效果。In this embodiment, the compensation effect can be adjusted by adjusting the conduction time of the third scanning signal S3 and the capacitance of the second capacitor C2.
可选地，显示装置在工作时会有不同的工作模式，其对应的刷新频率也不同，例如显示装置在显示静态图片和显示游戏的动态画面时，刷新频率是不同的。通常情况下，低刷新频率是在高刷新频率的基础上跳帧实现的，一个显示周期包括写入帧和保持帧。例如刷新频率为120Hz时，120个数据帧均为写入帧，在每个写入帧均进行数据的写入；在刷新频率为1Hz时，在120Hz的基础上，将一个数据帧作为写入帧，其他数据帧作为保持帧，只有在写入帧进行数据的写入，在保持帧不进行数据的写入。图7所示驱动时序可以为像素电路在写入帧的驱动时序。Optionally, the display device has different working modes during operation, and the corresponding refresh rates are also different. For example, when the display device displays static pictures and dynamic pictures of games, the refresh rates are different. Usually, a low refresh rate is realized by frame skipping based on a high refresh rate, and a display cycle includes writing frames and holding frames. For example, when the refresh frequency is 120Hz, 120 data frames are write frames, and data is written in each write frame; when the refresh frequency is 1Hz, on the basis of 120Hz, one data frame is used as a write frame. frame, other data frames are used as hold frames, data is only written in the write frame, and data is not written in the hold frame. The driving timing shown in FIG. 7 may be the driving timing of the pixel circuit in writing a frame.
经发明人研究还发现，在低刷新频率下，由于数据仅在写入帧通过第一晶体管M1写入，使得写入帧和保持帧内第一晶体管M1的动作不同，因此第一晶体管M1的特性存在差异，造成低频显示时出现闪烁现象，显示质量不佳。The inventor also found that, at a low refresh frequency, since the data is only written through the first transistor M1 in the write frame, the actions of the first transistor M1 in the write frame and the hold frame are different, so the first transistor M1 There are differences in characteristics, resulting in flickering at low frequency displays and poor display quality.
针对上述问题，本实施例提供的技术方案，通过设置偏置模块170在写入帧内的电压偏置阶段响应自身控制端G的第一扫描信号S1导通，将偏置电压VEH写入至驱动模块110的第一端S或第二端D，以及在保持帧内的电压偏置阶段响应自身控制端G的第一扫描信号S1导通，将偏置电压VEH再次写入至驱动模块110的第一端S或第二端D；以保证驱动模块110的第一端和第二端在写入帧和保持帧内分别保持相同电位，使得驱动模块110在写入帧和保持帧的偏置状态相同，从而改善切频和低频闪烁现象。In view of the above problems, the technical solution provided by this embodiment is to write the bias voltage VEH into The first terminal S or the second terminal D of the
图8为本发明实施例提供的另一种像素电路的驱动时序波形图，可适用于图5和图6所示像素电路，以图6所示像素电路为例，参考图6和图8该像素电路在写入帧内的工作过程如下：Fig. 8 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present invention, which is applicable to the pixel circuits shown in Fig. 5 and Fig. 6. Taking the pixel circuit shown in Fig. 6 as an example, refer to Fig. 6 and Fig. 8 The working process of the pixel circuit in the writing frame is as follows:
在第二初始化阶段T1，第一发光控制信号EM1为高电平，第二发光控制信号EM2为低电平，第一扫描信号S1为高电平，第二扫描信号S2为低电平，第三扫描信号S3为低电平，第四扫描信号S4为高电平。因此，第四晶体管M4、第六晶体管M6和第八晶体管M8导通，第一初始化电压Vref1经第六晶体管M6、第四晶体管M4和第八晶体管M8传输至发光二极管D1的第一极(阳极)，实现对发光二极管D1阳极电位的初始化。In the second initialization stage T1, the first light emission control signal EM1 is at high level, the second light emission control signal EM2 is at low level, the first scanning signal S1 is at high level, the second scanning signal S2 is at low level, and the second scanning signal S2 is at low level. The third scan signal S3 is at low level, and the fourth scan signal S4 is at high level. Therefore, the fourth transistor M4, the sixth transistor M6 and the eighth transistor M8 are turned on, and the first initialization voltage Vref1 is transmitted to the first pole (anode electrode) of the light emitting diode D1 through the sixth transistor M6, the fourth transistor M4 and the eighth transistor M8. ), realize the initialization of the anode potential of the light-emitting diode D1.
在第一初始化阶段T2，第一发光控制信号EM1为高电平，第二发光控制信号EM2为高电平，第一扫描信号S1为高电平，第二扫描信号S2为低电平，第三扫描信号S3为高电平，第四扫描信号S4为高电平。因此，第三晶体管M3、第四晶体管M4和第六晶体管M6导通，第一初始化电压Vref1经第六晶体管M6和第三晶体管M3写入至第一晶体管M1的栅极，实现对第一晶体管M1栅极电位的初始化。同时，第一初始化电压Vref1还通过第六晶体管M6和第四晶体管M4写入到第一晶体管M1的第二极，并通过第一晶体管M1传输至自身的第一极，实现对第一晶体管M1第一极和第二极电位的初始化，此时，第一晶体管M1有电流流过，有利于改善残影，进一步提高显示效果。在第一初始化阶段T2，第一晶体管M1的栅极和第二极的电压均为Vref，第一极电压为Vref-Vth1，其中，Vth1为第一晶体管M1的阈值电压。In the first initialization stage T2, the first light emission control signal EM1 is at high level, the second light emission control signal EM2 is at high level, the first scanning signal S1 is at high level, the second scanning signal S2 is at low level, and the second scanning signal S2 is at high level. The third scan signal S3 is at high level, and the fourth scan signal S4 is at high level. Therefore, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on, and the first initialization voltage Vref1 is written into the gate of the first transistor M1 through the sixth transistor M6 and the third transistor M3, so that the first transistor M1 Initialization of M1 gate potential. At the same time, the first initialization voltage Vref1 is also written into the second pole of the first transistor M1 through the sixth transistor M6 and the fourth transistor M4, and is transmitted to the first pole of itself through the first transistor M1, so as to implement the first transistor M1 Initialization of the potentials of the first pole and the second pole, at this time, the first transistor M1 has a current flowing, which is beneficial to improve afterimage and further improve the display effect. In the first initialization phase T2, the voltages of the gate and the second electrode of the first transistor M1 are both Vref, and the voltage of the first electrode is Vref-Vth1, wherein Vth1 is the threshold voltage of the first transistor M1.
在数据写入阶段T3，第一发光控制信号EM1为高电平，第二发光控制信号EM2为高电平，第一扫描信号S1为高电平，第二扫描信号S2为高电平，第三扫描信号S3为高电平，第四扫描信号S4为低电平。因此，第二晶体管M2、第三晶体管M3和第四晶体管M4导通，数据电压Vdata经第二晶体管M2、第一晶体管M1、第四晶体管M4和第三晶体管M3写入至第一晶体管M1的栅极，直至第一晶体管M1的栅极电压为Vdata+Vth1+Verror，同时数据电压Vdata存储在第二电容C2上。其中，Verror为误差电压。In the data writing phase T3, the first light emission control signal EM1 is at high level, the second light emission control signal EM2 is at high level, the first scanning signal S1 is at high level, the second scanning signal S2 is at high level, and the second scanning signal S2 is at high level. The third scan signal S3 is at high level, and the fourth scan signal S4 is at low level. Therefore, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on, and the data voltage Vdata is written into the first transistor M1 via the second transistor M2, the first transistor M1, the fourth transistor M4, and the third transistor M3. gate until the gate voltage of the first transistor M1 is Vdata+Vth1+Verror, and at the same time the data voltage Vdata is stored on the second capacitor C2. Among them, Verror is the error voltage.
在亚阈值补偿阶段T4，第一发光控制信号EM1为高电平，第二发光控制信号EM2为高电平，第一扫描信号S1为高电平，第二扫描信号S2为高电平，第三扫描信号S3为高电平，第四扫描信号S4为高电平。因此，第三晶体管M3和第四晶体管M4导通，在数据写入阶段T3存储在第二电容C2上的数据电压Vdata继续通过微弱打开的第一晶体管M1向第一电容C1充电，以微调第一晶体管M1栅极的电压，使得数据电压Vdata能够充分写入至第一晶体管M1栅极，直至第一晶体管M1的栅极电压为Vdata+Vth1。同时能够补偿第一晶体管M1的亚阈值摆幅，从而可以减小因第一晶体管M1亚阈值摆幅不同带来的驱动电流不一致的现象，可进一步提高显示均一性。In the sub-threshold compensation stage T4, the first light emission control signal EM1 is at high level, the second light emission control signal EM2 is at high level, the first scan signal S1 is at high level, the second scan signal S2 is at high level, and the second scan signal S2 is at high level. The third scan signal S3 is at high level, and the fourth scan signal S4 is at high level. Therefore, the third transistor M3 and the fourth transistor M4 are turned on, and the data voltage Vdata stored on the second capacitor C2 in the data writing phase T3 continues to charge the first capacitor C1 through the weakly turned on first transistor M1, so as to fine-tune the second capacitor C1. The gate voltage of a transistor M1 enables the data voltage Vdata to be fully written into the gate of the first transistor M1 until the gate voltage of the first transistor M1 is Vdata+Vth1. At the same time, the subthreshold swing of the first transistor M1 can be compensated, thereby reducing the inconsistency of the driving current caused by the different subthreshold swings of the first transistor M1, and further improving display uniformity.
在电压偏置阶段T5，第一发光控制信号EM1为高电平，第二发光控制信号EM2为高电平，第一扫描信号S1为低电平，第二扫描信号S2为高电平，第三扫描信号S3为低电平，第四扫描信号S4为高电平。因此，第四晶体管M4和第五晶体管M5导通，偏置电压VEH经第五晶体管M5写入至第一晶体管M1的第二极，并通过第一晶体管M1传输至自身的第一极，实现对第一晶体管M1的第一极和第二极电位的重置。In the voltage bias phase T5, the first light emission control signal EM1 is at high level, the second light emission control signal EM2 is at high level, the first scan signal S1 is at low level, the second scan signal S2 is at high level, and the second scan signal S2 is at high level. The third scan signal S3 is at low level, and the fourth scan signal S4 is at high level. Therefore, the fourth transistor M4 and the fifth transistor M5 are turned on, the bias voltage VEH is written into the second pole of the first transistor M1 through the fifth transistor M5, and transmitted to the first pole of itself through the first transistor M1, realizing Resetting the potentials of the first pole and the second pole of the first transistor M1.
在发光阶段T6，第一发光控制信号EM1为低电平，第二发光控制信号EM2为低电平，第一扫描信号S1为高电平，第二扫描信号S2为高电平，第三扫描信号S3为低电平，第四扫描信号S4为高电平。因此，第七晶体管M7和第八晶体管M8导通，第一晶体管M1生产成驱动电流，驱动发光二极管D1发光。In the light-emitting phase T6, the first light-emitting control signal EM1 is at low level, the second light-emitting control signal EM2 is at low level, the first scanning signal S1 is at high level, the second scanning signal S2 is at high level, and the third scanning signal S2 is at high level. The signal S3 is at low level, and the fourth scanning signal S4 is at high level. Therefore, the seventh transistor M7 and the eighth transistor M8 are turned on, and the first transistor M1 generates a driving current to drive the LED D1 to emit light.
该像素电路在保持帧的工作过程如下：The working process of the pixel circuit in maintaining the frame is as follows:
在第二初始化阶段T7，第一发光控制信号EM1为高电平，第二发光控制信号EM2为低电平，第一扫描信号S1为高电平，第二扫描信号S2为低电平，第三扫描信号S3为低电平，第四扫描信号S4为高电平。因此，第四晶体管M4、第六晶体管M6和第八晶体管M8导通，第一初始化电压Vref1经第六晶体管M6、第四晶体管M4和第八晶体管M8传输至发光二极管D1的第一极。In the second initialization stage T7, the first light emission control signal EM1 is at high level, the second light emission control signal EM2 is at low level, the first scanning signal S1 is at high level, the second scanning signal S2 is at low level, and the second scanning signal S2 is at low level. The third scan signal S3 is at low level, and the fourth scan signal S4 is at high level. Therefore, the fourth transistor M4, the sixth transistor M6 and the eighth transistor M8 are turned on, and the first initialization voltage Vref1 is transmitted to the first electrode of the light emitting diode D1 through the sixth transistor M6, the fourth transistor M4 and the eighth transistor M8.
在电压偏置阶段T8，第一发光控制信号EM1为高电平，第二发光控制信号EM2为高电平，第一扫描信号S1为低电平，第二扫描信号S2为高电平，第三扫描信号S3为低电平，第四扫描信号S4为高电平。因此，第四晶体管M4和第五晶体管M5导通，偏置电压VEH经第五晶体管M5写入至第一晶体管M1的第二极，并通过第一晶体管M1传输至自身的第一极，实现对第一晶体管M1的第一极和第二极电位的重置。在此阶段，由于第一晶体管M1的栅极和第一极之间的电压差发生变化，且由于第一晶体管M1的第一极和第二极之间导通，因此第一晶体管M1存在电流应力(stress)，以改变第一晶体管M1的偏置状态。In the voltage bias phase T8, the first light emitting control signal EM1 is at high level, the second light emitting control signal EM2 is at high level, the first scanning signal S1 is at low level, the second scanning signal S2 is at high level, and the second scanning signal S2 is at high level. The third scan signal S3 is at low level, and the fourth scan signal S4 is at high level. Therefore, the fourth transistor M4 and the fifth transistor M5 are turned on, the bias voltage VEH is written into the second pole of the first transistor M1 through the fifth transistor M5, and transmitted to the first pole of itself through the first transistor M1, realizing Resetting the potentials of the first pole and the second pole of the first transistor M1. At this stage, because the voltage difference between the gate of the first transistor M1 and the first pole changes, and because the first pole and the second pole of the first transistor M1 are turned on, there is a current in the first transistor M1 stress to change the bias state of the first transistor M1.
在发光阶段T9，第一发光控制信号EM1为低电平，第二发光控制信号EM2为低电平，第一扫描信号S1为高电平，第二扫描信号S2为高电平，第三扫描信号S3为低电平，第四扫描信号S4为高电平。因此，第七晶体管M7和第八晶体管M8导通，第一晶体管M1生产成驱动电流，驱动发光二极管D1发光。In the light-emitting phase T9, the first light-emitting control signal EM1 is at low level, the second light-emitting control signal EM2 is at low level, the first scanning signal S1 is at high level, the second scanning signal S2 is at high level, and the third scanning signal S2 is at high level. The signal S3 is at low level, and the fourth scanning signal S4 is at high level. Therefore, the seventh transistor M7 and the eighth transistor M8 are turned on, and the first transistor M1 generates a driving current to drive the LED D1 to emit light.
本实施例提供的像素电路，通过设置电压偏置模块170，在写入帧和保持帧的发光阶段之前均对驱动模块110的第二端的电位进行重置，从而使得在写入帧和保持帧的发光阶段之前，在同一灰阶条件下，驱动模块110的第二端的电位相同，第一端的电位也相同，进而使得驱动模块110在写入帧和保持帧的偏置状态相同，在低频显示时，发光模块160的亮度不会发生变化，有利于改善低频闪烁的问题，提高显示效果。进一步地，由于亚阈值补偿阶段的存在，使得数据电压Vdata能够充分写入至驱动模块110的控制端G，驱动模块110的阈值电压得到完全补偿，从而能够减小不同像素对应的驱动模块特性的差异，进而有利于改善显示亮度的差异，提高显示画质的均一性。因此，本实施例提供的像素电路在低频和高频下均具有良好的特性，能够满足宽频驱动。In the pixel circuit provided by this embodiment, by setting the
要说明的是，在本实施例中，写入帧和保持帧都包括电压偏置阶段和发光阶段，其工作原理相同。It should be noted that, in this embodiment, both the write-in frame and the sustain frame include a voltage bias phase and a light-emitting phase, and their working principles are the same.
可选地，第一发光控制信号线上传输的第一发光控制信号EM1在写入帧内的有效时长与在保持帧内的有效时长不同，第二发光控制信号线上传输的第二发光控制信号EM2在写入帧内的有效时长与在保持帧内的有效时长不同。通过改变保持帧的发光时长，可以调节保持帧的发光亮度，使得保持帧与写入帧的发光亮度一致，有利于消除切频和低频下的显示不良现象。Optionally, the effective duration of the first light emission control signal EM1 transmitted on the first light emission control signal line in the write frame is different from the effective time duration in the hold frame, and the second light emission control signal transmitted on the second light emission control signal line The active duration of the signal EM2 in the write frame is different from the active duration in the hold frame. By changing the light-emitting duration of the holding frame, the light-emitting brightness of the holding frame can be adjusted, so that the light-emitting brightness of the holding frame is consistent with that of the writing frame, which is beneficial to eliminate display defects under frequency cut and low frequency.
图9为本发明实施例提供的另一种像素电路的驱动时序波形图，其中，图9所示驱动时序与图8所示驱动时序不同之处在于，图9所示驱动时序中，偏置电压VEH在写入帧内的电压值与在保持帧内的电压值不同，第一扫描信号S1在写入帧内的有效时长与在保持帧内的有效时长不同。可以使得通过偏置电压VEH更加灵活的调节第一晶体管M1的stress特性，以保证第一晶体管M1在写入帧和保持帧具有相同的偏置状态。Fig. 9 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present invention, wherein the difference between the driving timing shown in Fig. 9 and the driving timing shown in Fig. 8 is that in the driving timing shown in Fig. 9, the bias The voltage value of the voltage VEH in the writing frame is different from that in the holding frame, and the effective duration of the first scanning signal S1 in the writing frame is different from that in the holding frame. The stress characteristic of the first transistor M1 can be adjusted more flexibly through the bias voltage VEH, so as to ensure that the first transistor M1 has the same bias state in the writing frame and the holding frame.
继续参考图9，第二扫描信号S2在写入帧内的有效时长与在保持帧内的有效时长不同。也即，第二扫描信号S2在写入帧和保持帧的脉宽不同，以灵活调节写入帧和保持帧内第一发光二极管D1的第一极的电压，使得第一发光二极管D1的第一极电压在发光阶段之前保持相同，从而改善切频闪烁现象。同样地，第一初始化电压Vref1在写入帧内的电压值与在保持帧内的电压值也可以不同。Continuing to refer to FIG. 9 , the effective duration of the second scanning signal S2 in the writing frame is different from that in the maintaining frame. That is, the pulse width of the second scan signal S2 is different in the writing frame and the holding frame, so as to flexibly adjust the voltage of the first pole of the first light-emitting diode D1 in the writing frame and the holding frame, so that the first electrode of the first light-emitting diode D1 One-pole voltage remains the same before the light-emitting phase, thereby improving the frequency-cut flicker phenomenon. Likewise, the voltage value of the first initialization voltage Vref1 in the writing frame and the voltage value in the maintaining frame may also be different.
需要说明的是，在写入帧的第二初始化阶段和第一初始化阶段，分别对发光二极管D1的第一极和第一晶体管M1的栅极初始化，而保持帧不包括第一初始化阶段，也即保持帧内不对第一晶体管M1的栅极初始化。并且，写入帧的数据写入阶段，第一晶体管M1导通，其栅极写入数据电压Vdata；而保持帧不进行数据写入。因此，第一晶体管M1在写入帧和保持帧的动作不一致，存在特性差异。在本实施例中，通过设置保持帧与写入帧的偏置时长、偏置电压VEH、发光模块160的初始化时长、第一初始化电压Vref1中至少一个不同，能够减小保持帧与写入帧之间第一晶体管M1的特性差异，从而有利于改善显示效果。It should be noted that, in the second initialization phase and the first initialization phase of the writing frame, the first pole of the light-emitting diode D1 and the gate of the first transistor M1 are respectively initialized, and the holding frame does not include the first initialization phase, and also That is, the gate of the first transistor M1 is not initialized within the frame. Moreover, in the data writing phase of writing the frame, the first transistor M1 is turned on, and the gate of the first transistor M1 is written with the data voltage Vdata; while the frame is kept without data writing. Therefore, the operations of the first transistor M1 in the writing frame and the holding frame are inconsistent, and there are characteristic differences. In this embodiment, by setting at least one of the offset duration, bias voltage VEH, initialization duration of the light-emitting
图10为本发明实施例提供的另一种像素电路的结构示意图，参考图10，在上述各技术方案的基础上，可选地，该像素电路还可以包括第二初始化化模块220，第二初始化模块220的第一端与第二初始化信号线连接，第二初始化模块220的第二端与发光模块160的第一端连接，第二初始化模块220的控制端接入第一扫描信号S1，第二初始化模块220用于在第二初始化阶段将第二初始化信号线上的第二初始化电压Vref2传输至发光模块160的第一端。也就是说，在第二初始化阶段，通过第二初始化模块220对发光模块160进行初始化，实现第一晶体管M1的栅极和发光二极管D1阳极分开复位，使得对发光二极管D1的阳极复位时间以及复位电压不受第一初始化电压Vref1的限制，增加了像素电路的灵活性，更加有利于改善低灰阶均一性问题。且第一初始化电压Vref1和第二初始化电压Vref2可实现不同程度的电压跳变，能够进一步改善切频时的闪烁现象。FIG. 10 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Referring to FIG. 10 , on the basis of the above technical solutions, optionally, the pixel circuit may also include a second initialization module 220, the second The first end of the initialization module 220 is connected to the second initialization signal line, the second end of the second initialization module 220 is connected to the first end of the
在本实施例中，由于第一晶体管M1的栅极和发光二极管D1阳极分开复位，因此第一发光控制信号EM1可以复用为第二发光控制信号EM2。为了实现第一初始化电压Vref1同时对第一晶体管M1的栅极和第二极进行复位，第四晶体管M4的栅极可以响应于其他控制信号，不限制于第一发光控制信号EM1。In this embodiment, since the gate of the first transistor M1 and the anode of the light emitting diode D1 are reset separately, the first light emission control signal EM1 can be multiplexed into the second light emission control signal EM2 . In order to realize that the first initialization voltage Vref1 resets the gate and the second electrode of the first transistor M1 at the same time, the gate of the fourth transistor M4 may respond to other control signals, not limited to the first light emission control signal EM1 .
图11为本发明实施例提供的另一种像素电路的驱动时序波形图，适用于图10所示的像素电路，其第二初始化阶段与电压偏置阶段同时进行。其他阶段的工作过程可参考对图9的相关描述，在此不再赘述。FIG. 11 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present invention, which is applicable to the pixel circuit shown in FIG. 10 , and the second initialization phase and the voltage bias phase are performed simultaneously. For the working process of other stages, reference may be made to the related description of FIG. 9 , which will not be repeated here.
可选地，本发明实施例还提供了一种像素电路的驱动方法，用于驱动本发明任意实施例所提供的像素电路。图12为本发明实施例提供的一种像素电路的驱动方法的流程图，参考图12，该驱动方法包括：Optionally, an embodiment of the present invention further provides a method for driving a pixel circuit, which is used to drive the pixel circuit provided by any embodiment of the present invention. FIG. 12 is a flowchart of a driving method for a pixel circuit provided by an embodiment of the present invention. Referring to FIG. 12 , the driving method includes:
S110、在第一初始化阶段，控制第一初始化模块对驱动模块的控制端、第一端和第二端的电位进行初始化。S110. In the first initialization stage, control the first initialization module to initialize the potentials of the control terminal, the first terminal and the second terminal of the driving module.
S120、在数据写入阶段，控制数据写入模块向驱动模块的控制端写入数据电压，以及控制补偿模块对驱动模块的阈值电压进行补偿。S120. In the data writing phase, control the data writing module to write the data voltage to the control terminal of the driving module, and control the compensating module to compensate the threshold voltage of the driving module.
S130、在电压偏置阶段，控制偏置模块对驱动模块的第一端和第二端进行电压偏置。S130. In the voltage biasing stage, control the biasing module to perform voltage biasing on the first terminal and the second terminal of the driving module.
S140、在发光阶段，控制驱动模块驱动发光模块发光。S140. In the light emitting stage, control the driving module to drive the light emitting module to emit light.
该驱动方法用于驱动本发明上述任意实施例的像素电路，具备本发明上述任意实施例的像素电路的有益效果，在此不再赘述。The driving method is used to drive the pixel circuit of any of the above-mentioned embodiments of the present invention, and has the beneficial effects of the pixel circuit of any of the above-mentioned embodiments of the present invention, and will not be repeated here.
可选地，像素电路还包括第一发光控制单元和第二发光控制单元，像素电路还包括第二存储模块。图13为本发明实施例提供的一种像素电路在写入帧的驱动方法的流程图，参考图13，像素电路的在写入帧的驱动方法包括：Optionally, the pixel circuit further includes a first light emission control unit and a second light emission control unit, and the pixel circuit further includes a second storage module. FIG. 13 is a flow chart of a method for driving a pixel circuit in a writing frame provided by an embodiment of the present invention. Referring to FIG. 13 , the driving method for a pixel circuit in writing a frame includes:
S2101、在写入帧的第二初始化阶段，控制第一初始化模块将第一初始化信号线上的第一初始化电压传输至发光模块的第一端。S2101. In the second initialization stage of writing a frame, control the first initialization module to transmit the first initialization voltage on the first initialization signal line to the first terminal of the light emitting module.
S1101、在写入帧的第一初始化阶段，控制第一初始化模块将第一初始化电压传输至驱动模块的控制端和第二端。S1101. In the first initialization stage of writing a frame, control the first initialization module to transmit the first initialization voltage to the control terminal and the second terminal of the driving module.
S120、在数据写入阶段，控制数据写入模块向驱动模块的控制端写入数据电压，以及控制补偿模块对驱动模块的阈值电压进行补偿。S120. In the data writing phase, control the data writing module to write the data voltage to the control terminal of the driving module, and control the compensating module to compensate the threshold voltage of the driving module.
S310、在亚阈值补偿阶段，控制第二存储模块上存储的数据电压经导通的漏电抑制模块和补偿模块写入至驱动模块的控制端。S310. In the sub-threshold compensation stage, control the data voltage stored on the second storage module to be written into the control terminal of the driving module through the turned-on leakage suppression module and compensation module.
S130、在电压偏置阶段，控制偏置模块对驱动模块的第一端和第二端进行电压偏置。S130. In the voltage biasing stage, control the biasing module to perform voltage biasing on the first terminal and the second terminal of the driving module.
S140、在发光阶段，控制驱动模块驱动发光模块发光。S140. In the light emitting stage, control the driving module to drive the light emitting module to emit light.
图14为本发明实施例提供的一种像素电路在保持帧的驱动方法的流程图，参考图14，像素电路的在保持帧的驱动方法包括：FIG. 14 is a flow chart of a method for driving a pixel circuit in a holding frame provided by an embodiment of the present invention. Referring to FIG. 14 , the driving method of a pixel circuit in a holding frame includes:
S2102、在保持帧的第二初始化阶段，控制第一初始化模块将第一初始化信号线上的第一初始化电压传输至发光模块的第一端。S2102. In the second initialization phase of the holding frame, control the first initialization module to transmit the first initialization voltage on the first initialization signal line to the first terminal of the light emitting module.
S130、在电压偏置阶段，控制偏置模块对驱动模块的第一端和第二端进行电压偏置。S130. In the voltage biasing stage, control the biasing module to perform voltage biasing on the first terminal and the second terminal of the driving module.
S140、在发光阶段，控制驱动模块驱动发光模块发光。S140. In the light emitting stage, control the driving module to drive the light emitting module to emit light.
其中，图13和图14所示像素电路的驱动方法的具体工作过程可参考上述实施例中关于图9所示像素电路的相关描述，同样具备上述技术方案所描述的有益效果，不再赘述。Wherein, the specific working process of the driving method of the pixel circuit shown in FIG. 13 and FIG. 14 can refer to the related description about the pixel circuit shown in FIG.
可选地，本发明实施例还提供了一种显示装置，包括上述实施例提供的像素电路，因此该显示装置同样具备上述任意实施例所描述的有益效果。图15为本发明实施例提供的一种显示装置的结构示意图，在本实施例中，该显示装置可以为手机，也可以为任何具有显示功能的电子产品，包括但不限于以下类别：电视机、笔记本电脑、桌上型显示器、平板电脑、数码相机、智能手环、智能眼镜、车载显示器、医疗设备、工控设备、触摸交互终端等，本发明实施例对此不作特殊限定。Optionally, an embodiment of the present invention further provides a display device, including the pixel circuit provided in the above embodiment, so the display device also has the beneficial effects described in any of the above embodiments. Figure 15 is a schematic structural diagram of a display device provided by an embodiment of the present invention. In this embodiment, the display device can be a mobile phone, or any electronic product with a display function, including but not limited to the following categories: TV , notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not specifically limited in the embodiments of the present invention.
应该理解，可以使用上面所示的各种形式的流程，重新排序、增加或删除步骤。例如，本发明中记载的各步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本发明的技术方案所期望的结果，本文在此不进行限制。It should be understood that steps may be reordered, added or deleted using the various forms of flow shown above. For example, each step described in the present invention may be executed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution of the present invention can be achieved, there is no limitation herein.
上述具体实施方式，并不构成对本发明保护范围的限制。本领域技术人员应该明白的是，根据设计要求和其他因素，可以进行各种修改、组合、子组合和替代。任何在本发明的精神和原则之内所作的修改、等同替换和改进等，均应包含在本发明保护范围之内。The above specific implementation methods do not constitute a limitation to the protection scope of the present invention. It should be apparent to those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made depending on design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
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