技术领域Technical Field
本发明涉及芯片仿真技术领域，特别涉及一种芯片仿真系统及仿真方法。The present invention relates to the technical field of chip simulation, and in particular to a chip simulation system and a simulation method.
背景技术Background technique
目前，芯片在通讯、电脑、智能化系统、自动控制和空间技术等诸多行业和领域都发挥着及其重要的作用，推动着整个社会的信息化发展。一般情况下，芯片生成包括两个阶段，芯片设计和芯片制造。由于芯片制造的成本很高，且一经流片，芯片内部的逻辑结构就无法改变，所以在芯片制造之前，需要进行谨慎、周密的芯片设计工作。At present, chips play an extremely important role in many industries and fields such as communications, computers, intelligent systems, automatic control and space technology, and promote the information development of the entire society. Generally speaking, chip generation includes two stages, chip design and chip manufacturing. Since the cost of chip manufacturing is very high and the internal logic structure of the chip cannot be changed once it is taped out, careful and thorough chip design work is required before chip manufacturing.
在基于IP的SOC芯片设计过程中，缺陷主要出现于系统整体架构以及各个子系统的配合中，而非孤立的子系统内部。因此项目前期需要在有限的时间与人力投入下，快速准确完成芯片系统架构的模型建立、仿真执行、结果分析，得到“正确且正好”的产品架构。避免由架构设计问题导致的芯片缺陷或高成本返工、过冗余设计与性能不足设计。In the IP-based SOC chip design process, defects mainly occur in the overall system architecture and the coordination of various subsystems, rather than in isolated subsystems. Therefore, in the early stage of the project, it is necessary to quickly and accurately complete the model establishment, simulation execution, and result analysis of the chip system architecture within limited time and manpower investment to obtain a "correct and just right" product architecture. Avoid chip defects or high-cost rework, overly redundant design, and insufficient performance design caused by architectural design problems.
为达成上述目标，需要有专用的仿真软件系统。但是现有技术中的芯片仿真系统存在如下问题与缺陷：1.仿真系统与各自公司的其他EDA工具强耦合，以“全家桶”形式对外呈现，使用成本高昂；2.用户使用门槛高，需要具备较高软硬件基础能力方可入门使用；3.系统生态封闭，通用性差，不具备扩展性。To achieve the above goals, a dedicated simulation software system is needed. However, the chip simulation system in the existing technology has the following problems and defects: 1. The simulation system is strongly coupled with other EDA tools of each company, and is presented to the outside in the form of a "family bucket", which is costly to use; 2. The user threshold is high, and a high level of basic software and hardware capabilities is required to get started; 3. The system ecosystem is closed, with poor versatility and lack of scalability.
发明内容Summary of the invention
本申请实施例提供了一种芯片仿真系统及仿真方法。为了对披露的实施例的一些方面有一个基本的理解，下面给出了简单的概括。该概括部分不是泛泛评述，也不是要确定关键/重要组成元素或描绘这些实施例的保护范围。其唯一目的是用简单的形式呈现一些概念，以此作为后面的详细说明的序言。The embodiments of the present application provide a chip simulation system and a simulation method. In order to have a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary is not a general review, nor is it intended to identify key/important components or describe the scope of protection of these embodiments. Its only purpose is to present some concepts in a simple form as a preface to the detailed description that follows.
第一方面，本申请实施例提供了一种芯片仿真系统，包括：In a first aspect, an embodiment of the present application provides a chip simulation system, including:
交互层单元，用于构建图形化交互界面，图形化交互界面具有动画显示效果，并在图形化交互界面设置多个交互窗口；The interactive layer unit is used to construct a graphical interactive interface with an animation display effect, and to set multiple interactive windows on the graphical interactive interface;
模型层单元，用于构建多个与芯片设计相关的组件模型，将构建的组件模型存入模型库，并对组件模型进行参数配置和分类管理；The model layer unit is used to construct multiple component models related to chip design, store the constructed component models in the model library, and perform parameter configuration and classification management on the component models;
仿真层单元，用于对搭建的芯片模型执行仿真操作，并生成仿真运行结果，所述芯片模型为所述组件模型搭建的整体模型；A simulation layer unit, used to perform simulation operations on the constructed chip model and generate simulation operation results, wherein the chip model is an overall model constructed by the component model;
其中，交互层单元、模型层单元与仿真层单元之间互相解耦。Among them, the interaction layer units, model layer units and simulation layer units are decoupled from each other.
在一个可选地实施例中，交互层单元中的图形化交互界面，包括：In an optional embodiment, the graphical interactive interface in the interactive layer unit includes:
主窗口，用于显示系统的菜单栏和各种功能键；The main window is used to display the system's menu bar and various function keys;
库窗口，用于分类显示模型库中的多个组件模型；The library window is used to display multiple component models in the model library in a classified manner;
全景窗口，用于显示当前编辑的芯片模型的全景；Panorama window, used to display the panorama of the chip model currently being edited;
编辑窗口，用于显示编辑组件模型的工作区；The editing window is used to display the workspace for editing the component model;
代码窗口，用于同步显示组件模型的代码，包括图形化交互界面接收输入的组件模型，通过MVC模式调用编译组件，生成所述组件模型的代码，将生成的组件模型的代码在代码窗口显示；A code window is used to synchronously display the code of the component model, including the component model received by the graphical interactive interface, calling the compilation component through the MVC mode, generating the code of the component model, and displaying the generated code of the component model in the code window;
信息窗口，用于显示芯片模型运行信息和运行的打印信息。Information window, used to display chip model running information and running print information.
在一个可选地实施例中，图形化交互界面，还包括：In an optional embodiment, the graphical interactive interface further includes:
悬浮文本框，用于自动弹出提示信息，提示信息包括芯片模型参数提示信息、运行状态提示信息以及错误提示信息。The floating text box is used to automatically pop up prompt information, including chip model parameter prompt information, operation status prompt information and error prompt information.
在一个可选地实施例中，错误提示信息，包括：In an optional embodiment, the error prompt information includes:
安装错误时的错误类型信息、错误位置信息；Error type information and error location information when an installation error occurs;
组件模型设置异常时的模块名称信息、错误类型信息、错误序号信息以及解决方案信息；Module name information, error type information, error sequence number information, and solution information when component model settings are abnormal;
系统运行异常时的错误类型信息、错误序号信息以及解决方案信息。Error type information, error sequence information, and solution information when the system runs abnormally.
在一个可选地实施例中，模型层单元，包括：In an optional embodiment, the model layer unit includes:
模型库配置模块，用于预先编译多个与芯片设计相关的组件模型，将编译好的组件模型存入模型库，并采用目录式的方法对组件模型进行分类管理；The model library configuration module is used to precompile multiple component models related to chip design, store the compiled component models into the model library, and classify and manage the component models using a catalog method;
数据库配置模块，用于为组件模型配置参数数据以及激励数据；A database configuration module is used to configure parameter data and stimulus data for component models;
分析库配置模块，用于采集芯片模型运行信息，根据采集到的运行信息综合分析系统性能。The analysis library configuration module is used to collect chip model operation information and comprehensively analyze system performance based on the collected operation information.
在一个可选地实施例中，In an alternative embodiment,
组件模型包括事务级模型和寄存器传输级模型；The component model includes transaction level model and register transfer level model;
事务级模型包括非定时模型、松散定时模型和近似定时模型。Transaction-level models include untimed models, loosely timed models, and approximate timed models.
在一个可选地实施例中，In an alternative embodiment,
数据库配置模块，用于根据配置的解析函数，解析Excel、XML、Json中的一种或多种文本格式的数据，根据解析的数据得到芯片模型输入的激励数据，或者根据配置的解析函数，将输出的数据转化成Excel、XML、Json中的一种或多种文本格式的数据。The database configuration module is used to parse data in one or more text formats such as Excel, XML, and Json according to the configured parsing function, obtain the stimulus data input by the chip model according to the parsed data, or convert the output data into data in one or more text formats such as Excel, XML, and Json according to the configured parsing function.
在一个可选地实施例中，分析库配置模块，用于在芯片模型中部署探针，根据部署的探针采集芯片模型的参数信息、名称信息、连接方式信息，并根据采集到的信息生成统计报告。In an optional embodiment, the analysis library configuration module is used to deploy probes in the chip model, collect parameter information, name information, and connection information of the chip model according to the deployed probes, and generate a statistical report based on the collected information.
在一个可选地实施例中，分析库配置模块，用于构建电源模型，根据电源模型监测系统计算次数，根据计算次数分析系统功耗；In an optional embodiment, the analysis library configuration module is used to construct a power model, monitor the number of system calculations according to the power model, and analyze the system power consumption according to the number of calculations;
分析库配置模块，用于构建细化统计模型，根据细化统计模型采集系统带宽信息、延迟信息、吞吐量信息以及利用率信息中的一种或多种性能数据，并根据采集的性能数据生成饼状图、条状图或曲线图。The analysis library configuration module is used to build a refined statistical model, collect one or more performance data of system bandwidth information, delay information, throughput information and utilization information according to the refined statistical model, and generate a pie chart, a bar chart or a curve chart based on the collected performance data.
第二方面，本申请实施例提供了一种芯片仿真方法，包括：In a second aspect, an embodiment of the present application provides a chip simulation method, comprising:
构建图形化交互界面，图形化交互界面具有动画显示效果，并在图形化交互界面设置多个交互窗口；Construct a graphical interactive interface with animation display effects, and set multiple interactive windows in the graphical interactive interface;
构建多个与芯片设计相关的组件模型，将构建的组件模型存入模型库，并对组件模型进行参数配置和分类管理；Construct multiple component models related to chip design, store the constructed component models in the model library, and perform parameter configuration and classification management on the component models;
从组件模型中选择多个目标组件模型，对选择的目标组件模型进行连接，形成构建好的芯片模型；Select multiple target component models from the component models, and connect the selected target component models to form a constructed chip model;
对搭建的芯片模型执行仿真操作，并生成仿真运行结果。Perform simulation operations on the constructed chip model and generate simulation operation results.
本申请实施例提供的技术方案可以包括以下有益效果：The technical solution provided by the embodiments of the present application may have the following beneficial effects:
根据本申请实施例提供的一种芯片仿真系统，支持图形化界面，所画即所得，大幅降低使用门槛；同时支持代码编辑，兼顾简单易用性需求与复杂定制性需求。且自带常用电路结构模型，同时支持第三方同标准模型库，将使用者的工作重心从底层模型实现转向上层系统架构分析。且系统交互层、模型层、仿真层相互解耦，具备高可扩展性。According to a chip simulation system provided in an embodiment of the present application, it supports a graphical interface, and what you draw is what you get, which greatly reduces the threshold for use; it also supports code editing, taking into account both the requirements of simple usability and complex customization. It also comes with commonly used circuit structure models, and supports third-party standard model libraries, shifting the user's work focus from the bottom-level model implementation to the upper-level system architecture analysis. The system interaction layer, model layer, and simulation layer are decoupled from each other, and have high scalability.
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本发明的实施例，并与说明书一起用于解释本发明的原理。The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
图1是根据一示例性实施例示出的一种芯片仿真系统的结构示意图；FIG1 is a schematic diagram showing the structure of a chip simulation system according to an exemplary embodiment;
图2是根据一示例性实施例示出的一种交互界面的示意图；Fig. 2 is a schematic diagram showing an interactive interface according to an exemplary embodiment;
图3是根据一示例性实施例示出的一种芯片仿真方法的示意图；FIG3 is a schematic diagram showing a chip simulation method according to an exemplary embodiment;
图4是根据一示例性实施例示出的一种图形转化代码的示意图。Fig. 4 is a schematic diagram showing a graphic conversion code according to an exemplary embodiment.
具体实施方式Detailed ways
以下描述和附图充分地示出本发明的具体实施方案，以使本领域的技术人员能够实践它们。The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them.
应当明确，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本发明相一致的所有实施方式。相反，它们仅是如所附权利要求书中所详述的、本发明的一些方面相一致的系统和方法的例子。When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are only examples of systems and methods consistent with some aspects of the present invention as detailed in the attached claims.
本申请实施例提供了一种可视化的、低代码风格的芯片开发系统，快速的将抽象的系统概要设计分层转换为具象的电路结构，并在系统整体架构层面上进行仿真，从而对系统的功能、性能和功耗进行综合评估，进而保证芯片从原始需求分析到架构设计，再到电路实现的准确性与一致性。The embodiment of the present application provides a visual, low-code style chip development system that quickly converts the abstract system outline design into a concrete circuit structure in layers, and simulates the overall system architecture level, thereby comprehensively evaluating the system's functions, performance, and power consumption, thereby ensuring the accuracy and consistency of the chip from original demand analysis to architecture design and then to circuit implementation.
下面将结合附图对本申请实施例提供的芯片仿真系统进行详细介绍。参见图1，本申请实施例采用分层架构来构建系统，总体结构分为交互层单元、模型层单元以及仿真层单元。The chip simulation system provided by the embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. Referring to Figure 1, the embodiment of the present application adopts a layered architecture to construct the system, and the overall structure is divided into an interaction layer unit, a model layer unit, and a simulation layer unit.
在一种可能的实现方式中，交互层单元，用于构建图形化交互界面，图形化交互界面具有动画显示效果，并在图形化交互界面设置多个交互窗口。In a possible implementation, the interaction layer unit is used to construct a graphical interaction interface with an animation display effect, and multiple interaction windows are set in the graphical interaction interface.
具体地，通过Qt图形化建模框架搭建图形化界面，在图形化界面环境下，可以利用已经编译好的参数化库和已有的SysmteC/Verilog/VHDL模型对设想的系统方案进行架构建模。Specifically, a graphical interface is built through the Qt graphical modeling framework. In the graphical interface environment, the compiled parameterized library and the existing SystemC/Verilog/VHDL models can be used to perform architectural modeling of the envisioned system solution.
图形化交互界面设置有多个窗口用于显示系统多种信息。例如，图形化交互界面包括主窗口，用于显示系统的菜单栏和各种功能键；库窗口，用于分类显示模型库中的多个组件模型，可以采用目录式的方法分类显示；全景窗口，用于显示当前编辑的芯片模型的全景；编辑窗口，用于显示编辑组件模型的工作区；信息窗口，用于显示模型运行信息和运行的打印信息等。还包括代码窗口，用于同步显示组件模型的代码，包括图形化交互界面接收输入的组件模型，通过MVC模式调用编译组件，生成所述组件模型的代码，将生成的组件模型的代码在代码窗口显示；并提供代码编辑功能。The graphical interactive interface is provided with multiple windows for displaying various information of the system. For example, the graphical interactive interface includes a main window for displaying the menu bar and various function keys of the system; a library window for displaying multiple component models in the model library in a classified manner, which can be displayed in a catalog-style manner; a panoramic window for displaying a panoramic view of the currently edited chip model; an editing window for displaying the work area for editing the component model; an information window for displaying model operation information and operation print information, etc. It also includes a code window for synchronously displaying the code of the component model, including the graphical interactive interface receiving the input component model, calling the compilation component through the MVC mode, generating the code of the component model, and displaying the generated component model code in the code window; and providing code editing function.
在一种可能的实现方式中，图形化交互界面具有图形转化代码的功能，如图4所示，在GUI图形化交互界面输入组件模型后，启动MVC模式，通过MVC(module+view+control)模式调用编译组件生成SystemC代码。将生成的代码在代码窗口显示。In a possible implementation, the graphical interactive interface has the function of converting graphics into code, as shown in FIG4 , after the component model is input in the GUI graphical interactive interface, the MVC mode is started, and the compilation component is called through the MVC (module+view+control) mode to generate SystemC code. The generated code is displayed in the code window.
具体地，首先从库窗口的组件模型列表中选出需要的组件模型，将选择的组件模型拖拽到编辑窗口后模型实例化，生成对应组件模型的item，模型的item包含了模型名称、数据类型、端口名、函数逻辑等关键数据，并配置了模型ID。Specifically, first select the required component model from the component model list in the library window, drag the selected component model to the editing window, instantiate the model, and generate the item of the corresponding component model. The model item contains key data such as model name, data type, port name, function logic, and configures the model ID.
进一步地，启动MVC模式调用编译组件，编译组件生成组件模型代码。具体地，编译组件通过toSourceCode函数生成SystemC的模块框架代码，并将item中的数据通过关键字识别的方法转换为SystemC中对应的代码，通过replace(src,“$moduleName”,className)将item中的模型名转换为SystemC的类名；通过setDataType将数据类型转换为对应代码数据类型；通过addPorts添加端口及方向；通过addMethod或者addThread添加进程或线程、敏感表，并生成函数。代码转换完成后，会生成.cpp文件存放代码。Furthermore, the MVC mode is started to call the compilation component, and the compilation component generates the component model code. Specifically, the compilation component generates the module framework code of SystemC through the toSourceCode function, and converts the data in the item into the corresponding code in SystemC through the keyword recognition method, and converts the model name in the item into the class name of SystemC through replace(src, "$moduleName", className); converts the data type into the corresponding code data type through setDataType; adds ports and directions through addPorts; adds processes or threads, sensitive tables through addMethod or addThread, and generates functions. After the code conversion is completed, a .cpp file will be generated to store the code.
进一步地，通过C++的文本文件的读写函数，读取.cpp文件，将文件中的SystemC代码同步显示在代码窗口中。Furthermore, the .cpp file is read through the reading and writing functions of the C++ text file, and the SystemC code in the file is synchronously displayed in the code window.
在一个可选地实施方式中，交互层中设计了模型动画化方法，对于一个系统，每一笔数据流都会隐式的添加事务号，脚本会实时追踪事务号，实现动画显示各个组件模型之间的数据流流动，显示系统的运行情况。In an optional implementation, a model animation method is designed in the interaction layer. For a system, a transaction number is implicitly added to each data flow. The script tracks the transaction number in real time to realize animation display of the data flow between each component model and display the operation status of the system.
在一个可选地实施方式中，交互层单元还包括悬浮文本框，基于tooltip创建了悬浮文本框，用于自动弹出提示信息，提示信息包括模型参数提示信息、运行状态提示信息以及错误提示信息等。In an optional implementation, the interaction layer unit further includes a floating text box, which is created based on the tooltip and is used to automatically pop up prompt information, including model parameter prompt information, operating status prompt information, and error prompt information.
在一个可选地实施方式中，安装错误会提供报错窗口和报错信息，包括：In an optional implementation, an installation error will provide an error window and error information, including:
(1)错误类型：指明错误原因；(1) Error type: Indicates the cause of the error;
(2)错误位置：指明错误文件位置。(2) Error location: Indicates the error file location.
模型设置出现异常时会提供报错窗口和报错信息，包括：When an exception occurs in the model settings, an error window and error information will be provided, including:
(1)模块名称：指定问题模块的确切位置，格式为：模型名.模块名；(1) Module name: specifies the exact location of the module in question, in the format of model name.module name;
(2)错误类型：指明错误可能的原因；(2) Error type: Indicates the possible cause of the error;
(3)错误序号：提供错误序号；(3) Error number: provide the error number;
(4)解决方案：提示可行的解决方案。(4)Solution: Propose feasible solutions.
系统运行异常提供报错窗口和报错信息，包括：When the system runs abnormally, it provides an error window and error information, including:
(1)错误类型：指明错误原因；(1) Error type: Indicates the cause of the error;
(2)错误序号：提供错误序号；(2) Error number: provide the error number;
(3)解决方案：提供可行的解决方案。(3)Solution: Provide feasible solutions.
通过设置图形化的交互界面，所画即所得，且动画显示各个组件模型之间的数据流，大幅降低使用门槛，提高用户的使用体验。By setting up a graphical interactive interface, what you draw is what you get, and animation displays the data flow between each component model, which greatly reduces the usage threshold and improves the user experience.
该仿真系统还包括模型层单元，用于构建多个与芯片设计相关的组件模型，将构建的组件模型存入模型库，并对组件模型进行参数配置和分类管理。The simulation system also includes a model layer unit for constructing a plurality of component models related to chip design, storing the constructed component models in a model library, and performing parameter configuration and classification management on the component models.
模型层采用目录式的分类管理，具有相似功能的组件被归入一个文件夹或者子文件夹中；模型层的一个模型组件可以是一个基本结构，例如激励发生器或者调度器，也可以是一个复杂的元件，例如一个处理器。每一个组件模型包含一组控制自身执行的参数集。模型组件库构成了仿真系统快速建模能力的基础。模型层的模型组件库，从模型组件库窗口的文件夹选中需要的组件，拖放到全景窗口中完成例化，配置组件实例的参数，用连线连接各组件实例的端口或者以虚拟动态映射实现拓扑结构设计。The model layer adopts catalog-style classification management, and components with similar functions are classified into a folder or subfolder; a model component in the model layer can be a basic structure, such as an excitation generator or scheduler, or a complex component, such as a processor. Each component model contains a set of parameters that control its own execution. The model component library forms the basis of the rapid modeling capability of the simulation system. In the model component library of the model layer, select the required component from the folder in the model component library window, drag and drop it into the panoramic window to complete the instantiation, configure the parameters of the component instance, connect the ports of each component instance with wires, or implement the topology design with virtual dynamic mapping.
模型的连接是总线化，总线归属于xx_interface模块。这些模块会把强相关信号进行封装传输，总线化连接提高模型的扩展性，简化模型结构。The model is connected in a bus-based manner, and the bus belongs to the xx_interface module. These modules will encapsulate and transmit strongly related signals. The bus-based connection improves the scalability of the model and simplifies the model structure.
在一个可选地实施方式中，模型层配置模型库，用于预先编译多个与芯片设计相关的组件模型，将编译好的组件模型存入模型库，并采用目录式的方法对组件模型进行分类管理。In an optional implementation, the model layer configures a model library for pre-compiling multiple component models related to chip design, storing the compiled component models in the model library, and classifying and managing the component models using a directory approach.
具体地，模型层中组件库的模型是一系列预先编译的SystemC模型，预编译模型主要分为两种：事务级模型和寄存器传输级模型。Specifically, the model of the component library in the model layer is a series of pre-compiled SystemC models. The pre-compiled models are mainly divided into two types: transaction-level models and register transfer-level models.
其中事务级模型构建，主要分为三种不同的事务级模型匹配不同情况下的协议要求，三种模型分别是：非定时模型(Untimed TLM)、松散定时模型(Loosely Timed)和近似定时模型(Approximately Timed)。The transaction-level model construction is mainly divided into three different transaction-level models to match the protocol requirements in different situations. The three models are: Untimed TLM, Loosely Timed, and Approximately Timed.
(1)非定时模型主要用于设计规范，有效信息较少，仿真速度快的情形。(1) Untimed models are mainly used in situations where design specifications, less effective information, and fast simulation speed are required.
非定时模型的建模方式是SC_THREAD进程；使用阻塞方式读/写；使用Δ(delta-cycle)来模拟进程推进，确定参数不会导致程序中的sc_start终止。为使程序终止使用了多种方案，例如对含有FIFO通道的模块，模型会运行到数据占满FIFO；给定仿真时间和数据相关退出条件的组合；创建终止模块并监控退出条件。The non-timed model is modeled as an SC_THREAD process; read/write in blocking mode; use Δ (delta-cycle) to simulate process advancement, and determine the parameters so that the sc_start in the program will not terminate. In order to terminate the program, a variety of schemes are used, such as for modules with FIFO channels, the model will run until the data fills the FIFO; a combination of simulation time and data-related exit conditions is given; a termination module is created and the exit conditions are monitored.
以RISC指令集的数据总线模型为例介绍非定时模型的代码风格：该模块使用的头文件包括systemc.h和tlm.h，它们定义了核心TLM2.0接口和所需的模型工具文件：Taking the data bus model of the RISC instruction set as an example, the code style of the non-timed model is introduced: the header files used by this module include systemc.h and tlm.h, which define the core TLM2.0 interface and the required model tool files:
#include“systemc.h”#include "systemc.h"
#include“tlm.h”#include "tlm.h"
#include“tlm_utiles/simple_initiator_socket.h”#include "tlm_utiles/simple_initiator_socket.h"
#include“databus.h”#include "databus.h"
该模块被声明为标准的SystemC模块，派生自sc_module.：The module is declared as a standard SystemC module, derived from sc_module.:
classrisc_bus:public sc_core::sc_moduleclassrisc_bus:public sc_core::sc_module
该模块的一个公共接口使用了TLM2.0库中的simple_initiator_socket方法，定义了一个宽度为32位的数据总线。该接口是一个模板，必须指定类使用：A public interface of this module uses the simple_initiator_socket method in the TLM2.0 library to define a data bus with a width of 32 bits. This interface is a template and must be specified as a class:
tlm_utils::simple_initiator_socket<risc_bus,32>dataBus；tlm_utils::simple_initiator_socket<risc_bus,32>dataBus;
该模块使用自定义的构造函数，也可以添加RISC的配置文件和其它参数等：This module uses a custom constructor, and can also add RISC configuration files and other parameters:
SC_HAS_PROCESS(risc_bus)；SC_HAS_PROCESS(risc_bus);
risc_bus(sc_core::sc_module_name name)；risc_bus(sc_core::sc_module_name name);
该模块具有单个线程，执行相应指令，函数实现如下，线程并不是公共接口的一部分，下面将在派生类重用，所以采用protected：This module has a single thread that executes the corresponding instructions. The function is implemented as follows. The thread is not part of the public interface and will be reused in the derived class below, so it is protected:
该模块中有效负载声明为类变量，采用了tlm_gengeric_payload方法：The payload in this module is declared as a class variable and the tlm_gengeric_payload method is used:
tlm::tlm_generic_payload trans；tlm::tlm_generic_payload trans;
该模块设置好负载字段后，将调用函数以将有效负载传输到目标。虽然是非定时模型，但仍需要提供时间变量。使用变量的原因是目标可以更新该时间。时间变量以SC_ZERO_TIME时间声明，b_transport是虚拟接口，虚拟接口使用有效负载传递给目标：After the module sets the payload field, it calls a function to transfer the payload to the target. Although it is a non-timed model, a time variable is still required. The reason for using a variable is that the target can update the time. The time variable is declared with SC_ZERO_TIME time, and b_transport is a virtual interface that uses the payload to pass to the target:
sc_core::sc_timebusDelay＝sc_core::SC_ZEOR_TIME；sc_core::sc_timebusDelay = sc_core::SC_ZEOR_TIME;
dataBus->b_transport(trans,busDelay)；dataBus->b_transport(trans,busDelay);
松散定时模型用于软件开发、性能评估和体系结构分析。该模型中每一个事物被处理对应两个时间点，即事物的开始点和结束点。在TLM协议中，这两个时间点与请求相位的开始和相应相位的开始相对应。正常情况下，事务处理的结束时间点要晚于事务处理的开始时间点，也可以是相同的。The loose timing model is used for software development, performance evaluation, and architecture analysis. In this model, each transaction is processed at two time points, namely the start point and the end point of the transaction. In the TLM protocol, these two time points correspond to the start of the request phase and the start of the corresponding phase. Normally, the end time point of the transaction is later than the start time point of the transaction, or they can be the same.
松散定时模型支持时间解耦，模型的一部分可以在当前仿真事件之前运行，直到一个需要与其他部分同步的一个同步点。时间解耦降低了进程允许的仿真精度，但是有效的调高了模型仿真速度；松散定时模型建模方式是SC_THREAD进程，使用阻塞传输接口。以Jtag模型为例介绍松散定时模型的代码风格：The loose timing model supports time decoupling. A part of the model can run before the current simulation event until a synchronization point that needs to be synchronized with other parts. Time decoupling reduces the simulation accuracy allowed by the process, but effectively increases the simulation speed of the model; the loose timing model modeling method is the SC_THREAD process, using a blocking transmission interface. Take the Jtag model as an example to introduce the code style of the loose timing model:
模块的头文件：The module's header file:
模块的源文件：Module source files:
建立近似定时模型目的是支持近似时序或者时间精确的事务级模型，以便进行性能建模和体系结构探索。近似定时模型使用非阻塞传输接口，该接口允许事务分多个阶段执行，根据TLM协议可分为四个阶段：begin_req，end_req，begin_resp，end_resp，在一些模型中根据一些特殊协议增加了其他阶段。The purpose of building an approximate timing model is to support approximate timing or time-accurate transaction-level models for performance modeling and architecture exploration. The approximate timing model uses a non-blocking transmission interface that allows transactions to be executed in multiple stages. According to the TLM protocol, it can be divided into four stages: begin_req, end_req, begin_resp, end_resp. In some models, other stages are added according to some special protocols.
上述四个阶段的介绍：请求从发起方通过零个或多个互连向前传播到目标，响应从目标通过零个或多个互连向后传播到发起方。发起方有义务在发送begin_req之前设置通用有效负载的所有属性，并且不允许随后修改这些属性。仅允许目标在接收begin_req和发送begin_resp之间修改通用负载属性。Introduction to the above four phases: Requests propagate forward from the initiator through zero or more interconnects to the target, and responses propagate backward from the target through zero or more interconnects to the initiator. The initiator is obliged to set all properties of the generic payload before sending begin_req, and is not allowed to modify these properties subsequently. The target is only allowed to modify the generic payload properties between receiving begin_req and sending begin_resp.
由于近似定时模型有四个不同的阶段，因此它们能够对接受延迟和延迟进行建模。由于一个近似定时模型涉及模块较多，这里以begin_req阶段的模型为例介绍代码风格：Since the approximate timing models have four different stages, they are able to model acceptance delays and latency. Since an approximate timing model involves many modules, here we take the model of the begin_req stage as an example to introduce the coding style:
三种事务级模型在需要的情况下可以对底层代码进行修改，使他们可以相互转换位。例如，松散定时模型可以加入wait(xx,xx)等语句，让模型具有近似定时模型的特性。The three transaction-level models can modify the underlying code when necessary so that they can be converted to each other. For example, the loosely timed model can add statements such as wait(xx,xx) to make the model have the characteristics of an approximate timed model.
寄存器传输级模型是可以进行综合的硬件模型，构建寄存器传输级模型的目的是架构最终确定但需要进一步验证规范。寄存器传输级模型建模方式时SC_METHOD进程；一个完整的硬件电路会被抽象为多个模块相互连接而成，每个模块通过端口通信，内部可以通过信号连接多个进程、子模块。以2输入与门模型为例介绍寄存器传输级模型代码风格：The register transfer level model is a hardware model that can be synthesized. The purpose of building a register transfer level model is to finalize the architecture but further verify the specifications. The modeling method of the register transfer level model is the SC_METHOD process; a complete hardware circuit will be abstracted into multiple modules connected to each other. Each module communicates through ports, and multiple processes and sub-modules can be connected internally through signals. Take the 2-input AND gate model as an example to introduce the register transfer level model code style:
将构建的组件模型存入模型库。Store the constructed component model into the model library.
还包括数据库配置模块，用于为组件模型配置参数数据以及激励数据。A database configuration module is also included, which is used to configure parameter data and excitation data for the component model.
模型层中的参数组件用于产生事务级激励、事务流程定义与控制处理、资源与架构模型、结构输出。通过使用参数库内的参数名，可以将参数连接到同一级别块中的等效参数，参数使用了字符串进行定义。对于生成的模型通过将变量替换为参数化的字符串，实现参数的可配置性。参数可以添加到任何模型和层次结构的任何级别，可以是包含其他参数名的表达式。在模拟过程中，参数是恒定的，即在模拟开始时进行评估，在各个过程中保持不变。The parameter components in the model layer are used to generate transaction-level incentives, transaction process definition and control processing, resource and architecture models, and structural outputs. Parameters can be connected to equivalent parameters in the same level block by using parameter names in the parameter library. Parameters are defined using strings. For the generated model, the configurability of parameters is achieved by replacing variables with parameterized strings. Parameters can be added to any model and any level of the hierarchy and can be expressions containing other parameter names. During the simulation, parameters are constant, that is, they are evaluated at the beginning of the simulation and remain unchanged during each process.
模型层提供数据写入写出模块。模型中会设置基于正则表达式的解析函数，Excel、XML、Json等多种文本格式的文件都可以作为激励源来给模型输入数据。也可以对于需要的输出参数和数据生成excel、XML、文本文档。The model layer provides data writing and writing modules. Regular expression-based parsing functions are set in the model. Files in various text formats such as Excel, XML, and Json can be used as stimulus sources to input data to the model. Excel, XML, and text documents can also be generated for the required output parameters and data.
模型通过跨模块的函数调用来实现发送数据模拟的。设计了一个名为DataStruct的通用数据结构用于传递数据，这些数据可以整形、浮点型、字符串、向量、数据或者矩阵。这种开放式的数据格式方便了性能和体系结构的分析。The model implements the simulation of sending data through cross-module function calls. A general data structure called DataStruct is designed to pass data, which can be integer, floating point, string, vector, data or matrix. This open data format facilitates performance and architecture analysis.
还包括分析库配置模块，用于采集模型运行信息，根据采集到的运行信息综合分析系统性能。It also includes an analysis library configuration module for collecting model operation information and comprehensively analyzing system performance based on the collected operation information.
在一个可选地实施方式中，分析库配置模块，用于在模型中部署探针，拖放的模型会实例化，内部会启动探针工具，允许在模型的任何节点放置探针，根据部署的探针采集模型的参数信息、名称信息、连接方式信息等多种信息，并根据采集到的信息生成统计报告或图表。In an optional implementation, the analysis library configuration module is used to deploy probes in the model. The dragged and dropped model will be instantiated, and the probe tool will be started internally, allowing probes to be placed at any node in the model. The deployed probes will collect various information such as the model's parameter information, name information, connection method information, etc., and generate statistical reports or charts based on the collected information.
在一个可选地实施方式中，分析库配置模块，用于构建电源模型，根据电源模型监测系统计算次数，根据计算次数分析系统功耗。In an optional implementation, the analysis library configuration module is used to construct a power supply model, monitor the number of system calculations according to the power supply model, and analyze the system power consumption according to the number of calculations.
电源模型是系统级的控制和分析模型。可以监测整个模型的动态电源。电源模型是一种类似分布式的网络系统，使设备的动态状态变化信息更新瞬时、平均和累计功率，功耗可以在现有的系统模型上分析，并为每个设备或者模型输入特定的功耗属性。功耗分析需要在模块中放置相应的属性信息来执行。通过该模型可以估算出整个系统或者特定模型的瞬时和平均功耗，该模型既可以用于标准化的组件也可以处理定制组件。The power model is a system-level control and analysis model. The dynamic power supply of the entire model can be monitored. The power model is a distributed network system that updates the instantaneous, average and cumulative power of the device's dynamic state change information. The power consumption can be analyzed on the existing system model and specific power consumption attributes can be entered for each device or model. Power consumption analysis requires placing the corresponding attribute information in the module to perform. The model can be used to estimate the instantaneous and average power consumption of the entire system or a specific model. The model can be used for both standardized components and customized components.
还用于构建细化统计模型，根据细化统计模型采集系统带宽信息、延迟信息、吞吐量信息以及利用率信息中的一种或多种性能数据，并根据采集的性能数据生成饼状图、条状图或曲线图。It is also used to build a refined statistical model, collect one or more performance data of system bandwidth information, delay information, throughput information and utilization information according to the refined statistical model, and generate a pie chart, bar chart or curve chart according to the collected performance data.
模型层建立了细化统计模型，细化统计模型是针对想要详细的探索潜在架构问题而设计的。高抽象级的事务级模型对于功能的精确度范围为60％～80％，对于模型的事务流的准确度范围为80％左右，如果加上详细的处理信息，足以在峰值利用率、吞吐量或者延迟方面做出有价值的设计策略。The model layer establishes a detailed statistical model, which is designed for exploring potential architectural issues in detail. The high-level transaction-level model has an accuracy range of 60% to 80% for functions and an accuracy range of about 80% for transaction flows of the model. If detailed processing information is added, it is sufficient to make valuable design strategies in terms of peak utilization, throughput or latency.
细化统计模型的性能分析模块使用资源和处理模块来构建。性能分析模型监测系统的整体指标，如系统带宽信息、延迟信息、吞吐量信息以及利用率信息等。该模型是基于事件触发的，通过记录工作负载和流量控制，来研究分析模型的容量限制和系统瓶颈。The performance analysis module of the refined statistical model is built using resource and processing modules. The performance analysis model monitors the overall indicators of the system, such as system bandwidth information, latency information, throughput information, and utilization information. The model is event-triggered and records workload and flow control to study the capacity limitations and system bottlenecks of the analysis model.
细化统计模型包括绘图模块，绘图模块可以将关键信息和指定的信号的值输出图表。该模块通过Qt自带的QChart模块设计，支持饼状图、条状图、曲线图(折线图)等。通过定时器的槽和获取模型数据的方法，曲线图可以实时反应模型的性能。The refined statistical model includes a drawing module, which can output key information and the value of the specified signal to a chart. This module is designed with Qt's own QChart module and supports pie charts, bar charts, curve charts (broken line charts), etc. Through the timer slot and the method of obtaining model data, the curve chart can reflect the performance of the model in real time.
分析模块还用于获取系统的仿真运行结果，对仿真结果进行分析，模型的仿真结果打印信息，使用sc_report_handler函数生成打印信息和相应的打印报告。模型的仿真波形信息，通过sc_trance函数生成波形文件，而后调用linux系统的vcs+verdi或者windows的gtkwave工具用于显示波形。模型的仿真延时使用sc_time类定义，也可以是自定义的宏或者字符串。对于模型使用标签来显示模型的延时信息。The analysis module is also used to obtain the simulation results of the system, analyze the simulation results, print the simulation results of the model, and use the sc_report_handler function to generate the print information and the corresponding print report. The simulation waveform information of the model is generated by the sc_trance function to generate a waveform file, and then the vcs+verdi of the Linux system or the gtkwave tool of Windows is called to display the waveform. The simulation delay of the model is defined by the sc_time class, which can also be a custom macro or string. For the model, use a label to display the delay information of the model.
在一个可选地实施方式中，模型库中构建有限状态机模型，同时提供API接口用于实现python脚本。有限状态机或者基于脚本的模块，可以进一步细化模型，如细化性能和模型分级。In an optional implementation, a finite state machine model is constructed in the model library, and an API interface is provided for implementing a python script. The finite state machine or script-based module can further refine the model, such as refining performance and model grading.
本申请实施例提供的芯片仿真系统还包括仿真层单元，用于对搭建的芯片模型执行仿真操作，并生成仿真运行结果。The chip simulation system provided in the embodiment of the present application also includes a simulation layer unit, which is used to perform simulation operations on the constructed chip model and generate simulation operation results.
仿真层中的仿真协议使用了SystemC的仿真核。仿真层控制和协调整个系统的运行，并实现进程的并行运行。仿真内核是通过事件驱动的，这里的事件指SystemC的event，event是指特定时间发生的事件。The simulation protocol in the simulation layer uses the simulation kernel of SystemC. The simulation layer controls and coordinates the operation of the entire system and implements parallel operation of processes. The simulation kernel is event-driven. The event here refers to the SystemC event, which means an event that occurs at a specific time.
仿真层定义了一个分层模块，目的是使顶层系统模型在系统组件或者模块之间发送。对于时间的模拟，可以将本地模拟器图标添加到具有许多层次结构的大型模型中。The simulation layer defines a hierarchical model to enable top-level system models to be sent between system components or modules. For time-dependent simulations, local simulator icons can be added to large models with many hierarchical structures.
仿真层中提供了基于API的接口，以实现符合标准的Verilog、C/C++、Python等仿真器进行协同仿真。对于VHDL则可以与使用SystemC或者C++编程接口实现系统的协同仿真。The simulation layer provides an API-based interface to implement co-simulation with standard simulators such as Verilog, C/C++, Python, etc. For VHDL, co-simulation of the system can be achieved using SystemC or C++ programming interfaces.
本申请实施例中的交互层单元、模型层单元与仿真层单元之间互相解耦，具备高可扩展性。The interaction layer unit, model layer unit and simulation layer unit in the embodiment of the present application are decoupled from each other and have high scalability.
根据本申请实施例提供的芯片仿真系统，支持图形化界面，所画即所得，大幅降低使用门槛；同时支持代码编辑，兼顾简单易用性需求与复杂定制性需求。且自带常用电路结构模型，同时支持第三方同标准模型库，将使用者的工作重心从底层模型实现转向上层系统架构分析。且系统交互层、模型层、仿真层相互解耦，具备高可扩展性。The chip simulation system provided in the embodiment of the present application supports a graphical interface, and what you draw is what you get, which greatly reduces the threshold for use; it also supports code editing, taking into account both the requirements of simple usability and complex customization. It also comes with commonly used circuit structure models, and supports third-party standard model libraries, shifting the user's work focus from the bottom-level model implementation to the upper-level system architecture analysis. The system interaction layer, model layer, and simulation layer are decoupled from each other, and have high scalability.
第二方面，本申请实施例提供了一种芯片仿真方法，如图3所示，包括如下步骤：In a second aspect, an embodiment of the present application provides a chip simulation method, as shown in FIG3 , comprising the following steps:
S301构建图形化交互界面，图形化交互界面具有动画显示效果，并在图形化交互界面设置多个交互窗口；S301 constructs a graphical interactive interface, the graphical interactive interface has an animation display effect, and sets multiple interactive windows on the graphical interactive interface;
S302构建多个与芯片设计相关的组件模型，将构建的组件模型存入模型库，并对组件模型进行参数配置和分类管理；S302 constructs multiple component models related to chip design, stores the constructed component models in a model library, and performs parameter configuration and classification management on the component models;
S303从组件模型中选择多个目标组件模型，对选择的目标组件模型进行连接，形成构建好的芯片模型；S303 selects multiple target component models from the component models, and connects the selected target component models to form a constructed chip model;
S304对搭建的芯片模型执行仿真操作，并生成仿真运行结果。S304 performs simulation operations on the constructed chip model and generates simulation operation results.
在一个示例性实施方式中，构建一个芯片模型并进行仿真的步骤如下：In an exemplary embodiment, the steps of constructing a chip model and performing simulation are as follows:
如图2所示，是交互层一个CPU和DRAM的通信示意图，其中左侧模型库区域，右上侧模型参数配置区域，右下侧命令输入及仿真打印信息，中部是模型编辑区域，上部是工具栏区域。As shown in Figure 2, it is a communication diagram of a CPU and DRAM in the interactive layer, in which the left side is the model library area, the upper right side is the model parameter configuration area, the lower right side is the command input and simulation printing information, the middle is the model editing area, and the upper part is the toolbar area.
首先，工具栏区域选择新建项目文件，选择相应的保存路径和配置。First, select New Project File in the toolbar area and choose the corresponding save path and configuration.
进一步地，在树形表格中定义数据结构字段。数据结构字段中的内容作为事务进行解析。Furthermore, data structure fields are defined in the tree table, and the contents in the data structure fields are parsed as transactions.
进一步地，选则模型库窗口的CPU模型、DRAM模型，拖动并放置在编辑窗口中。Further, select the CPU model and DRAM model in the model library window, drag and place them in the editing window.
进一步地，根据需求在右上侧配置模块中的参数。Furthermore, configure the parameters in the module on the upper right side as required.
进一步地，连接各个模型，并运行系统。Further, connect the models and run the system.
进一步地，从库中拖放绘图组件和文本显示组件。Further, drag and drop drawing components and text display components from the library.
进一步地，可以使框图变成动画调试模拟，或者简单的查看系统模型的动态操作。通过“动画执行”按钮，高亮显示执行组件来动画模型。Furthermore, you can animate the block diagram to debug the simulation, or simply view the dynamic operation of the system model. Use the "Animate Execution" button to highlight the execution components to animate the model.
最后，运行后的结果会在右下角打印出来，如果需要更多可见信息，可以在代码窗口找到相应代码位置输入对应的C++或者SystemC命令。Finally, the results of the run will be printed out in the lower right corner. If you need more visible information, you can find the corresponding code location in the code window and enter the corresponding C++ or SystemC command.
需要说明的是，上述实施例提供的芯片仿真系统在执行芯片仿真方法时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的芯片仿真系统与芯片仿真方法实施例属于同一构思，其体现实现过程详见方法实施例，这里不再赘述。It should be noted that the chip simulation system provided in the above embodiment only uses the division of the above functional modules as an example when executing the chip simulation method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the chip simulation system provided in the above embodiment and the chip simulation method embodiment belong to the same concept, and the implementation process thereof is detailed in the method embodiment, which will not be repeated here.
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the attached claims.
| Application Number | Priority Date | Filing Date | Title |
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| CN202211090629.0ACN116305713B (en) | 2022-09-07 | 2022-09-07 | Chip simulation system and simulation method |
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| CN202211090629.0ACN116305713B (en) | 2022-09-07 | 2022-09-07 | Chip simulation system and simulation method |
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| CN202211090629.0AActiveCN116305713B (en) | 2022-09-07 | 2022-09-07 | Chip simulation system and simulation method |
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