技术领域Technical field
本发明涉及窄脉冲产生技术，具体涉及一种基于超高速与门的非均匀周期超窄脉冲产The invention relates to narrow pulse generation technology, specifically to a non-uniform period ultra-narrow pulse generation based on ultra-high-speed AND gates.
生电路及方法，本发明能为超宽带的奈奎斯特折叠接收机产生采样所需要的窄脉冲，属于射频电路技术领域。Generating circuits and methods, the present invention can generate narrow pulses required for sampling for ultra-wideband Nyquist folding receivers, and belongs to the technical field of radio frequency circuits.
背景技术Background technique
奈奎斯特折叠接收技术是基于压缩感知理论的一种模拟信息接收技术，在低速率采样情况下可实现单通道全频段信号接收的结构。其本质是利用非均匀周期的射频脉冲串对接收信号在模拟与进行一次采样，从而将射频LO中的相位信息调制到接收信号的每一个奈奎斯特区域内，且利用不同奈奎斯特区域（NZ）内所调制的带宽和幅度不尽一致的特点实现对不同NZ信号的区分。Nyquist folding reception technology is an analog information reception technology based on compressed sensing theory. It can achieve a single-channel full-band signal reception structure under low-rate sampling conditions. Its essence is to use non-uniform periodic radio frequency pulse trains to simulate and sample the received signal once, thereby modulating the phase information in the radio frequency LO into each Nyquist area of the received signal, and using different Nyquist areas (NZ) The modulated bandwidth and amplitude are not consistent to distinguish different NZ signals.
在上述一次采样过程中，根据输入被采样信号的频率和带宽，需要相应的窄采样脉冲与其进行匹配，理论上其关系如下：In the above-mentioned sampling process, according to the frequency and bandwidth of the input sampled signal, a corresponding narrow sampling pulse is required to match it. Theoretically, the relationship is as follows:
脉冲宽度的倒数≥被采样信号带宽+二次采样带宽The reciprocal of pulse width ≥ sampled signal bandwidth + secondary sampling bandwidth
因此，当被采样信号的带宽越宽，则需要采样脉冲越窄，以16GHz带宽为例，需要50ps以下的窄脉冲才可满足使用要求。Therefore, when the bandwidth of the sampled signal is wider, the sampling pulse needs to be narrower. Taking the 16GHz bandwidth as an example, a narrow pulse of less than 50ps is required to meet the usage requirements.
传统的窄脉冲大多采用纯模拟方式产生，该方式采用阶跃二极管，利用其非线性，其缺点是使用不灵活，脉宽不可调。而现有的大多低速数字逻辑方式的产生方式，其脉冲宽度大多仅为纳秒量级。Traditional narrow pulses are mostly generated using a pure analog method, which uses step diodes to take advantage of their nonlinearity. Its disadvantages are inflexible use and unadjustable pulse width. However, most of the existing low-speed digital logic generation methods have pulse widths of only nanoseconds.
发明内容Contents of the invention
针对现有技术存在的上述不足，本发明的目的是提供一种基于超高速与门的非均匀周期超窄脉冲产生电路及方法，本发明脉冲宽度超窄（可达ps级），且脉冲宽度灵活可控。In view of the above-mentioned deficiencies in the existing technology, the purpose of the present invention is to provide a non-uniform period ultra-narrow pulse generation circuit and method based on ultra-high-speed AND gates. The pulse width of the present invention is ultra-narrow (up to ps level), and the pulse width Flexible and controllable.
为了实现上述目的，本发明采用的技术方案如下：In order to achieve the above objects, the technical solutions adopted by the present invention are as follows:
一种基于超高速与门的非均匀周期超窄脉冲产生电路，包括放大器，用于对输入的射频信号放大，放大器的输出接射频功分器，射频功分器用于将放大的输入信号输出为等功率的两路信号，其中一路信号依次通过数控延时器Ⅰ、放大器Ⅰ、幅度调整电路Ⅰ和变压器Ⅰ接逻辑与门电路的一路输入，另一路信号通过幅度调整电路Ⅱ和变压器Ⅱ接逻辑与门电路的另一路输入，逻辑与门电路的输出即为窄脉冲信号；变压器Ⅰ和变压器Ⅱ用于将单端射频信号转换为等幅的差分信号。A non-uniform period ultra-narrow pulse generation circuit based on ultra-high-speed AND gates, including an amplifier for amplifying the input radio frequency signal. The output of the amplifier is connected to a radio frequency power divider, and the radio frequency power divider is used to output the amplified input signal as Two signals of equal power, one of which passes through the digital control delayer Ⅰ, amplifier Ⅰ, amplitude adjustment circuit Ⅰ and transformer Ⅰ and is connected to one input of the logic AND gate circuit, and the other signal passes through the amplitude adjustment circuit Ⅱ and transformer Ⅱ and is connected to the logic The other input of the AND gate circuit, the output of the logic AND gate circuit is a narrow pulse signal; transformer I and transformer II are used to convert the single-ended radio frequency signal into a differential signal of equal amplitude.
进一步地，射频功分器的另一路信号通过数控延时器Ⅱ、放大器Ⅱ接入幅度调整电路Ⅱ，其中数控延时器Ⅱ、放大器Ⅱ、幅度调整电路Ⅱ、变压器Ⅱ与对应的数控延时器Ⅰ、放大器Ⅰ、幅度调整电路Ⅰ、变压器Ⅰ采用相同的型号且对称设置。Further, the other signal of the radio frequency power divider is connected to the amplitude adjustment circuit II through the numerically controlled delayer II and the amplifier II. The numerically controlled delayer II, the amplifier II, the amplitude adjustment circuit II, the transformer II and the corresponding numerically controlled delay The device I, amplifier I, amplitude adjustment circuit I, and transformer I are of the same model and are set up symmetrically.
进一步地，输入的射频信号通过射频连接器Ⅰ与放大器连接；逻辑与门电路通过射频连接器Ⅱ输出所述窄脉冲信号。Further, the input radio frequency signal is connected to the amplifier through radio frequency connector I; the logic AND gate circuit outputs the narrow pulse signal through radio frequency connector II.
更进一步地，所述幅度调整电路Ⅰ和幅度调整电路Ⅱ均由电容C1、C2、电阻R1、R2和R3组成，输入信号依次通过电容C1、电阻R3、电容C2后输出，电阻R1一端接地，另一端接于电容C1和电阻R3之间；电阻R2一端接地，另一端接于电容C2和电阻R3之间；其中电容C1、C2对直流信号起阻断作用；电阻R1、R2和R3共同实现信号幅度的调整并实现输入输出阻抗的要求。Furthermore, the amplitude adjustment circuit I and the amplitude adjustment circuit II are composed of capacitors C1, C2, resistors R1, R2 and R3. The input signal passes through the capacitor C1, the resistor R3 and the capacitor C2 in sequence and is output. One end of the resistor R1 is connected to the ground. The other end is connected between capacitor C1 and resistor R3; one end of resistor R2 is connected to ground, and the other end is connected between capacitor C2 and resistor R3; capacitors C1 and C2 block the DC signal; resistors R1, R2 and R3 work together to achieve Adjust signal amplitude and achieve input and output impedance requirements.
具体地，所述逻辑与门电路采用型号为ASNT5160-KMC的逻辑与门器件。Specifically, the logic AND gate circuit uses a logic AND gate device modeled as ASNT5160-KMC.
优选地，所述放大器、射频功分器、数控延时器Ⅱ、放大器Ⅱ、幅度调整电路Ⅱ、变压器Ⅱ、数控延时器Ⅰ、放大器Ⅰ、幅度调整电路Ⅰ、变压器Ⅰ和逻辑与门电路集成在同一电路基板上。Preferably, the amplifier, radio frequency power divider, numerically controlled delayer II, amplifier II, amplitude adjustment circuit II, transformer II, numerically controlled delayer I, amplifier I, amplitude adjustment circuit I, transformer I and logic AND gate circuit Integrated on the same circuit substrate.
本发明同时提供了一种基于超高速与门的非均匀周期超窄脉冲产生方法，将正弦波信号通过射频功分器等功率分成两路信号，并使两路信号产生需要的延时，然后将产生延时的两路信号输入给逻辑与门电路进行与操作，当两路输入信号均为高电平时，则逻辑与门电路输出高电平，否则输出低电平，从而实现窄脉冲信号输出。The invention also provides a non-uniform period ultra-narrow pulse generation method based on ultra-high-speed AND gates, which divides the sine wave signal into two signals with equal power through a radio frequency power divider, and causes the two signals to generate the required delay, and then Input the two signals that cause delay to the logic AND gate circuit for AND operation. When the two input signals are high level, the logic AND gate circuit outputs high level, otherwise it outputs low level, thereby realizing a narrow pulse signal. output.
使两路信号产生需要的延时的方法为，使至少一路信号进入数控延时器，通过数控延时器产生需要的延时。The method to generate the required delay for two signals is to make at least one signal enter the CNC delayer and generate the required delay through the CNC delayer.
进一步地，射频功分器分成的两路信号先分别通过数控延时器产生延时的两路信号后，再分别经过放大器、幅度调整电路和变压器输入给逻辑与门电路进行与操作，两路信号对应的数控延时器、放大器、幅度调整电路和变压器采用相同的型号且对称设置，以使得输入给逻辑与门电路的两路延时信号的延时绝对误差和随机误差最小化。Further, the two signals divided by the radio frequency power divider first pass through the numerically controlled delay device to generate the two delayed signals, and then pass through the amplifier, the amplitude adjustment circuit and the transformer respectively and are input to the logic AND gate circuit for AND operation. The numerically controlled delays, amplifiers, amplitude adjustment circuits and transformers corresponding to the signals are of the same model and are set up symmetrically to minimize the absolute delay error and random error of the two delay signals input to the logic AND gate circuit.
相比现有技术，本发明具有如下有益效果：Compared with the existing technology, the present invention has the following beneficial effects:
本发明的核心是基于超高速数字逻辑器件与射频延时器件，同时结合微波电路设计方法和工艺，具有脉宽可控、灵活性高、脉冲宽度超窄等优点。传统的阶跃二极管等模拟方式，产生的脉冲宽度不够窄，波形不规整，电路设计好后脉宽不可调等缺点。本发明采用数字控制方式实现信号的延迟，脉冲宽度可灵活控制；采用了微波电路的设计思想，保证了其在高频信号情况下信号的完整性。The core of the invention is based on ultra-high-speed digital logic devices and radio frequency delay devices, combined with microwave circuit design methods and processes, and has the advantages of controllable pulse width, high flexibility, and ultra-narrow pulse width. Traditional analog methods such as step diodes produce shortcomings such as pulse width that is not narrow enough, waveforms are irregular, and the pulse width cannot be adjusted after circuit design. The invention adopts digital control mode to realize signal delay, and the pulse width can be flexibly controlled; it adopts the design idea of microwave circuit to ensure the integrity of its signal in the case of high-frequency signals.
本发明采用了对称架构的设计方式，使器件对电路的影响降至最小，保证各种环境下和使用过程中的参数一致性。The present invention adopts a symmetrical architecture design method to minimize the impact of the device on the circuit and ensure parameter consistency under various environments and during use.
本发明以超高速与门ASNT5160-KMC为核心，其工作最高频率可达50GHz，并且结合射频微波电路的设计方法，使其同时具有脉冲宽度窄（ps级）与脉冲宽度灵活可控的特点。The invention uses the ultra-high-speed AND gate ASNT5160-KMC as the core, and its maximum operating frequency can reach 50GHz. Combined with the design method of radio frequency microwave circuits, it has the characteristics of narrow pulse width (ps level) and flexible and controllable pulse width.
附图说明Description of drawings
图1-本发明窄脉冲产生电路原理图。Figure 1 - Principle diagram of the narrow pulse generating circuit of the present invention.
图2-本发明幅度调整电路结构图。Figure 2 - Structural diagram of the amplitude adjustment circuit of the present invention.
图3-本发明高速与门产生窄脉冲示意图。Figure 3 - Schematic diagram of the high-speed AND gate of the present invention generating narrow pulses.
图4-本发明非对称架构的延时电路图。Figure 4 - Delay circuit diagram of the asymmetric architecture of the present invention.
图5-本发明对称架构的延时电路图。Figure 5 - Delay circuit diagram of the symmetrical architecture of the present invention.
具体实施方式Detailed ways
以下结合附图和具体实施方式对本发明做进一步详细说明。The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
参见图1，本发明一种基于超高速与门的非均匀周期超窄脉冲产生电路，包括放大器，用于对输入的射频信号放大，放大器的输出接射频功分器，射频功分器用于将放大的输入信号输出为等功率的两路信号，其中一路信号依次通过数控延时器Ⅰ、放大器Ⅰ、幅度调整电路Ⅰ和变压器Ⅰ接逻辑与门电路的一路输入，另一路信号通过幅度调整电路Ⅱ和变压器Ⅱ接逻辑与门电路的另一路输入，逻辑与门电路的输出即为窄脉冲信号；变压器Ⅰ和变压器Ⅱ用于将单端射频信号转换为等幅的差分信号。Referring to Figure 1, the present invention is a non-uniform period ultra-narrow pulse generation circuit based on ultra-high-speed AND gates, including an amplifier for amplifying the input radio frequency signal. The output of the amplifier is connected to a radio frequency power divider, and the radio frequency power divider is used to amplify the input radio frequency signal. The amplified input signal is output as two signals of equal power. One of the signals passes through the digital control delayer I, the amplifier I, the amplitude adjustment circuit I and the transformer I in sequence and is connected to one input of the logic AND gate circuit. The other signal passes through the amplitude adjustment circuit. II and transformer II are connected to the other input of the logic AND gate circuit, and the output of the logic AND gate circuit is a narrow pulse signal; transformer I and transformer II are used to convert the single-ended radio frequency signal into a differential signal of equal amplitude.
进一步地，射频功分器的另一路信号通过数控延时器Ⅱ、放大器Ⅱ接入幅度调整电路Ⅱ，其中数控延时器Ⅱ、放大器Ⅱ、幅度调整电路Ⅱ、变压器Ⅱ与对应的数控延时器Ⅰ、放大器Ⅰ、幅度调整电路Ⅰ、变压器Ⅰ采用相同的型号且对称设置。Further, the other signal of the radio frequency power divider is connected to the amplitude adjustment circuit II through the numerically controlled delayer II and the amplifier II. The numerically controlled delayer II, the amplifier II, the amplitude adjustment circuit II, the transformer II and the corresponding numerically controlled delay The device I, amplifier I, amplitude adjustment circuit I, and transformer I are of the same model and are set up symmetrically.
为更方便地实现信号输入与输出，本发明输入的射频信号通过射频连接器Ⅰ与放大器连接；逻辑与门电路通过射频连接器Ⅱ输出所述窄脉冲信号。这样，信号输入端直接与射频连接器Ⅰ插接，即实现信号输入；输出信号接收端直接与射频连接器Ⅱ插接，即实现信号输出。In order to realize signal input and output more conveniently, the input radio frequency signal of the present invention is connected to the amplifier through the radio frequency connector I; the logic AND gate circuit outputs the narrow pulse signal through the radio frequency connector II. In this way, the signal input end is directly plugged into the RF connector I, which realizes signal input; the output signal receiving end is directly plugged into the RF connector II, which realizes signal output.
具体地，本发明所述幅度调整电路Ⅰ和幅度调整电路Ⅱ均由电容C1、C2、电阻R1、R2和R3组成，输入信号依次通过电容C1、电阻R3、电容C2后输出，电阻R1一端接地，另一端接于电容C1和电阻R3之间；电阻R2一端接地，另一端接于电容C2和电阻R3之间；其中电容C1、C2对直流信号起阻断作用；电阻R1、R2和R3共同实现信号幅度的调整并实现输入输出阻抗的要求。Specifically, the amplitude adjustment circuit I and the amplitude adjustment circuit II of the present invention are composed of capacitors C1, C2, resistors R1, R2 and R3. The input signal passes through the capacitor C1, the resistor R3 and the capacitor C2 in sequence and is output. One end of the resistor R1 is grounded. , the other end is connected between the capacitor C1 and the resistor R3; one end of the resistor R2 is connected to ground, and the other end is connected between the capacitor C2 and the resistor R3; the capacitors C1 and C2 block the DC signal; the resistors R1, R2 and R3 jointly Achieve signal amplitude adjustment and achieve input and output impedance requirements.
所述放大器、射频功分器、数控延时器Ⅱ、放大器Ⅱ、幅度调整电路Ⅱ、变压器Ⅱ、数控延时器Ⅰ、放大器Ⅰ、幅度调整电路Ⅰ、变压器Ⅰ和逻辑与门电路集成在同一电路基板上。The amplifier, radio frequency power divider, numerically controlled delayer II, amplifier II, amplitude adjustment circuit II, transformer II, numerically controlled delayer I, amplifier I, amplitude adjustment circuit I, transformer I and logic AND gate circuit are integrated in the same on the circuit board.
本发明同时提供了一种基于超高速与门的非均匀周期超窄脉冲产生方法，将正弦波信号通过射频功分器等功率分成两路信号，并使两路信号产生需要的延时，然后将产生延时的两路信号输入给逻辑与门电路进行与操作，当两路输入信号均为高电平时，则逻辑与门电路输出高电平，否则输出低电平，从而实现窄脉冲信号输出。The invention also provides a non-uniform period ultra-narrow pulse generation method based on ultra-high-speed AND gates, which divides the sine wave signal into two signals with equal power through a radio frequency power divider, and causes the two signals to generate the required delay, and then Input the two signals that cause delay to the logic AND gate circuit for AND operation. When the two input signals are high level, the logic AND gate circuit outputs high level, otherwise it outputs low level, thereby realizing a narrow pulse signal. output.
使两路信号产生需要的延时的方法为，使至少一路信号进入数控延时器，通过数控延时器产生需要的延时。The method to generate the required delay for two signals is to make at least one signal enter the CNC delayer and generate the required delay through the CNC delayer.
优选地，射频功分器分成的两路信号先分别通过数控延时器产生延时的两路信号后，再分别经过放大器、幅度调整电路和变压器输入给逻辑与门电路进行与操作，两路信号对应的数控延时器、放大器、幅度调整电路和变压器采用相同的型号且对称设置，以使得输入给逻辑与门电路的两路延时信号的延时绝对误差和随机误差最小化。Preferably, the two signals divided by the radio frequency power divider first pass through the numerically controlled delay device to generate the two delayed signals, and then pass through the amplifier, the amplitude adjustment circuit and the transformer respectively and are input to the logic AND gate circuit for AND operation. The numerically controlled delays, amplifiers, amplitude adjustment circuits and transformers corresponding to the signals are of the same model and are set up symmetrically to minimize the absolute delay error and random error of the two delay signals input to the logic AND gate circuit.
下面结合实施例对本发明作进一步详细的描述，但本发明的实施方式不限于此。The present invention will be described in further detail below with reference to examples, but the implementation of the present invention is not limited thereto.
参见图1，本发明整个电路具有一个正弦波信号的输入口和一个窄脉冲信号的输出口，输入口的频率设计为2GHz±100MHz,该信号的频率即为输出脉冲的重频频率。输出口输出约30ps宽度的窄脉冲信号，对应的主频率大约为脉宽的倒数，约为30GHz。为尽量保证其性能，选用工作频率可到50GHz的射频连接器，在本发明实施例中选用艾利特公司的2.4-KFD2型连接器，其特征阻抗为50欧姆，工作频率可达50GHz。Referring to Figure 1, the entire circuit of the present invention has an input port for a sine wave signal and an output port for a narrow pulse signal. The frequency of the input port is designed to be 2GHz±100MHz. The frequency of this signal is the repetition frequency of the output pulse. The output port outputs a narrow pulse signal with a width of about 30ps, and the corresponding main frequency is about the reciprocal of the pulse width, which is about 30GHz. In order to ensure its performance as much as possible, a radio frequency connector with an operating frequency of up to 50 GHz is selected. In the embodiment of the present invention, the 2.4-KFD2 connector of Elite Company is selected, with a characteristic impedance of 50 ohms and an operating frequency of up to 50 GHz.
图1所示的A1为放大器，用于对输入射频信号的放大，实施例中选用型号为NC10200C-103，工作频率为1-3GHz,增益为14dB。A1 shown in Figure 1 is an amplifier, used to amplify the input radio frequency signal. In the embodiment, the selected model is NC10200C-103, the operating frequency is 1-3GHz, and the gain is 14dB.
B1为射频功分器，实现将一路射频信号等功率分成两路信号，用于后续的与处理,实施例中选用型号为NC6520C-103。B1 is a radio frequency power splitter, which can divide one radio frequency signal into two signals with equal power for subsequent processing. The model selected in the embodiment is NC6520C-103.
C1、C2为数控延时器Ⅰ和数控延时器Ⅱ，实施例中选用电子十三所生产的型号为NC12115C-106的数控延时器，其每一bit对应的延时步进为5ps，控制位数为8bit。由此可计算出其最大延时时间为C1 and C2 are the numerical control delayer I and the numerical control delayer II. In the embodiment, the numerical control delayer model NC12115C-106 produced by Electronic 13 is used. The delay step corresponding to each bit is 5ps. The number of control bits is 8bit. From this, the maximum delay time can be calculated as
因此，当输入信号为2GHz，即周期500ps时，该数控延时器可覆盖2GHz信号整个波形的延时。Therefore, when the input signal is 2GHz, that is, the period is 500ps, the numerically controlled delayer can cover the delay of the entire waveform of the 2GHz signal.
D1、D2为放大器Ⅰ和放大器Ⅱ，两放大器用于补偿延时器和信号链路传输过程中的衰减，保证信号在后续使用中满足幅度要求。实施例中两放大器型号为NC10200C-103，工作频率为0.3-3GHz，增益为29dB。D1 and D2 are amplifier I and amplifier II. The two amplifiers are used to compensate for the delay and the attenuation during signal link transmission to ensure that the signal meets the amplitude requirements in subsequent use. In the embodiment, the two amplifier models are NC10200C-103, the operating frequency is 0.3-3GHz, and the gain is 29dB.
E1、E2为幅度调整电路Ⅰ和幅度调整电路Ⅱ，将信号幅度调整到大约6dB，使得信号经变压器转换为差分信号后,CML电平标准满足器件ASNT5160-KMC的CML电平标准。如图2所示，两幅度调整电路为Π型电阻衰减网络，由电容C1，C2，电阻R1，R2，R3组成，其中C1，C2对直流信号起阻断作用；R1，R2，R3共同实现信号幅度的调整并实现输入输出阻抗50欧姆的要求，根据不同的电阻值可得到不同的信号输出输入功率比。E1 and E2 are amplitude adjustment circuit I and amplitude adjustment circuit II, which adjust the signal amplitude to about 6dB, so that after the signal is converted into a differential signal by the transformer, the CML level standard meets the CML level standard of the device ASNT5160-KMC. As shown in Figure 2, the two-amplitude adjustment circuit is a Π-shaped resistance attenuation network, consisting of capacitors C1, C2, and resistors R1, R2, and R3. C1 and C2 block the DC signal; R1, R2, and R3 jointly implement Adjust the signal amplitude and achieve the input and output impedance requirement of 50 ohms. Different signal output to input power ratios can be obtained according to different resistance values.
F1、F2为射频变压器Ⅰ和射频变压器Ⅱ，用于将单端射频信号转换为等幅的差分信号，实施例中两射频变压器选用型号均为RFT-5-1T，工作频率为0.3～6GHz，插入损耗大约3dB；该变压器结合幅度调整电路，巧妙地将单端射频信号转为为CML电平标准，相比于传统的采用数字CML电平芯片的转换方式，几乎不需要外围的辅助电路，电路更简单，更易于集成化。F1 and F2 are RF transformers I and RF transformers II, which are used to convert single-ended RF signals into differential signals of equal amplitude. In the embodiment, the selected models of the two RF transformers are RFT-5-1T, and the operating frequency is 0.3~6GHz. The insertion loss is about 3dB; the transformer combined with the amplitude adjustment circuit cleverly converts the single-ended RF signal to the CML level standard. Compared with the traditional conversion method using digital CML level chips, there is almost no need for peripheral auxiliary circuits. The circuit is simpler and easier to integrate.
G1为高速逻辑与门电路，实施例中选用型号为ASNT5160-KMC，通过两组输入信号的与操作，实现窄脉冲信号产生目的。当两路输入信号均为高电平时，则输出为高电平，否则输出为低电平。其信号产生示意图如图3所示。G1 is a high-speed logic AND gate circuit. The model selected in the embodiment is ASNT5160-KMC. Through the AND operation of two sets of input signals, the purpose of generating narrow pulse signals is achieved. When both input signals are high level, the output is high level, otherwise the output is low level. The schematic diagram of its signal generation is shown in Figure 3.
上述设计过程中，采用了对称架构的设计，使两路相与信号具有相同的参数特性，进而可以将一些随机因素同向抵消，保证链路的一致性。In the above design process, a symmetrical architecture design is adopted so that the two phases and signals have the same parameter characteristics, which can offset some random factors in the same direction and ensure the consistency of the link.
从功能上考虑，只需要一路射频延时器即可实现延时功能；但由于在各种环境下，器件的幅度，相位变化特性将会导致两条链路的相对时延发生变化。同时为了满足使用要求，两路信号的绝对延时不允许超过一个正弦波周期，因而，采用对称架构的设计，采用对等的布局和走线方式，同型号同批次的器件，使得两路延时信号的延时绝对误差和随机误差都最小化。两种架构的原理框图见图4和图5。From a functional perspective, only one radio frequency delay is needed to achieve the delay function; however, due to the amplitude and phase change characteristics of the device in various environments, the relative delay of the two links will change. At the same time, in order to meet the usage requirements, the absolute delay of the two signals is not allowed to exceed one sine wave cycle. Therefore, a symmetrical architecture design is adopted, an equivalent layout and routing method, and devices of the same model and batch are used, so that the two channels Both the absolute delay error and the random error of the delayed signal are minimized. The schematic block diagrams of the two architectures are shown in Figures 4 and 5.
本发明基于超高速逻辑器件和射频微波电路来实现变周期超窄脉冲信号的产生。结合了射频电路和超高速数字电路的优点，采用数控射频延时的方式实现信号的延迟，进而通过对两路具有时间差异的信号相与，产生皮秒级的超窄脉冲信号。The invention is based on ultra-high-speed logic devices and radio frequency microwave circuits to realize the generation of variable-period ultra-narrow pulse signals. It combines the advantages of radio frequency circuits and ultra-high-speed digital circuits, uses numerically controlled radio frequency delay to achieve signal delay, and then generates picosecond-level ultra-narrow pulse signals by summing two signals with time differences.
本发明电路中，输入信号频率为2GHz±100MHz的频率调制信号，选用射频延时器的时移步进约为5ps，由于其采用数字控制方式，可非常方便实现时间的可调延迟。在设计中，延时电路采用了对称架构，选用相同的器件，设计相同的信号传输路径，保证两路相与信号随温度等环境变化的一致性，使得最终可以产生稳定的窄脉冲输出。同时采用了射频的差分转换方法替代数字式的CML电平转化方式，结构更简单，更易于集成化。由于脉冲信号窄，对应的信号频率高，在整个电路的设计考虑中，在信号的传输，器件的使用上，均采用了微波电路的设计方法，电路板采用具有良好高频特性的罗杰斯5880基材。In the circuit of the present invention, the input signal frequency is a frequency modulation signal of 2GHz±100MHz, and the time-shift step of the radio frequency delay device is about 5 ps. Since it adopts a digital control method, it is very convenient to realize the adjustable delay of time. In the design, the delay circuit adopts a symmetrical architecture, uses the same components, and designs the same signal transmission path to ensure the consistency of the two phases and signals with changes in the environment such as temperature, so that a stable narrow pulse output can ultimately be generated. At the same time, the radio frequency differential conversion method is used to replace the digital CML level conversion method, which has a simpler structure and is easier to integrate. Because the pulse signal is narrow and the corresponding signal frequency is high, the microwave circuit design method is adopted in the design of the entire circuit, signal transmission, and device use. The circuit board uses Rogers 5880 base with good high-frequency characteristics. material.
本发明的上述实施例仅仅是为说明本发明所作的举例，而并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其他不同形式的变化和变动。这里无法对所有的实施方式予以穷举。凡是属于本发明的技术方案所引申出的显而易见的变化或变动仍处于本发明的保护范围之列。The above-mentioned embodiments of the present invention are only examples for illustrating the present invention, and are not intended to limit the implementation of the present invention. For those of ordinary skill in the art, other different forms of changes and modifications can be made based on the above description. It is not possible to exhaustively list all possible implementations here. All obvious changes or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310298950.6ACN116260429B (en) | 2023-03-24 | 2023-03-24 | Non-uniform period ultra-narrow pulse generation circuit and method based on ultra-high speed AND gate |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310298950.6ACN116260429B (en) | 2023-03-24 | 2023-03-24 | Non-uniform period ultra-narrow pulse generation circuit and method based on ultra-high speed AND gate |
| Publication Number | Publication Date |
|---|---|
| CN116260429A CN116260429A (en) | 2023-06-13 |
| CN116260429Btrue CN116260429B (en) | 2023-09-12 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310298950.6AActiveCN116260429B (en) | 2023-03-24 | 2023-03-24 | Non-uniform period ultra-narrow pulse generation circuit and method based on ultra-high speed AND gate |
| Country | Link |
|---|---|
| CN (1) | CN116260429B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102170277A (en)* | 2011-01-20 | 2011-08-31 | 中国科学院半导体研究所 | Picosecond-accuracy narrow-pulse width transistor-transistor logic (TTL) signal acquisition method based on phase shift AND operation |
| CN102324951A (en)* | 2011-08-24 | 2012-01-18 | 东南大学 | A UWB Pulse Generator Based on Digital Circuit |
| CN111200236A (en)* | 2018-11-20 | 2020-05-26 | 余姚舜宇智能光学技术有限公司 | A high frequency narrow pulse semiconductor laser drive circuit |
| WO2022258034A1 (en)* | 2021-06-11 | 2022-12-15 | 成都飞云科技有限公司 | Pulse generation apparatus and pulse control method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10355320B3 (en)* | 2003-11-27 | 2005-04-14 | Infineon Technologies Ag | High resolution digital pulse width modulator for control of DC-DC converter with combining of 2 pulse width modulated intermediate signals via logic stage |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102170277A (en)* | 2011-01-20 | 2011-08-31 | 中国科学院半导体研究所 | Picosecond-accuracy narrow-pulse width transistor-transistor logic (TTL) signal acquisition method based on phase shift AND operation |
| CN102324951A (en)* | 2011-08-24 | 2012-01-18 | 东南大学 | A UWB Pulse Generator Based on Digital Circuit |
| CN111200236A (en)* | 2018-11-20 | 2020-05-26 | 余姚舜宇智能光学技术有限公司 | A high frequency narrow pulse semiconductor laser drive circuit |
| WO2022258034A1 (en)* | 2021-06-11 | 2022-12-15 | 成都飞云科技有限公司 | Pulse generation apparatus and pulse control method |
| Publication number | Publication date |
|---|---|
| CN116260429A (en) | 2023-06-13 |
| Publication | Publication Date | Title |
|---|---|---|
| KR101874008B1 (en) | Method and device for generating ultra wide band pulses(uwb) | |
| US20020039052A1 (en) | Quadrature oscillator with phase error correction | |
| JP2008205733A (en) | Transmission circuit and wireless transmission device | |
| CN112671428B (en) | Multichannel radio frequency signal receiving and transmitting amplitude-phase control device | |
| CN115225086A (en) | Analog-digital conversion device and method based on non-uniform sampling | |
| CN102565485A (en) | Preamplifier for digital phosphor oscilloscope | |
| CN114567337B (en) | Ultra-wideband transmitter based on FPGA | |
| CN116260429B (en) | Non-uniform period ultra-narrow pulse generation circuit and method based on ultra-high speed AND gate | |
| Chen et al. | A 56-Gbaud 7.3-V ppd Linear Modulator Transmitter with AMUX-Based Reconfigurable FFE and Dynamic Triple-Stacked Driver in 130-nm SiGe BiCMOS | |
| CN207399144U (en) | A kind of broadband Doherty power amplifier | |
| Yodprasit et al. | 20-gbps 60-ghz ook modulator in sige bicmos technology | |
| Ali et al. | Hybrid predistorter for broadband power amplifiers linearization with relaxed DAC speed in the signal transmit path | |
| Yoo et al. | A 28 GHz RF-DAC with analog LO leakage cancellation | |
| CN109495090B (en) | Digital Precision Time Delay Matching Circuit | |
| CN107294546B (en) | A radio frequency link in a digital predistortion system and its working method | |
| CN117595838A (en) | Amplitude and phase synchronous calibration circuit | |
| Veenstra et al. | 15-27 GHz pseudo-noise UWB transmitter for short-range automotive radar in a production SiGe technology | |
| Chen et al. | A 56-Gb/s PAM-4 VCSEL transmitter with piecewise compensation scheme in 40-nm CMOS | |
| Fan et al. | A 32 Gb/s simultaneous bidirectional source-synchronous transceiver with adaptive echo cancellation in 28nm CMOS | |
| CN111683027B (en) | Satellite up-converter based on intermediate frequency analog predistortion | |
| CN114650037B (en) | A UWB Transmitter Based on Each Stage Programmable Delay Line | |
| CN205015676U (en) | High -speed parallel DA clock synchronization device | |
| US20200412316A1 (en) | Low-voltage high-speed programmable equalization circuit | |
| Saoudi et al. | A Digitally Controlled Multichannel Spectrally Efficient Low-Power Transceiver for Ultra-Wideband Cognitive Radio Applications | |
| Ibrahim et al. | A Quadrature Harmonic Rejection Voltage-Domain Mixer with 20 dBm OIP3 and 800 MHz IF Bandwidth |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |