Disclosure of Invention
The embodiment of the disclosure provides an array substrate, a preparation method thereof, a display panel and a display device, which are used for solving or relieving one or more technical problems in the prior art.
As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide an array substrate including a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, the plurality of gate lines and the plurality of data lines intersecting each other to define a plurality of sub-pixel regions, the array substrate including:
A substrate;
the first active layer is positioned on one side of the substrate, at least part of orthographic projection of the first active layer on the substrate is positioned in the sub-pixel area, the material of the first active layer comprises an oxide semiconductor material, and the first active layer is connected with the data line;
The first conductive layer is positioned on one side of the substrate facing the first active layer, the first conductive layer comprises a grid line and a first grid electrode, the material of the grid line comprises a conductive metal material, the first grid electrode is connected with the grid line, the material of the first grid electrode comprises a transparent conductive material, a first overlapping area exists between the orthographic projection of the first grid electrode on the substrate and the orthographic projection of the first active layer on the substrate, and the first overlapping area is positioned in the sub-pixel area;
a first insulating layer between the first active layer and the first conductive layer;
The second insulating layer is positioned on one side of the first active layer and the first conductive layer, which is away from the substrate;
and the pixel electrode is positioned on one side of the second insulating layer, which is away from the substrate, and is connected with the first active layer.
In one embodiment, the first active layers extend in a first direction within the sub-pixel regions, and in the first direction, the first active layers in adjacent sub-pixel regions are disposed offset from each other in a second direction.
In one embodiment, the extending direction of the first active layer is not perpendicular to the first direction, and the extending direction of the first active layer is not perpendicular to the second direction.
In one embodiment, the array substrate further comprises a flat layer and a connection electrode, the flat layer is located between the second insulating layer and the pixel electrode, the connection electrode is located between the second insulating layer and the flat layer, the second insulating layer is provided with a third through hole penetrating through the second insulating layer, the connection electrode is connected with the first active layer through the third through hole, the flat layer is provided with a fourth through hole, the pixel electrode is connected with the connection electrode through the fourth through hole, and the connection electrode is made of transparent conductive materials.
In one embodiment, the orthographic projection of the third via on the substrate is located in the same sub-pixel region as the first overlap region.
In one embodiment, the orthographic projection of the fourth via hole on the substrate is positioned in the orthographic projection range of the grid line on the substrate, the array substrate further comprises a third insulating layer and a boss, the third insulating layer is positioned on one side of the pixel electrode, which is away from the substrate, the boss is positioned on one side of the third insulating layer, which is away from the substrate, and the orthographic projection of the boss on the substrate is positioned in the orthographic projection range of the fourth via hole on the substrate.
In one embodiment, the first conductive layer is located on a side of the first active layer facing away from the substrate, the data line is located between the substrate and the first active layer, the data line includes a first surface area, and the first active layer is in lap joint with a portion of the first surface area.
In one embodiment, the array substrate further includes a buffer layer, the buffer layer is located between the data line and the first active layer, the buffer layer is provided with a first via hole, a surface of the data line exposed by the first via hole is a first surface area, and the first active layer is in lap joint with a part of the first surface area through the first via hole.
In one embodiment, the first active layer includes a first conductive region located outside the first overlap region, the first conductive region being in overlap connection with a portion of the first surface region through the first via, the first conductive region including a sidewall along an overlap boundary of the first conductive region and the first surface region, the sidewall having a slope angle of less than 90 °.
In one embodiment, the array substrate further includes a fourth insulating layer between the second insulating layer and the connection electrode, and the data line is between the second insulating layer and the fourth insulating layer.
In one embodiment, the array substrate comprises a display area, a frame area outside the display area, a data line, a first active layer, a first conductive layer and a pixel electrode all located in the display area, and further comprises a first electrode, a second active layer, a second electrode and a second gate electrode located in the frame area, wherein the second active layer is arranged on the same layer as the first active layer, and the second gate electrode is arranged on the same layer as the gate line;
The first pole and the second pole are positioned on one side of the second insulating layer, which is away from the substrate, or the first pole and the second pole are arranged on the same layer as the grid line.
As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for manufacturing an array substrate, the array substrate including a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, the plurality of gate lines and the plurality of data lines intersecting each other to define a plurality of sub-pixel regions, the method for manufacturing the array substrate including:
forming a first active layer on a substrate, wherein at least part of orthographic projection of the first active layer on the substrate is positioned in a sub-pixel area, the material of the first active layer comprises oxide, and the first active layer is connected with a data line;
forming a first insulating layer on a side of the first active layer facing away from the substrate;
Forming a first conductive layer on one side of the first insulating layer, which is far away from the substrate, wherein the first conductive layer comprises a grid line and a first grid electrode, the grid line is made of metal, the first grid electrode is connected with the grid line, the first grid electrode is made of transparent conductive material, and a first overlapping area exists between the orthographic projection of the first grid electrode on the substrate and the orthographic projection of the first active layer on the substrate and is positioned in the sub-pixel area;
forming a second insulating layer on one side of the first conductive layer facing away from the substrate;
and forming a pixel electrode on one side of the second insulating layer, which is away from the substrate, wherein the pixel electrode is connected with the first active layer.
As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel, including an array substrate in the embodiments of the present disclosure, further including a color film substrate, where the color film substrate is disposed opposite to the array substrate, and the pixel electrode faces the color film substrate, and the display panel further includes a liquid crystal disposed between the array substrate and the color film substrate.
As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device including an array substrate or a display panel in the embodiments of the present disclosure.
According to the array substrate disclosed by the embodiment of the disclosure, the material of the first active layer comprises an oxide semiconductor material, and the first active layer is made of a transparent material, so that the first active layer and the first gate electrode are made of transparent materials. At least part of the first active layer is arranged in the sub-pixel area, and the first overlapping area is arranged in the sub-pixel area, so that the space occupied by the first active layer and the first overlapping area outside the sub-pixel area is reduced, and the opening ratio of a product is improved. In addition, the first active layer and the first gate electrode are made of transparent materials, so that the transmittance of the sub-pixel area cannot be affected by the first active layer and the first gate electrode in the sub-pixel area.
The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will become apparent by reference to the drawings and the following detailed description.
Detailed Description
Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways, and the different embodiments may be combined arbitrarily without conflict, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
Fig. 1 is a schematic partial plan view of an array substrate according to an embodiment of the present disclosure, fig. 2 is a schematic A-A cross-sectional view of the array substrate shown in fig. 1 according to an embodiment, fig. 3 is a schematic partial plan view of an array substrate according to another embodiment of the present disclosure, and fig. 4 is a schematic partial plan view of an array substrate according to another embodiment of the present disclosure. In one embodiment, as shown in fig. 1 and 2, the array substrate includes a plurality of gate lines 161 extending in a first direction X and a plurality of data lines 121 extending in a second direction Y. The plurality of gate lines 161 are sequentially spaced apart in the second direction Y, and the plurality of data lines 121 are sequentially spaced apart in the first direction X. The plurality of gate lines 161 and the plurality of data lines 121 cross each other to define a plurality of sub-pixel regions. The array substrate includes a base 11, a first active layer 140, a first conductive layer, a first insulating layer 15, a second insulating layer 17, and a pixel electrode 19. Wherein the second direction Y is not parallel to the first direction X. Illustratively, the second direction Y is perpendicular to the first direction X.
As shown in fig. 2, the first active layer 140 is located on one side of the substrate 11, and the orthographic projection of the first active layer 140 on the substrate 11 is at least partially located in the sub-pixel region. The material of the first active layer 140 includes an oxide, and the first active layer 140 is connected to the data line 121.
The first conductive layer is located on a side of the substrate 11 facing the first active layer 140, and includes a gate line 161 and a first gate electrode 163. The gate line 161 may include a conductive metal. The first gate electrode 163 is connected to the gate line 161. The material of the first gate electrode 163 includes a transparent conductive material. There is a first overlap region between the front projection of the first gate electrode 163 on the substrate 11 and the front projection of the first active layer 140 on the substrate 11. The first overlapping region is located in the sub-pixel region.
The first insulating layer 15 is located between the first active layer 140 and the first conductive layer. The second insulating layer 17 is located on the side of the first active layer 140 and the first conductive layer facing away from the substrate 11. The pixel electrode 19 is located at a side of the second insulating layer 17 facing away from the substrate 11, and the pixel electrode 19 is connected to the first active layer 140.
In the array substrate of the embodiment of the present disclosure, the material of the first active layer 140 includes an oxide semiconductor material, and such first active layer 140 is a transparent material, and thus, both the first active layer 140 and the first gate electrode 163 are transparent materials. At least part of the first active layer 140 is arranged in the sub-pixel region, and the first overlapping region is arranged in the sub-pixel region, so that the space occupied by the first active layer 140 and the first overlapping region outside the sub-pixel region is reduced, and the pixel aperture ratio is improved. In addition, since the first active layer 140 and the first gate electrode 163 are both made of transparent materials, the first active layer 140 and the first gate electrode 163 located in the sub-pixel region do not affect the transmittance of the sub-pixel region.
The technical scheme of the display device can be applied to the display product with the ultra-high PPI, when the display device is applied to the display product with the ultra-high PPI, the first active layer is made of a transparent material, the first gate electrode is made of a transparent material, at least part of the first active layer is located in a sub-pixel area, and the first overlapping area is located in the sub-pixel area, so that occupation of the first active layer and the first gate electrode to the non-pixel area is reduced, the product aperture ratio is improved, and the influence of metal wires in the ultra-high PPI product on the product aperture ratio is reduced.
Illustratively, the material of the substrate 11 may include glass, for example, the material of the substrate 11 is glass. Illustratively, the material of the substrate 11 may include an organic material, for example, the material of the substrate 11 may be Polyimide (PI).
The material of the first active layer 140 may include an oxide semiconductor material, the material of the first active layer 140 may include indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) or indium zinc oxide (Indium Zinc Oxide, IZO) or indium gallium oxide (Indium Gallium Oxide, IGO), etc., or the material of the first active layer 140 may be an oxide semiconductor material to be doped.
Illustratively, the material of the first active layer 140 may include an oxide semiconductor material with high mobility and high light stability, for example, the material of the first active layer 140 may include an oxide semiconductor doped with a rare earth element. The oxide material with high light stability is less affected by illumination, and the negative bias of the thin film transistor with the oxide with high light stability as an active layer is smaller and is generally smaller than 1V after the thin film transistor is illuminated by illumination. The first active layer 140 of the embodiment of the present disclosure is less affected by light, and the light shielding layer 27 may not be provided (as shown in fig. 10).
As shown in fig. 2, the first active layer 140 is closer to the substrate than the first conductive layer, that is, the first conductive layer is located at a side of the first active layer 140 facing away from the substrate 11. In another embodiment, the first conductive layer is closer to the substrate 11 than the first active layer 140, that is, the first active layer 140 is located on a side of the first conductive layer facing away from the substrate 11.
As shown in fig. 1, the first active layer 140 may extend in the first direction X within the sub-pixel region. The first gate electrode 163 may extend in the second direction Y within the sub-pixel region. In the first direction X, the first active layers 140 in adjacent sub-pixel regions may be located on the same straight line extending in the first direction X.
In one embodiment, as shown in fig. 3, the first active layers 140 in adjacent sub-pixel regions are disposed to be staggered from each other in the first direction X. As shown in fig. 3, the first active layers 140 are disposed to be offset from each other in the first direction X and are disposed to be offset from each other in the second direction Y. If both the first active layers 140 in the adjacent two sub-pixel regions are translated in the first direction X to the same straight line extending in the second direction Y, there is no overlapping region of the two first active layers 140. For example, in fig. 1, the first active layer 140 in the sub-pixel region P1 and the first active layer 140 in the sub-pixel region P2 are both shifted onto the same data line 121a along the first direction X, and there is no overlapping region between the two first active layers 140.
In the embodiment shown in fig. 1, in the first direction X, the first active layers 140 in adjacent sub-pixel regions are located on the same straight line extending along the first direction X, and in order to meet the requirement of the first active layer 140 manufacturing process, the distance d between two adjacent first active layers 140 along the first direction X needs to be greater than or equal to a preset value. This results in a limited number of first active layers 140 disposed in the first direction X, such that the number of sub-pixels in the first direction X is limited, limiting the resolution improvement.
In the embodiment shown in fig. 3, by arranging adjacent first active layers 140 in the first direction X to be staggered with each other, the value of the spacing d may be reduced, for example, d2 in fig. 3 may be smaller than d1 in fig. 1. Therefore, the number of the first active layers 140 in the first direction X can be increased, the number of the sub-pixels in the first direction X is increased, the resolution of the product is improved, and the ultra-high resolution of the product is facilitated.
In one embodiment, as shown in fig. 4, the extension direction of the first active layer 140 is not perpendicular to the first direction X, and the extension direction of the first active layer 140 is not perpendicular to the second direction Y. That is, the first active layer 140 is disposed obliquely with respect to both the gate line and the data line in the sub-pixel region. In this way, the size of the first active layer 140 in the first direction X can be reduced, the number of the first active layers 140 in the first direction X can be increased, the number of sub-pixels in the first direction X can be increased, and the resolution of the product can be improved.
In one embodiment, as shown in fig. 2, the array substrate may further include a planarization layer 18 and a connection electrode 21. The planarization layer 18 is located between the second insulating layer 17 and the pixel electrode 19, and the connection electrode 21 is located between the second insulating layer 17 and the planarization layer 18. The second insulating layer 17 is provided with a third via hole 33 penetrating the second insulating layer 17, and the connection electrode 21 is connected to the first active layer 140 through the third via hole 33. The planarization layer 18 is provided with a fourth via 34. The fourth via 34 exposes at least a portion of the surface of the connection electrode 21. The pixel electrode 19 is connected to the connection electrode 21 through the fourth via hole 34, and the material of the connection electrode 21 includes a transparent conductive material. The connection electrode 21 using the transparent conductive material does not block light, so that the aperture ratio and transmittance of the product can be further improved.
In the embodiment of the present disclosure, the transparent conductive material may include Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) or the like. The material of the connection electrode 21 may include at least one of ITO and IZO.
In the array substrate shown in fig. 2, the pixel electrode 19 is directly connected to the first active layer 140 through the connection electrode 21, so that the use of a drain electrode metal layer is reduced. With the structure, the opaque metal patterns are reduced, and the aperture ratio and the transmittance of the array substrate are improved.
In one embodiment, as shown in fig. 1-4, the orthographic projection of the fourth via 34 on the substrate 11 is within the range of the orthographic projection of the gate line 161 on the substrate 11. The array substrate may further include a third insulating layer 22 and a boss 23. The third insulating layer 22 is located on the side of the pixel electrode 19 facing away from the substrate 11. The boss 23 is located on a side of the third insulating layer 22 facing away from the substrate 11, and the orthographic projection of the boss 23 on the substrate 11 is located within the range of the orthographic projection of the fourth via 34 on the substrate 11.
It should be noted that, in the LCD, the boss 23 may be used to support the main spacer on the color film substrate, so as to maintain the thickness of the LCD case. The front projection of the fourth via 34 on the substrate 11 is set to be within the range of the front projection of the grid line 161 on the substrate 11, and the front projection of the boss 23 on the substrate 11 is set to be within the range of the front projection of the fourth via 34 on the substrate 11, so that the front projection of the boss 23 on the substrate 11 is within the range of the front projection of the grid line 161 on the substrate 11, and the influence of the boss 23 on the opening ratio of the product is avoided.
The light leakage of the fourth via 34 can be prevented by setting the orthographic projection of the fourth via 34 on the substrate 11 to lie within the range of the orthographic projection of the gate line 161 on the substrate 11.
In addition, the fourth via hole 34 is a pit, and if the boss 23 is located at a position other than the fourth via hole 34, the pit at the fourth via hole 34 may affect the flatness of the upper surface of the array substrate, and further affect the flatness of the alignment film, and affect the alignment of the liquid crystal. In the process of forming the boss 23, the material for forming the boss 23 may fill the recess at the position of the fourth via hole 34, and thus form the boss 23 above the filled recess, which makes the boss 23 supported by the boss 23 material, and may increase the stability of the boss 23. And the boss 23 is located at the position of the fourth via hole 34, so that the influence of the pit at the position of the fourth via hole 34 on the flatness of the upper surface of the array substrate can be avoided, the flatness of the upper surface of the array substrate can be improved, the flatness of the alignment film is further improved, and the alignment of liquid crystals is facilitated.
In one embodiment, the material of the planarization layer 18 may include an organic material, for example, the material of the planarization layer 18 may include an organic resin material or a photoresist, or the like.
In one embodiment, the material of the boss 23 may include an organic material, for example, the material of the planarization layer 18 may include an organic resin material or photoresist, or the like.
In one embodiment, as shown in fig. 1 to 4, the orthographic projection of the third via hole 33 on the substrate 11 and the first overlapping region are located in the same sub-pixel region. The portion of the data line 121 connected to the first active layer 140 may be referred to as a source electrode, and the connection electrode 21 may be referred to as a drain electrode. The source electrode and the drain electrode are structures in one thin film transistor. It is understood that the via holes are prone to light leakage. The third via hole 33 is disposed in the sub-pixel region, and the sub-pixel region is a light transmitting region, so that unnecessary light leakage caused by the third via hole 33 can be avoided. The orthographic projection of the third via hole 33 on the substrate 11 is set to be located in the same sub-pixel region with the first overlapping region, so that the third via hole 33 can be prevented from occupying the space of other sub-pixel regions, the area of the pixel electrode in the sub-pixel region can be increased, the liquid crystal molecules at the edge of the sub-pixel region are prevented from being disordered, and the display effect is improved.
Fig. 5 is a schematic A-A cross-sectional view of an array substrate according to another embodiment of the disclosure. In one embodiment, as shown in fig. 5, the first conductive layer is located at a side of the first active layer 140 facing away from the substrate 11, and the data line is located between the substrate 11 and the first active layer 140. The data line 121 includes a first surface region, and the first active layer 140 is overlapped with a portion of the first surface region. In the embodiment shown in fig. 5, there is no insulating layer between the first active layer 140 and the data line 121. The surfaces of the data lines 121 facing away from the substrate 11 are all first surface areas.
In the related art, the data line is located at one side of the gate line away from the first active layer 140, at least two insulating film layers are spaced between the data line and the first active layer 140, and the connection resistance between the data line and the first active layer 140 is relatively high, so that the product power consumption is increased. In the embodiment shown in fig. 5, the data line 121 is disposed between the substrate 11 and the first active layer 140, so that the connection resistance between the data line 121 and the first active layer 140 can be reduced, and the power consumption of the product can be reduced.
FIG. 6 is a schematic A-A cross-sectional view of an array substrate according to another embodiment of the disclosure. In one embodiment, as shown in fig. 6, the array substrate may further include a buffer layer 13, and the buffer layer 13 is located between the data line 121 and the first active layer 140. The buffer layer 13 is provided with a first via hole 31, and the front projection of the first via hole 31 on the substrate 11 at least partially overlaps with the front projection of the data line 121 on the substrate 11. The surface of the data line 121 exposed through the first via hole 31 is a first surface area. The first active layer 140 is overlapped with a portion of the first surface region through the first via hole 31.
Fig. 7 is an enlarged schematic view of a portion B in fig. 6. It is understood that after the first active layer 140 is patterned, the first active layer 140 is subjected to a conductive process, and thus, the first active layer 140 includes a first conductive region 141, a second conductive region 142, and a first channel 143 between the first conductive region 141 and the second conductive region 142. The first conductive region 141 is in lap joint with a portion of the first surface region. The pixel electrode is connected to the second conductive region 142. As shown in fig. 7, after the first active layer 140 is made conductive, there is a problem that the upper surface portion (i.e., the portion near the upper surface) of the conductive region is sufficiently conductive, and the lower surface portion (i.e., the portion near the lower surface) is insufficiently conductive. For example, the upper surface portion (i.e., a portion close to the upper surface) 141a of the first conductive region 141 is sufficiently conductive, whereas the lower surface portion (i.e., a portion close to the lower surface) 141b of the first conductive region 141 is insufficiently conductive.
If the first conductive region 141 is in full overlap with the first surface region, the first surface region will be in overlap with only the lower surface portion 141b of the first conductive region 141. The lower surface portion 141b of the first conductive region 141 is insufficiently conductive, so that the contact resistance between the first conductive region 141 and the data line 121 is larger, resulting in a lower on-current Ion of the thin film transistor, which affects the performance of the thin film transistor.
In the embodiment of the present disclosure, as shown in fig. 5 and 6, the first active layer 140 is overlapped with a portion of the first surface region such that the first surface region is in contact connection with not only the lower surface portion 141b of the first conductive region 141 but also the upper surface portion 141a of the first conductive region 141. Even if the lower surface portion 141b of the first conductive region 141 has a problem of insufficient conduction, the contact connection between the first surface region and the upper surface portion 141a of the first conductive region 141 can enable the data line 121 to maintain good electrical contact with the first conductive region 141, reduce the contact resistance between the data line 121 and the first conductive region 141, avoid the problems of larger contact resistance and lower thin film transistor turn-on current Ion of the data line 121 and the first conductive region 141 due to insufficient conduction, enable the thin film transistor to have higher turn-on current, and improve the performance of the thin film transistor.
In one embodiment, as shown in fig. 7, the first conductive region 141 includes a sidewall disposed along a bridging boundary of the first conductive region 141 and the first surface region, the sidewall having a slope angle β of less than 90 °. The slope angle beta of the side wall is set to be smaller than 90 degrees, so that the thickness of the first active layer 140 material at the side wall position is smaller, and complete conductor of the first active layer 140 material at the side wall position is facilitated. Therefore, when the insufficient conduction problem exists, the complete conduction of the material of the first active layer 140 at the side wall position can further increase the contact area between the first surface area and the first conductive area 141, reduce the contact resistance between the data line 121 and the first conductive area 141, and improve the performance of the thin film transistor.
Illustratively, the slope angle β of the sidewall may be less than any value of 90 °, for example, the slope angle β may be 30 °, 45 °, or 60 °.
Fig. 8 is a schematic A-A cross-sectional view of an array substrate according to another embodiment of the disclosure, and fig. 9 is an enlarged schematic view of a portion C in fig. 8. In one embodiment, as shown in fig. 8 and 9, the first conductive region 141 is provided with a second via 32 penetrating the material of the first active layer 140, and the orthographic projection of the second via 32 on the substrate 11 overlaps with the orthographic projection of the first surface region on the substrate 11, so that a part of the surface of the first surface region is exposed through the second via 32, and further, the first conductive region 141 is in lap joint with a part of the first surface region. As can be seen from fig. 9, the first surface region is in contact connection not only with the lower surface portion 141b of the first conductor region 141, but also with the upper surface portion 141a of the first conductor region 141. Even if the lower surface portion 141b of the first conductive region 141 has a problem of insufficient conductive, the contact connection of the first surface region with the upper surface portion 141a of the first conductive region 141 can maintain good electrical contact between the data line 121 and the first conductive region 141, reducing contact resistance between the data line 121 and the first conductive region 141.
In one embodiment, as shown in fig. 2, the array substrate may further include a fourth insulating layer 26, the fourth insulating layer 26 being located between the second insulating layer 17 and the connection electrode, and the data line 121 being located between the second insulating layer 17 and the fourth insulating layer 26. The data line 121 is connected to the first active layer 140 through a fifth via 35 penetrating the fourth insulating layer 26 and the second insulating layer 17.
In another embodiment, the data line 121 may be disposed in the same layer as the connection electrode 21, that is, the data line 121 may be located between the second insulating layer 17 and the planarization layer 18. The material of the data line 121 may include a conductive metal.
It should be noted that, in the present disclosure, E and F are disposed in the same layer, that is, E and F are located between the same two film layers. For example, the data line 121 and the connection electrode 21 are disposed on the same layer, that is, the data line 121 and the connection electrode 21 are disposed between the second insulating layer 17 and the planarization layer 18.
Illustratively, the data lines 121 may have a width of 0.5 μm to 2 μm (inclusive). For example, the width of the data line 121 may be 0.5 μm, 1 μm, 1.5 μm, or 2 μm.
In one embodiment, as shown in fig. 2 and 5, the array substrate may further include a third insulating layer 22 and an auxiliary shielding line 25. The third insulating layer 22 is located on the side of the pixel electrode 19 facing away from the substrate 11. The auxiliary shielding line 25 is located on a side of the third insulating layer 22 facing away from the substrate 11. The front projection of the auxiliary shielding line 25 on the substrate 11 is located within the front projection range of the data line 121 on the substrate 11. The material of the auxiliary shielding line 25 may be an opaque conductive material, such as metal.
In the related art, for LCD products, a black matrix is disposed on a color film substrate to block light to avoid cross color between pixels. The black matrix on the color film substrate is farther from the backlight than the array substrate, and the effect of preventing cross color is limited. According to the array substrate provided by the embodiment of the disclosure, the auxiliary shielding line 25 is arranged on the array substrate, and the auxiliary shielding line 25 is closer to the backlight than the black matrix, so that light rays can be better shielded, cross color between adjacent pixels is improved, and the display effect is improved.
In one embodiment, as shown in fig. 2 and 5, the array substrate further includes a common electrode layer 24. The common electrode layer 24 is located on a side of the third insulating layer 22 facing away from the substrate 11, and the common electrode layer 24 is in contact with the auxiliary shielding line 25. The auxiliary shielding line 25 is arranged to be connected with the common electrode layer 24, so that the auxiliary shielding line 25 can be connected with a common electrode signal to avoid instability caused by the fact that the auxiliary shielding line 25 is in a floating state, and the auxiliary shielding line 25 is connected with the common electrode layer 24 to avoid the auxiliary shielding line 25 from avoiding the common electrode layer 24, and the auxiliary shielding line 25 and the common electrode layer 24 can be simultaneously arranged on the upper surface of the third insulating layer 22 to simplify the manufacturing process.
In one embodiment, as shown in fig. 2 and 5, the front projection of the auxiliary shielding line 25 on the substrate 11 is within the range of the front projection of the common electrode layer 24 on the substrate 11. As shown in fig. 2 and 5, the auxiliary shielding line 25 may be disposed at a side of the third insulating layer 22 facing away from the substrate 11, and the common electrode layer 24 is disposed at a side of the auxiliary shielding line 25 facing away from the substrate 11.
In another embodiment, as shown in fig. 6, the common electrode layer 24 may be disposed on a side of the third insulating layer 22 facing away from the substrate 11, and the auxiliary shielding line 25 is disposed on a side of the common electrode layer 24 facing away from the substrate 11.
Fig. 10 is a schematic cross-sectional view of an array substrate according to another embodiment of the disclosure. In one embodiment, as shown in fig. 10, the array substrate may further include a light shielding layer 27. The light shielding layer 27 is located between the substrate 11 and the buffer layer 13. The orthographic projection of the light shielding layer 27 on the substrate 11 includes the orthographic projection of the first trench 143 on the substrate 11.
By arranging the light shielding layer 27, the light shielding effect on the first channel 143 can be improved, the first channel 143 is prevented from generating negative bias due to illumination, and the performance of the thin film transistor is further improved.
Fig. 11 is a schematic plan view of an array substrate according to an embodiment of the disclosure. Fig. 12 is a schematic cross-sectional view of an array substrate according to an embodiment of the disclosure, and fig. 13 is a schematic cross-sectional view of an array substrate according to another embodiment of the disclosure.
In one embodiment, as shown in fig. 11, the array substrate includes a display area 101 and a frame area 102 located outside the display area. The data line 121, the first active layer 140, the first conductive layer, and the pixel electrode 19 are all located in the display area.
The array substrate further includes a second thin film transistor located in the frame region 102, and the second thin film transistor may include a first electrode 41, a second active layer, a second electrode 42, and a second gate electrode 162. One of the first and second poles 41 and 42 may be a source electrode and the other may be a drain electrode. The second gate electrode 162 is arranged in the same layer as the gate line, that is, the second gate electrode 162 and the gate line are located between the same two film layers, for example, the gate line is located between the first insulating layer 15 and the second insulating layer 17, and the second gate electrode 162 is also located between the first insulating layer 15 and the second insulating layer 17.
As shown in fig. 12 and 13, the second active layer is disposed in the same layer as the first active layer 140. For example, the second active layer and the first active layer 140 are located between the same two film layers, for example, in fig. 12, the second active layer and the first active layer 140 are both located between the buffer layer 13 and the first insulating layer 15.
In one embodiment, the second active layer is formed simultaneously with the first active layer 140, and the second active layer is made of the same material as the first active layer 140. In another embodiment, the material of the second active layer is different from that of the first active layer 140, and the material of the second active layer may include various materials such as amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, and polythiophene.
As shown in fig. 12 and 13, the second active layer includes a third conductive region 144, a fourth conductive region 145, and a second channel 146 between the third conductive region 144 and the fourth conductive region 145. The third conductive region 144 is connected to the first electrode 41, and the second electrode 42 is connected to the fourth conductive region 145. The orthographic projection of the second channel 146 onto the substrate 11 is within the range of the orthographic projection of the second gate electrode 162 onto the substrate 11.
In one embodiment, as shown in fig. 12, the first pole 41 and the second pole 42 may be disposed in the same layer as the gate line 161. That is, the first and second poles 41 and 42 are located between the first and second insulating layers 15 and 17, and the first and second poles 41 and 42 are connected to the third and sixth conductive regions 144 and 145, respectively, through vias penetrating the first insulating layer 15.
In one embodiment, as shown in fig. 13, the first pole 41 and the second pole 42 may be located on a side of the second insulating layer 17 facing away from the substrate 11. For example, the first pole 41 and the second pole 42 may be provided in the same layer as the connection pole 21, that is, the first pole 41 and the second pole 42 may be located between the second insulating layer 17 and the flat layer 18. When the first pole 41 and the second pole 42 are provided in the same layer as the connection pole 21, the material of the first pole 41 and the second pole 42 may be the same as or different from the material of the connection pole 21. When the materials of the first pole 41 and the second pole 42 may be different from those of the connection pole 21, the first pole 41 and the second pole 42 may be formed by different patterning processes with respect to the connection pole 21. The first electrode 41 is connected to the third conductive region 144 through a seventh via penetrating the second insulating layer 17 and the first insulating layer 15, and the second electrode 42 is connected to the fourth conductive region 145 through an eighth via penetrating the second insulating layer 17 and the first insulating layer 15. In another embodiment, first pole 41 and second pole 42 may be located between fourth insulating layer 26 and planar layer 18.
The second thin film transistor in the frame region is typically used for a gate driving circuit (GOA circuit) in which the thin film transistor is subjected to higher voltage and current than the thin film transistor in the display region. In the embodiment of the present disclosure, the materials of the first pole 41 and the second pole 42 of the second thin film transistor in the frame region may each be a conductive metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), may be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, or the like. Therefore, the voltage-resistant capability of the second thin film transistor can be enhanced, and the requirement of the GOA circuit can be met.
In the array substrate of the embodiment of the present disclosure, the first active layer 140 of the thin film transistor corresponding to the sub-pixel region is made of an oxide material, and the second active layer of the thin film transistor in the GOA circuit may be made of various materials such as an oxide material, amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene or polythiophene.
The embodiment of the disclosure also provides a preparation method of the array substrate. The array substrate comprises a plurality of grid lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the grid lines and the data lines mutually intersect to define a plurality of sub-pixel areas. In one embodiment, the method for manufacturing the array substrate may include:
In step S11, a first active layer 140 is formed on one side of the substrate 11, at least a portion of the orthographic projection of the first active layer 140 on the substrate 11 is located in the sub-pixel region, the material of the first active layer 140 includes an oxide semiconductor material, and the first active layer 140 is connected to the data line.
In step S12, a first insulating layer 15 is formed on a side of the first active layer 140 facing away from the substrate 11.
In step S13, a first conductive layer is formed on a side of the first insulating layer 15 facing away from the substrate 11, where the first conductive layer includes a gate line 161 and a first gate electrode 163, the material of the gate line 161 includes a conductive metal, the first gate electrode 163 is connected to the gate line 161, the material of the first gate electrode 163 includes a transparent conductive material, and there is a first overlapping area between the front projection of the first gate electrode 163 on the substrate 11 and the front projection of the first active layer 140 on the substrate 11, where the first overlapping area is located in the sub-pixel area.
In step S14, a second insulating layer 17 is formed on the side of the first conductive layer facing away from the substrate 11.
In step S15, a pixel electrode 19 is formed on a side of the second insulating layer 17 facing away from the substrate 11, the pixel electrode 19 being connected to the first active layer 140.
According to the preparation method of the array substrate, the first insulating layer 15 is reserved, that is, the active layer is covered by the first insulating layer 15, and the first part to be conductive and the second part to be conductive are subjected to conductive by adopting an ion doping process, so that the diffusion of film oxygen can be reduced, the effect of a short channel is further improved, and the formation of a short channel thin film transistor device is facilitated.
Illustratively, the material of the first active layer 140 may include an oxide material with high mobility and high light stability, for example, the material of the first active layer 140 may include an oxide semiconductor doped with a rare earth element. Illustratively, the first active layer 140 may be an oxide material, and the mobility of the material of the first active layer 140 is greater than 20 cm 2/(volt-seconds). The light stability of the material of the first active layer 140 may be represented by NBTIS, for example, the negative bias of the thin film transistor of the first active layer 140 is less than 2V within 2 hours, the test condition is that the light irradiation temperature is 65 ℃ to 75 ℃, the light irradiation intensity is 6000 nit to 30000 nit, and the gate electrode voltage is 20V to 30V. In the embodiment of the disclosure, the high mobility and ion doping process of the high mobility material is utilized to ensure the charging rate of the thin film transistor, and the high temperature annealing of the second insulating layer 17 is no longer needed to activate the conductive region of the first active layer 140, so the high temperature annealing process of the second insulating layer 17 can be omitted, and the process is further simplified.
The technical scheme of the embodiment of the present disclosure is further described below through a preparation process of the array substrate shown in fig. 2. It should be understood that, as used herein, the term "patterning" includes processes such as photoresist coating, mask exposure, development, etching, photoresist stripping, etc. when the patterned material is inorganic or metal, and processes such as mask exposure, development, etc. when the patterned material is organic, evaporation, deposition, coating, etc. are all well-known processes in the related art.
In step S11, a first active layer 140 is formed on one side of the substrate. The steps may include depositing a buffer layer 13 on a substrate, depositing a first active thin film on a side of the buffer layer 13 facing away from the substrate 11, and processing the first active thin film by a patterning process to form a first active layer 140, wherein at least a portion of an orthographic projection of the first active layer 140 on the substrate 11 is located in a sub-pixel region, and a material of the first active layer 140 includes an oxide semiconductor material. The material of the buffer layer can comprise at least one of silicon oxide, silicon nitride and silicon oxynitride, and the buffer layer can be of a single-layer structure or a composite film structure with more than two layers. The thickness of the buffer layer may be 1000 to 6000. The material of the first active layer 140 may include an oxide semiconductor material, the material of the first active layer 140 may include indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) or indium zinc oxide (Indium Zinc Oxide, IZO) or indium gallium oxide (Indium Gallium Oxide, IGO), etc., or the material of the first active layer 140 may be an oxide semiconductor material to be doped. The first active layer 140 using the oxide semiconductor material has a higher transmittance, and such a first active layer 140 can improve the transmittance of the product and can embody the aperture ratio of the product.
In step S12, a first insulating layer 15 is formed on a side of the first active layer 140 facing away from the substrate. The thickness of the first insulating layer 15 may be 500 to 3000 a.
In step S13, a first conductive layer is formed on the side of the first insulating layer 15 facing away from the substrate 11. This step may include forming a gate line 161 on a side of the first insulating layer 15 facing away from the substrate, depositing a transparent conductive film on a side of the gate line 161 facing away from the substrate 11, and patterning the transparent conductive film to form a first gate electrode 163. The material of the gate line 161 includes a conductive metal, and the first gate electrode 163 is connected to the gate line 161, and the material of the first gate electrode 163 includes a transparent conductive material. The front projection of the first gate electrode 163 on the substrate and the front projection of the first active layer 140 on the substrate 11 have a first overlapping region, and the first overlapping region is located in the sub-pixel region. In other embodiments, the first gate electrode 163 may be formed on the side of the first insulating layer 15 facing away from the substrate 11, and then the gate line 161 may be formed.
In step S14, a second insulating layer 17 is formed on the side of the first conductive layer facing away from the substrate 11. The second insulating layer 17 is provided with a sixth via hole, which may expose at least a portion of the surface of the first conductive region of the first active layer 140.
In step S15, a pixel electrode 19 is formed on a side of the second insulating layer 17 facing away from the substrate 11, the pixel electrode 19 being connected to the first active layer 140. The step may include forming a data line 121 on a side of the second insulating layer 17 facing away from the substrate 11, the data line 121 being connected to the first conductive region through a sixth via hole, forming a fourth insulating layer 26 on a side of the data line 121 facing away from the substrate 11, the fourth insulating layer 26 being provided with a third via hole 33 penetrating the fourth insulating layer 26, the second insulating layer 17 and the first insulating layer 15, the third via hole 33 exposing at least a portion of a surface of the second conductive region of the first active layer 140, forming a connection electrode 21 on a side of the fourth insulating layer 26 facing away from the substrate 11, the connection electrode 21 being connected to the second conductive region of the first active layer 140 through the third via hole 33, forming a planarization layer 18 on a side of the connection electrode 21 facing away from the substrate 11, the planarization layer 18 being provided with a fourth via hole 34, the fourth via hole 34 exposing at least a portion of a surface of the connection electrode 21, forming a pixel electrode 19 on a side of the planarization layer 18 facing away from the substrate 11, the pixel electrode 19 being connected to the connection electrode 21 through the fourth via hole.
In an exemplary embodiment, the first insulating layer 15, the second insulating layer 17, the third insulating layer 22, the fourth insulating layer 26, and the buffer layer 13 may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. A Buffer (Buffer) layer for improving the water-oxygen resistance of the substrate 11, the first insulating layer 15 may be referred to as a Gate Insulating (GI) layer, and the second insulating layer 17 may be referred to as an interlayer Insulating (ILD) layer. The data lines 121, the gate lines 161, the first and second electrodes 41 and 42 may be made of a conductive metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), and may be a single-layer structure or a multi-layer composite structure such as Ti/Al/Ti.
The embodiment of the disclosure also provides a display panel, which can include the array substrate in any embodiment of the disclosure, and further can include a color film substrate, where the color film substrate is disposed opposite to the array substrate. The pixel electrode 19 of the array substrate faces the color film substrate. The color film substrate comprises a second substrate, and a black matrix is arranged on one side of the second substrate, which faces the array substrate. The color film substrate may further include color films located in the sub-pixel regions, and the black matrix may be located between adjacent color films. The orthographic projections of the gate lines 161 and the data lines 121 on the substrate 11 are within the range of the orthographic projection of the black matrix on the substrate 11.
Illustratively, the orthographic projection of the auxiliary shielding line 25 on the substrate 11 is within the range of the orthographic projection of the black matrix on the substrate 11.
The display panel may further include a liquid crystal between the array substrate and the color film substrate, for example.
The embodiments of the present disclosure also provide a display device, which may include an array substrate in any of the embodiments of the present disclosure or a display panel in the embodiments of the present disclosure.
The display device can be any product or component with display function such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The display device may be applied in VR or AR scenes.
It should be noted that the structures of the display area and the frame area described in the different embodiments of the present disclosure may be arbitrarily combined with each other without collision.
In the description of the present specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present disclosure.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed, mechanically connected, electrically connected, or in communication, directly connected, or indirectly connected via an intervening medium, or in communication between two elements or in an interaction relationship between two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.
In this disclosure, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.
The above disclosure provides many different embodiments or examples for implementing different structures of the disclosure. The components and arrangements of specific examples are described above in order to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Furthermore, the present disclosure may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed.
The above is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the disclosure, which should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.