CN116130411A - A semiconductor manufacturing method with a structure for preventing copper diffusion - Google Patents
A semiconductor manufacturing method with a structure for preventing copper diffusionDownload PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本申请涉及一种半导体制造方法，具体涉及一种具备防止铜扩散结构的半导体制造方法。The present application relates to a semiconductor manufacturing method, in particular to a semiconductor manufacturing method with a structure for preventing copper diffusion.
背景技术Background technique
随着集成电路集成度的不断提高，Al作为内连线材料其性能已难以很好满足集成电路的要求。Cu较Al具有低的电阻率和高的抗电迁移能力在深亚微米技术中得到广泛的应用。然而，Cu又是导致器件失效的元凶，这主要因为Cu是一种重金属，在高温和加电场的情况下，可以在半导体硅片和二氧化硅中快速扩散，引起器件可靠性方面的问题。所以，在Cu布线层和介质隔离层之间，必须加上防止Cu扩散的扩散阻挡层材料，例如TaN、TiSiN、Ta等来实现防止Cu扩散的目的。With the continuous improvement of the integration level of integrated circuits, the performance of Al as an interconnection material has been difficult to meet the requirements of integrated circuits. Cu has lower resistivity and higher electromigration resistance than Al, and has been widely used in deep submicron technology. However, Cu is the culprit leading to device failure, mainly because Cu is a heavy metal that can rapidly diffuse in semiconductor silicon wafers and silicon dioxide under high temperature and electric field, causing problems in device reliability. Therefore, between the Cu wiring layer and the dielectric isolation layer, a diffusion barrier layer material that prevents Cu diffusion must be added, such as TaN, TiSiN, Ta, etc., to achieve the purpose of preventing Cu diffusion.
同时，随着芯片集成度的提高，互连引线变得更细、更窄、更薄，因此其中的电流密度越来越大。在较高的电流密度作用下，互连引线中的金属原子将会沿着电子运动方向进行迁移，这种现象就是电迁移(EM)。电迁移能使IC中的互连引线在工作过程中产生断路或短路，是引起集成电路失效的一种重要机制。所以，在Cu布线层和介质隔离层之间加上扩散阻挡层材料还可以阻止Cu发生电迁移，另外可以提高Cu和介质隔离层地粘附性。At the same time, with the improvement of chip integration, interconnection leads become thinner, narrower, and thinner, so the current density in them is increasing. Under the effect of higher current density, the metal atoms in the interconnection wire will migrate along the direction of electron movement, which is called electromigration (EM). Electromigration can cause an open circuit or a short circuit in the interconnection wires in the IC during operation, which is an important mechanism that causes the failure of the integrated circuit. Therefore, adding a diffusion barrier material between the Cu wiring layer and the dielectric isolation layer can also prevent Cu from electromigrating, and can also improve the adhesion between Cu and the dielectric isolation layer.
基于上述原因，半导体制造工艺中，90nm以下的工艺节点中多采用铜金属互连(interconnection)以降低电阻，铜金属互连工艺通常采用大马士革工艺实现，即：先形成介质层的凹槽，再在凹槽中电镀铜，这样通过介质层的凹槽实现铜连线的图形化，而不需要对铜层进行刻蚀。镶嵌技术最主要的特点是不需要进行金属层的蚀刻。当金属导线的材料由铝转换成电阻率更低的铜的时候，由于铜的干蚀刻较为困难，因此镶嵌技术对铜制程来说便极为重要。Based on the above reasons, in the semiconductor manufacturing process, copper metal interconnection (interconnection) is often used in the process nodes below 90nm to reduce resistance. Copper is electroplated in the groove, so that the patterning of the copper wiring is realized through the groove of the dielectric layer without etching the copper layer. The main feature of the damascene technology is that it does not need to etch the metal layer. When the material of the metal wire is changed from aluminum to copper with lower resistivity, because copper dry etching is more difficult, damascene technology is very important for copper process.
参考图1A～图1C，其分别为现有技术大马士革工艺中电镀铜工艺、研磨工艺以及阻挡层沉积工艺的示意图。如图1A所示，铜填充工艺通常采用电镀铜(ECP)工艺形成，在电镀铜之前，还需要形成铜籽晶层A1。同时，为了防止铜扩散到介质层A3(如层间膜)中，还需要在铜籽晶层A1形成之前形成铜扩散阻挡层A2。其中，电镀铜在图1A～图1C中以铜金属层Cu来表示。Referring to FIGS. 1A to 1C , they are schematic diagrams of the copper electroplating process, the grinding process and the barrier layer deposition process in the prior art damascene process. As shown in FIG. 1A , the copper filling process is usually formed by an electroplating copper (ECP) process, and a copper seed layer A1 needs to be formed before electroplating copper. At the same time, in order to prevent copper from diffusing into the dielectric layer A3 (such as an interlayer film), it is also necessary to form a copper diffusion barrier layer A2 before forming the copper seed layer A1. Wherein, electroplated copper is represented by a copper metal layer Cu in FIGS. 1A to 1C .
接着，如图1B所示，电镀铜(ECP)工艺完成后，采用化学机械研磨工艺，平坦化结构表面，裸露介质层A3和铜金属层Cu。化学机械研磨工艺中，由于金属铜的研磨速率相比于介质层A3要快，结构表面平坦化后介质层A3与铜金属层Cu并非处于同一水平面上，而是呈现类似碟型的凹陷结构(简称碟型结构)，如图1B中半导体上方的凹陷部位所示。接着，如图1C所示，“碟状”结构的存在会使得后续铜扩散阻挡层A2沉积时在角落处形成孔洞结构，如孔洞H1所示。在高温下，铜会经孔洞H1扩散，影响工艺良率和器件性能。综上所述，实有需要一种新颖的铜金属互连工艺来改善半导体制造方法的良率和器件性能。Next, as shown in FIG. 1B , after the electrolytic copper plating (ECP) process is completed, a chemical mechanical polishing process is used to planarize the surface of the structure, exposing the dielectric layer A3 and the copper metal layer Cu. In the chemical mechanical polishing process, since the grinding rate of metal copper is faster than that of the dielectric layer A3, the dielectric layer A3 and the copper metal layer Cu are not on the same level after the surface of the structure is planarized, but present a dish-like concave structure ( (referred to as a disk structure), as shown in the concave portion above the semiconductor in FIG. 1B . Next, as shown in FIG. 1C , the existence of the “disk” structure will cause a hole structure to be formed at the corner when the subsequent copper diffusion barrier layer A2 is deposited, as shown by the hole H1 . At high temperature, copper will diffuse through the hole H1, affecting process yield and device performance. In summary, there is a real need for a novel copper metal interconnection process to improve the yield and device performance of semiconductor manufacturing methods.
发明内容Contents of the invention
针对以上问题，本申请实施例采用一种具备实时侦测功能的具备防止铜扩散结构的半导体制造方法，能够很好的改善现有技术的问题。In view of the above problems, the embodiment of the present application adopts a semiconductor manufacturing method with a real-time detection function and a copper diffusion prevention structure, which can well improve the problems in the prior art.
具体的，本申请实施例公开一种具备防止铜扩散结构的半导体制造方法，其包括：沉积介质层；对所述介质层进行刻蚀，以开出沟槽；于所述沟槽沉积第一扩散阻挡层；于所述第一扩散阻挡层上方形成铜金属层；对所述铜金属层进行研磨，其中所述铜金属层于研磨后与所述介质层呈现非等高；以带负偏压的沉积方式在所述铜金属层表面沉积第二扩散阻挡层；以及对所述第二扩散阻挡层进行研磨。Specifically, the embodiment of the present application discloses a semiconductor manufacturing method with a structure for preventing copper diffusion, which includes: depositing a dielectric layer; etching the dielectric layer to open a trench; depositing a first Diffusion barrier layer; forming a copper metal layer above the first diffusion barrier layer; grinding the copper metal layer, wherein the copper metal layer is non-equal to the dielectric layer after grinding; to be negatively biased Depositing a second diffusion barrier layer on the surface of the copper metal layer by means of pressure deposition; and grinding the second diffusion barrier layer.
可选的，在本申请的一些实施例中，所述半导体制造方法还包括：于所述第一扩散阻挡层上依序沉积黏合层以及铜籽晶层。Optionally, in some embodiments of the present application, the semiconductor manufacturing method further includes: sequentially depositing an adhesive layer and a copper seed layer on the first diffusion barrier layer.
可选的，在本申请的一些实施例中，所述半导体制造方法还包括：于所述铜籽晶层上方形成铜填充层，以作为铜金属层。Optionally, in some embodiments of the present application, the semiconductor manufacturing method further includes: forming a copper filling layer on the copper seed layer as a copper metal layer.
可选的，在本申请的一些实施例中，所述铜填充层是通过ECP方法电镀于所述铜籽晶层上。Optionally, in some embodiments of the present application, the copper filling layer is electroplated on the copper seed layer by an ECP method.
可选的，在本申请的一些实施例中，对所述铜金属层进行的研磨是化学机械研磨，以使所述铜金属层呈现所述凹陷结构。Optionally, in some embodiments of the present application, the grinding of the copper metal layer is chemical mechanical grinding, so that the copper metal layer presents the concave structure.
可选的，在本申请的一些实施例中，所述第二扩散阻挡层经研磨后，与所述介质层等高。Optionally, in some embodiments of the present application, the second diffusion barrier layer is at the same height as the medium layer after being ground.
可选的，在本申请的一些实施例中，所述第一扩散阻挡层和所述第二扩散阻挡层中任一者的材料为以下材料其中一者：钽、氮化钽、钛、氮化钛、钨化钛、钨、氮化钨、钛-氮化钛、氮硅化钛、氮硅化钨、氮硅化钽、以及氮化硅。Optionally, in some embodiments of the present application, the material of any one of the first diffusion barrier layer and the second diffusion barrier layer is one of the following materials: tantalum, tantalum nitride, titanium, nitrogen titanium nitride, titanium tungsten nitride, tungsten, tungsten nitride, titanium-titanium nitride, titanium silicon nitride, tungsten silicon nitride, tantalum silicon nitride, and silicon nitride.
可选的，在本申请的一些实施例中，所述第一扩散阻挡层和所述第二扩散阻挡层中任一者的材料由氮化钽、钽和钌中至少二者组成。Optionally, in some embodiments of the present application, the material of any one of the first diffusion barrier layer and the second diffusion barrier layer consists of at least two of tantalum nitride, tantalum and ruthenium.
可选的，在本申请的一些实施例中，所述第一扩散阻挡层和所述第二扩散阻挡层中任一者的沉积是通过以下工艺中至少一者来完成：物理气相沉积、化学气相沉积、原子层沉积以及金属有机化学气相沉积。Optionally, in some embodiments of the present application, the deposition of any one of the first diffusion barrier layer and the second diffusion barrier layer is accomplished by at least one of the following processes: physical vapor deposition, chemical Vapor deposition, atomic layer deposition, and metal organic chemical vapor deposition.
可选的，在本申请的一些实施例中，所述第一扩散阻挡层和所述第二扩散阻挡层中任一者的厚度为0.5nm～200nm。Optionally, in some embodiments of the present application, the thickness of any one of the first diffusion barrier layer and the second diffusion barrier layer is 0.5 nm˜200 nm.
综上所述，本申请公开了一种铜扩散阻挡层结构及其制备方法，在铜线工艺中以带负偏压的工艺形式沉积金属阻挡层并覆盖在化学机械研磨后裸露的铜金属表面，与侧边及底部对铜金属形成“全包围结构”，能够完全防止孔洞现象，故可有效抑制因孔洞问题而导致的铜扩散现象，从而防止后续工艺中出现铜污染，保证了产品良率和器件性能。In summary, the present application discloses a copper diffusion barrier layer structure and its preparation method. In the copper wire process, the metal barrier layer is deposited in the form of a negative bias process and covered on the exposed copper metal surface after chemical mechanical polishing. , forming a "full surrounding structure" with the copper metal on the side and bottom, which can completely prevent the hole phenomenon, so it can effectively suppress the copper diffusion phenomenon caused by the hole problem, thereby preventing copper pollution in the subsequent process and ensuring the product yield. and device performance.
附图说明Description of drawings
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所下面针对需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments below. Obviously, the drawings in the following descriptions are only some implementations of the present application For example, those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1A～图1C分别为现有技术大马士革工艺中电镀铜工艺、研磨工艺以及阻挡层沉积工艺的示意图。1A to 1C are schematic diagrams of the copper electroplating process, the grinding process and the barrier layer deposition process in the prior art Damascus process, respectively.
图2A至图2G分别为本申请半导体制造方法中各阶段工艺的示意图。FIG. 2A to FIG. 2G are schematic diagrams of processes at various stages in the semiconductor manufacturing method of the present application.
图3为本申请离子化PVD原理的示意图。Fig. 3 is a schematic diagram of the ionization PVD principle of the present application.
图4为对应图2A至图2G半导体制造方法的流程图。FIG. 4 is a flow chart of the semiconductor manufacturing method corresponding to FIGS. 2A to 2G .
图中标号说明：Explanation of symbols in the figure:
1：电源；2：金属靶；3：氩气等离子体；4：射频电源；5：硅片；6：硅片片座；7：衬底电源；A1：铜籽晶层；A3：介质层；A2：铜扩散阻挡层；Cu：铜金属层；H1：孔洞；D1：介质层；D2：第一扩散阻挡层；D3：黏合层；D4：铜籽晶层；D5：第二扩散阻挡层；S302-S314：步骤。1: power supply; 2: metal target; 3: argon plasma; 4: radio frequency power supply; 5: silicon wafer; 6: silicon wafer holder; 7: substrate power supply; A1: copper seed layer; A3: dielectric layer ;A2: copper diffusion barrier layer; Cu: copper metal layer; H1: hole; D1: dielectric layer; D2: first diffusion barrier layer; D3: adhesion layer; D4: copper seed layer; D5: second diffusion barrier layer ; S302-S314: steps.
具体实施方式Detailed ways
以下实施例仅是用以举例说明而已，因为对于熟习此技艺者而言，在不脱离本申请内容的精神和范围内，当可作各种的更动与润饰，因此本申请内容的保护范围当视后附的权利要求所界定者为准。在通篇说明书与权利要求中，除非内容清楚指定，否则“一”以及“所述”的意义包括这一类叙述包括“一或至少一”所述组件或成分。此外，如本揭露所用，除非从特定上下文明显可见将复数个排除在外，否则单数冠词亦包括复数个组件或成分的叙述。而且，应用在此描述中与下述的全部权利要求中时，除非内容清楚指定，否则“在其中”的意思可包括“在其中”与“在其上”。在通篇说明书与权利要求所使用的用词，除有特别注明，通常具有每个用词使用在此领域中、在此揭露的内容中与特殊内容中的平常意义。某些用以描述本揭露的用词将于下或在此说明书的别处讨论，以提供从业人员在有关本揭露的描述上额外的引导。在通篇说明书的任何地方的例子，包括在此所讨论的任何用词的例子的使用，仅是用以举例说明，当然不限制本揭露或任何例示用词的范围与意义。同样地，本揭露并不限于此说明书中所提出的各种实施例。The following examples are only for illustration, because for those skilled in the art, without departing from the spirit and scope of the content of the application, various changes and modifications can be made, so the protection scope of the content of the application It shall prevail as defined in the appended claims. Throughout the specification and claims, unless the content clearly dictates otherwise, the meaning of "a" and "the" includes that such recitation includes "one or at least one" of said element or component. Furthermore, as used in the present disclosure, a singular article also includes the description of a plurality of components or ingredients unless it is obvious from the specific context that the plurality is excluded. Furthermore, as applied in this description and all the claims that follow, the meaning of "in" may include "in" and "on" unless the content clearly dictates otherwise. The terms used throughout the specification and claims, unless otherwise noted, generally have the ordinary meaning of each term as used in the art, in this disclosure and in the special context. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide practitioners with additional guidance in describing the disclosure. The use of examples anywhere throughout the specification, including examples of any terms discussed herein, is for illustration only and certainly does not limit the scope and meaning of the disclosure or any exemplified terms. Likewise, the present disclosure is not limited to the various embodiments presented in this specification.
在此所使用的用词“大约”、“约”或“近乎”应大体上意味在给定值或误差范围在20％以内，较佳是在10％以内。此外，在此所提供的数量可为近似的，因此意味着若无特别陈述，可用词“大约”、“约”或“近乎”加以表示。当一数量、浓度或其他数值或参数有指定的范围、较佳范围或表列出上下理想值的时，应视为特别揭露由任何上下限的数对或理想值所构成的所有范围，不论所述等范围是否分别揭露。举例而言，如揭露范围某长度为X公分到Y公分，应视为揭露长度为H公分且H可为X到Y中间的任意实数。The words "about", "approximately" or "approximately" as used herein shall generally mean within 20%, preferably within 10%, of a given value or error range. Furthermore, quantities provided herein may be approximate, thus meaning that the words "about", "about" or "approximately" may be used unless otherwise stated. When a quantity, concentration, or other value or parameter has a specified range, preferred range, or tabulated upper and lower ideal values, it shall be deemed to specifically disclose all ranges formed by any pair of upper and lower limits or ideal values, regardless of Whether the above scopes are disclosed separately. For example, if a certain length of the disclosed range is X centimeters to Y centimeters, it should be deemed that the disclosed length is H centimeters and H can be any real number between X and Y.
此外，“电(性)耦接”或“电(性)连接”在此是包括任何直接及间接的电气连接手段。举例而言，若文中描述一第一装置电性耦接于一第二装置，则代表所述第一装置可直接连接于所述第二装置，或通过其他装置或连接手段间接地连接至所述第二装置。另外，若描述关于电信号的传输、提供，熟习此技艺者应可了解电信号的传递过程中可能伴随衰减或其他非理想性的变化，但电信号传输或提供的来源与接收端若无特别叙明，实质上应视为同一信号。举例而言，若由电子电路的端点A传输(或提供)电信号S给电子电路的端点B，其中可能经过一晶体管开关的源极和漏极两端及/或可能的杂散电容而产生电压降，但此设计的目的若非刻意使用传输时产生的衰减或其他非理想性的变化而达到某些特定的技术效果，电信号S在电子电路的端点A与端点B应可视为实质上为同一信号。In addition, "electrical (sexual) coupling" or "electrical (sexual) connection" here includes any direct and indirect electrical connection means. For example, if it is described that a first device is electrically coupled to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means. Describe the second device. In addition, when describing the transmission and provision of electrical signals, those skilled in the art should be able to understand that the transmission of electrical signals may be accompanied by attenuation or other non-ideal changes, but if there is no special In essence, it should be regarded as the same signal. For example, if an electrical signal S is transmitted (or supplied) from terminal A of the electronic circuit to terminal B of the electronic circuit, which may be generated across the source and drain terminals of a transistor switch and/or possible stray capacitance Voltage drop, but if the purpose of this design is not to deliberately use attenuation or other non-ideal changes during transmission to achieve certain specific technical effects, the electrical signal S at the terminal A and terminal B of the electronic circuit should be regarded as substantially for the same signal.
可了解如在此所使用的用词“包括”、“具有”、“含有”等等，为开放性的用词，即意指包括但不限于。另外，本申请的任一实施例或权利要求不须达成本申请所揭露的全部目的或优势或特点。此外，摘要部分和标题仅是用来辅助专利文件搜寻，并非用来限制本申请的范畴。It can be understood that the terms "including", "having", "containing" and the like as used herein are open terms, meaning including but not limited to. In addition, any embodiment or claim of the present application does not need to achieve all the purposes or advantages or features disclosed in the present application. In addition, the abstract and titles are only used to aid in searching patent documents and are not intended to limit the scope of the application.
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向，而“内”和“外”则是针对装置的轮廓而言的。The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some, not all, embodiments of the application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application. In addition, it should be understood that the specific implementations described here are only used to illustrate and explain the present application, and are not intended to limit the present application. In this application, unless stated to the contrary, the used orientation words such as "up" and "down" usually refer to up and down in the actual use or working state of the device, specifically the direction of the drawing in the drawings , while "inside" and "outside" refer to the outline of the device.
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本申请具体实施例，其不应被视为限制本申请未在此详述的其它具体实施例。Please refer to the drawings in the accompanying drawings, wherein like reference numerals refer to like components. The following description is based on illustrated specific embodiments of the present application, which should not be construed as limiting other specific embodiments of the present application that are not described in detail here.
铜对于晶体管是有害的，所以采用铜连线技术时，必须防止铜扩散到晶体管。因此在“大马士革”技术中，在填充铜之前，会采用离子化物理气相淀积(I-PVD)先淀积一层扩散阻挡层。本申请提供半导体制造方法中的一种铜扩散阻挡层结构及其制备方法，解决化学机械研磨铜线工艺中存在的碟型的凹陷结构问题。特别注意的是，碟型结构形成的原因是介质层与铜技术层不在同一水平面上，化学机械研磨工艺中，由于金属铜的研磨速率比介质层快，结构表面平坦化后介质层与铜金属层非等高(不处于同一水平面)，而呈现碟型结构。此外，在化学机械研磨后的铜表面，通过以带负偏压的形式沉积一层金属阻挡层，充分覆盖铜金属表面，保证“碟型结构”角落处的充分沉积，藉此避免现有技术中沉积铜扩散阻挡层时在角落处形成孔洞结构。最后，利用化学机械研磨平坦化阻挡层表面并研磨至介质层，完成整体半导体制造方法。需要注意的是，在后续的说明中，本申请主要以铜作为沉积的金属，但本申请实际上也可应用其他金属。Copper is detrimental to transistors, so when using copper wiring technology, it is necessary to prevent copper from diffusing into transistors. Therefore, in the "Damascus" technology, before the copper is filled, a diffusion barrier layer is first deposited by ionized physical vapor deposition (I-PVD). The present application provides a copper diffusion barrier layer structure and a preparation method thereof in a semiconductor manufacturing method, which solves the problem of a dish-shaped concave structure existing in a chemical mechanical polishing copper wire process. It should be noted that the disc structure is formed because the dielectric layer and the copper technology layer are not on the same level. In the chemical mechanical polishing process, since the grinding rate of metal copper is faster than that of the dielectric layer, the dielectric layer and the copper metal will The layers are not of the same height (not at the same level), but present a dish-shaped structure. In addition, on the copper surface after chemical mechanical polishing, a metal barrier layer is deposited in the form of a negative bias to fully cover the copper metal surface to ensure sufficient deposition at the corners of the "disk structure", thereby avoiding the existing technology. Void structures are formed at the corners when depositing the copper diffusion barrier layer. Finally, chemical mechanical polishing is used to planarize the surface of the barrier layer and grind down to the dielectric layer to complete the overall semiconductor manufacturing method. It should be noted that, in the following description, the present application mainly uses copper as the deposited metal, but the present application can also be applied to other metals.
本申请的细部作法说明如下。The detailed method of this application is described as follows.
请参考图2A至图2G，图2A至图2G分别为本申请半导体制造方法(或称大马士革工艺)中各阶段工艺的示意图，详细说明如下。Please refer to FIG. 2A to FIG. 2G . FIG. 2A to FIG. 2G are schematic diagrams of each stage of the semiconductor manufacturing method (or Damascus process) of the present application, and the details are as follows.
首先，与现有技术中的步骤一样，如图2A所示先沉积介质层；接着如图2B所示，对沉积的介质层进行刻蚀，开出沟槽；接下来，如图2C所示，于介质层D1上依序沉积第一扩散阻挡层(diffusion barrier)D2、黏合层D3以及铜籽晶层D4，其中第一扩散阻挡层D2可通过物理气相沉积(physical vapor deposition，PVD)、化学气相沉积(Chemical VaporDeposition,CVD)、原子层沉积(Atomic Layer Deposition,ALD)以及金属有机化学气相沉积(metalorganic chemical vapor deposition,MOCVD)中至少一者来完成，且厚度可为0.5nm～200nm，但本申请不以此为限。此外，第一扩散阻挡层D2可以是刻蚀终止层或/和CMP终止层，如氮化硅(SiN)或碳氧化硅(SiCO)。铜籽晶层D4可通过PVD或ALD方法沉积，其厚度为0.5nm～1000nm。First, as in the steps in the prior art, a dielectric layer is first deposited as shown in Figure 2A; then, as shown in Figure 2B, the deposited dielectric layer is etched to open a trench; next, as shown in Figure 2C , sequentially depositing a first diffusion barrier layer (diffusion barrier) D2, an adhesive layer D3 and a copper seed layer D4 on the dielectric layer D1, wherein the first diffusion barrier layer D2 can be deposited by physical vapor deposition (physical vapor deposition, PVD), At least one of chemical vapor deposition (Chemical VaporDeposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD) and metal organic chemical vapor deposition (metalorganic chemical vapor deposition, MOCVD), and the thickness can be 0.5nm ~ 200nm, But the present application is not limited thereto. In addition, the first diffusion barrier layer D2 may be an etch stop layer or/and a CMP stop layer, such as silicon nitride (SiN) or silicon oxycarbide (SiCO). The copper seed layer D4 can be deposited by PVD or ALD method, and its thickness is 0.5nm˜1000nm.
下一步，如图2D所示，对铜籽晶层D4进行电镀铜工艺，例如用ECP方法电镀且其厚度可为200nm～3000nm，或通过化学方法进行铜沉积于铜籽晶层D4上方形成铜填充层。由于铜填充层只沉积在沟槽中的铜籽晶层D4上且两者材质相仿，为简洁之故，图2D及后续图示以铜金属层Cu来统称铜籽晶层D4和铜填充层。接下来，如图2E所示，可进一步利用高选择性的铜化学机械研磨液(Cu-CMP slurry)对图2D中沉积后突起的铜金属层Cu进行研磨，使之呈现碟型结构。在本申请中，“化学机械研磨”一词是指同时包括化学研磨和机械研磨，因为CMP化学机械研磨是综合了化学研磨和机械研磨，且对于金属材料的研磨都会一并采用化学作用和机械研磨。举例来说，会先用氧化剂把金属表面弄成硬度低的金属氧化物，然后再用机械力将金属氧化物磨掉。之后，在图2F中，通过以带负偏压的沉积方式，在铜线工艺中化学机械研磨后的铜金属层Cu表面沉积第二扩散阻挡层D5，从而充分覆盖裸露的铜金属表面，其中第二扩散阻挡层D5是一种铜扩散阻挡层，可通过物理气相沉积来完成，但本申请不以此为限。而由于所采用的是带负偏压的沉积方式，故由于介质层与铜金属层研磨速率不同而产生的碟型结构不会出现现有技术所遭遇的孔洞问题。In the next step, as shown in FIG. 2D , the electroplating copper process is performed on the copper seed layer D4, for example, the ECP method is used for electroplating and its thickness can be 200 nm to 3000 nm, or copper is deposited on the copper seed layer D4 by a chemical method to form copper. fill layer. Since the copper filling layer is only deposited on the copper seed layer D4 in the trench and the materials of the two are similar, for the sake of simplicity, the copper metal layer Cu is used to collectively refer to the copper seed layer D4 and the copper filling layer in FIG. 2D . Next, as shown in FIG. 2E , the copper metal layer Cu raised after deposition in FIG. 2D can be further polished with a highly selective copper chemical mechanical polishing fluid (Cu-CMP slurry) to make it present a dish-shaped structure. In this application, the term "chemical mechanical polishing" refers to both chemical polishing and mechanical polishing, because CMP chemical mechanical polishing is a combination of chemical polishing and mechanical polishing, and both chemical and mechanical polishing are used for the grinding of metal materials. grind. For example, an oxidizing agent is used to turn the metal surface into metal oxides with low hardness, and then mechanical force is used to grind the metal oxides away. Afterwards, in FIG. 2F , the second diffusion barrier layer D5 is deposited on the surface of the copper metal layer Cu after chemical mechanical grinding in the copper wire process by depositing with a negative bias, so as to fully cover the bare copper metal surface, wherein The second diffusion barrier layer D5 is a copper diffusion barrier layer and can be formed by physical vapor deposition, but the present application is not limited thereto. And because the deposition method with negative bias is adopted, the disc structure produced by the different grinding rates of the dielectric layer and the copper metal layer does not have the hole problem encountered in the prior art.
最后，如图2G所示，对图2F中沉积后突起的第二扩散阻挡层D5进行研磨，使之平坦，更确切来说，使第二扩散阻挡层D5与介质层D1为等高。相似于第一扩散阻挡层D2，第二扩散阻挡层D5可通过物理气相沉积、化学气相沉积、原子层沉积或金属有机化学气相沉积来完成，且厚度可为0.5nm～200nm，但本申请不以此为限。Finally, as shown in FIG. 2G , grind the protruding second diffusion barrier layer D5 in FIG. 2F to make it flat, more precisely, make the second diffusion barrier layer D5 and the dielectric layer D1 have the same height. Similar to the first diffusion barrier layer D2, the second diffusion barrier layer D5 can be completed by physical vapor deposition, chemical vapor deposition, atomic layer deposition or metal organic chemical vapor deposition, and the thickness can be 0.5 nm to 200 nm, but the present application does not This is the limit.
第一扩散阻挡层D2和第二扩散阻挡层D5的材料可包括但不受限于：钽(Ta)、氮化钽(TaN)、钛(Ti)、氮化钛(TiN)、钨化钛(TiW)、钨(W)、氮化钨(WN)、钛-氮化钛(Ti-TiN)、氮硅化钛(TiSiN)、氮硅化钨(WSiN)、氮硅化钽(TaSiN)、以及氮化硅(silicon nitrid)。在一些实施例中，第一扩散阻挡层D2和第二扩散阻挡层D5的材料可由氮化钽、钽和钌中至少二者组成。The materials of the first diffusion barrier layer D2 and the second diffusion barrier layer D5 may include but not limited to: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tungsten (W), tungsten nitride (WN), titanium-titanium nitride (Ti-TiN), titanium silicide nitride (TiSiN), tungsten silicide nitride (WSiN), tantalum silicide nitride (TaSiN), and nitrogen silicide silicon (silicon nitrid). In some embodiments, the material of the first diffusion barrier layer D2 and the second diffusion barrier layer D5 may consist of at least two of tantalum nitride, tantalum and ruthenium.
关于使用负偏压的形式沉积金属阻挡层，请参考图3，其为本申请离子化PVD原理的示意图。首先，将氩气通入工艺腔室，金属靶2连接电源1，使得在金属靶与硅片之间形成氩气等离子体3。氩气离子轰击金属靶，将金属原子从靶上溅射出来，淀积在硅片5上。在电感耦合式离子化PVD工艺中，在氩气等离子体周围增加了一个金属线圈，并连接射频电源4，以通过电感耦合增加了等离子体的密度，从而增加金属原子的离化率。硅片片座6连接衬底电源7，可使硅片表面带负偏压。在负偏压的吸引下，正金属离子会以较垂直的方向淀积到硅片5上，从而更好地覆盖沟槽的底部和侧壁。Regarding the use of negative bias to deposit the metal barrier layer, please refer to FIG. 3 , which is a schematic diagram of the ionization PVD principle of the present application. First, argon gas is introduced into the process chamber, and the
总的来说，本申请公开了一种具备防止铜扩散阻挡层结构的半导体制造方法，在铜线工艺中以带负偏压的工艺形式沉积金属阻挡层并覆盖在化学机械研磨后裸露的铜金属表面，与侧边及底部对铜金属形成“全包围结构”，能够完全防止孔洞现象，故可有效抑制因孔洞问题而导致的铜扩散现象，从而防止后续工艺中出现铜污染，保证了产品良率和器件性能。In general, the present application discloses a semiconductor manufacturing method with a copper diffusion barrier structure, in which a metal barrier layer is deposited in a negatively biased process in a copper wire process and covers exposed copper after chemical mechanical polishing The metal surface forms a "full surrounding structure" with the copper metal on the side and bottom, which can completely prevent the hole phenomenon, so it can effectively suppress the copper diffusion phenomenon caused by the hole problem, thereby preventing copper pollution in the subsequent process and ensuring the quality of the product. yield and device performance.
请参考图4，其为对应图2A至图2G半导体制造方法的流程图，包括以下步骤:Please refer to FIG. 4, which is a flowchart of the semiconductor manufacturing method corresponding to FIG. 2A to FIG. 2G, including the following steps:
步骤S302：沉积介质层；Step S302: depositing a dielectric layer;
步骤S304：对沉积的介质层进行刻蚀，开出沟槽；Step S304: Etching the deposited dielectric layer to open a trench;
步骤S306：于沟槽依序沉积第一扩散阻挡层、黏合层以及铜籽晶层；Step S306: sequentially depositing a first diffusion barrier layer, an adhesive layer, and a copper seed layer in the trench;
步骤S308：于铜籽晶层上方形成铜填充层，以作为铜金属层；Step S308: forming a copper filling layer on the copper seed layer as a copper metal layer;
步骤S310：对沉积后突起的铜金属层进行研磨，使之呈现碟型结构；Step S310: Grinding the protruding copper metal layer after deposition to make it present a dish-shaped structure;
步骤S312：以带负偏压的沉积方式，在铜金属层表面沉积第二扩散阻挡层；Step S312: Depositing a second diffusion barrier layer on the surface of the copper metal layer in a deposition manner with a negative bias;
步骤S314：对第二扩散阻挡层进行研磨，使第二扩散阻挡层与介质层等高。Step S314: Grinding the second diffusion barrier layer so that the height of the second diffusion barrier layer is equal to that of the dielectric layer.
请注意，只要能达到相同/相仿功效，本申请并不限制必须完全遵照上述步骤，例如，一些额外的步骤可插入其中，且有的步骤在特定条件下可予以省略。Please note that as long as the same/similar effect can be achieved, the present application does not limit the above-mentioned steps to be completely followed, for example, some additional steps can be inserted therein, and some steps can be omitted under certain conditions.
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。上述所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得所有其他实施例，除本申请实施例提到的与本申请实施例方案一致的此类设计，都属于本申请保护的范围。In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments. The embodiments described above are only some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work, except for such designs mentioned in the embodiments of this application that are consistent with the solutions of the embodiments of this application, all belong to this application scope of protection.
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想。本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换，而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。The above is a detailed introduction to the embodiments of the present application. In this paper, specific examples are used to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features, and these modifications or replacements do not deviate from the essence of the corresponding technical solutions The scope of the technical solutions of each embodiment of the application.
综上，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。In summary, although the present application has disclosed the above with preferred embodiments, the above preferred embodiments are not intended to limit the present application, and those skilled in the art can make various modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is subject to the scope defined by the claims.
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