CN116113309A

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Info

Publication number: CN116113309A
Application number: CN202310388847.0A
Authority: CN
Inventors: 徐跃; 刘源
Original assignee: Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University of Posts and Telecommunications
Priority date: 2023-04-13
Filing date: 2023-04-13
Publication date: 2023-05-12
Anticipated expiration: 2043-04-13
Also published as: CN116113309B

Abstract

Translated fromChinese

本发明公开了一种采用双保护环的低失调霍尔器件及其使用方法，其中一种采用双保护环的低失调霍尔器件包括横向层组，所述横向层组包括P型衬底、设置于P型衬底中心区域的N+埋层和设置于N+埋层顶部中心区域的P‑埋层，P‑埋层上方设置有N阱有源区，N+埋层和P‑埋层形成横向保护环；侧围层组，所述侧围层组包括设置于N阱有源区外侧的P型外延层，所述P型外延层中设置有与N+埋层顶部连接的高压N阱，所述P型外延层中设置有与P型衬底顶部连接的高压P阱，高压P阱设置于高压N阱外侧，P型外延层和N+埋层形成纵向保护环；本发明的霍尔器件具有低失调、高灵敏度和强抗干扰能力。

The invention discloses a low offset Hall device using double guard rings and a method for using the same, wherein a low offset Hall device using double guard rings includes a lateral layer group, and the lateral layer group includes a P-type substrate, The N+ buried layer arranged in the central region of the P-type substrate and the P-buried layer arranged in the top central region of the N+ buried layer, the N well active region is arranged above the P-buried layer, and the N+ buried layer and the P-buried layer form a lateral Guard ring; side surrounding layer group, the side surrounding layer group includes a P-type epitaxial layer arranged outside the N well active region, and a high-voltage N well connected to the top of the N+ buried layer is arranged in the P-type epitaxial layer, so The P-type epitaxial layer is provided with a high-voltage P well connected to the top of the P-type substrate, the high-voltage P well is arranged outside the high-voltage N well, and the P-type epitaxial layer and the N+ buried layer form a longitudinal guard ring; the Hall device of the present invention has Low offset, high sensitivity and strong anti-interference ability.

Description

Translated fromChinese

一种采用双保护环的低失调霍尔器件及其使用方法A low-offset Hall device using double guard rings and its application method

技术领域technical field

本发明涉及传感器技术领域，尤其是一种采用双保护环的低失调霍尔器件及其使用方法。The invention relates to the technical field of sensors, in particular to a low-offset Hall device using double guard rings and its application method.

背景技术Background technique

近年来霍尔传感器由于具有成本低、功耗低、集成度高等优点，成为了一种主流的磁性传感器。其能够检测交、直流磁场并产生与磁场强度成比例的输出电信号，被广泛用于汽车控制、电池充电器、无刷动直流电机、功率计和光伏逆变器等领域。目前，霍尔传感器正朝着高线性度、高精度和宽带的方向发展，对霍尔器件的高灵敏度和低失调特性提出了更高的要求。In recent years, the Hall sensor has become a mainstream magnetic sensor due to its advantages of low cost, low power consumption, and high integration. It can detect AC and DC magnetic fields and generate an output electrical signal proportional to the strength of the magnetic field. It is widely used in automotive control, battery chargers, brushless DC motors, power meters, and photovoltaic inverters. At present, the Hall sensor is developing towards the direction of high linearity, high precision and broadband, which puts forward higher requirements for the high sensitivity and low offset characteristics of the Hall device.

硅基霍尔器件凭借低成本、较高的温度稳定性以及与标准CMOS工艺良好的兼容性而得到最广泛的研究与应用。然而集成的CMOS霍尔器件由于采用掺杂浓度较高的N阱作为有源区，增大了电离杂质散射对载流子运动的影响，降低了霍尔器件的迁移率，导致霍尔器件的灵敏度比较低。另一方面，CMOS工艺下的N阱杂质浓度分布不均、封装应力、器件接触孔和N阱之间掩膜版的对准误差造成霍尔器件输出失调非常大，失调电压可达到几毫伏至几十毫伏，将微弱的霍尔信号淹没。除此之外，传统霍尔器件通常仅采用P阱环对有源区进行隔离，无法克服电路中高频信号和衬底噪声的干扰，导致霍尔器件的抗干扰能力比较差，使硅基霍尔器件无法满足低磁场、高分辨率的工作要求，因此如何减小霍尔器件失调、提高灵敏度和信噪比是硅基霍尔传感器急需解决的关键性技术问题。Silicon-based Hall devices have been the most widely researched and applied due to their low cost, high temperature stability, and good compatibility with standard CMOS processes. However, because the integrated CMOS Hall device uses the N-well with higher doping concentration as the active region, the impact of ionized impurity scattering on the movement of carriers is increased, the mobility of the Hall device is reduced, and the Hall device's The sensitivity is relatively low. On the other hand, the uneven distribution of impurity concentration in the N-well under the CMOS process, the packaging stress, and the alignment error of the mask between the device contact hole and the N-well cause a very large output offset of the Hall device, and the offset voltage can reach several millivolts. To tens of millivolts, the weak Hall signal will be submerged. In addition, traditional Hall devices usually only use P-well rings to isolate the active area, which cannot overcome the interference of high-frequency signals and substrate noise in the circuit, resulting in poor anti-interference ability of Hall devices, making silicon-based Hall devices Hall devices cannot meet the working requirements of low magnetic field and high resolution. Therefore, how to reduce the offset of Hall devices, improve sensitivity and signal-to-noise ratio is a key technical problem that needs to be solved urgently for silicon-based Hall sensors.

发明内容Contents of the invention

本部分的目的在于概述本发明的实施例的一些方面以及简要介绍一些较佳实施例，在本部分以及本申请的说明书摘要和发明名称中可能会做些简化或省略以避免使本部分、说明书摘要和发明名称的目的模糊，而这种简化或省略不能用于限制本发明的范围。The purpose of this section is to summarize some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and in the abstract and title of the application to avoid making this section, the specification The abstract and titles are intended to be vague, and such simplifications or omissions should not be used to limit the scope of the invention.

鉴于上述和/或现有技术中所存在的问题，提出了本发明。In view of the problems mentioned above and/or in the prior art, the present invention is proposed.

因此，本发明所要解决的技术问题是现有CMOS工艺下霍尔器件的失调大、灵敏度低、抗噪声和干扰能力差的问题。Therefore, the technical problem to be solved by the present invention is the problems of large offset, low sensitivity, and poor anti-noise and interference ability of the Hall device under the existing CMOS technology.

为解决上述技术问题，本发明提供如下技术方案：一种采用双保护环的低失调霍尔器件，包括，In order to solve the above technical problems, the present invention provides the following technical solutions: a low offset Hall device using double guard rings, comprising,

横向层组，所述横向层组包括P型衬底、设置于P型衬底中心区域的N+埋层和设置于N+埋层顶部中心区域的P-埋层，P-埋层上方设置有N阱有源区，N+埋层和P-埋层形成横向保护环；The lateral layer group, the lateral layer group includes a P-type substrate, an N+ buried layer arranged in the central region of the P-type substrate, and a P-buried layer arranged in the top central region of the N+ buried layer, and an N+ buried layer is arranged above the P-buried layer In the well active region, the N+ buried layer and the P- buried layer form a lateral guard ring;

侧围层组，所述侧围层组包括设置于N阱有源区外侧的P型外延层，所述P型外延层中设置有与N+埋层顶部连接的高压N阱，所述P型外延层中设置有与P型衬底顶部连接的高压P阱，高压P阱设置于高压N阱外侧，P型外延层和高压N阱形成纵向保护环。The side surrounding layer group, the side surrounding layer group includes a P-type epitaxial layer arranged outside the N well active region, the P type epitaxial layer is provided with a high-voltage N well connected to the top of the N+ buried layer, and the P type A high-voltage P-well connected to the top of the P-type substrate is arranged in the epitaxial layer, and the high-voltage P-well is arranged outside the high-voltage N-well, and the P-type epitaxial layer and the high-voltage N-well form a longitudinal protection ring.

作为本发明所述采用双保护环的低失调霍尔器件的一种优选方案，其中：所述侧围层组为对称结构，关于第一对称轴对称；所述N阱有源区为对称结构，关于第二对称轴对称，所述第一对称轴和第二对称轴重合。As a preferred solution of the low-offset Hall device using double guard rings in the present invention, wherein: the side surrounding layer group is a symmetrical structure, which is symmetrical about the first axis of symmetry; the N-well active region is a symmetrical structure , symmetric about a second axis of symmetry, the first axis of symmetry and the second axis of symmetry coincide.

作为本发明所述采用双保护环的低失调霍尔器件的一种优选方案，其中：所述N阱有源区的边缘均匀分布设置有第一N+区，第一N+区关于第二对称轴对称，第一N+区平行于N阱有源区的边缘放置。As a preferred solution of the low-offset Hall device using double guard rings in the present invention, wherein: the edge of the N-well active region is evenly distributed with first N+ regions, and the first N+ regions are about the second symmetry axis Symmetrically, the first N+ region is placed parallel to the edge of the N-well active region.

作为本发明所述采用双保护环的低失调霍尔器件的一种优选方案，其中：四个所述第一N+区上均设置有金属，形成四个偏置电极。As a preferred solution of the low-offset Hall device using double guard rings in the present invention, metal is provided on each of the four first N+ regions to form four bias electrodes.

作为本发明所述采用双保护环的低失调霍尔器件的一种优选方案，其中：相邻的所述第一N+区中心的N阱有源区中设置有第二N+区，第二N+区关于第二对称轴对称，第二N+区平行于N阱有源区的边缘放置；As a preferred solution of the low offset Hall device using double guard rings in the present invention, wherein: a second N+ region is arranged in the N well active region at the center of the adjacent first N+ region, and the second N+ The region is symmetrical about the second axis of symmetry, and the second N+ region is placed parallel to the edge of the N-well active region;

第一N+区尺寸大于第二N+区。The size of the first N+ region is larger than that of the second N+ region.

作为本发明所述采用双保护环的低失调霍尔器件的一种优选方案，其中：四个所述第二N+区上均设置有金属，形成四个输出电极；As a preferred solution of the low-offset Hall device using double guard rings in the present invention, wherein: the four second N+ regions are all provided with metal to form four output electrodes;

对角的两个输出电极通过金属连线短接。The two output electrodes at the opposite corners are short-circuited through metal wires.

作为本发明所述采用双保护环的低失调霍尔器件的一种优选方案，其中：所述高压N阱表面设置有第三N+区，所述第三N+区上设置有金属，形成第一接触电极。As a preferred solution of the low-offset Hall device using double guard rings in the present invention, a third N+ region is arranged on the surface of the high-voltage N well, and metal is arranged on the third N+ region to form a first contact electrodes.

作为本发明所述采用双保护环的低失调霍尔器件的一种优选方案，其中：所述N阱有源区上方非电极部分覆盖有第一P+区；As a preferred solution of the low-offset Hall device using double guard rings in the present invention, wherein: the non-electrode part above the N-well active region is covered with a first P+ region;

所述高压P阱表面设有第二P+区，所述第二P+区上设置有金属，形成第二接触电极。A second P+ region is provided on the surface of the high-voltage P well, and metal is arranged on the second P+ region to form a second contact electrode.

作为本发明所述采用双保护环的低失调霍尔器件的一种优选方案，其中：在所述第一N+区和第三N+区之间、第一N+区和第一P+区、第三N+区和第二P+区之间设有隔离浅沟槽。As a preferred solution of the low offset Hall device using double guard rings in the present invention, wherein: between the first N+ region and the third N+ region, the first N+ region and the first P+ region, the third An isolation shallow trench is provided between the N+ region and the second P+ region.

本发明还公开了一种前述采用双保护环的低失调霍尔器件的使用方法：The present invention also discloses a method of using the aforementioned low-offset Hall device using double guard rings:

对两个相对的偏置电极输入大小相等、方向相反的电流或电压偏置信号；Input current or voltage bias signals of equal magnitude and opposite directions to two opposite bias electrodes;

另外两个相对的偏置电极接地；The other two opposite bias electrodes are grounded;

输出电极之间输出霍尔电流或霍尔电压信号；Output Hall current or Hall voltage signal between the output electrodes;

第一接触电极接高电平；第二接触电极接地。The first contact electrode is connected to high level; the second contact electrode is connected to ground.

本发明的有益效果：本发明的霍尔器件具有低失调、高灵敏度和强抗干扰能力。Beneficial effects of the present invention: the Hall device of the present invention has low offset, high sensitivity and strong anti-interference ability.

附图说明Description of drawings

为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort. in:

图1为本发明提供的一种实施例所述的采用双保护环的低失调霍尔器件的俯视示意图；FIG. 1 is a schematic top view of a low-offset Hall device using double guard rings according to an embodiment of the present invention;

图2为本发明提供的一种实施例所述的采用双保护环的低失调霍尔器件中N阱有源区与外轮廓的相对位置示意图；2 is a schematic diagram of the relative position of the N-well active region and the outer contour in the low-offset Hall device using double guard rings according to an embodiment of the present invention;

图3为本发明提供的一种实施例所述的采用双保护环的低失调霍尔器件的剖面结构示意图；3 is a schematic cross-sectional structure diagram of a low-offset Hall device using double guard rings according to an embodiment of the present invention;

图4为本发明提供的一种实施例所述的采用双保护环的低失调霍尔器件的双保护环结构示意图；FIG. 4 is a schematic diagram of a double guard ring structure of a low offset Hall device using double guard rings according to an embodiment of the present invention;

图5为本发明提供的一种实施例所述的采用双保护环的低失调霍尔器件的工作偏置结构示意图；FIG. 5 is a schematic diagram of a working bias structure of a low-offset Hall device using double guard rings according to an embodiment of the present invention;

图6为本发明与传统十字形霍尔器件结构进行三维仿真得到的输出失调对比图。FIG. 6 is a comparison diagram of output offset obtained by three-dimensional simulation between the present invention and the traditional cross-shaped Hall device structure.

具体实施方式Detailed ways

为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合说明书附图对本发明的具体实施方式做详细的说明。In order to make the above objects, features and advantages of the present invention more obvious and comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

再其次，此处所称的“一个实施例”或“实施例”是指可包含于本发明至少一个实现方式中的特定特征、结构或特性。在本说明书中不同地方出现的“在一个实施例中”并非均指同一个实施例，也不是单独的或选择性的与其他实施例互相排斥的实施例。Second, "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. "In one embodiment" appearing in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments.

实施例1Example 1

参照图1和图3为本发明提供的一种实施例所述的采用双保护环的低失调霍尔器件的俯视示意图和剖面结构示意图，本实施例提供了一种采用双保护环的低失调霍尔器件，包括，Referring to FIG. 1 and FIG. 3, it is a schematic top view and a schematic cross-sectional structure diagram of a low offset Hall device using double guard rings according to an embodiment of the present invention. This embodiment provides a low offset Hall device using double guard rings. Hall devices, including,

横向层组100，横向层组100包括P型衬底101、设置于P型衬底101中心区域的N+埋层102和设置于N+埋层102顶部中心区域的P-埋层103，P-埋层103上方设置有N阱有源区104，N+埋层102和P-埋层103形成横向保护环；Thelateral layer group 100, thelateral layer group 100 includes a P-type substrate 101, an N+ buriedlayer 102 arranged in the central region of the P-type substrate 101, and a P-buriedlayer 103 arranged in the top central region of the N+ buriedlayer 102, the P-buried layer An N wellactive region 104 is arranged above thelayer 103, and the N+ buriedlayer 102 and the P- buriedlayer 103 form a lateral protection ring;

N+埋层102处于P型衬底101中心上方，N+埋层102部分嵌于P型衬底101中。The N+ buriedlayer 102 is above the center of the P-type substrate 101 , and the N+ buriedlayer 102 is partially embedded in the P-type substrate 101 .

具体的，P型衬底101可以为半导体硅材料，Specifically, the P-type substrate 101 may be a semiconductor silicon material,

侧围层组200，侧围层组200包括设置于N阱有源区104外侧的P型外延层201，P型外延层201中设置有与N+埋层102顶部连接的高压N阱202，P型外延层201中设置有与P型衬底101顶部连接的高压P阱203，高压P阱203设置于高压N阱202外侧，P型外延层201和高压N阱202形成纵向保护环。The side surroundinglayer group 200, the side surroundinglayer group 200 includes the Ptype epitaxial layer 201 arranged outside the N wellactive region 104, the Ptype epitaxial layer 201 is provided with a high voltage N well 202 connected to the top of the N+ buriedlayer 102, P A high-voltage P-well 203 connected to the top of the P-type substrate 101 is arranged in theepitaxial layer 201. The high-voltage P-well 203 is arranged outside the high-voltage N-well 202. The P-type epitaxial layer 201 and the high-voltage N-well 202 form a vertical protection ring.

高压P阱203和高压N阱202之间间隔设置有一定厚度的P型外延层201。A P-type epitaxial layer 201 with a certain thickness is disposed between the high-voltage P-well 203 and the high-voltage N-well 202 .

需要说明的是，本发明所提出的双保护环，分别是纵向保护环和横向保护环，参照图4。横向保护环是N+埋层102和P-埋层103之间形成的PN结。纵向保护环是在高压N阱202和P型外延层201之间形成的PN结。It should be noted that the double guard rings proposed in the present invention are respectively a longitudinal guard ring and a transverse guard ring, as shown in FIG. 4 . The lateral guard ring is a PN junction formed between the N+ buriedlayer 102 and the P− buriedlayer 103 . The vertical guard ring is a PN junction formed between the high voltage N well 202 and the P-type epitaxial layer 201 .

进一步的，参照图2，侧围层组200为对称结构，关于第一对称轴Y1对称；N阱有源区104为对称结构，关于第二对称轴Y2对称，第一对称轴Y1和第二对称轴Y2重合。Further, referring to FIG. 2 , the lateral surroundinglayer group 200 has a symmetrical structure, which is symmetrical about the first axis of symmetry Y1; the N-wellactive region 104 has a symmetrical structure, and is symmetrical about the second axis of symmetry Y2, and the first axis of symmetry Y1 and the second The axis of symmetry Y2 coincides.

具体的，参照图2（a），所述正方形侧环组件200关于第一对称轴Y1对称轴对称，所述切角正方形N阱有源区104关于第二对称轴Y2对称，所述第一N+区104a均匀分布在N阱有源区104边缘，关于第二对称轴Y2对称，所述第二N+区104b均匀分布在N阱有源区104边缘，关于第二对称轴Y2对称，第一N+区104a和第二N+区104b平行于N阱有源区104边缘放置。第二N+区104b分布在相邻两个第一N+区中心的N阱有源区104上。Specifically, referring to FIG. 2( a ), the squareside ring assembly 200 is axisymmetric about the first axis of symmetry Y1, theactive region 104 of the corner-cut square N-well is symmetrical about the second axis of symmetry Y2, and the first TheN+ region 104a is evenly distributed on the edge of the N-wellactive region 104 and is symmetrical about the second symmetry axis Y2, and thesecond N+ region 104b is evenly distributed on the edge of the N-wellactive region 104 and is symmetrical about the second symmetry axis Y2. TheN+ region 104 a and thesecond N+ region 104 b are arranged parallel to the edge of the N-wellactive region 104 . Thesecond N+ region 104b is distributed on the N-wellactive region 104 at the center of two adjacent first N+ regions.

参照图2（b），所述正八边形侧环组件200关于第一对称轴Y1对称轴对称，所述切角菱形N阱有源区104关于第二对称轴Y2对称，所述第一N+区104a均匀分布在N阱有源区104边缘，关于第二对称轴Y2对称，所述第二N+区104b均匀分布在N阱有源区104边缘，关于第二对称轴Y2对称，第一N+区104a和第二N+区104b平行于N阱有源区104边缘放置。第二N+区104b分布在相邻两个第一N+区中心的N阱有源区104上。Referring to FIG. 2( b ), the regular octagonalside ring assembly 200 is axisymmetric about the first axis of symmetry Y1, theactive region 104 of the corner-cut diamond-shaped N-well is symmetrical about the second axis of symmetry Y2, and the first N+ Theregion 104a is evenly distributed on the edge of the N-wellactive region 104, and is symmetrical about the second symmetry axis Y2, and thesecond N+ region 104b is evenly distributed on the edge of the N-wellactive region 104, and is symmetrical about the second symmetry axis Y2, and the first N+ Theregion 104a and thesecond N+ region 104b are placed parallel to the edge of the N-wellactive region 104 . Thesecond N+ region 104b is distributed on the N-wellactive region 104 at the center of two adjacent first N+ regions.

参照图2（c），所述正方形侧环组件200关于第一对称轴Y1对称轴对称，所述切角菱形N阱有源区104关于第二对称轴Y2对称，所述第一N+区104a均匀分布在N阱有源区104边缘，关于第二对称轴Y2对称，所述第二N+区104b均匀分布在N阱有源区104边缘，关于第二对称轴Y2对称，第一N+区104a和第二N+区104b平行于N阱有源区104边缘放置。第二N+区104b分布在相邻两个第一N+区中心的N阱有源区104上。Referring to FIG. 2(c), the squareside ring assembly 200 is axisymmetric about the first axis of symmetry Y1, theactive region 104 of the corner-cut diamond-shaped N-well is symmetrical about the second axis of symmetry Y2, and thefirst N+ region 104a Evenly distributed on the edge of the N-wellactive region 104, symmetrical about the second symmetry axis Y2, thesecond N+ region 104b is evenly distributed on the edge of the N-wellactive region 104, symmetrical about the second symmetry axis Y2, thefirst N+ region 104a and thesecond N+ region 104b are placed parallel to the edge of the N wellactive region 104 . Thesecond N+ region 104b is distributed on the N-wellactive region 104 at the center of two adjacent first N+ regions.

参照图2（d），所述圆形侧环组件200关于第一对称轴Y1对称轴对称，所述切角菱形N阱有源区104关于第二对称轴Y2对称，所述第一N+区104a均匀分布在N阱有源区104边缘，关于第二对称轴Y2对称，所述第二N+区104b均匀分布在N阱有源区104边缘，关于第二对称轴Y2对称，第一N+区104a和第二N+区104b平行于N阱有源区104边缘放置。第二N+区104b分布在相邻两个第一N+区中心的N阱有源区104上。Referring to FIG. 2( d ), the circularside ring component 200 is axisymmetric about the first axis of symmetry Y1, theactive region 104 of the cut-off diamond-shaped N-well is symmetrical about the second axis of symmetry Y2, and thefirst N+ region 104a is evenly distributed on the edge of the N-wellactive region 104, symmetrical about the second symmetry axis Y2, and thesecond N+ region 104b is evenly distributed on the edge of the N-wellactive region 104, symmetrical about the second symmetry axis Y2, and thefirst N+ region 104 a and thesecond N+ region 104 b are placed parallel to the edge of the N-wellactive region 104 . Thesecond N+ region 104b is distributed on the N-wellactive region 104 at the center of two adjacent first N+ regions.

N阱有源区104的边缘均匀分布设置有第一N+区104a，第一N+区104a关于第二对称轴Y2对称，第一N+区104a平行于N阱有源区104的边缘放置。The edge of the N-wellactive region 104 is evenly distributed withfirst N+ regions 104a, thefirst N+ regions 104a are symmetrical about the second symmetry axis Y2, and thefirst N+ regions 104a are placed parallel to the edge of the N-wellactive region 104 .

四个第一N+区104a上均设置有金属，形成四个偏置电极A、B、C和D。Metal is disposed on the fourfirst N+ regions 104a to form four bias electrodes A, B, C and D.

相邻的第一N+区104a中心的N阱有源区中设置有第二N+区104b，第二N+区104b关于第二对称轴Y2对称，第二N+区104b平行于N阱有源区104的边缘放置；Asecond N+ region 104b is arranged in the N well active region at the center of the adjacentfirst N+ region 104a, thesecond N+ region 104b is symmetrical about the second symmetry axis Y2, and thesecond N+ region 104b is parallel to the N wellactive region 104 edge placement;

第一N+区104a尺寸大于第二N+区104b。The size of thefirst N+ region 104a is larger than that of thesecond N+ region 104b.

对角的两个第一N+区104a距其之间的第二N+区104b的距离相同。Diagonally twofirst N+ regions 104a are at the same distance from thesecond N+ region 104b between them.

四个第二N+区104b上均设置有金属，形成四个输出电极E、F、G和H；Metal is provided on the foursecond N+ regions 104b to form four output electrodes E, F, G and H;

相对的两个输出电极E和H以及F和G通过金属连线短接。The two opposite output electrodes E and H and F and G are short-circuited through metal wires.

高压N阱202表面设置有第三N+区104c，第三N+区104c上设置有金属，形成第一接触电极J。Athird N+ region 104c is disposed on the surface of the high voltage N well 202, and a metal is disposed on thethird N+ region 104c to form a first contact electrode J.

N阱有源区104上方非电极部分覆盖有第一P+区104d。The non-electrode portion above the N-wellactive region 104 is covered with afirst P+ region 104d.

高压P阱203表面设有第二P+区203a，第二P+区203a上设置有金属，形成第二接触电极K。Asecond P+ region 203a is disposed on the surface of the high voltage P well 203, and metal is disposed on thesecond P+ region 203a to form a second contact electrode K.

在第一N+区104a和第三N+区104c之间、第一N+区104a和第一P+区104d、第三N+区104c和第二P+区203a之间设有隔离浅沟槽300。Isolationshallow trenches 300 are provided between thefirst N+ region 104a and thethird N+ region 104c, between thefirst N+ region 104a and thefirst P+ region 104d, between thethird N+ region 104c and thesecond P+ region 203a.

进一步地，对所用层次结构的作用进行详细阐述，Further, elaborating on the role of the hierarchy used,

P-埋层103可以控制掺杂分布，和N+埋层102之间形成更加均匀的PN结，即横向PN结，改善N阱有源区104底部杂质浓度分布，从而提高霍尔器件的对称性，减小输出失调。The P-buriedlayer 103 can control the doping distribution, and form a more uniform PN junction with the N+ buriedlayer 102, that is, a lateral PN junction, which improves the impurity concentration distribution at the bottom of the N-wellactive region 104, thereby improving the symmetry of the Hall device. , reducing the output offset.

横向PN结形成内建电场可以减小N阱有源区104底部的电流损耗，降低器件工作时外部噪声干扰。The built-in electric field formed by the lateral PN junction can reduce the current loss at the bottom of the N-wellactive region 104 and reduce external noise interference when the device is working.

第一P+区104d和N阱104之间形成耗尽层，从而增加电流输运路径，避免短路效应，也可以减小N阱厚度来增加其电流相关灵敏度。第一P+区104d还可以形成PMOS晶体管，由于PMOS管是“埋沟”器件，可以有效降低器件的闪烁噪声和电流的表面损耗，增大霍尔电压。A depletion layer is formed between thefirst P+ region 104d and the N well 104, so as to increase the current transport path, avoid the short circuit effect, and reduce the thickness of the N well to increase its current-related sensitivity. Thefirst P+ region 104d can also form a PMOS transistor. Since the PMOS transistor is a "buried trench" device, it can effectively reduce device flicker noise and surface loss of current, and increase the Hall voltage.

高压N阱202与P型外延层201之间形成PN结，即为纵向保护环有效减小横向漏电流和1/f噪声。A PN junction is formed between the high-voltage N-well 202 and the P-type epitaxial layer 201 , that is, the vertical guard ring effectively reduces lateral leakage current and 1/f noise.

本发明采用N+埋层102和P-埋层103形成横向PN结作为保护环，代替了原本P型外延层与N阱有源区之间的PN结，有效改善了N阱有源区104的杂质浓度分布，减小了霍尔器件由于N阱有源区104杂质浓度呈高斯分布造成的输出失调，而且所形成的的PN结耗尽层更宽，并进一步提高霍尔器件的抗干扰能力，减小底部漏电流。The present invention uses the N+ buriedlayer 102 and the P- buriedlayer 103 to form a lateral PN junction as a guard ring, replacing the original PN junction between the P-type epitaxial layer and the N-well active region, and effectively improving the N-wellactive region 104. The impurity concentration distribution reduces the output offset of the Hall device due to the Gaussian distribution of the impurity concentration in the N-wellactive region 104, and the formed PN junction depletion layer is wider, and further improves the anti-interference ability of the Hall device , reducing the bottom leakage current.

本发明采用高压N阱202与N+埋层102接触，将高压N阱202顶部的第一接触电极J接高电平，从而使N+埋层102接高电平，N+埋层102和P-埋层103之间的横向PN结反偏，进一步加宽横向PN结耗尽层，使霍尔器件的抗干扰能力更强，失调更小，同时这种方式减小了N阱有源区104的有效深度，提高霍尔器件的灵敏度。高压N阱202还可以与P型外延层201之间形成纵向PN结，进一步减小霍尔器件的横向漏电流和噪声，对霍尔器件起到了双重保护。The present invention adopts the high-voltage N well 202 to contact the N+ buriedlayer 102, and connects the first contact electrode J on the top of the high-voltage N well 202 to a high level, so that the N+ buriedlayer 102 is connected to a high level, and the N+ buriedlayer 102 and the P-buried layer The lateral PN junction between thelayers 103 is reverse-biased, and the lateral PN junction depletion layer is further widened, so that the anti-interference ability of the Hall device is stronger and the offset is smaller. At the same time, this method reduces the The effective depth improves the sensitivity of the Hall device. The high-voltage N-well 202 can also form a vertical PN junction with the P-type epitaxial layer 201 to further reduce the lateral leakage current and noise of the Hall device and provide double protection for the Hall device.

实施例2Example 2

参照图5和6，本实施例还提出了上述采用双保护环的低失调霍尔器件的使用方法，为：Referring to Figures 5 and 6, this embodiment also proposes the method of using the above-mentioned low-offset Hall device with double guard rings, which is:

所提出的霍尔器件的偏置电极A、B、C、D中，其中两个相对的偏置电极输入大小相等、方向相反的电流或电压偏置信号，另外两个相对的偏置电极接地，例如偏置电极A和C中输入大小相等、方向相反的电流或电压偏置信号则偏置电极B和D接地；所提出的霍尔器件的两个短接的输出电极E（或H）和F（或G）之间输出霍尔电流或霍尔电压信号；所提出的第一接触电极J接高电平；所提出的第二接触电极K接地。Among the bias electrodes A, B, C, and D of the proposed Hall device, two opposite bias electrodes input current or voltage bias signals of equal size and opposite directions, and the other two opposite bias electrodes are grounded , For example, the bias electrodes A and C are input with equal and opposite current or voltage bias signals, and the bias electrodes B and D are grounded; the two short-circuited output electrodes E (or H) of the proposed Hall device Output Hall current or Hall voltage signal between F and F (or G); the proposed first contact electrode J is connected to high level; the proposed second contact electrode K is grounded.

进一步，所提出的霍尔器件的衬底材料不仅限于硅（Si）半导体，还可以利用锗硅（SiGe）、砷化镓（GaAs）、磷化铟(InP)、氮化镓（GaN）、碳化硅（SiC）和铟镓砷（InGaAs）等多种半导体材料作为衬底。Further, the substrate material of the proposed Hall device is not limited to silicon (Si) semiconductor, but silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), Various semiconductor materials such as silicon carbide (SiC) and indium gallium arsenide (InGaAs) are used as substrates.

进一步，所提出的霍尔器件的N阱有源区104还可以设计为八边形、菱形和圆形结构。Further, the N-wellactive region 104 of the proposed Hall device can also be designed in octagonal, rhombus and circular structures.

制作本发明提出的低失调霍尔器件结构的工艺步骤为：The process steps for making the low offset Hall device structure proposed by the present invention are:

步骤S1，首先在P型衬底101上的中心区域形成N+埋层102。In step S1 , an N+ buriedlayer 102 is first formed on the central region of the P-type substrate 101 .

步骤S2，在P型衬底101上生长一层P型外延层201，并在P型外延层201顶部形成隔离浅沟槽300。In step S2 , a P-type epitaxial layer 201 is grown on the P-type substrate 101 , and an isolationshallow trench 300 is formed on the top of the P-type epitaxial layer 201 .

步骤S3，在N+埋层102上方的外延层中形成P-埋层103，P-埋层103底部与N+埋层102顶部连接。In step S3 , a P-buriedlayer 103 is formed in the epitaxial layer above the N+ buriedlayer 102 , and the bottom of the P-buriedlayer 103 is connected to the top of the N+ buriedlayer 102 .

步骤S4，在P-埋层103上的P型外延层201中注入N阱有源区104。Step S4 , implanting the N-wellactive region 104 into the P-type epitaxial layer 201 on the P-buriedlayer 103 .

步骤S5，在N阱有源区104周围的P型外延层201中形成高压N阱202，高压N阱底部与N+埋层102顶部相连接。In step S5 , a high voltage N well 202 is formed in the P-type epitaxial layer 201 around the N wellactive region 104 , and the bottom of the high voltage N well is connected to the top of the N+ buriedlayer 102 .

步骤S6，在高压N阱202周围的P型外延层201中形成高压P阱203，高压P阱203底部与P型衬底101相连接。Step S6 , forming a high voltage P well 203 in the Ptype epitaxial layer 201 around the high voltage N well 202 , and the bottom of the high voltage P well 203 is connected to theP type substrate 101 .

步骤S7，在N阱有源区104顶部形成第一N+区104a和第二N+区104b，在高压N阱202表面形成第三N+区104c。In step S7 , afirst N+ region 104 a and asecond N+ region 104 b are formed on the top of the N wellactive region 104 , and athird N+ region 104 c is formed on the surface of the high voltage N well 202 .

步骤S8，在N阱有源区104表面形成第一P+区104d，在高压P阱203表面形成第二P+区203a。In step S8 , afirst P+ region 104 d is formed on the surface of the N-wellactive region 104 , and asecond P+ region 203 a is formed on the surface of the high-voltage P-well 203 .

步骤S9，在P型外延层201上设有接触孔，形成金属互连线。In step S9, a contact hole is provided on the P-type epitaxial layer 201 to form a metal interconnection line.

结合图5中低失调霍尔器件的工作偏置示意图，进一步说明所提出的霍尔器件工作方法：Combined with the working bias diagram of the low offset Hall device in Figure 5, the proposed working method of the Hall device is further explained:

当霍尔偏置电极A、C输入大小相等极性相反的电流偏置，另外两个偏置电极B、D连接到地，无外加磁场时，假设N阱有源区104整体浓度分布均匀，这时四个输出电极E、F、G、H附近的电流密度相同，理想上输出的电压为0。When the Hall bias electrodes A and C input current biases of equal magnitude and opposite polarity, the other two bias electrodes B and D are connected to ground, and there is no external magnetic field, assuming that the overall concentration distribution of the N-wellactive region 104 is uniform, At this time, the current densities near the four output electrodes E, F, G, and H are the same, and the output voltage is ideally zero.

进一步地，当施加垂直纸面向内的磁场，载流子受到洛伦兹力发生偏转，同时极化四个输出电极，由于实际情况下，霍尔器件有源区杂质分布不均，所以四个输出电极附近的电流密度存在不对称的现象。Furthermore, when a magnetic field perpendicular to the surface of the paper is applied inward, the carriers are deflected by the Lorentz force, and the four output electrodes are polarized at the same time. Due to the uneven distribution of impurities in the active region of the Hall device, the four There is an asymmetry in the current density near the output electrode.

进一步地，本发明中霍尔器件的对角输出电极E和H、F和G短接，迫使电流在有源区中均匀分布，减小了由于电阻率、杂质浓度不均或工艺应力不均产生的失调，实现了静态消除失调信号，且不需要旋转电流技术，减小了前端电路的寄生电容。Further, in the present invention, the diagonal output electrodes E and H, F and G of the Hall device are short-circuited, forcing the current to be evenly distributed in the active region, reducing the resistance due to resistivity, uneven impurity concentration, or uneven process stress. The generated offset realizes the static elimination of the offset signal, and does not require the spinning current technology, which reduces the parasitic capacitance of the front-end circuit.

进一步地，由于第一接触电极J始终接高电平，第二接触电极K始终接地，可以使所述的横向保护环和纵向保护环反偏，减小了漏电流和工作时电路中高频信号干扰，增强了霍尔器件的抗干扰能力。Further, since the first contact electrode J is always connected to a high level and the second contact electrode K is always connected to the ground, the horizontal guard ring and the longitudinal guard ring can be reverse-biased, reducing the leakage current and the high-frequency signal in the circuit during operation. Interference, enhance the anti-interference ability of the Hall device.

参照图6为本发明与传统十字形霍尔器件结构的输出失调对比仿真图。Referring to FIG. 6 , it is a comparison simulation diagram of the output offset between the present invention and the traditional cross-shaped Hall device structure.

具体的，针对图1和图2所示的器件结构，根据高压BCD工艺的工艺流程参数，使用Silvaco TCAD仿真工具对低失调霍尔器件结构进行了器件电学特性仿真，得到图5低失调霍尔器件与传统四接触孔的霍尔器件的输出失调大小的对比，可以发现在0-5mA的偏置电流下，低失调霍尔器件的输出失调始终在1mV以下，而传统十字形霍尔器件输出失调在5mA偏置电流下就达到了4.5mV左右，说明本发明设计的低失调霍尔器件方案具有可行性。Specifically, for the device structure shown in Figure 1 and Figure 2, according to the process parameters of the high-voltage BCD process, the Silvaco TCAD simulation tool was used to simulate the device electrical characteristics of the low-offset Hall device structure, and the low-offset Hall device structure in Figure 5 was obtained. Comparing the output offset of the device with the traditional four-contact Hall device, it can be found that under the bias current of 0-5mA, the output offset of the low-offset Hall device is always below 1mV, while the output of the traditional cross-shaped Hall device The offset reaches about 4.5mV under the bias current of 5mA, which shows that the low offset Hall device solution designed by the present invention is feasible.

重要的是，应注意，在多个不同示例性实施方案中示出的本申请的构造和布置仅是例示性的。尽管在此公开内容中仅详细描述了几个实施方案，但参阅此公开内容的人员应容易理解，在实质上不偏离该申请中所描述的主题的新颖教导和优点的前提下，许多改型是可能的（例如，各种元件的尺寸、尺度、结构、形状和比例、以及参数值（例如，温度、压力等）、安装布置、材料的使用、颜色、定向的变化等）。例如，示出为整体成形的元件可以由多个部分或元件构成，元件的位置可被倒置或以其它方式改变，并且分立元件的性质或数目或位置可被更改或改变。因此，所有这样的改型旨在被包含在本发明的范围内。可以根据替代的实施方案改变或重新排序任何过程或方法步骤的次序或顺序。在权利要求中，任何“装置加功能”的条款都旨在覆盖在本文中所描述的执行所述功能的结构，且不仅是结构等同而且还是等同结构。在不背离本发明的范围的前提下，可以在示例性实施方案的设计、运行状况和布置中做出其他替换、改型、改变和省略。因此，本发明不限制于特定的实施方案，而是扩展至仍落在所附的权利要求书的范围内的多种改型。It is important to note that the construction and arrangement of the application, shown in the various exemplary embodiments, are illustrative only. Although only a few embodiments have been described in detail in this disclosure, it should be readily apparent to those who review this disclosure that many modifications are possible without materially departing from the novel teachings and advantages of the subject matter described in this application. are possible (e.g., variations in dimensions, dimensions, structures, shapes and proportions of various elements, as well as parameter values (e.g., temperature, pressure, etc.), mounting arrangements, use of materials, colors, orientations, etc.). For example, elements shown as integrally formed may be constructed of multiple parts or elements, the position of elements may be inverted or otherwise varied, and the nature or number or positions of discrete elements may be altered or varied. Accordingly, all such modifications are intended to be included within the scope of this invention. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative embodiments. In the claims, any "means-plus-function" clause is intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operation and arrangement of the exemplary embodiments without departing from the scope of the invention. Accordingly, the invention is not limited to a particular embodiment, but extends to various modifications still falling within the scope of the appended claims.

此外，为了提供示例性实施方案的简练描述，可以不描述实际实施方案的所有特征（即，与当前考虑的执行本发明的最佳模式不相关的那些特征，或于实现本发明不相关的那些特征）。Furthermore, in order to provide a concise description of exemplary embodiments, not all features of an actual embodiment (i.e., those features not relevant to the best mode presently considered for carrying out the invention, or to practicing the invention feature).

应理解的是，在任何实际实施方式的开发过程中，如在任何工程或设计项目中，可做出大量的具体实施方式决定。这样的开发努力可能是复杂的且耗时的，但对于那些得益于此公开内容的普通技术人员来说，不需要过多实验，所述开发努力将是一个设计、制造和生产的常规工作。It should be appreciated that during the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort would be complex and time-consuming, but would be a routine matter of design, fabrication, and production without undue experimentation to those of ordinary skill having the benefit of this disclosure .

应说明的是，以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的精神和范围，其均应涵盖在本发明的权利要求范围当中。It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention without limitation, although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be carried out Modifications or equivalent replacements without departing from the spirit and scope of the technical solution of the present invention shall be covered by the claims of the present invention.