CN116017986A - Logic gate circuit - Google Patents

Abstract

The present application relates to a logic gate circuit comprising: the ferroelectric transistor comprises a pull-up resistor and a ferroelectric transistor, wherein a main grid electrode, a channel and a back grid electrode are sequentially arranged in the ferroelectric transistor from top to bottom, two ends of the channel are respectively provided with a source electrode and a drain electrode, a ferroelectric layer and an interface layer are sequentially arranged between the main grid electrode and the channel from top to bottom, and a blocking oxide layer, a charge trapping layer and a tunneling oxide layer are sequentially arranged between the channel and the back grid electrode from top to bottom; the pull-up resistor is connected with the drain electrode. According to the logic gate circuit and the logic gate circuit control method, the problem that the working energy consumption of the logic gate circuit is high in the related art is solved, and the working energy consumption of the logic gate circuit is reduced.

Description

Translated fromChinese

逻辑门电路logic gate circuit

技术领域technical field

本申请涉及芯片存储器存储技术领域，特别是涉及一种逻辑门电路。The present application relates to the technical field of chip memory storage, in particular to a logic gate circuit.

背景技术Background technique

当前大数据时代，数据量的高速增长对芯片算力与能效提出了更高的要求，而传统存算分离的冯-诺伊曼架构限制了算力与能效的进一步提升。因此，亟需发展出基于新型非易失性存储器的新型存算架构。铁电存储器是利用铁电材料的极化翻转实现0/1存储的存储技术，其基本构成单元为铁电场效应晶体管(Ferroelectric Field EffectTransistor，FeFET)。图1是相关技术中铁电晶体管的结构示意图，如图1所示，铁电晶体管由栅极、沟道和衬底构成，沟道的两端分别设置有源极和漏极，栅极和沟道之间由上至下依次设置有铁电层和界面层。在栅极上施加正电压或负电压，且施加在铁电材料上的电压超过矫顽电压Vc时，会导致铁电极化正向或负向翻转，铁电材料中的极化电荷会在沟道吸引电性相反的电荷，改变晶体管的阈值电压，铁电晶体管在进行编程和擦除时的极化状态如图1中的(a)、(b)所示。在对铁电晶体管进行编程或擦除操作后，通过改变铁电晶体管衬底的偏置电压Vsub，可以调节铁电晶体管的阈值电压，从而做到逻辑门的切换。但是对逻辑门进行逻辑切换时，若想长时间保持某一逻辑功能，需要对铁电晶体管衬底长时间施加偏压，导致逻辑门电路工作能耗高。In the current era of big data, the rapid growth of data volume puts forward higher requirements for chip computing power and energy efficiency, while the traditional Von Neumann architecture of separation of storage and computing limits the further improvement of computing power and energy efficiency. Therefore, it is urgent to develop a new storage and computing architecture based on a new type of non-volatile memory. Ferroelectric memory is a storage technology that uses the polarization reversal of ferroelectric materials to realize 0/1 storage. Its basic constituent unit is a ferroelectric field effect transistor (Ferroelectric Field Effect Transistor, FeFET). Fig. 1 is a schematic diagram of the structure of a ferroelectric transistor in the related art. As shown in Fig. 1, the ferroelectric transistor consists of a gate, a channel and a substrate. The two ends of the channel are respectively provided with a source and a drain, and the gate and the channel A ferroelectric layer and an interface layer are sequentially arranged between the tracks from top to bottom. When a positive or negative voltage is applied to the gate, and the voltage applied to the ferroelectric material exceeds the coercive voltage Vc, the ferroelectric polarization will be reversed positively or negatively, and the polarization charge in the ferroelectric material will be in the channel The channel attracts oppositely charged charges and changes the threshold voltage of the transistor. The polarization state of the ferroelectric transistor during programming and erasing is shown in (a) and (b) in Figure 1. After programming or erasing the ferroelectric transistor, by changing the bias voltage Vsub of the substrate of the ferroelectric transistor, the threshold voltage of the ferroelectric transistor can be adjusted, so as to switch the logic gate. However, when switching logic gates, if you want to maintain a certain logic function for a long time, you need to apply a bias voltage to the substrate of the ferroelectric transistor for a long time, resulting in high energy consumption for the logic gate circuit.

针对相关技术中存在逻辑门电路工作能耗高的问题，目前还没有提出有效的解决方案。Aiming at the problem of high energy consumption of logic gate circuits in the related art, no effective solution has been proposed yet.

发明内容Contents of the invention

在本实施例中提供了一种逻辑门电路，以解决相关技术中逻辑门电路工作能耗高的问题。In this embodiment, a logic gate circuit is provided to solve the problem of high energy consumption of the logic gate circuit in the related art.

本实施例提供了一种逻辑门电路，包括：上拉电阻和铁电晶体管，所述铁电晶体管内部由上至下依次设置有主栅极、沟道和背栅极，其中，所述沟道的两端分别设置有源极和漏极，所述主栅极和所述沟道之间由上至下依次设置有铁电层和界面层，所述沟道和所述背栅极之间由上至下依次设置有阻绝氧化层、电荷俘获层和隧穿氧化层；所述上拉电阻与所述漏极连接。This embodiment provides a logic gate circuit, including: a pull-up resistor and a ferroelectric transistor, wherein a main gate, a channel and a back gate are sequentially arranged inside the ferroelectric transistor, wherein the channel The two ends of the channel are respectively provided with a source and a drain, a ferroelectric layer and an interface layer are sequentially provided between the main gate and the channel from top to bottom, and between the channel and the back gate A blocking oxide layer, a charge trapping layer and a tunneling oxide layer are disposed in sequence from top to bottom; the pull-up resistor is connected to the drain.

在其中的一些实施例中，制成所述阻绝氧化层的材料包括Al₂O₃，制成所述电荷俘获层的材料包括Si₃N₄，制成所述隧穿氧化层的材料包括SiO₂。In some of these embodiments, the material for the blocking oxide layer includes Al₂ O₃ , the material for the charge trapping layer includes Si₃ N₄ , and the material for the tunnel oxide layer includes SiO₂ .

在其中的一些实施例中，所述阻绝氧化层通过原子层沉积法生长一层Al₂O₃形成；所述电荷俘获层通过化学气相沉积法生长一层Si₃N₄形成；所述隧穿氧化层通过原子层沉积法生长一层SiO₂形成。In some of these embodiments, the blocking oxide layer is formed by growing a layer of Al₂ O₃ by atomic layer deposition; the charge trapping layer is formed by growing a layer of Si₃ N₄ by chemical vapor deposition; the tunneling The oxide layer is formed by growing a layer of_SiO2 by atomic layer deposition.

在其中的一些实施例中，制成所述铁电层的材料包括HfZrO_X，制成所述界面层的材料包括SiO₂。In some of the embodiments, the material of the ferroelectric layer includes HfZrO_x , and the material of the interface layer includes SiO₂ .

在其中的一些实施例中，所述铁电层通过原子层沉积法生长一层HfZrO_X形成，所述界面层通过臭氧氧化法生长一层SiO₂形成。In some of the embodiments, the ferroelectric layer is formed by growing a layer of HfZrO_X by atomic layer deposition, and the interface layer is formed by growing a layer of SiO₂ by ozone oxidation.

在其中的一些实施例中，当所述铁电晶体管的电荷俘获层保持在电中性状态时，所述铁电晶体管构成第一逻辑门。In some of these embodiments, when the charge trapping layer of the ferroelectric transistor is maintained in an electrically neutral state, the ferroelectric transistor constitutes the first logic gate.

在其中的一些实施例中，当向所述铁电晶体管的背栅极施加第一预设电压时，所述铁电晶体管的电荷俘获层处于负电荷俘获态，所述铁电晶体管所实现的功能从第一逻辑门切换至第二逻辑门，且在撤去所述第一预设电压后，所述铁电晶体管保持所述第二逻辑门的功能。In some of these embodiments, when the first preset voltage is applied to the back gate of the ferroelectric transistor, the charge trapping layer of the ferroelectric transistor is in a negative charge trapping state, and the ferroelectric transistor achieves The function is switched from the first logic gate to the second logic gate, and the ferroelectric transistor maintains the function of the second logic gate after the first preset voltage is removed.

在其中的一些实施例中，对于n型铁电晶体管，所述第一逻辑门为“与非”门，所述第二逻辑门为“或非”门；对于p型铁电晶体管，所述第一逻辑门为“或”门，所述第二逻辑门为“与”门。In some of these embodiments, for an n-type ferroelectric transistor, the first logic gate is a "NAND" gate, and the second logic gate is a "NOR" gate; for a p-type ferroelectric transistor, the The first logic gate is an "OR" gate, and the second logic gate is an "AND" gate.

在其中的一些实施例中，当向所述铁电晶体管的主栅极施加第二预设电压时，所述铁电晶体管发生铁电极化正向翻转，所述铁电晶体管的阈值电压变小。In some of these embodiments, when a second preset voltage is applied to the main gate of the ferroelectric transistor, the ferroelectric transistor undergoes a forward reversal of ferroelectric polarization, and the threshold voltage of the ferroelectric transistor becomes smaller .

在其中的一些实施例中，当向所述铁电晶体管的主栅极施加第三预设电压时，所述铁电晶体管发生铁电极化负向翻转，所述铁电晶体管的阈值电压变大。In some of these embodiments, when a third preset voltage is applied to the main gate of the ferroelectric transistor, the ferroelectric transistor undergoes negative reversal of ferroelectric polarization, and the threshold voltage of the ferroelectric transistor becomes larger .

与相关技术相比，在本实施例中提供的逻辑门电路，包括：上拉电阻和铁电晶体管，铁电晶体管内部由上至下依次设置有主栅极、沟道和背栅极，其中，沟道的两端分别设置有源极和漏极，主栅极和沟道之间由上至下依次设置有铁电层和界面层，沟道和背栅极之间由上至下依次设置有阻绝氧化层、电荷俘获层和隧穿氧化层；上拉电阻与漏极连接。通过本申请，解决了相关技术中逻辑门电路工作能耗高的问题，降低了逻辑门电路的工作能耗。Compared with related technologies, the logic gate circuit provided in this embodiment includes: a pull-up resistor and a ferroelectric transistor, and the ferroelectric transistor is provided with a main gate, a channel and a back gate in order from top to bottom, wherein , the two ends of the channel are respectively provided with a source and a drain, the main gate and the channel are provided with a ferroelectric layer and an interface layer from top to bottom, and the channel and the back gate are arranged from top to bottom in order A blocking oxide layer, a charge trapping layer and a tunneling oxide layer are provided; the pull-up resistor is connected to the drain. Through the present application, the problem of high energy consumption of the logic gate circuit in the related art is solved, and the energy consumption of the logic gate circuit is reduced.

本申请的一个或多个实施例的细节在以下附图和描述中提出，以使本申请的其他特征、目的和优点更加简明易懂。The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below, so as to make other features, objects, and advantages of the application more comprehensible.

附图说明Description of drawings

此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The schematic embodiments and descriptions of the application are used to explain the application and do not constitute an improper limitation to the application. In the attached picture:

图1是相关技术的铁电晶体管的结构示意图；FIG. 1 is a schematic structural view of a ferroelectric transistor of the related art;

图2是本申请一实施例中逻辑门电路的结构示意图；Fig. 2 is a schematic structural diagram of a logic gate circuit in an embodiment of the present application;

图3是本申请一实施例中基于n型铁电晶体管的逻辑门电路的Id-Vg特性曲线图；Fig. 3 is the Id-Vg characteristic curve of the logic gate circuit based on n-type ferroelectric transistor in an embodiment of the present application;

图4是本申请一实施例中基于n型铁电晶体管的逻辑门电路的操作表和真值表；Fig. 4 is an operation table and a truth table of a logic gate circuit based on an n-type ferroelectric transistor in an embodiment of the present application;

图5是本申请一实施例中基于p型铁电晶体管的逻辑门电路的Id-Vg特性曲线图；Fig. 5 is the Id-Vg characteristic curve of the logic gate circuit based on p-type ferroelectric transistor in an embodiment of the present application;

图6是本申请一实施例中基于p型铁电晶体管的逻辑门电路的操作表和真值表。FIG. 6 is an operation table and a truth table of a p-type ferroelectric transistor-based logic gate circuit in an embodiment of the present application.

具体实施方式Detailed ways

为更清楚地理解本申请的目的、技术方案和优点，下面结合附图和实施例，对本申请进行了描述和说明。In order to understand the purpose, technical solution and advantages of the present application more clearly, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

除另作定义外，本申请所涉及的技术术语或者科学术语应具有本申请所属技术领域具备一般技能的人所理解的一般含义。在本申请中的“一”、“一个”、“一种”、“该”、“这些”等类似的词并不表示数量上的限制，它们可以是单数或者复数。在本申请中所涉及的术语“包括”、“包含”、“具有”及其任何变体，其目的是涵盖不排他的包含；例如，包含一系列步骤或模块(单元)的过程、方法和系统、产品或设备并未限定于列出的步骤或模块(单元)，而可包括未列出的步骤或模块(单元)，或者可包括这些过程、方法、产品或设备固有的其他步骤或模块(单元)。在本申请中所涉及的“连接”、“相连”、“耦接”等类似的词语并不限定于物理的或机械连接，而可以包括电气连接，无论是直接连接还是间接连接。在本申请中所涉及的“多个”是指两个或两个以上。“和/或”描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。通常情况下，字符“/”表示前后关联的对象是一种“或”的关系。在本申请中所涉及的术语“第一”、“第二”、“第三”等，只是对相似对象进行区分，并不代表针对对象的特定排序。Unless otherwise defined, the technical terms or scientific terms involved in the application shall have the general meanings understood by those skilled in the technical field to which the application belongs. In this application, words like "a", "an", "an", "the", "these" and the like do not denote quantitative limitations, and they may be singular or plural. The terms "comprising", "comprising", "having" and any variants thereof referred to in this application are intended to cover non-exclusive inclusion; for example, processes, methods and The system, product or device is not limited to the steps or modules (units) listed, but may include steps or modules (units) not listed, or may include other steps or modules inherent to the process, method, product or device (unit). The terms "connected", "connected", "coupled" and the like referred to in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Plurality" referred to in this application means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships. For example, "A and/or B" may indicate: A exists alone, A and B exist simultaneously, and B exists independently. Usually, the character "/" indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third" and the like involved in this application are only for distinguishing similar objects, and do not represent a specific ordering of objects.

在一个实施例中，提供了一种逻辑门电路，图2是本实施例提供的逻辑门电路的结构示意图。如图2中的(a)所示，该逻辑门电路包括上拉电阻(PU)和铁电晶体管。如图2中的(b)所示，铁电晶体管内部由上至下依次设置有主栅极、沟道和背栅极，其中，沟道的两端分别设置有源极和漏极，主栅极和沟道之间由上至下依次设置有铁电层和界面层，沟道和背栅极之间由上至下依次设置有阻绝氧化层(Blocking Oxide)、电荷俘获层(ChargeTrapping Layer)和隧穿氧化层(Tunneling Oxide)。其中，上拉电阻与漏极连接。In one embodiment, a logic gate circuit is provided, and FIG. 2 is a schematic structural diagram of the logic gate circuit provided in this embodiment. As shown in (a) of FIG. 2, the logic gate circuit includes a pull-up resistor (PU) and a ferroelectric transistor. As shown in (b) in Figure 2, the ferroelectric transistor is provided with a main gate, a channel and a back gate sequentially from top to bottom, wherein the two ends of the channel are respectively provided with a source and a drain, and the main Between the gate and the channel, a ferroelectric layer and an interface layer are arranged in sequence from top to bottom, and between the channel and the back gate, a blocking oxide layer (Blocking Oxide), a charge trapping layer (ChargeTrapping Layer) are arranged in sequence from top to bottom. ) and tunneling oxide (Tunneling Oxide). Wherein, the pull-up resistor is connected to the drain.

相比于相关技术的铁电晶体管，本实施例在铁电晶体管的衬底背部添加一个三层结构，如图2中的(b)所示，上层为阻绝氧化层(Blocking Oxide)，中间一层则是由电荷俘获材料制成的电荷俘获层(Charge Trapping Layer)，下层为隧穿氧化层(TunnelingOxide)。当对底部的背栅极施加一个电压脉冲信号(Vtrap)后，外加电场能向电荷俘获层中注入一部分电荷，这些电荷会被俘获在层中，使得铁电晶体管底部的电荷俘获层在撤去外加电压后，仍然能长时间带电，从而无须对衬底长时间加偏压，就能使铁电晶体管Id-Vg特性曲线发生偏移。铁电晶体管在随后的操作中，仅需对衬底施加一次偏压，便能够长时间保持某一逻辑门的功能，实现可重构逻辑门切换的非易失性，有效地减小工作能耗，这对实现新型计算架构、改善计算速度与能效、提高电路集成密度具有重要作用。Compared with the ferroelectric transistor of the related art, this embodiment adds a three-layer structure on the back of the substrate of the ferroelectric transistor, as shown in (b) in Figure 2, the upper layer is a blocking oxide layer (Blocking Oxide), the middle one The first layer is a charge trapping layer made of a charge trapping material, and the lower layer is a tunneling oxide layer (TunnelingOxide). When a voltage pulse signal (Vtrap) is applied to the bottom back gate, the external electric field can inject a part of charges into the charge-trapping layer, and these charges will be trapped in the layer, so that the charge-trapping layer at the bottom of the ferroelectric transistor is removed. After a certain voltage, it can still be charged for a long time, so that the Id-Vg characteristic curve of the ferroelectric transistor can be shifted without applying a bias voltage to the substrate for a long time. In the subsequent operation, the ferroelectric transistor only needs to apply a bias voltage to the substrate once, and it can maintain the function of a certain logic gate for a long time, realize the non-volatility of reconfigurable logic gate switching, and effectively reduce the working energy. This plays an important role in realizing new computing architectures, improving computing speed and energy efficiency, and increasing circuit integration density.

可选地，阻绝氧化层、电荷俘获层和隧穿氧化层分别由Al₂O₃、Si₃N₄、SiO₂材料制成。铁电层和界面层分别由HfZrO_X(也称之为HZO)、SiO₂材料制成。主栅极、背栅极、源极、漏极、沟道分别由TiN、TiN、Si、Si、Si材料制成。Optionally, the blocking oxide layer, the charge trapping layer, and the tunneling oxide layer are made of Al₂ O₃ , Si₃ N₄ , and SiO₂ materials, respectively. The ferroelectric layer and interface layer are made of HfZrO_x (also known as HZO) and SiO₂ materials respectively. The main gate, the back gate, the source, the drain and the channel are respectively made of TiN, TiN, Si, Si and Si materials.

在一个实施例中，给出了铁电晶体管的制作工艺，包括器件背面结构和正面结构的工艺。以n型器件为例，器件背面结构的工艺包括如下步骤：In one embodiment, the manufacturing process of the ferroelectric transistor is given, including the processes of the back structure and the front structure of the device. Taking an n-type device as an example, the process of the back structure of the device includes the following steps:

步骤S11，制作工艺始于p型Si衬底，采用原子层沉积法(ALD)，在Si衬底的背面生长一层Al₂O₃形成阻绝氧化层；Step S11, the manufacturing process starts with a p-type Si substrate, and grows a layer of_Al2O3 on the back of the Si substrate by atomic layer deposition (ALD) to form a barrier oxide layer_;

步骤S12，利用化学气相沉积法，在背部生长一层Si₃N₄，形成电荷俘获层；Step S12, using a chemical vapor deposition method to grow a layer of Si₃ N₄ on the back to form a charge trapping layer;

步骤S13，采用原子层沉积法在器件背部生长一层薄的SiO₂作为隧穿氧化层；Step S13, growing a thin layer of_SiO2 as a tunneling oxide layer on the back of the device by atomic layer deposition;

步骤S14，通过磁控溅射法在背部沉积20nm TiN，形成背栅极。Step S14, depositing 20nm TiN on the back by magnetron sputtering to form a back gate.

器件正面结构的工艺包括如下步骤：The process of the device front structure includes the following steps:

步骤S21，在光刻胶的掩蔽作用下，对p型Si衬底正面的两块区域进行砷离子注入，之后在1050℃下退火以活化掺杂剂，形成源极和漏极；Step S21, under the masking effect of the photoresist, perform arsenic ion implantation on the two areas on the front side of the p-type Si substrate, and then anneal at 1050° C. to activate the dopant to form the source and drain;

步骤S22，利用臭氧氧化的方法在衬底的正面生成一层SiO₂作为界面层；Step S22, using the method of ozone oxidation to generate a layer of_SiO2 on the front side of the substrate as an interface layer;

步骤S23，采用原子层沉积法在上层的SiO₂界面层上沉积10nm的HfZrO_X，形成铁电层；Step S23, depositing 10 nm of HfZrO_x on the upper SiO₂ interface layer by atomic layer deposition to form a ferroelectric layer;

步骤S24，通过磁控溅射法在器件正面沉积一层20nm TiN，形成主栅；Step S24, depositing a layer of 20nm TiN on the front of the device by magnetron sputtering to form a main gate;

步骤S25，在N₂氛围中，550℃下进行快速热退火(RTA)1分钟，使HfZrO_X结晶。Step S25, performing rapid thermal annealing (RTA) at 550° C. for 1 minute in N₂ atmosphere to crystallize HfZrO_X.

在一个实施例中，当铁电晶体管的电荷俘获层保持在电中性状态时，铁电晶体管构成第一逻辑门。当向铁电晶体管的背栅极施加第一预设电压时，铁电晶体管的电荷俘获层处于负电荷俘获态，铁电晶体管所实现的功能从第一逻辑门切换至第二逻辑门，且在撤去第一预设电压后，铁电晶体管保持第二逻辑门的功能。In one embodiment, the ferroelectric transistor constitutes the first logic gate when the charge trapping layer of the ferroelectric transistor is maintained in an electrically neutral state. When the first preset voltage is applied to the back gate of the ferroelectric transistor, the charge trapping layer of the ferroelectric transistor is in a negative charge trapping state, and the function realized by the ferroelectric transistor is switched from the first logic gate to the second logic gate, and After removing the first predetermined voltage, the ferroelectric transistor maintains the function of the second logic gate.

对于n型铁电晶体管，第一逻辑门为“与非”门(NAND)，第二逻辑门为“或非”门(NOR)；对于p型铁电晶体管，第一逻辑门为“或”门(OR)，第二逻辑门为“与”门(AND)。当向铁电晶体管的主栅极施加第二预设电压时，铁电晶体管发生铁电极化正向翻转，铁电晶体管的阈值电压变小。当向铁电晶体管的主栅极施加第三预设电压时，铁电晶体管发生铁电极化负向翻转，铁电晶体管的阈值电压变大。For n-type ferroelectric transistors, the first logic gate is "NAND" gate (NAND), and the second logic gate is "NOR" gate (NOR); for p-type ferroelectric transistors, the first logic gate is "OR" gate (OR), and the second logic gate is an "and" gate (AND). When the second preset voltage is applied to the main gate of the ferroelectric transistor, the ferroelectric transistor undergoes forward reversal of ferroelectric polarization, and the threshold voltage of the ferroelectric transistor becomes smaller. When the third preset voltage is applied to the main gate of the ferroelectric transistor, the ferroelectric transistor undergoes negative reversal of ferroelectric polarization, and the threshold voltage of the ferroelectric transistor becomes larger.

在本实施例中，沟道的电导状态是由铁电层的极化状态(输入信号1)以及施加在主栅上的读取电压(输入信号2)来共同决定的，通过铁电电荷的正/负向翻转来调控沟道中的载流子浓度，从而改变铁电晶体管的阈值电压。通过在背栅极施加的预处理电压，让电荷俘获层俘获/释放电荷，从而在撤走电压后起到类似于在晶体管底部持续施加一定的偏压来影响晶体管阈值电压的作用。在整个铁电晶体管的工作期间，电荷俘获层并不与沟道发生电荷交换，不会随着逻辑功能的实现而被中和，即整个铁电晶体管的逻辑功能不会就此重置，不需要重新从预处理操作阶段开始来给铁电晶体管设定之后的逻辑功能。在本实施例中，铁电晶体管的沟道类型以及预处理操作确定后，整个铁电晶体管的逻辑功能就已经被确定，输入信号1与2用于确定最后真值的测量条件，逻辑功能的切换则由电荷俘获层的电荷俘获状态来控制。In this embodiment, the conductance state of the channel is jointly determined by the polarization state of the ferroelectric layer (input signal 1) and the read voltage (input signal 2) applied to the main gate. Positive/negative inversion is used to regulate the carrier concentration in the channel, thereby changing the threshold voltage of the ferroelectric transistor. Through the pretreatment voltage applied on the back gate, the charge trapping layer traps/releases the charge, which acts similar to continuously applying a certain bias voltage at the bottom of the transistor to affect the threshold voltage of the transistor after the voltage is withdrawn. During the working period of the entire ferroelectric transistor, the charge trapping layer does not exchange charges with the channel, and will not be neutralized with the realization of the logic function, that is, the logic function of the entire ferroelectric transistor will not be reset, no need The ferroelectric transistors are assigned subsequent logic functions starting again from the preprocessing operation phase. In this embodiment, after the channel type of the ferroelectric transistor and the preprocessing operation are determined, the logic function of the entire ferroelectric transistor has been determined, and the input signals 1 and 2 are used to determine the measurement conditions of the final true value, and the logic function Switching is then controlled by the charge-trapping state of the charge-trapping layer.

在本实施例中，“非易失性”不单指铁电晶体管沟道的电导状态，也包括整个逻辑门电路的逻辑功能的“非易失性”，因为铁电晶体管的电荷俘获层在工作过程中，全程不与沟道发生电荷交换，而是通过类似于极化的效果，来影响铁电晶体管的阈值电压。因此在本实施例中，通过背栅极给电荷俘获层注入电荷后，铁电晶体管的逻辑功能已被确定，并且不会随着逻辑电路的工作而重置，具有逻辑功能的“非易失性”，而通过背栅极对电荷俘获层进行放电，又能实现逻辑功能的切换，从而也满足了“可重构性”。In this embodiment, "non-volatile" not only refers to the conductance state of the channel of the ferroelectric transistor, but also includes the "non-volatile" of the logic function of the entire logic gate circuit, because the charge trapping layer of the ferroelectric transistor is working During the process, there is no charge exchange with the channel in the whole process, but the threshold voltage of the ferroelectric transistor is affected by an effect similar to polarization. Therefore, in this embodiment, after charge is injected into the charge trapping layer through the back gate, the logic function of the ferroelectric transistor has been determined and will not be reset with the operation of the logic circuit. And the discharge of the charge trapping layer through the back gate can realize the switching of the logic function, thus also satisfying the "reconfigurability".

在一个实施例中，提供了一种基于n型铁电晶体管的逻辑门电路，该逻辑门电路包括上拉电阻(PU)和n型铁电晶体管，上拉电阻与n型铁电晶体管的漏极连接，该逻辑门电路可以实现“与非”门和“或非”门之间的切换。其中，n型铁电晶体管的阈值电压可受外界物理场调控，除了将主栅极的输入电压Vin作为一个逻辑输入状态外，还能够利用n型铁电晶体管的铁电极化状态作为逻辑门的另一个输入状态，而漏极的输出电压则为输出信号。在读取输出信号时，通过改变在n型铁电晶体管背栅极上施加的电压Vsub，可以移动Id-Vg特性曲线，从而做到逻辑门在“与非”门(Vsub＝0)和“或非”门(Vsub<0)之间的切换。图3是本实施例中基于n型铁电晶体管的逻辑门电路的Id-Vg特性曲线图，实现“与非”门逻辑时，使衬底背部的电荷俘获层保持在电中性状态。当n型铁电晶体管的输入信号1为“1”时，主栅极施加足够大的正脉冲电压，源极、漏极电压设为0V，背栅极保持悬浮状态(floating)。此时铁电极化正向翻转，n型铁电晶体管的阈值电压变小。相反地输入信号1为“0”时，主栅极施加足够小的负脉冲电压，源极、漏极电压设为0V，背栅极保持悬浮状态。此时铁电极化负向翻转，n型铁电晶体管的阈值电压变大。读取n型铁电晶体管的信息时，源极电压设为0，漏极电压设为Vdd，由主栅输入电压Vin，视为输入信号2：较小的Vin视为“0”，较大的视为“1”。输出信号为n型铁电晶体管漏极的输出电压Vout，低电平为“0”，高电平为“1”。图4是本实施例中基于n型铁电晶体管的逻辑门电路的操作表和真值表，输入信号为“00”时，输出信号“1”；输入信号为“01”、“10”或者“11”时，输出信号“0”。若需要切换成“或非”门逻辑，则先对背栅极施加一定的负电压，使底部的电荷俘获层俘获一定的负电荷。由于底部的电荷俘获层俘获了一定的负电荷，输入信号为“00”、“01”或者“10”时，输出信号“1”；输入信号为“11”时，输出信号“0”。通过本实施例，可减小切换逻辑门所需要的能耗，仅需一次操作，便可长期地将一个逻辑门电路切换成另一种逻辑功能，从而实现具有非易失性的可重构逻辑门的切换。需要说明的是，本实施例相较于传统CMOS晶体管的逻辑电路结构，可以大大减小存储单元与运算单元之间数据搬运带来的时延和功耗；而相较于一般的铁电晶体管的逻辑电路结构，本实施例则能实现可重构逻辑门切换的非易失性，从而进一步降低相关技术中逻辑门工作的能耗，这对实现新型计算架构、改善计算速度与能效、提高电路集成密度具有重要作用。In one embodiment, a logic gate circuit based on an n-type ferroelectric transistor is provided, the logic gate circuit includes a pull-up resistor (PU) and an n-type ferroelectric transistor, the pull-up resistor and the drain of the n-type ferroelectric transistor Pole connection, the logic gate circuit can realize switching between "NAND" gate and "NOR" gate. Among them, the threshold voltage of the n-type ferroelectric transistor can be regulated by the external physical field. In addition to using the input voltage Vin of the main gate as a logic input state, the ferroelectric polarization state of the n-type ferroelectric transistor can also be used as the logic gate. The other input state, while the output voltage at the drain is the output signal. When reading the output signal, by changing the voltage Vsub applied on the back gate of the n-type ferroelectric transistor, the Id-Vg characteristic curve can be moved, so that the logic gate is in the "NAND" gate (Vsub=0) and " Switch between NOR gates (Vsub<0). Fig. 3 is the Id-Vg characteristic curve of the logic gate circuit based on the n-type ferroelectric transistor in this embodiment, when implementing the "NAND" gate logic, the charge trapping layer on the back of the substrate is kept in an electrically neutral state. When theinput signal 1 of the n-type ferroelectric transistor is "1", a sufficiently large positive pulse voltage is applied to the main gate, the source and drain voltages are set to 0V, and the back gate remains in a floating state. At this time, the ferroelectric polarization reverses forward, and the threshold voltage of the n-type ferroelectric transistor becomes smaller. Conversely, when theinput signal 1 is "0", a sufficiently small negative pulse voltage is applied to the main gate, the source and drain voltages are set to 0V, and the back gate remains in a floating state. At this time, the ferroelectric polarization is reversed negatively, and the threshold voltage of the n-type ferroelectric transistor becomes larger. When reading the information of n-type ferroelectric transistors, the source voltage is set to 0, the drain voltage is set to Vdd, and the main gate input voltage Vin is regarded as input signal 2: the smaller Vin is regarded as "0", the larger is regarded as "1". The output signal is the output voltage Vout of the drain of the n-type ferroelectric transistor, the low level is "0", and the high level is "1". Fig. 4 is the operation table and the truth table based on the logic gate circuit of n-type ferroelectric transistor in the present embodiment, when the input signal is "00", output signal "1"; Input signal is "01", "10" or When "11", output signal "0". If it is necessary to switch to "NOR" gate logic, first apply a certain negative voltage to the back gate, so that the charge trapping layer at the bottom captures a certain negative charge. Since the charge trapping layer at the bottom traps certain negative charges, when the input signal is "00", "01" or "10", the output signal is "1"; when the input signal is "11", the output signal is "0". Through this embodiment, the energy consumption required for switching logic gates can be reduced, and a logic gate circuit can be switched to another logic function for a long time with only one operation, thereby realizing non-volatile reconfigurable Switching of logic gates. It should be noted that, compared with the logic circuit structure of traditional CMOS transistors, this embodiment can greatly reduce the time delay and power consumption caused by data transfer between the storage unit and the operation unit; logic circuit structure, this embodiment can realize the non-volatility of reconfigurable logic gate switching, thereby further reducing the energy consumption of logic gate work in related technologies, which is helpful for realizing new computing architecture, improving computing speed and energy efficiency, and improving Circuit integration density plays an important role.

在一个实施例中，提供了一种基于p型铁电晶体管的逻辑门电路，该逻辑门电路包括上拉电阻(PU)和p型铁电晶体管，上拉电阻与p型铁电晶体管的漏极连接，该逻辑门电路可以实现“或”门和“与”门之间的切换。其中，p型铁电晶体管的阈值电压可受外界物理场调控，除了将主栅极的输入电压Vin作为一个逻辑输入状态外，还能够利用p型铁电晶体管的铁电极化状态作为逻辑门的另一个输入状态，而漏极的输出电压则为输出信号。在读取输出信号时，通过改变在p型铁电晶体管背栅极上施加的电压Vsub，可以移动Id-Vg特性曲线，从而做到逻辑门在“或”门和“与”门之间的切换。图5是本实施例中基于p型铁电晶体管的逻辑门电路的Id-Vg特性曲线图，实现“或”门逻辑时，使衬底背部的电荷俘获层保持在电中性状态。主栅极施加大的正脉冲电压，源极，漏极电压设为0，铁电极化正向翻转时，可看作输入信号1为“1”；反之，主栅极施加负脉冲电压，源极，漏极电压设为0，铁电极化负向翻转时，可看作输入信号1为“0”；读取p型铁电晶体管的信息时，源极电压设为0，漏极电压设为Vdd，由主栅输入读取电压Vin，视为输入信号2：较小的Vin视为“0”，较大的视为“1”。输出信号为p型铁电晶体管的漏极的输出电压Vout，低电平为“0”，高电平为“1”。图6是本实施例中基于p型铁电晶体管的逻辑门电路的操作表和真值表，输入信号为“00”时，输出信号“0”；输入信号为“01”“10”“11”时，输出信号“1”。若需要切换成“与”门逻辑，则先对背栅极施加一定的负电压，使衬底背部的电荷俘获层俘获一定的负电荷。由于底部的电荷俘获层俘获了一定的负电荷，输入信号为“00”“01”“10”时，输出信号“0”；输入信号为“11”时，输出信号“1”。通过本实施例，可减小切换逻辑门所需要的能耗，仅需一次操作，便可长期地将一个逻辑门电路切换成另一种逻辑功能，从而实现具有非易失性的可重构逻辑门的切换。需要说明的是，本实施例相较于传统CMOS晶体管的逻辑电路结构，可以大大减小存储单元与运算单元之间数据搬运带来的时延和功耗；而相较于一般的铁电晶体管的逻辑电路结构，本实施例则能实现可重构逻辑门切换的非易失性，从而进一步降低相关技术中逻辑门工作的能耗，这对实现新型计算架构、改善计算速度与能效、提高电路集成密度具有重要作用。In one embodiment, a logic gate circuit based on a p-type ferroelectric transistor is provided, the logic gate circuit includes a pull-up resistor (PU) and a p-type ferroelectric transistor, the pull-up resistor and the drain of the p-type ferroelectric transistor Pole connection, the logic gate circuit can realize switching between "OR" gate and "AND" gate. Among them, the threshold voltage of the p-type ferroelectric transistor can be regulated by the external physical field. In addition to using the input voltage Vin of the main gate as a logic input state, the ferroelectric polarization state of the p-type ferroelectric transistor can also be used as the logic gate. The other input state, while the output voltage at the drain is the output signal. When reading the output signal, by changing the voltage Vsub applied on the back gate of the p-type ferroelectric transistor, the Id-Vg characteristic curve can be moved, so that the logic gate is between the "OR" gate and the "AND" gate. switch. FIG. 5 is an Id-Vg characteristic curve of a logic gate circuit based on a p-type ferroelectric transistor in this embodiment. When implementing "OR" gate logic, the charge trapping layer on the back of the substrate is kept in an electrically neutral state. A large positive pulse voltage is applied to the main gate, and the source and drain voltages are set to 0. When the ferroelectric polarization is reversed, it can be regarded as theinput signal 1 is "1"; otherwise, the main gate applies a negative pulse voltage, and the source pole, the drain voltage is set to 0, when the ferroelectric polarization is reversed negatively, it can be regarded as theinput signal 1 is "0"; when reading the information of the p-type ferroelectric transistor, the source voltage is set to 0, and the drain voltage is set to It is Vdd, and the voltage Vin is read from the main gate input, which is regarded as input signal 2: the smaller Vin is regarded as "0", and the larger one is regarded as "1". The output signal is the output voltage Vout of the drain of the p-type ferroelectric transistor, the low level is "0", and the high level is "1". Fig. 6 is the operation table and the truth table of the logic gate circuit based on p-type ferroelectric transistor in the present embodiment, when the input signal is "00", the output signal is "0"; the input signal is "01", "10" and "11" ", output signal "1". If it is necessary to switch to "AND" gate logic, a certain negative voltage is first applied to the back gate, so that the charge trapping layer on the back of the substrate captures a certain negative charge. Since the charge trapping layer at the bottom traps certain negative charges, when the input signal is "00", "01" and "10", the output signal is "0"; when the input signal is "11", the output signal is "1". Through this embodiment, the energy consumption required for switching logic gates can be reduced, and a logic gate circuit can be switched to another logic function for a long time with only one operation, thereby realizing non-volatile reconfigurable Switching of logic gates. It should be noted that, compared with the logic circuit structure of traditional CMOS transistors, this embodiment can greatly reduce the time delay and power consumption caused by data transfer between the storage unit and the operation unit; logic circuit structure, this embodiment can realize the non-volatility of reconfigurable logic gate switching, thereby further reducing the energy consumption of logic gate work in related technologies, which is helpful for realizing new computing architecture, improving computing speed and energy efficiency, and improving Circuit integration density plays an important role.

应该明白的是，这里描述的具体实施例只是用来解释这个应用，而不是用来对它进行限定。根据本申请提供的实施例，本领域普通技术人员在不进行创造性劳动的情况下得到的所有其它实施例，均属本申请保护范围。It should be understood that the specific embodiments described here are only used to illustrate the application, not to limit it. According to the embodiments provided in the present application, all other embodiments obtained by persons of ordinary skill in the art without creative work shall fall within the scope of protection of the present application.

显然，附图只是本申请的一些例子或实施例，对本领域的普通技术人员来说，也可以根据这些附图将本申请适用于其他类似情况，但无需付出创造性劳动。另外，可以理解的是，尽管在此开发过程中所做的工作可能是复杂和漫长的，但是，对于本领域的普通技术人员来说，根据本申请披露的技术内容进行的某些设计、制造或生产等更改仅是常规的技术手段，不应被视为本申请公开的内容不足。Apparently, the drawings are only some examples or embodiments of the present application, and those skilled in the art can also apply the present application to other similar situations according to these drawings, but no creative work is required. In addition, it can be understood that although the work done in this development process may be complicated and lengthy, for those of ordinary skill in the art, certain designs, manufactures based on the technical content disclosed in this application Or production and other changes are only conventional technical means, and should not be regarded as insufficient in the content disclosed in this application.

“实施例”一词在本申请中指的是结合实施例描述的具体特征、结构或特性可以包括在本申请的至少一个实施例中。该短语出现在说明书中的各个位置并不一定意味着相同的实施例，也不意味着与其它实施例相互排斥而具有独立性或可供选择。本领域的普通技术人员能够清楚或隐含地理解的是，本申请中描述的实施例在没有冲突的情况下，可以与其它实施例结合。The term "an embodiment" in this application means that a specific feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply mutual exclusion or independence or alternatives to other embodiments. Those of ordinary skill in the art can clearly or implicitly understand that the embodiments described in this application can be combined with other embodiments without conflict.

以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对专利保护范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请的保护范围应以所附权利要求为准。The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the protection scope of the patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be determined by the appended claims.

Claims (10)

1. A logic gate circuit, comprising: the ferroelectric transistor comprises a pull-up resistor and a ferroelectric transistor, wherein a main grid, a channel and a back grid are sequentially arranged in the ferroelectric transistor from top to bottom, two ends of the channel are respectively provided with a source electrode and a drain electrode, a ferroelectric layer and an interface layer are sequentially arranged between the main grid and the channel from top to bottom, and a blocking oxide layer, a charge trapping layer and a tunneling oxide layer are sequentially arranged between the channel and the back grid from top to bottom; the pull-up resistor is connected with the drain electrode.

2. The logic gate circuit according to claim 1, wherein the material from which the blocking oxide layer is made comprises Al₂ O₃ The material of which the charge trapping layer is made comprises Si₃ N₄ The tunneling oxide layer is made of SiO₂ 。

3. The logic gate circuit according to claim 2, wherein the blocking oxide layer is grown by atomic layer deposition of a layer of Al₂ O₃ Forming; the charge trapping layer grows a layer of Si by chemical vapor deposition₃ N₄ Forming; the tunneling oxide layer grows a layer of SiO through an atomic layer deposition method₂ And (5) forming.

4. The logic gate circuit according to claim 1, wherein the material from which the ferroelectric layer is made comprises HfZrO_X The material of which the interface layer is made comprises SiO₂ 。

5. The logic gate circuit according to claim 4, wherein the ferroelectric layer is grown by atomic layer deposition as a layer of HfZrO_X Forming the interface layer by growing a layer of SiO through an ozone oxidation method₂ And (5) forming.

6. The logic gate circuit of claim 1 wherein the ferroelectric transistor constitutes a first logic gate when the charge trapping layer of the ferroelectric transistor is maintained in a charge neutral state.

7. The logic gate circuit of claim 6, wherein the charge trapping layer of the ferroelectric transistor is in a negative charge trapping state when a first preset voltage is applied to the back gate of the ferroelectric transistor, the function performed by the ferroelectric transistor is switched from a first logic gate to a second logic gate, and the ferroelectric transistor maintains the function of the second logic gate after the first preset voltage is removed.

8. The logic gate circuit of claim 7, wherein for an n-type ferroelectric transistor, the first logic gate is a nand gate and the second logic gate is a nor gate; for a p-type ferroelectric transistor, the first logic gate is an or gate and the second logic gate is an and gate.

9. The logic gate circuit according to claim 6, wherein when a second preset voltage is applied to the main gate of the ferroelectric transistor, the ferroelectric transistor undergoes ferroelectric polarization forward inversion, and the threshold voltage of the ferroelectric transistor becomes smaller.

10. The logic gate circuit according to claim 6, wherein when a third preset voltage is applied to the main gate of the ferroelectric transistor, the ferroelectric transistor undergoes a negative reversal of ferroelectric polarization, and the threshold voltage of the ferroelectric transistor becomes large.

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