CN116013846A - Semiconductor structure and forming method thereof - Google Patents

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the structure comprises: a semiconductor substrate comprising a first surface; a metal isolation structure located in and penetrating through the semiconductor substrate; at least one dielectric layer positioned on the first surface of the semiconductor substrate; the metal connecting structure is positioned in the at least one dielectric layer and is electrically connected with the metal isolation structure; the metal connecting structure and the metal isolating structure are positioned on two sides of the pre-designed through silicon via structure. According to the semiconductor structure and the forming method thereof, the metal isolation structure and the metal connection structure are formed on the two sides of the through silicon via structure, so that crosstalk and coupling noise between the through silicon via structures can be reduced under the condition that the performance of the device is not affected, and the reliability of the device is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In some 3D integrated circuit processes, through silicon via structures (Through Silicon Via, TSVs) are used to connect wafers in the vertical direction to shorten the connection, thereby reducing the continuous resistance (Rc) delay to achieve higher bandwidth. Since one of the advantages of using TSVs is that the density of the metal layers connecting the TSVs is higher, crosstalk and coupling noise can occur between these transistors.

To suppress crosstalk and coupling noise, additional circuitry is required, which generates additional heat. This will raise the temperature of the chip and exponentially increase the leakage of the circuit. To improve the performance of stacked chips, we need to reduce crosstalk and coupling noise between TSVs.

Therefore, there is a need to provide a more efficient and reliable solution.

Disclosure of Invention

The semiconductor structure and the forming method thereof can reduce crosstalk and coupling noise between through silicon via structures and improve device reliability under the condition of not affecting device performance.

One aspect of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface; forming a metal isolation structure penetrating through the semiconductor substrate in the semiconductor substrate; forming at least one dielectric layer on the first surface of the semiconductor substrate; forming a metal connection structure in the at least one dielectric layer, wherein the metal connection structure is electrically connected with the metal isolation structure; the metal connecting structure and the metal isolating structure are positioned on two sides of the pre-designed through silicon via structure.

In some embodiments of the present application, a method of forming a metal isolation structure in the semiconductor substrate that extends through the semiconductor substrate includes: forming a metal isolation structure in the semiconductor substrate; and thinning the second surface of the semiconductor substrate until the metal isolation structure is exposed.

In some embodiments of the present application, the through silicon via structure extends through the at least one dielectric layer and the semiconductor substrate.

In some embodiments of the present application, the through-silicon via structure includes a through-silicon via and a top metal, the top metal being located on a surface of the plurality of first dielectric layers and electrically connected to the through-silicon via.

In some embodiments of the present application, the method for forming a semiconductor structure further includes: and forming an interlayer dielectric layer on the second surface of the semiconductor substrate.

In some embodiments of the present application, the through silicon via structure extends through the at least one dielectric layer, the semiconductor substrate, and the interlayer dielectric layer.

In some embodiments of the present application, the through-silicon via structure includes a through-silicon via, a top metal, and a bottom metal, where the top metal and the bottom metal are located at two ends of the through-silicon via, the top metal is located on the surfaces of the plurality of first dielectric layers, and the bottom metal is located on the surface of the interlayer dielectric layer.

In some embodiments of the present application, the at least one dielectric layer includes a first dielectric layer and a second dielectric layer stacked in sequence, and the metal connection structure includes a first metal connection structure located in the first dielectric layer and a second metal connection structure located in the second dielectric layer.

In some embodiments of the present application, the method for forming the at least one dielectric layer and the metal connection structure includes: forming a first dielectric layer on the first surface of the semiconductor substrate; forming a first metal connection structure penetrating through the first dielectric layer and electrically connected with the metal isolation structure in the first dielectric layer; forming a second dielectric layer on the surface of the first dielectric layer; and forming a second metal connection structure penetrating through the second dielectric layer and electrically connected with the first metal connection structure in the second dielectric layer.

In some embodiments of the present application, the location of the metal isolation structure corresponds to the location of the metal connection structure.

In some embodiments of the present application, the sidewall of the metal isolation structure is further formed with an insulating layer.

Another aspect of the present application also provides a semiconductor structure, comprising: a semiconductor substrate comprising a first surface; a metal isolation structure located in and penetrating through the semiconductor substrate; at least one dielectric layer positioned on the first surface of the semiconductor substrate; the metal connecting structure is positioned in the at least one dielectric layer and is electrically connected with the metal isolation structure; the metal connecting structure and the metal isolating structure are positioned on two sides of the pre-designed through silicon via structure.

In some embodiments of the present application, the through silicon via structure extends through the at least one dielectric layer and the semiconductor substrate.

In some embodiments of the present application, the through-silicon via structure includes a through-silicon via and a top metal, the top metal being located on a surface of the plurality of first dielectric layers and electrically connected to the through-silicon via.

In some embodiments of the present application, the semiconductor structure further comprises: and the interlayer dielectric layer is positioned on the second surface of the semiconductor substrate.

In some embodiments of the present application, the through silicon via structure extends through the at least one dielectric layer, the semiconductor substrate, and the interlayer dielectric layer.

In some embodiments of the present application, the through-silicon via structure includes a through-silicon via, a top metal, and a bottom metal, where the top metal and the bottom metal are located at two ends of the through-silicon via, the top metal is located on the surfaces of the plurality of first dielectric layers, and the bottom metal is located on the surface of the interlayer dielectric layer.

In some embodiments of the present application, the at least one dielectric layer includes a first dielectric layer and a second dielectric layer stacked in sequence, and the metal connection structure includes a first metal connection structure located in the first dielectric layer and a second metal connection structure located in the second dielectric layer.

In some embodiments of the present application, the location of the metal isolation structure corresponds to the location of the metal connection structure.

In some embodiments of the present application, the sidewall of the metal isolation structure is further formed with an insulating layer.

The application provides a semiconductor structure and a forming method thereof, wherein metal isolation structures and metal connection structures are formed on two sides of a through silicon via structure, so that crosstalk and coupling noise between the through silicon via structures can be reduced without affecting the performance of the device, and the reliability of the device is improved.

Drawings

The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale. Wherein:

FIG. 1 is a schematic diagram of a semiconductor structure;

FIG. 2 is a schematic diagram of another semiconductor structure;

Fig. 3-11 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to some embodiments of the present application;

fig. 12 to 19 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to other embodiments of the present application.

Detailed Description

The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.

Fig. 1 is a schematic diagram of a semiconductor structure.

Referring to fig. 1, the semiconductor structure includes: asemiconductor substrate 100, thesemiconductor substrate 100 including a first surface and a second surface (i.e., an upper surface and a lower surface in the drawing).

With continued reference to fig. 1, a firstdielectric layer 110 is formed on a first surface of thesemiconductor substrate 100, and a seconddielectric layer 120 is formed on a second surface of thesemiconductor substrate 100.

With continued reference to fig. 1, the semiconductor structure further includes a through silicon via structure extending through thesemiconductor substrate 100, the firstdielectric layer 110, and the seconddielectric layer 120. The through silicon via structure comprises a through silicon via 130, atop metal 131 and abottom metal 132, wherein thetop metal 131 and thebottom metal 132 are respectively located at two ends of the through silicon via 130, thetop metal 131 is located on the surface of the firstdielectric layer 110, and thebottom metal 132 is located on the surface of the seconddielectric layer 132.

Fig. 2 is a schematic diagram of another semiconductor structure.

Referring to fig. 2, the semiconductor structure includes: asemiconductor substrate 200, thesemiconductor substrate 200 comprising a first surface (i.e. the upper surface in the figure).

With continued reference to fig. 2, a firstdielectric layer 210 is formed on a first surface of thesemiconductor substrate 200.

With continued reference to fig. 2, the semiconductor structure further includes a through silicon via structure extending through thesemiconductor substrate 200 and the firstdielectric layer 210. The through-silicon via structure includes a through-silicon via 220 and atop metal 221, thetop metal 221 being located on the surface of the firstdielectric layer 210 and electrically connected to the through-silicon via 220.

The two semiconductor structures shown in fig. 1 and 2 are two different structures in a 3D wafer package structure, respectively. The main difference between the semiconductor structures of fig. 1 and 2 is that the back side (second surface) of the semiconductor substrate of the structure shown in fig. 1 has a second dielectric layer.

As shown with reference to fig. 1 and 2, in both semiconductor structures, crosstalk and coupling noise can occur between adjacent through-silicon via structures, thereby affecting device reliability. While there are some approaches to reduce crosstalk and coupling noise (e.g., adding circuitry to reduce crosstalk and coupling noise in a semiconductor substrate), this in turn results in the semiconductor substrate generating more heat and also affects device performance. It is a challenge to reduce crosstalk and coupling noise between through-silicon via structures without affecting device performance.

In view of the above problems, the present application provides a semiconductor structure and a forming method thereof, in which a metal isolation structure and a metal connection structure are formed on two sides of a through silicon via structure, so that crosstalk and coupling noise between through silicon via structures can be reduced without affecting performance of a device, and reliability of the device is improved.

As described above, the 3D wafer package structure mainly has two different structures as shown in fig. 1 and 2. Therefore, in the technical solution of the present application, two embodiments are respectively designed for these two different structures. The technical solutions described in the present application are described in detail below with reference to the accompanying drawings and these two embodiments.

Fig. 3-12 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to some embodiments of the present disclosure.

Referring to fig. 3, asemiconductor substrate 300 is provided, thesemiconductor substrate 300 including a first surface and a second surface (i.e., an upper surface and a lower surface in the drawing).

In some embodiments of the present application, the material of thesemiconductor substrate 300 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above. In addition, thesemiconductor substrate 300 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, thesemiconductor substrate 300 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

Referring to fig. 4, ametal isolation structure 310 is formed in thesemiconductor substrate 300. Themetal isolation structures 310 are located on both sides of the pre-designed through-silicon via structure. The through-silicon via structure is formed in a subsequent process, which will be described later. Themetal isolation structures 310 are used to isolate adjacent through-silicon via structures to reduce cross-talk and coupling noise between adjacent through-silicon via structures.

It should be noted that, although only three metal isolation structures are shown in the drawings, it should be understood that the number of metal isolation structures is related to the number of through silicon via structures. In some embodiments of the present application, the number ofmetal isolation structures 310 is one greater than the number of through silicon via structures. This ensures that exactly one through silicon via structure is sandwiched between every twometal isolation structures 310. I.e., a minimum number ofmetal isolation structures 310 are used for the purpose of reducing crosstalk and coupling noise. Of course, in other embodiments of the present application, the number ofmetal isolation structures 310 may be greater, such as sandwiching a through-silicon via structure every three or every fourmetal isolation structures 310.

In some embodiments of the present application, the method for forming themetal isolation structure 310 in thesemiconductor substrate 300 is, for example: forming a plurality of first trenches in thesemiconductor substrate 300; themetal isolation structures 310 are formed by filling metal materials in the plurality of first trenches.

In some embodiments of the present application, the material of themetal isolation structure 310 includes at least one of copper, tungsten, aluminum, and the like.

In some embodiments of the present application, the width of themetal isolation structure 310 is one third to two thirds of the distance between adjacent through-silicon via structures.

In some embodiments of the present application, the sidewall and bottom of themetal isolation structure 310 are further formed with an insulating layer (not shown in the figures). Themetal isolation structure 310 cannot directly contact thesemiconductor substrate 300, and thus an insulating layer may be used to isolate themetal isolation structure 310 from thesemiconductor substrate 300.

Referring to fig. 5, the second surface of thesemiconductor substrate 300 is thinned to expose themetal isolation structures 310.

In some embodiments of the present application, the method for thinning the second surface of thesemiconductor substrate 300 includes a chemical mechanical polishing process.

Referring to fig. 6, aninterlayer dielectric layer 340 is formed on the second surface of thesemiconductor substrate 300.

In some embodiments of the present application, the method for forming theinterlayer dielectric layer 340 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The material of theinterlayer dielectric layer 340 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

Referring to fig. 7 to 10, at least onedielectric layer 320 is formed on the first surface of thesemiconductor substrate 300; ametal connection structure 330 is formed in the at least onedielectric layer 320, and themetal connection structure 330 is electrically connected to themetal isolation structure 310. Wherein themetal connection structure 330 is located at two sides of the pre-designed through silicon via structure. In some embodiments of the present application, the location of themetal isolation structure 310 corresponds to the location of themetal connection structure 330. The correspondence refers to the projection coincidence of themetal isolation structure 310 and themetal connection structure 330 in the vertical direction. Themetal isolation structures 330 are used to reduce cross-talk and coupling noise between through-silicon via structures.

In some embodiments of the present application, the at least onedielectric layer 320 includes a firstdielectric layer 321 and asecond dielectric layer 322 stacked in sequence, and themetal connection structure 330 includes a firstmetal connection structure 331 located in thefirst dielectric layer 321 and a secondmetal connection structure 332 located in thesecond dielectric layer 322.

In some embodiments of the present application, the thickness of the at least onedielectric layer 320 is 5-7 times the thickness of theinterlayer dielectric layer 340. Because the thickness of theinterlayer dielectric layer 340 is thinner than that of the whole semiconductor structure, the crosstalk and coupling noise of the adjacent through silicon via structure in theinterlayer dielectric layer 340 are less, and the influence on the whole device is less; and because the thickness of theinterlayer dielectric layer 340 is thin, it is inconvenient to fabricate devices in theinterlayer dielectric layer 340. Thus, in some embodiments of the present application,metal isolation structures 310 andmetal connection structures 330 are formed only in thesemiconductor substrate 300 and in the at least onedielectric layer 320 to reduce cross-talk and coupling noise between through-silicon via structures, without fabricating corresponding devices in theinterlayer dielectric layer 340 to reduce cross-talk and coupling noise between through-silicon via structures.

Of course, in other embodiments of the present application, corresponding devices (e.g., structures similar to themetal isolation structures 310 and the metal connection structures 330) may also be fabricated in theinterlayer dielectric layer 340 to reduce cross-talk and coupling noise between through-silicon via structures.

Referring to fig. 7, a firstdielectric layer 321 is formed on a first surface of thesemiconductor substrate 300.

In some embodiments of the present application, the method for forming thefirst dielectric layer 321 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The material of thefirst dielectric layer 321 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

Referring to fig. 8, a firstmetal connection structure 331 penetrating thefirst dielectric layer 321 and electrically connecting themetal isolation structure 310 is formed in thefirst dielectric layer 321.

In some embodiments of the present application, the method of forming the firstmetal connection structure 331 includes: forming a second trench penetrating thefirst dielectric layer 321 and exposing themetal isolation structure 310 in thefirst dielectric layer 321; and filling a metal material in the second groove to form the firstmetal connection structure 331. The material of the firstmetal connection structure 331 includes at least one of copper, tungsten, aluminum, and the like.

In some embodiments of the present application, the sidewalls and the bottom of the firstmetal connection structure 331 may be further sequentially formed with a seed layer, a barrier layer, and the like (not shown in the drawings).

Referring to fig. 9, asecond dielectric layer 322 is formed on the surface of thefirst dielectric layer 321.

In some embodiments of the present application, the method of forming thesecond dielectric layer 322 includes a chemical vapor deposition process, a physical vapor deposition process, or the like. The material of thesecond dielectric layer 322 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

Referring to fig. 10, a secondmetal connection structure 332 penetrating thesecond dielectric layer 322 and electrically connecting the firstmetal connection structure 331 is formed in thesecond dielectric layer 322.

In some embodiments of the present application, the method of forming the secondmetal connection structure 332 includes: forming a third trench in thesecond dielectric layer 322, penetrating thesecond dielectric layer 322 and exposing the firstmetal connection structure 331; and filling a metal material in the third trench to form the secondmetal connection structure 332. The material of the secondmetal connection structure 332 includes at least one of copper, tungsten, aluminum, and the like.

In some embodiments of the present application, the sidewalls and the bottom of the secondmetal connection structure 332 may be further formed with a seed layer, a barrier layer, and the like (not shown in the drawings) in sequence.

The embodiment of the present application uses only two dielectric layers (thefirst dielectric layer 321 and the second dielectric layer 322) and two metal connection structures (the firstmetal connection structure 331 and the second metal connection structure 332) as examples. It should be understood that the number of the at least onedielectric layer 320 may be greater, and the number of themetal connection structures 330 may be greater.

In some embodiments of the present application, the forming steps of themetal connection structure 330 and the at least onedielectric layer 320 may be performed simultaneously with the forming of the metal interconnection structure at other locations (not shown) on thesemiconductor substrate 300, so as to simplify the process. Accordingly, the specific structure of themetal connection structure 330 is the same as the metal interconnection structure at other locations on thesemiconductor substrate 300. In other embodiments of the present application, themetal connection structure 330 may also be separately manufactured, and the specific structure of themetal connection structure 330 may be the same as that of themetal isolation structure 310.

Referring to fig. 11, a through-silicon via structure is formed in thesemiconductor substrate 300, the at least onedielectric layer 320 and theinterlayer dielectric layer 340, and penetrates the at least onedielectric layer 320, thesemiconductor substrate 300 and theinterlayer dielectric layer 340.

With continued reference to fig. 11, the through-silicon via structure includes a through-silicon via 350, atop metal 351 and abottom metal 352, where thetop metal 351 and thebottom metal 352 are respectively located at two ends of the through-silicon via 350, thetop metal 351 is located on the surfaces of the plurality of firstdielectric layers 320, and thebottom metal 352 is located on the surface of theinterlayer dielectric layer 340.

With continued reference to fig. 11, in some embodiments of the present application, themetal isolation structure 310 and themetal connection structure 330 may be electrically connected to a ground line in a subsequent process. In conventional semiconductor structures, the through-silicon via structure may have metal ions and electrons, etc. escaping, and these escaping metal ions and electrons, etc. flow between adjacent through-silicon via structures, causing cross-talk and coupling noise. In the technical scheme of the application, the metal isolation structures and the metal connection structures which are electrically connected with the grounding wire are formed on two sides of the through silicon via structure, and metal ions, electrons and the like escaping from the through silicon via structure can be guided to the grounding wire by the metal isolation structures and the metal connection structures, so that crosstalk and coupling noise are reduced.

According to the method for forming the semiconductor structure, the metal isolation structures and the metal connection structures are formed on the two sides of the through silicon via structure, so that crosstalk and coupling noise between the through silicon via structures can be reduced under the condition that the performance of the device is not affected, and the reliability of the device is improved.

Some embodiments of the present application further provide a semiconductor structure, as shown with reference to fig. 11, comprising: asemiconductor substrate 300, thesemiconductor substrate 300 comprising a first surface and a second surface; ametal isolation structure 310 located in thesemiconductor substrate 300 and penetrating through thesemiconductor substrate 300; at least onedielectric layer 320 located on the first surface of thesemiconductor substrate 300; ametal connection structure 330 located in the at least onedielectric layer 320 and electrically connected to themetal isolation structure 310; wherein themetal connection structure 330 and themetal isolation structure 310 are located at two sides of the pre-designed through silicon via structure.

Referring to fig. 11, in some embodiments of the present application, the material of thesemiconductor substrate 300 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above. In addition, thesemiconductor substrate 300 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, thesemiconductor substrate 300 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

With continued reference to fig. 11, themetal isolation structures 310 serve to isolate adjacent through-silicon via structures to reduce cross-talk and coupling noise between adjacent through-silicon via structures. Themetal isolation structures 310 are located on both sides of the through-silicon via structure.

It should be noted that, although only three metal isolation structures are shown in the drawings, it should be understood that the number of metal isolation structures is related to the number of through silicon via structures. In some embodiments of the present application, the number ofmetal isolation structures 310 is one greater than the number of through silicon via structures. This ensures that exactly one through silicon via structure is sandwiched between every twometal isolation structures 310. I.e., a minimum number ofmetal isolation structures 310 are used for the purpose of reducing crosstalk and coupling noise. Of course, in other embodiments of the present application, the number ofmetal isolation structures 310 may be greater, such as sandwiching a through-silicon via structure every three or every fourmetal isolation structures 310.

In some embodiments of the present application, the material of themetal isolation structure 310 includes at least one of copper, tungsten, aluminum, and the like.

In some embodiments of the present application, the width of themetal isolation structure 310 is one third to two thirds of the distance between adjacent through-silicon via structures.

In some embodiments of the present application, the sidewall and bottom of themetal isolation structure 310 are further formed with an insulating layer (not shown in the figures). Themetal isolation structure 310 cannot directly contact thesemiconductor substrate 300, and thus an insulating layer may be used to isolate themetal isolation structure 310 from thesemiconductor substrate 300.

With continued reference to fig. 11, the second surface of thesemiconductor substrate 300 is further provided with aninterlayer dielectric layer 340.

In some embodiments of the present application, the material of theinterlayer dielectric layer 340 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

With continued reference to fig. 11, the first surface of thesemiconductor substrate 300 is provided with at least onedielectric layer 320; ametal connection structure 330 is disposed in the at least onedielectric layer 320, and themetal connection structure 330 is electrically connected to themetal isolation structure 310. Wherein themetal connection structure 330 is located at two sides of the through silicon via structure. In some embodiments of the present application, the location of themetal isolation structure 310 corresponds to the location of themetal connection structure 330. The correspondence refers to the projection coincidence of themetal isolation structure 310 and themetal connection structure 330 in the vertical direction. Themetal isolation structures 330 are used to reduce cross-talk and coupling noise between through-silicon via structures.

In some embodiments of the present application, the at least onedielectric layer 320 includes a firstdielectric layer 321 and asecond dielectric layer 322 stacked in sequence, and themetal connection structure 330 includes a firstmetal connection structure 331 located in thefirst dielectric layer 321 and a secondmetal connection structure 332 located in thesecond dielectric layer 322.

In some embodiments of the present application, the thickness of the at least onedielectric layer 320 is 5-7 times the thickness of theinterlayer dielectric layer 340. Because the thickness of theinterlayer dielectric layer 340 is thinner than that of the whole semiconductor structure, the crosstalk and coupling noise of the adjacent through silicon via structure in theinterlayer dielectric layer 340 are less, and the influence on the whole device is less; and because the thickness of theinterlayer dielectric layer 340 is thin, it is inconvenient to fabricate devices in theinterlayer dielectric layer 340. Thus, in some embodiments of the present application, onlymetal isolation structures 310 andmetal connection structures 330 are provided in thesemiconductor substrate 300 and in the at least onedielectric layer 320 to reduce cross-talk and coupling noise between through-silicon via structures, while no corresponding devices are provided in theinterlayer dielectric layer 340 to reduce cross-talk and coupling noise between through-silicon via structures.

Of course, in other embodiments of the present application, corresponding devices (e.g., structures similar to themetal isolation structures 310 and the metal connection structures 330) may also be disposed in theinterlayer dielectric layer 340 to reduce crosstalk and coupling noise between through-silicon via structures.

In some embodiments of the present application, the material of thefirst dielectric layer 321 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

In some embodiments of the present application, the material of the firstmetal connection structure 331 includes at least one of copper, tungsten, aluminum, or the like.

In some embodiments of the present application, the sidewalls and the bottom of the firstmetal connection structure 331 may be further sequentially formed with a seed layer, a barrier layer, and the like (not shown in the drawings).

In some embodiments of the present application, the material of thesecond dielectric layer 322 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

In some embodiments of the present application, the material of the secondmetal connection structure 332 includes at least one of copper, tungsten, aluminum, or the like.

In some embodiments of the present application, the sidewalls and the bottom of the secondmetal connection structure 332 may be further formed with a seed layer, a barrier layer, and the like (not shown in the drawings) in sequence.

The embodiment of the present application uses only two dielectric layers (thefirst dielectric layer 321 and the second dielectric layer 322) and two metal connection structures (the firstmetal connection structure 331 and the second metal connection structure 332) as examples. It should be understood that the number of the at least onedielectric layer 320 may be greater, and the number of themetal connection structures 330 may be greater.

With continued reference to fig. 11, through-silicon via structures are disposed in thesemiconductor substrate 300, the at least onedielectric layer 320, and theinterlayer dielectric layer 340, and the through-silicon via structures penetrate through the at least onedielectric layer 320, thesemiconductor substrate 300, and theinterlayer dielectric layer 340.

With continued reference to fig. 11, the through-silicon via structure includes a through-silicon via 350, atop metal 351 and abottom metal 352, where thetop metal 351 and thebottom metal 352 are respectively located at two ends of the through-silicon via 350, thetop metal 351 is located on the surfaces of the plurality of firstdielectric layers 320, and thebottom metal 352 is located on the surface of theinterlayer dielectric layer 340.

With continued reference to fig. 11, in some embodiments of the present application, themetal isolation structure 310 and themetal connection structure 330 may be electrically connected to a ground line in a subsequent process. In conventional semiconductor structures, the through-silicon via structure may have metal ions and electrons, etc. escaping, and these escaping metal ions and electrons, etc. flow between adjacent through-silicon via structures, causing cross-talk and coupling noise. In the technical scheme of the application, the metal isolation structures and the metal connection structures which are electrically connected with the grounding wire are formed on two sides of the through silicon via structure, and metal ions, electrons and the like escaping from the through silicon via structure can be guided to the grounding wire by the metal isolation structures and the metal connection structures, so that crosstalk and coupling noise are reduced.

According to the semiconductor structure, the metal isolation structures and the metal connection structures are formed on the two sides of the through silicon via structure, so that crosstalk and coupling noise between the through silicon via structures can be reduced under the condition that the performance of the device is not affected, and the reliability of the device is improved.

Fig. 12 to 19 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to other embodiments of the present application.

Referring to fig. 12, asemiconductor substrate 400 is provided, thesemiconductor substrate 400 including a first surface and a second surface (i.e., an upper surface and a lower surface in the drawing).

In some embodiments of the present application, the material of thesemiconductor substrate 400 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above. In addition, thesemiconductor substrate 400 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, thesemiconductor substrate 400 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

Referring to fig. 13, ametal isolation structure 410 is formed in thesemiconductor substrate 400. Themetal isolation structures 410 are located on both sides of the pre-designed through-silicon via structure. The through-silicon via structure is formed in a subsequent process, which will be described later. Themetal isolation structures 410 are used to isolate adjacent through-silicon via structures to reduce cross-talk and coupling noise between adjacent through-silicon via structures.

It should be noted that, although only three metal isolation structures are shown in the drawings, it should be understood that the number of metal isolation structures is related to the number of through silicon via structures. In some embodiments of the present application, the number ofmetal isolation structures 410 is one greater than the number of through silicon via structures. This ensures that exactly one through silicon via structure is sandwiched between every twometal isolation structures 410. I.e., a minimum number ofmetal isolation structures 410 are used for the purpose of reducing crosstalk and coupling noise. Of course, in other embodiments of the present application, the number ofmetal isolation structures 410 may be greater, such as sandwiching a through-silicon via structure every three or every fourmetal isolation structures 410.

In some embodiments of the present application, the method for forming themetal isolation structure 410 in thesemiconductor substrate 400 is, for example: forming a plurality of first trenches in thesemiconductor substrate 400; themetal isolation structures 410 are formed by filling a metal material in the plurality of first trenches.

In some embodiments of the present application, the material of themetal isolation structure 410 includes at least one of copper, tungsten, aluminum, and the like.

In some embodiments of the present application, the width of themetal isolation structure 410 is one third to two thirds of the distance between adjacent through-silicon via structures.

In some embodiments of the present application, the sidewalls and bottom of themetal isolation structure 410 are further formed with an insulating layer (not shown). Themetal isolation structure 410 cannot directly contact thesemiconductor substrate 400, and thus an insulating layer may be used to isolate themetal isolation structure 410 from thesemiconductor substrate 400.

Referring to fig. 14 to 17, at least onedielectric layer 420 is formed on the first surface of thesemiconductor substrate 400; ametal connection structure 430 is formed in the at least onedielectric layer 420, and themetal connection structure 430 is electrically connected to themetal isolation structure 410. Wherein themetal connection structure 430 is located at two sides of the pre-designed through silicon via structure. In some embodiments of the present application, the location of themetal isolation structure 410 corresponds to the location of themetal connection structure 430. The correspondence refers to the projection coincidence of themetal isolation structure 410 and themetal connection structure 430 in the vertical direction. Themetal isolation structures 430 are used to reduce cross-talk and coupling noise between through-silicon via structures.

In some embodiments of the present application, the at least onedielectric layer 420 includes a firstdielectric layer 421 and asecond dielectric layer 422 stacked in sequence, and themetal connection structure 430 includes a firstmetal connection structure 431 located in thefirst dielectric layer 421 and a secondmetal connection structure 432 located in thesecond dielectric layer 422.

Referring to fig. 14, a firstdielectric layer 421 is formed on a first surface of thesemiconductor substrate 400.

In some embodiments of the present application, the method for forming thefirst dielectric layer 421 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The material of thefirst dielectric layer 421 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

Referring to fig. 15, a firstmetal connection structure 431 penetrating thefirst dielectric layer 421 and electrically connecting themetal isolation structure 410 is formed in thefirst dielectric layer 421.

In some embodiments of the present application, the method for forming the firstmetal connection structure 431 includes: forming a second trench in thefirst dielectric layer 421, penetrating thefirst dielectric layer 421 and exposing themetal isolation structure 410; the second trench is filled with a metal material to form the firstmetal connection structure 431. The material of the firstmetal connection structure 431 includes at least one of copper, tungsten, aluminum, and the like.

In some embodiments of the present application, the sidewalls and the bottom of the firstmetal connection structure 431 may be further formed with a seed layer, a barrier layer, and the like (not shown in the drawings) in sequence.

Referring to fig. 16, asecond dielectric layer 422 is formed on the surface of thefirst dielectric layer 421.

In some embodiments of the present application, the method of forming thesecond dielectric layer 422 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The material of thesecond dielectric layer 422 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

Referring to fig. 17, a secondmetal connection structure 432 penetrating thesecond dielectric layer 422 and electrically connecting the firstmetal connection structure 431 is formed in thesecond dielectric layer 422.

In some embodiments of the present application, a method of forming the secondmetal connection structure 432 includes: forming a third trench in thesecond dielectric layer 422, penetrating thesecond dielectric layer 422 and exposing the firstmetal connection structure 431; and filling a metal material in the third trench to form the secondmetal connection structure 432. The material of the secondmetal connection structure 432 includes at least one of copper, tungsten, aluminum, or the like.

In some embodiments of the present application, the sidewalls and bottom of the secondmetal connection structure 432 may be further formed with a seed layer, a barrier layer, and the like (not shown in the drawings) in sequence.

Only two dielectric layers (thefirst dielectric layer 421 and the second dielectric layer 422) and two metal connection structures (the firstmetal connection structure 431 and the second metal connection structure 432) are exemplified in the embodiments of the present application. It should be understood that the number of the at least onedielectric layer 420 may be greater, and the number of themetal connection structures 430 may be greater.

In some embodiments of the present application, the forming steps of themetal connection structure 430 and the at least onedielectric layer 420 may be performed simultaneously with the forming of the metal interconnection structure at other locations (not shown) on thesemiconductor substrate 400, so as to simplify the process. Accordingly, the specific structure of themetal connection structure 430 is the same as the metal interconnection structure at other locations on thesemiconductor substrate 400. In other embodiments of the present application, themetal connection structure 430 may also be manufactured separately, and the specific structure of themetal connection structure 430 may be the same as that of themetal isolation structure 410.

Referring to fig. 18, a through-silicon via structure is formed in thesemiconductor substrate 400 and the at least onedielectric layer 420, the through-silicon via structure extending through the at least onedielectric layer 420 and into thesemiconductor substrate 400, the bottom of the through-silicon via structure being coplanar with the bottom of themetal isolation structure 410.

With continued reference to fig. 18, the through-silicon via structure includes a through-silicon via 450 and atop metal 451, thetop metal 451 being located on the surface of the plurality of firstdielectric layers 420 and electrically connected to the through-silicon via 450.

Referring to fig. 19, the second surface of thesemiconductor substrate 400 is thinned to expose themetal isolation structures 410 and the surface of the through silicon via 450.

In some embodiments of the present application, the method for thinning the second surface of thesemiconductor substrate 400 includes a chemical mechanical polishing process.

With continued reference to fig. 19, in some embodiments of the present application, themetal isolation structure 410 and themetal connection structure 430 may be electrically connected to a ground line in a subsequent process. In conventional semiconductor structures, the through-silicon via structure may have metal ions and electrons, etc. escaping, and these escaping metal ions and electrons, etc. flow between adjacent through-silicon via structures, causing cross-talk and coupling noise. In the technical scheme of the application, the metal isolation structures and the metal connection structures which are electrically connected with the grounding wire are formed on two sides of the through silicon via structure, and metal ions, electrons and the like escaping from the through silicon via structure can be guided to the grounding wire by the metal isolation structures and the metal connection structures, so that crosstalk and coupling noise are reduced.

According to the method for forming the semiconductor structure, the metal isolation structures and the metal connection structures are formed on the two sides of the through silicon via structure, so that crosstalk and coupling noise between the through silicon via structures can be reduced under the condition that the performance of the device is not affected, and the reliability of the device is improved.

Still further embodiments of the present application provide a semiconductor structure, as shown with reference to fig. 19, comprising: asemiconductor substrate 400, thesemiconductor substrate 400 comprising a first surface and a second surface; ametal isolation structure 410 located in thesemiconductor substrate 400 and penetrating through thesemiconductor substrate 400; at least onedielectric layer 420 located on the first surface of thesemiconductor substrate 400; ametal connection structure 430 located in the at least onedielectric layer 420 and electrically connected to themetal isolation structure 410; wherein themetal connection structure 430 and themetal isolation structure 410 are located at two sides of the pre-designed through silicon via structure.

Referring to fig. 19, in some embodiments of the present application, the material of thesemiconductor substrate 400 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above. In addition, thesemiconductor substrate 400 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, thesemiconductor substrate 400 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

With continued reference to fig. 19, themetal isolation structures 410 are used to isolate adjacent through-silicon via structures to reduce cross-talk and coupling noise between adjacent through-silicon via structures. Themetal isolation structures 410 are located on both sides of the through-silicon via structure.

It should be noted that, although only three metal isolation structures are shown in the drawings, it should be understood that the number of metal isolation structures is related to the number of through silicon via structures. In some embodiments of the present application, the number ofmetal isolation structures 410 is one greater than the number of through silicon via structures. This ensures that exactly one through silicon via structure is sandwiched between every twometal isolation structures 410. I.e., a minimum number ofmetal isolation structures 410 are used for the purpose of reducing crosstalk and coupling noise. Of course, in other embodiments of the present application, the number ofmetal isolation structures 410 may be greater, such as sandwiching a through-silicon via structure every three or every fourmetal isolation structures 410.

In some embodiments of the present application, the material of themetal isolation structure 410 includes at least one of copper, tungsten, aluminum, and the like.

In some embodiments of the present application, the width of themetal isolation structure 410 is one third to two thirds of the distance between adjacent through-silicon via structures.

In some embodiments of the present application, the sidewalls and bottom of themetal isolation structure 410 are further formed with an insulating layer (not shown). Themetal isolation structure 410 cannot directly contact thesemiconductor substrate 400, and thus an insulating layer may be used to isolate themetal isolation structure 410 from thesemiconductor substrate 400.

With continued reference to fig. 19, the first surface of thesemiconductor substrate 400 is provided with at least onedielectric layer 420; ametal connection structure 430 is disposed in the at least onedielectric layer 420, and themetal connection structure 430 is electrically connected to themetal isolation structure 410. Wherein, themetal connection structure 430 is located at two sides of the through silicon via structure. In some embodiments of the present application, the location of themetal isolation structure 410 corresponds to the location of themetal connection structure 430. The correspondence refers to the projection coincidence of themetal isolation structure 410 and themetal connection structure 430 in the vertical direction. Themetal isolation structures 430 are used to reduce cross-talk and coupling noise between through-silicon via structures.

In some embodiments of the present application, the at least onedielectric layer 420 includes a firstdielectric layer 421 and asecond dielectric layer 422 stacked in sequence, and themetal connection structure 430 includes a firstmetal connection structure 431 located in thefirst dielectric layer 421 and a secondmetal connection structure 432 located in thesecond dielectric layer 422.

In some embodiments of the present application, the material of thefirst dielectric layer 421 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

In some embodiments of the present application, the material of the firstmetal connection structure 431 includes at least one of copper, tungsten, aluminum, or the like.

In some embodiments of the present application, the sidewalls and the bottom of the firstmetal connection structure 431 may be further formed with a seed layer, a barrier layer, and the like (not shown in the drawings) in sequence.

In some embodiments of the present application, the material of thesecond dielectric layer 422 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like.

In some embodiments of the present application, the material of the secondmetal connection structure 432 includes at least one of copper, tungsten, aluminum, or the like.

In some embodiments of the present application, the sidewalls and bottom of the secondmetal connection structure 432 may be further formed with a seed layer, a barrier layer, and the like (not shown in the drawings) in sequence.

Only two dielectric layers (thefirst dielectric layer 421 and the second dielectric layer 422) and two metal connection structures (the firstmetal connection structure 431 and the second metal connection structure 432) are exemplified in the embodiments of the present application. It should be understood that the number of the at least onedielectric layer 420 may be greater, and the number of themetal connection structures 430 may be greater.

With continued reference to fig. 19, through-silicon via structures are disposed in thesemiconductor substrate 400 and the at least onedielectric layer 420, and the through-silicon via structures penetrate through the at least onedielectric layer 420 and thesemiconductor substrate 300.

With continued reference to fig. 19, the through-silicon via structure includes a through-silicon via 450 and atop metal 451, thetop metal 451 being located on the surface of the plurality of firstdielectric layers 420 and electrically connected to the through-silicon via 450.

With continued reference to fig. 19, in some embodiments of the present application, themetal isolation structure 410 and themetal connection structure 430 may be electrically connected to a ground line in a subsequent process. In conventional semiconductor structures, the through-silicon via structure may have metal ions and electrons, etc. escaping, and these escaping metal ions and electrons, etc. flow between adjacent through-silicon via structures, causing cross-talk and coupling noise. In the technical scheme of the application, the metal isolation structures and the metal connection structures which are electrically connected with the grounding wire are formed on two sides of the through silicon via structure, and metal ions, electrons and the like escaping from the through silicon via structure can be guided to the grounding wire by the metal isolation structures and the metal connection structures, so that crosstalk and coupling noise are reduced.

According to the semiconductor structure and the forming method thereof, the metal isolation structure and the metal connection structure are formed on the two sides of the through silicon via structure, so that crosstalk and coupling noise between the through silicon via structures can be reduced under the condition that the performance of the device is not affected, and the reliability of the device is improved.

In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.

It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.

Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (20)

1. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface;

forming a metal isolation structure penetrating through the semiconductor substrate in the semiconductor substrate;

forming at least one dielectric layer on the first surface of the semiconductor substrate;

forming a metal connection structure in the at least one dielectric layer, wherein the metal connection structure is electrically connected with the metal isolation structure;

the metal connecting structure and the metal isolating structure are positioned on two sides of the pre-designed through silicon via structure.

2. The method of forming a semiconductor structure of claim 1, wherein forming a metal isolation structure in the semiconductor substrate that extends through the semiconductor substrate comprises:

forming a metal isolation structure in the semiconductor substrate;

and thinning the second surface of the semiconductor substrate until the metal isolation structure is exposed.

3. The method of forming a semiconductor structure of claim 1, wherein the through silicon via structure extends through the at least one dielectric layer and the semiconductor substrate.

4. The method of forming a semiconductor structure of claim 3, wherein said through-silicon via structure comprises a through-silicon via and a top metal, said top metal being located on a surface of said plurality of first dielectric layers and electrically connected to said through-silicon via.

5. The method of forming a semiconductor structure of claim 1, further comprising: and forming an interlayer dielectric layer on the second surface of the semiconductor substrate.

6. The method of forming a semiconductor structure of claim 5, wherein said through silicon via structure extends through said at least one dielectric layer, said semiconductor substrate and said interlevel dielectric layer.

7. The method of forming a semiconductor structure of claim 6, wherein the through-silicon via structure comprises a through-silicon via, a top metal and a bottom metal, wherein the top metal and the bottom metal are located at two ends of the through-silicon via, respectively, the top metal is located on the surfaces of the plurality of first dielectric layers, and the bottom metal is located on the surface of the interlayer dielectric layer.

8. The method of forming a semiconductor structure of claim 1, wherein the at least one dielectric layer comprises a first dielectric layer and a second dielectric layer stacked in sequence, the metal connection structure comprising a first metal connection structure in the first dielectric layer and a second metal connection structure in the second dielectric layer.

9. The method of forming a semiconductor structure of claim 8, wherein forming the at least one dielectric layer and forming the metal connection structure comprises:

Forming a first dielectric layer on the first surface of the semiconductor substrate;

forming a first metal connection structure penetrating through the first dielectric layer and electrically connected with the metal isolation structure in the first dielectric layer;

forming a second dielectric layer on the surface of the first dielectric layer;

and forming a second metal connection structure penetrating through the second dielectric layer and electrically connected with the first metal connection structure in the second dielectric layer.

10. The method of forming a semiconductor structure of claim 1, wherein a location of the metal isolation structure corresponds to a location of the metal connection structure.

11. The method of forming a semiconductor structure of claim 1, wherein the sidewall of the metal isolation structure is further formed with an insulating layer.

12. A semiconductor structure, comprising:

a semiconductor substrate comprising a first surface;

a metal isolation structure located in and penetrating through the semiconductor substrate;

at least one dielectric layer positioned on the first surface of the semiconductor substrate;

the metal connecting structure is positioned in the at least one dielectric layer and is electrically connected with the metal isolation structure;

The metal connecting structure and the metal isolating structure are positioned on two sides of the pre-designed through silicon via structure.

13. The semiconductor structure of claim 12, wherein the through silicon via structure extends through the at least one dielectric layer and the semiconductor substrate.

14. The semiconductor structure of claim 13, wherein the through-silicon via structure comprises a through-silicon via and a top metal located on a surface of the plurality of first dielectric layers and electrically connected to the through-silicon via.

15. The semiconductor structure of claim 12, further comprising: and the interlayer dielectric layer is positioned on the second surface of the semiconductor substrate.

16. The semiconductor structure of claim 15, wherein the through silicon via structure extends through the at least one dielectric layer, the semiconductor substrate, and the interlayer dielectric layer.

17. The semiconductor structure of claim 16, wherein the through-silicon via structure comprises a through-silicon via, a top metal and a bottom metal, wherein the top metal and the bottom metal are located at two ends of the through-silicon via, respectively, the top metal is located at the first dielectric layer surfaces, and the bottom metal is located at the interlayer dielectric layer surface.

18. The semiconductor structure of claim 12, wherein the at least one dielectric layer comprises a first dielectric layer and a second dielectric layer stacked in sequence, the metal connection structure comprising a first metal connection structure in the first dielectric layer and a second metal connection structure in the second dielectric layer.

19. The semiconductor structure of claim 12, wherein a location of the metal isolation structure corresponds to a location of the metal connection structure.

20. The semiconductor structure of claim 12, wherein sidewalls of the metal isolation structure are further formed with an insulating layer.

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