Disclosure of Invention
The embodiment of the application provides an anti-fuse array structure and a memory, and provides a novel layout mode of an anti-fuse array, so that the memory array with the same capacity only occupies a smaller layout area, the space between anti-fuse memory cells is increased on the basis of the original layout area, and the electric isolation effect of electric elements between the anti-fuse memory cells is ensured.
The embodiment of the application provides an anti-fuse array structure, which comprises a plurality of anti-fuse integrated structures, wherein the anti-fuse integrated structures are arranged in an anti-fuse matrix in a bit line extending direction and a word line extending direction, the bit line extending direction and the word line extending direction are intersected, each anti-fuse integrated structure comprises a first anti-fuse storage MOS tube, a first switch tube, a second switch tube and a second anti-fuse storage MOS tube which are sequentially arranged along the extending direction of an active area, the first anti-fuse storage MOS tube, the first switch tube, the second switch tube and the second anti-fuse storage MOS tube share an active area, the extending direction of the active area is intersected with the extending direction of a bit line and the extending direction of the word line respectively, the first switch tube and the second switch tube are controlled by two adjacent word lines respectively, the shared end of the first switch tube and the second switch tube is connected with the bit line, the first anti-fuse storage MOS tube and the second anti-fuse storage MOS tube are controlled by adjacent programming wires respectively, and the programming wires are also used for controlling the adjacent anti-fuse integrated structures in the extending direction of the bit line respectively.
The anti-fuse integrated structure comprises a first anti-fuse storage MOS tube, a second anti-fuse storage MOS tube, a first switch tube and a second switch tube, wherein the first anti-fuse storage MOS tube and the second anti-fuse storage MOS tube are controlled through adjacent programming wires, namely two anti-fuse storage units are controlled through adjacent programming wires, the first switch tube and the second switch tube serve as switch tubes of the anti-fuse storage units and are controlled through adjacent word lines, the extending direction of the programming wires is the same as the extending direction of the word lines in the anti-fuse array, namely the extending direction of the programming wires is perpendicular to the extending direction of the bit lines, the programming wires are also used for controlling two adjacent anti-fuse integrated structures which are connected on the same bit line in the extending direction of the bit lines, the same programming wires are used for controlling one anti-fuse storage unit in the adjacent two anti-fuse integrated structures, the two anti-fuse storage units respectively belong to the two adjacent anti-fuse integrated structures, so that the layout length of the anti-fuse array is reduced in the extending direction of the bit line, the layout area of the anti-fuse array is increased, and the isolation effect of the anti-fuse storage units in the same layout area is ensured between the anti-fuse array and the original storage unit.
In addition, the active region comprises an active region main body, the length direction of the active region main body is the extending direction of the active region, and the widths of the active region main body are the same in the extending direction of the active region, so that the same interval between active devices in the anti-fuse matrix is ensured, and the electric isolation effect of the active devices in the anti-fuse matrix is further ensured.
In addition, the active region further comprises a protruding portion, the protruding portion is arranged on at least one side of the active region main body, the length of the protruding portion is smaller than that of the active region main body in the extending direction of the active region, and the width of the middle of the active region is larger than that of the two ends of the active region. Through the arrangement of the protruding part, the width-to-length ratio of the active areas where the first switching tube and the second switching tube are located is increased, the electric conduction capacity of the first switching tube and the second switching tube is improved, and the situation that the data read-out errors of the anti-fuse memory unit are caused due to poor electric conduction capacity of the first switching tube and the second switching tube is avoided.
In addition, the active region includes one protruding portion, and the protruding portions of two adjacent active regions are located at different sides of the active region body in a direction perpendicular to the extending direction of the active region.
In addition, in the extending direction of the bit line, the grid electrode of the second anti-fuse storage MOS tube of each anti-fuse integrated structure is connected with the same programming lead with the grid electrode of the first anti-fuse storage MOS tube of the adjacent anti-fuse integrated structure.
In addition, a grid electrode of the first anti-fuse storage MOS tube is connected with a first programming lead, a grid electrode of the first switch tube is connected with a first word line, a source electrode of the first switch tube is connected with the first anti-fuse storage MOS tube, a drain electrode of the second switch tube is connected with a second word line, a source electrode of the second switch tube is connected with the second anti-fuse storage MOS tube, a drain electrode of the second switch tube is connected with the bit line, and a grid electrode of the second anti-fuse storage MOS tube is connected with a second programming lead.
The active region comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region which are sequentially arranged along the extending direction of the active region, wherein the first doped region is an empty end of a first anti-fuse MOS tube, the second doped region is a shared end of the first anti-fuse storage MOS tube and the first switch tube, the third doped region is a shared end of the first switch tube and the second switch tube, the fourth doped region is a shared end of the second switch tube and the second anti-fuse storage MOS tube, the fifth doped region is an empty end of the second anti-fuse MOS tube, and a bit line is electrically connected with the third doped region.
In addition, the anti-fuse array structure further comprises an insulating layer covering the active region, wherein the bit line is arranged on the insulating layer. The insulating layer is also provided with a conductive through hole which exposes the top surface of the third doped region, and the conductive layer is filled with the conductive through hole, one end of the conductive through hole is contacted with the third doped region, and the other end of the conductive through hole is contacted with the bit line so that the bit line is electrically connected with the third doped region. The bit line extension layer is used for connecting the bit line and the conductive layer, so that the stability of electric contact between the bit line and the conductive layer is ensured, and the formed anti-fuse matrix is prevented from having conductive defects.
In addition, the conductive vias are located on the same line in the bit line extending direction, and the conductive vias are located on the same line in the word line extending direction. The positions of the conductive through holes are regularly arranged, so that the subsequent bit lines are arranged along the straight line, and the formation process of the bit lines is simplified.
In addition, the grid electrode of the first anti-fuse storage MOS tube is arranged on the top surface of the active region between the first doping region and the second doping region, the grid electrode of the first switch tube is arranged on the top surface of the active region between the second doping region and the third doping region, the grid electrode of the second switch tube is arranged on the top surface of the active region between the third doping region and the fourth doping region, and the grid electrode of the second anti-fuse storage MOS tube is arranged on the top surface of the active region between the fourth doping region and the fifth doping region.
In addition, the gate buried type of the first antifuse memory MOS transistor is arranged in an active region between the first doping region and the second doping region, the gate buried type of the first switching transistor is arranged in an active region between the second doping region and the third doping region, the gate buried type of the second switching transistor is arranged in an active region between the third doping region and the fourth doping region, and the gate buried type of the second antifuse memory MOS transistor is arranged in an active region between the fourth doping region and the fifth doping region.
In addition, the anti-fuse matrix comprises a plurality of rows of anti-fuse integrated structures arranged along the extending direction of the word lines, wherein the bit lines connected with the first row of anti-fuse integrated structures are first virtual bit lines, and the bit lines connected with the last row of anti-fuse integrated structures are second virtual bit lines. By arranging the virtual bit line at the edge of the anti-fuse matrix, the anti-fuse integrated structure at the edge of the anti-fuse matrix is consistent with the layout environment of the anti-fuse integrated structure in the matrix, so that the defect of the edge anti-fuse memory cell is prevented, and the anti-fuse memory cell cannot work normally.
In addition, the anti-fuse matrix comprises a plurality of rows of anti-fuse integrated structures arranged along the extending direction of the bit lines, wherein the grid electrode of a first anti-fuse MOS tube in the first row of anti-fuse integrated structures is connected with a first virtual programming wire, and the grid electrode of a second anti-fuse MOS tube in the last row of anti-fuse integrated structures is connected with a second virtual programming wire. By arranging the virtual programming wires at the edge of the anti-fuse matrix, the anti-fuse integrated structure at the edge of the anti-fuse matrix is consistent with the layout environment of the anti-fuse integrated structure in the matrix, so that the defect of the edge anti-fuse memory cell is prevented, and the anti-fuse memory cell cannot work normally.
In addition, a grid electrode of a first switching tube in the first row of anti-fuse integrated structures is connected with a first virtual word line, a grid electrode of a second switching tube in the last row of anti-fuse integrated structures is connected with a second virtual word line, wherein a first dotted programming wire and a second virtual programming wire are positioned at the outermost side of an anti-fuse matrix, and the first virtual word line and the second virtual word line are positioned at the secondary outer side of the anti-fuse matrix. By arranging the virtual word line at the edge of the anti-fuse matrix, the anti-fuse integrated structure at the edge of the anti-fuse matrix is consistent with the layout environment of the anti-fuse integrated structure in the matrix, so that the defect of the edge anti-fuse memory cell is prevented, and the anti-fuse memory cell cannot work normally.
The embodiment of the application also provides a memory, which comprises a memory array, wherein the memory array adopts the antifuse array structure.
In the extending direction of the bit line, the layout length of the anti-fuse memory array is reduced, so that the distance between the switch unit and the anti-fuse memory unit in the same active area is increased on the basis of the original layout area and the memory array with the same layout capacity, and the electric isolation effect of electric elements in the memory array formed by the anti-fuse integrated structure is ensured.
Detailed Description
For antifuse memories, the density of the memory array increases, the spacing between antifuse memory cells decreases, and it is difficult to ensure the electrical isolation of electrical components between antifuse memory cells.
An embodiment of the application provides an anti-fuse array structure, and provides a novel layout mode of an anti-fuse array, so that a memory array with the same capacity only occupies a smaller layout area, and therefore, the space between anti-fuse memory cells is increased on the basis of the original layout area, and the electric isolation effect of electric elements between the anti-fuse memory cells is ensured.
Those of ordinary skill in the art will understand that in various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. The claimed application may be practiced without these specific details and with various changes and modifications based on the following embodiments.
Fig. 1 is a schematic circuit diagram of an antifuse integrated structure provided in this embodiment, fig. 2 is a schematic circuit diagram of an antifuse matrix provided in this embodiment, fig. 3 is a schematic diagram of an antifuse memory cell connected to the same programming wire in an adjacent antifuse integrated structure provided in this embodiment, fig. 4 and 5 are schematic plan views of layout structures of antifuse integrated structures provided in this embodiment, fig. 6 is a schematic cross-sectional view of layout structures of one antifuse integrated structure provided in this embodiment, fig. 7 is a schematic cross-sectional view of layout structures of another antifuse integrated structure provided in this embodiment, fig. 8 and 9 are schematic cross-sectional views of layout structures of antifuse matrices provided in this embodiment, fig. 10 and 11 are schematic cross-sectional views of bit lines of an antifuse matrix provided in this embodiment, and the antifuse array structures provided in this embodiment are described in further detail below with reference to the drawings, specifically as follows:
referring to fig. 1 and 2, an antifuse array structure includes:
The plurality of antifuse integrated structures 100 (see fig. 1) are arranged in an antifuse matrix (see fig. 2) in a bit line BL extending direction and a word line WL extending direction, and the bit line BL extending direction and the word line WL extending direction intersect.
The drawings of the present embodiment illustrate an example in which the extending direction of the bit line BL and the extending direction of the word line WL are perpendicular to each other, and are not limited to this embodiment, and in other embodiments, the extending direction of the bit line BL and the extending direction of the word line WL may be appropriately adjusted so that the extending direction of the bit line BL and the extending direction of the word line WL intersect but are not perpendicular.
Referring to fig. 4 and 5, each antifuse integrated structure 100 includes a first antifuse storage MOS 101, a first switching tube 111, a second switching tube 112, and a second antifuse storage MOS 102 sequentially arranged along an extension direction of an active region 200, and the first antifuse storage MOS 101, the first switching tube 111, the second switching tube 112, and the second antifuse storage MOS 102 share the active region 200.
Wherein the extension direction of the active region 200 intersects the extension direction of the bit line BL and the extension direction of the word line WL, respectively.
The first switching tube 111 and the second switching tube 112 are respectively controlled by two adjacent word lines WL, the common ends of the first switching tube 111 and the second switching tube 112 are connected with the bit line BL, the first antifuse memory MOS tube 101 and the second antifuse memory MOS tube are respectively controlled by a programming wire PGM between every two word lines WL, and the programming wire PGM is also used for controlling the adjacent antifuse integrated structure 100 in the extending direction of the bit line BL.
It should be noted that fig. 2 is only a schematic diagram of a portion of the formed antifuse matrix, and is only used to represent the arrangement of the antifuse matrix in the embodiment of the present application, and does not constitute limitation in the number of the bit lines BL, the word lines WL and the program conductors PGM, and in specific use, the number of the corresponding bit lines BL, word lines WL and program conductors PGM may be selected according to the capacity of the required memory array, and in addition, the numerical value in "< >" is only used to distinguish between different bit lines BL, word lines WL or program conductors PGM, and does not constitute limitation of the embodiment.
The anti-fuse integrated structure 100 comprises a first anti-fuse storage MOS tube 101, a second anti-fuse storage MOS tube 102, a first switch tube 111 and a second switch tube 112, wherein the first anti-fuse storage MOS tube 101 and the second anti-fuse storage MOS tube 102 are controlled through adjacent programming wires PGM, namely two anti-fuse storage units are controlled through adjacent programming wires PGM, the first switch tube 111 and the second switch tube 112 serve as switching tubes of the anti-fuse storage units and are controlled through adjacent word lines WL, as known by a person skilled in the art, in an anti-fuse array, the extending direction of the programming wires PGM is the same as the extending direction of the word lines WL, namely the extending direction of the programming wires PGM is perpendicular to the extending direction of the bit lines BL, wherein the programming wires PGM are also used for controlling two adjacent anti-fuse integrated structures 100 arranged along the extending direction of the bit lines BL, the same programming wires PGM are used for controlling one anti-fuse storage unit in the adjacent two anti-fuse integrated structures 100 connected on the same bit line BL, so that the extending direction of the bit lines BL is reduced, the extending direction of the programming wires PGM is the same as the bit line BL, the length of the anti-fuse storage units in the same layout area is increased, and the storage space between the anti-fuse storage units in the same layout area is ensured, and the storage space between the anti-fuse array and the storage area is enlarged.
Specifically, the gate of the first antifuse storage MOS 101 is connected to the first programming wire PGM <1>, the gate of the first switch 111 is connected to the first word line WL <1>, one end of the source or drain is connected to the first antifuse storage MOS 101, the other end is connected to the bit line BL, the gate of the second switch 112 is connected to the second word line WL <2>, one end of the source or drain is connected to the second antifuse storage MOS 102, the other end is connected to the bit line BL, and the gate of the second antifuse storage MOS 102 is connected to the second programming wire PGM <2>.
In addition, referring to fig. 3, for any two adjacent antifuse integrated structures 100 in the direction of bit line BL extension, the gate of the second switching transistor 112 of one antifuse integrated structure 100 is connected to word line WL < n-2>, the gate of the second antifuse memory MOS transistor 102 is connected to programming conductor PGM < m >, the gate of the first antifuse memory MOS transistor 101 of the other antifuse integrated structure 100 is connected to programming conductor PGM < m >, the gate of the first switching transistor 111 is connected to word line WL < n-1>, and for any two adjacent antifuses integrated structures 100 in the direction of bit line BL extension, the first switching transistor 111 and the second switching transistor 112 are both connected to bit line BL < n >.
That is, in the extending direction of the bit line BL, the gate of the second antifuse storage MOS transistor 102 of each antifuse integrated structure 100 is connected to the same programming wire PGM < m > as the gate of the first antifuse storage MOS transistor 101 of the adjacent antifuse integrated structure 100.
It should be noted that, in other examples, it may be configured that the gate of the first antifuse storage MOS transistor of each antifuse integrated structure is connected to the same programming wire as the gate of the second antifuse storage MOS transistor of the adjacent antifuse integrated structure in the direction of bit line extension.
Referring to fig. 4 and 5, for the first antifuse memory MOS transistor 101, the first switching transistor 111, the second switching transistor 112, and the second antifuse memory MOS transistor 102 disposed in the same active region, referring to fig. 5, in one example, the active region 200 includes an active region body, a length direction of the active region body is an extending direction of the active region 200, and widths of the active region body are the same throughout the extending direction of the active region 200 to ensure that a pitch between active devices in an antifuse matrix is the same, and further ensure an electrical isolation effect of the active devices in the antifuse matrix.
Further, the active region further includes a protrusion disposed on at least one side of the active region body, specifically disposed on at least one side of the active region in the length direction. The length of the protruding portion is smaller than the length of the active region body in the extending direction of the active region 200, and the width of the middle of the active region 200 is larger than the width of both ends of the active region 200 in the extending direction of the word line WL. The bump and the active region body are used to form the first switching tube 111 and the second switching tube 112 such that the channel region widths of the first switching tube 111 and the second switching tube 112 are the sum of the widths of the bump and the active region body. Through the arrangement of the protruding portion, the width-to-length ratio of the active areas where the first switch tube 111 and the second switch tube 112 are located is increased, the conductive capacity of the first switch tube 111 and the second switch tube 112 is improved, the first antifuse storage MOS tube 101 and the second antifuse storage MOS tube 102 are guaranteed to flow through enough fusing voltage, the situation that the data read-write errors of the antifuse storage unit are caused due to poor conductive capacity of the first switch tube 111 and the second switch tube 112 is avoided, and in addition, the increase of the width of the middle portion of the active area 200 is convenient for preparing the first switch tube 111 and the second switch tube 112.
In one example, active region 200 includes one protrusion, and for every two adjacent antifuse structures 100 in the same row, the protrusions of adjacent two active regions are located on different sides of the body of active region 200 in a direction perpendicular to the extension of active region 200. The protruding portions of the two adjacent rows of anti-fuse integrated structures 100 are respectively located at different sides of the active region main body, so that the active regions of the two adjacent rows can be closely arranged while the area of the active region is increased, and the area of the anti-fuse array structure is reduced.
In this example, for a pair of adjacent antifuse structures 100 in the same column, the bosses of adjacent two active regions may be located on the same side or different sides of the body of active region 200 in a direction perpendicular to the extension of active region 200, and in another example, referring to fig. 4, active region 200 includes two bosses disposed on opposite sides of the body of the active region, and the bosses are symmetrically disposed based on the body of the active region.
In some embodiments, the orthographic projections of the active region bodies of adjacent two antifuse integrated structures 100 in a plane perpendicular to the direction of extension of the bit line BL at least partially overlap, thereby enabling further reduction of the area of the antifuse array structure.
In some embodiments, the orthographic projections of the active region bodies of adjacent two antifuse integrated structures 100 in a plane perpendicular to the direction in which the bit lines BL extend at least partially overlap along the direction in which the word lines WL extend, thereby enabling further reduction in the area of the antifuse array structure.
Specifically, referring to fig. 6 and 7, the active region 200 includes:
The first doped region 212, the second doped region 222, the third doped region 232, the fourth doped region 242, and the fifth doped region 252 are sequentially arranged along the extension direction of the active region 200.
The active region 200 is surrounded by an isolation region 201, the first doped region 212 is an empty end of the first antifuse storage MOS 101, the second doped region 222 is a common end of the first antifuse storage MOS 101 and the first switch tube 111, the third doped region 232 is a common end of the first switch tube 111 and the second switch tube 112, the fourth doped region 242 is a common end of the second switch tube 112 and the second antifuse storage MOS 102, and the fifth doped region 252 is an empty end of the second antifuse storage MOS 102.
That is, the source of the first antifuse memory MOS transistor 101 is empty, the drain is connected to the drain of the first switching transistor 111, and the source of the first switching transistor 111 is connected to the bit line BL, so that electrical conduction between the first antifuse memory MOS transistor 101 and the bit line BL is achieved after the first switching transistor 111 is turned on. The source electrode of the second anti-fuse storage MOS tube 102 is empty, the drain electrode is connected with the drain electrode of the second switch tube 112, and the source electrode of the second switch tube 112 is connected with the bit line BL so as to realize electric conduction between the second anti-fuse storage MOS tube 102 and the bit line BL after the second switch tube 112 is conducted.
Since the source connection relationship of the first switch tube 111 and the second switch tube 112 is the same, the layout area of the antifuse integrated structure 100 is reduced by sharing the source, that is, by sharing the same doped region by the first switch tube 111 and the second switch tube 112.
For the anti-fuse memory cell, the memory cell is formed after the anti-fuse MOS tube is controlled to be conducted through the programming line PGM, the word line WL controls the switching tube to facilitate the bit line BL to write in storage data, when the corresponding word line WL is gated, the anti-fuse memory cell is electrically connected with the bit line BL, and whether the anti-fuse memory cell is broken down or not can be judged through the discharge speed of the anti-fuse memory cell to the charge of the bit line BL (after the preset time, through comparing the voltage of the bit line BL with the standard voltage), so that 1bit binary data stored in the anti-fuse memory cell is obtained.
In a specific example, referring to fig. 6, the gate of the first antifuse memory MOS transistor 101 is disposed on the top surface of the active region 200 between the first doped region 212 and the second doped region 222, the gate of the first switching transistor 111 is disposed on the top surface of the active region 200 between the second doped region 222 and the third doped region 232, the gate of the second switching transistor 112 is disposed on the top surface of the active region 200 between the third doped region 232 and the fourth doped region 242, and the gate of the second antifuse memory MOS transistor 102 is disposed on the top surface of the active region 200 between the fourth doped region 242 and the fifth doped region 252. Namely, the active areas of the first antifuse memory MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse memory MOS transistor 102 are arranged in a top gate manner.
In a specific example, referring to fig. 7, the gate buried type of the first antifuse memory MOS transistor 101 is disposed in the active region 200 between the first doped region 212 and the second doped region 222, the gate buried type of the first switching transistor 111 is disposed in the active region 200 between the second doped region 222 and the third doped region 232, the gate buried type of the second switching transistor 112 is disposed in the active region 200 between the third doped region 232 and the fourth doped region 242, and the gate buried type of the second antifuse memory MOS transistor 102 is disposed in the active region 200 between the fourth doped region 242 and the fifth doped region 252. I.e. the active areas of the first antifuse memory MOS transistor 101, the first switching transistor 111, the second switching transistor 112, and the second antifuse memory MOS transistor 102 are provided by means of buried gates.
Referring to fig. 6 and 7, the antifuse integrated structure 100 further includes an insulating layer 203 covering the active region 200, and a bit line BL (205) disposed on the insulating layer 203 and electrically connected to the third doped region 232.
Specifically, the insulating layer 200 has a conductive via (not shown) and a conductive layer 204, wherein the conductive via (not shown) exposes a top surface of the third doped region 232, and the conductive layer 204 fills the conductive via (not shown), one end of which is in contact with the third doped region 232, and one end of which is in contact with the BL (205) so that the bit line is electrically connected to the third doped region 232.
For the layout of the antifuse matrix, referring to fig. 8 and 10, the antifuse matrix includes a plurality of rows of antifuse integrated structures 100 arranged in the direction in which the bit lines BL extend, and a plurality of columns of antifuse integrated structures 100 arranged in the direction in which the word lines WL extend, each row of antifuse integrated structures 100 including a plurality of antifuse integrated structures 100 arranged in the direction in which the word lines WL extend, and each column of antifuse integrated structures 100 including a plurality of antifuse integrated structures 100 arranged in the direction in which the bit lines BL extend.
Referring to fig. 9 and 11, the conductive vias are located on the same line in the direction in which the bit line BL extends, and the conductive vias are located on the same line in the direction in which the word line WL extends. The conductive layer 204 (refer to fig. 6 and 7) formed to fill the conductive via is located on the same line in both the extending direction of the word line WL and the extending direction of the bit line BL. By regularly arranging the positions of the conductive through holes, the subsequent BL (205) is arranged along a straight line, and the formation process of the bit line BL (205) is simplified.
In one example, antifuse integrated structures 100 connected by the same word line WL are equally spaced. That is, the spacing between adjacent antifuse integrated structures 100 is equal in the direction of extension of the word line WL, avoiding the presence of smaller spaces between adjacent antifuse integrated structures 100 to undermine the electrical isolation effect of the entire antifuse memory array.
In one example, antifuse integrated structures 100 connected by the same bit line BL are equally spaced. I.e., the spacing between adjacent antifuse integrated structures 100 is equal in the direction of extension of the bit line BL, avoiding the presence of smaller spaces between adjacent antifuse integrated structures 100 to undermine the electrical isolation effect of the antifuse memory array as a whole.
In one example, the bit line BL connected to the first column of antifuse integrated structures 100 is the first Dummy bit line Dummy1, and the bit line BL connected to the last column of antifuse integrated structures 100 is the second Dummy bit line Dummy2. By arranging the virtual bit lines at the edge of the anti-fuse matrix, the anti-fuse integrated structure 100 positioned at the edge of the anti-fuse matrix is ensured to be consistent with the layout environment of the anti-fuse integrated structure in the matrix, so that the defect of the edge anti-fuse memory cell is prevented, and the anti-fuse memory cell cannot work normally.
In one example, the gate of the first memory MOS 101 in the first row of antifuse integrated structure 100 is connected to the first Dummy programming line Dummy3, and the gate of the second memory MOS in the last row of antifuse integrated structure 100 is connected to the second Dummy programming line Dummy4. By arranging the virtual programming wires at the edge of the anti-fuse matrix, the anti-fuse integrated structure 100 positioned at the edge of the anti-fuse matrix is ensured to be consistent with the layout environment of the anti-fuse integrated structure in the matrix, so that the defect of the edge anti-fuse memory cell is prevented, and the anti-fuse memory cell cannot work normally.
Further, the gate of the first switch tube 111 in the first row of anti-fuse integrated structure 100 is connected to the first Dummy word line Dummy5, and the gate of the second switch tube 112 in the last row of anti-fuse integrated structure 100 is connected to the second Dummy word line Dummy6. Wherein the first and second Dummy program conductors Dummy3 and Dummy4 are located at the outermost sides of the antifuse matrix, and the first and second Dummy word lines Dummy5 and Dummy6 are located at the next outer sides of the antifuse matrix. By arranging the virtual word lines at the edge of the anti-fuse matrix, the anti-fuse integrated structure 100 positioned at the edge of the anti-fuse matrix is ensured to be consistent with the layout environment of the anti-fuse integrated structure in the matrix, so that the defect of the edge anti-fuse memory cell is prevented, and the anti-fuse memory cell cannot work normally.
According to the embodiment of the application, the layout length of the anti-fuse memory array is reduced in the extending direction of the bit line, so that the distance between the switch unit and the anti-fuse memory unit in the same active area is increased on the basis of the original layout area and the memory array with the same layout capacity, and the electric isolation effect of the electric elements in the memory array formed by the anti-fuse integrated structure is ensured.
It should be noted that the connection manner of the specific "source" and "drain" defined above is not limited to the embodiment of the present application, and in other embodiments, the connection manner of "drain" instead of "source" and "source" instead of "drain" may be adopted. In addition, in order to highlight the innovative part of the present application, units less closely related to solving the technical problem presented by the present application are not introduced in the present embodiment, but it does not indicate that other units are not present in the present embodiment.
In another embodiment of the present application, a memory array of the memory is provided, where the antifuse array structure provided by the foregoing embodiment is applied as the memory array, and on the basis of the memory array with the same layout area and the same layout capacity, the space between the switch unit and the antifuse memory unit in the same active area is increased, so as to ensure the electrical isolation effect of the electrical element in the memory array formed by the antifuse integrated structure.
Fig. 12 is a schematic diagram of a virtual structure of a memory according to the present embodiment, fig. 13 is a timing diagram of a programming phase and a reading phase of the memory according to the present embodiment, and the memory according to the present embodiment is described in further detail below with reference to the accompanying drawings, which are specifically as follows:
Referring to fig. 12, the memory includes a memory array 403 employing the antifuse array structure provided in the above-described embodiment, a control unit 401 for receiving a Row address signal row_add, a program enable signal pgm_en, and a word line enable signal wl_en, a Row select control unit 402 connected to the memory array 403 and the control unit 401 for generating a program gate signal PGM < n/2:0> according to the Row address signal row_add and the program enable signal pgm_en, and a word line gate signal WL < n:0> according to the Row address signal row_add and the word line enable signal wl_en, and a column select control unit 404 connected to the memory array 403 for turning on corresponding bit lines WL of the memory array 403 according to a bit line gate signal (not shown).
Wherein the program enable signal pgm_en is used to indicate that the program conductor is conductive, the word line enable signal wl_en is used to indicate that the bit line is conductive, the program gate signal PGM < n/2:0> is used to conduct the program conductor PGM in the corresponding memory array 403, and the word line gate signal WL < n:0> is used to conduct the word line WL in the corresponding memory array 403.
Referring specifically to fig. 13, in the programming stage, a program enable signal pgm_en and a Row address signal row_add are provided to generate a program gate signal PGM < n/2:0> to select a corresponding antifuse MOS transistor to be blown to form an antifuse memory cell, and a word line gate signal WL < n:0> is used to control the switching transistor to be opened to perform data writing to the antifuse memory cell through a corresponding bit line BL. In the read-out stage, a word line enable signal wl_en and a Row address signal row_add are provided to generate a word line strobe signal WL < n:0> to select the corresponding antifuse memory cell to be electrically connected to the bit line BL.
Through the common control of the bit line BL and the word line WL, after the corresponding word line WL is gated, the anti-fuse memory cell is electrically connected with the bit line BL, and through the release speed of the anti-fuse memory cell to the charge of the bit line BL (after the preset time, through comparing the voltage of the bit line BL with the standard voltage VREF), whether the anti-fuse memory cell is broken down can be judged, so that 1bit binary data stored in the anti-fuse memory cell can be obtained.
It should be noted that, since the program conductive line PGM in this embodiment is connected to two antifuse memory cells controlled by different word lines WL, that is, the high-level duration required by the program gate signal PGM < n/2:0> needs to cover the time when the word line gate signal WL < n:0> is high twice, so as to complete the programming of data.
It should be noted that, each unit referred to in this embodiment is a logic unit, and in practical application, one logic unit may be one physical unit, or may be a part of one physical unit, or may be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, units less closely related to solving the technical problem presented by the present application are not introduced in the present embodiment, but it does not indicate that other units are not present in the present embodiment.
It should be noted that, in order to highlight the innovative part of the present application, elements which are not very relevant to solving the technical problem presented by the present application are not introduced in the present embodiment, but are not meant to indicate the absence of other elements in the present embodiment, and those skilled in the art will understand that each of the above embodiments is a specific embodiment of the present application, and that various changes may be made in form and detail in practical application without departing from the spirit and scope of the present application.