CN115763400A - Chip fan-out packaging method and chip fan-out packaging part - Google Patents

Abstract

The invention provides a chip fan-out packaging method and a chip fan-out packaging piece, wherein the chip fan-out packaging method comprises the following steps: attaching at least one group of bare chips on a heat dissipation carrier, wherein each group of bare chips comprises at least one bare chip, and each bare chip is in heat conduction connection with the heat dissipation carrier; carrying out plastic package on at least one group of bare chips, and forming a plastic package layer on the heat dissipation slide glass; growing a rewiring layer on the plastic packaging layer; growing a conductive bump on the redistribution layer; cutting the rewiring layer, the plastic packaging layer and the heat dissipation carrier, and separating out at least one chip fan-out packaging piece; wherein each chip fan-out package comprises a group of bare chips. The reliability of large-size chip packaging is improved, and the heat dissipation capacity of fan-out packaging is also improved. Meanwhile, the bare chip can be attached to the radiating slide by adopting a firmer fixing mode, so that the chip offset phenomenon in the process of a wafer plastic package technology is improved, the dislocation between the redistribution layer and the bare chip is reduced, and the high-density redistribution layer is convenient to manufacture.

Description

Chip fan-out packaging method and chip fan-out packaging part

Technical Field

The invention relates to the technical field of chip packaging, in particular to a chip fan-out packaging method and a chip fan-out packaging piece.

Background

The fan-out process is to fan out the input and output interfaces on the bare chip to the conductive bumps on the surface of the redistribution layer through the redistribution layer. In the existing fan-out packaging process, the back surface of a bare chip is bonded on a bearing sheet, and then plastic package, a rewiring layer and a conductive bump of the bare chip are processed under the support of the bearing sheet; then, the bearing sheet and the bare chip are subjected to debonding; and then, carrying out a back gold process on the back surface of the bare chip, and mounting a heat sink on the back surface of the bare chip. In the fan-out packaging process, temporary bonding and debonding treatment needs to be carried out by using a transitional bearing sheet, and a large-size fan-out chip has reliability risk after the temporary bonding is removed due to warping.

Disclosure of Invention

The invention provides a chip fan-out packaging method and a chip fan-out packaging piece, which can improve the packaging reliability of a large-size chip.

In a first aspect, the present invention provides a chip fan-out packaging method, including: attaching at least one group of bare chips on a heat dissipation carrier, wherein each group of bare chips comprises at least one bare chip, and each bare chip is in heat conduction connection with the heat dissipation carrier; carrying out plastic package on at least one group of bare chips, and forming a plastic package layer on the heat dissipation slide; growing a rewiring layer on the plastic packaging layer; growing a conductive bump on the redistribution layer; cutting the rewiring layer, the plastic packaging layer and the heat dissipation carrier, and separating out at least one chip fan-out packaging piece; each chip fan-out package comprises a group of bare chips.

In the scheme, the bare chip is directly attached to the radiating carrier, then the bare chip is subjected to plastic package, the rewiring layer and the conductive bumps are grown under the support of the radiating carrier, finally the rewiring layer, the plastic package layer and the radiating carrier are cut, and at least one chip fan-out package is separated, so that the package of the chip fan-out package can be completed. In the process, a bearing sheet in intermediate transition is not needed, the radiating slide glass is directly used as the bearing sheet, and the temporary bonding is not needed to be removed subsequently, so that the reliability risk of the large-size fan-out chip after the temporary bonding is removed due to warping is avoided, the packaging reliability of the large-size chip is improved, and the radiating capacity of the fan-out package is also improved. Meanwhile, the bare chip can be attached to the radiating carrier by adopting a firmer fixing mode, the chip offset phenomenon in the wafer plastic package process is improved, the dislocation between the rewiring layer and the bare chip is reduced, the high-density rewiring layer is convenient to manufacture, and the difficulty of arranging the radiating fin on the back of the bare chip is also simplified.

In a specific embodiment, the material of the heat dissipation slide is a heat sink material, further improving the heat dissipation capability of the fan-out package.

In a specific implementation mode, the heat sink material is one or more of copper, iron, aluminum, stainless steel, tungsten and molybdenum, so that a proper heat sink material is convenient to select, and meanwhile, the heat dissipation carrier is prepared from a metal material, so that the stability of a packaging structure can be improved, and the reliability of large-size chip packaging can be improved.

In a specific embodiment, each die has opposite front and back sides, wherein the front side of the die is provided with an input-output interface. Attaching at least one set of dies to a heat sink slide includes: and attaching the back surface of each bare chip in at least one group of bare chips to the heat dissipation carrier.

In a specific embodiment, attaching at least one set of dies to a heat sink slide further comprises: the back side of each bare chip in at least one group of bare chips is fixed on the heat dissipation carrier through a metal brazing material. Compared with a bonding connection mode, the die moving and shifting phenomena caused by softening of bonding materials in the wafer plastic packaging process can be avoided, the chip shifting phenomena in the wafer plastic packaging process are improved, dislocation between the redistribution layer and the die is reduced, and the high-density redistribution layer is convenient to manufacture.

In a specific embodiment, the metal brazing material is indium, indium-silver alloy, silver, tin-silver alloy or tin-lead alloy, so that a suitable metal brazing material can be selected conveniently.

In a specific implementation, the soldering flux is sprayed between the metal brazing material and the heat dissipation carrier, and/or the soldering flux is sprayed between the metal brazing material and the back surface of the bare chip, so that the connection firmness between the metal brazing material and the heat dissipation carrier and between the metal brazing material and the bare chip is improved, the chip offset phenomenon in the wafer plastic packaging process is improved, the dislocation between the redistribution layer and the bare chip is reduced, and the manufacture of the high-density redistribution layer is facilitated.

In one specific embodiment, growing a redistribution layer on the molding layer comprises: grinding the plastic packaging layer to expose the input/output interface on the front surface of each bare chip; growing a rewiring layer on the plastic packaging layer, wherein the rewiring layer is provided with a first surface and a second surface which are opposite, the first surface is provided with at least one first interface, and the second surface is provided with at least one second interface; the first surface is attached to the front surface of each bare chip, and each input/output interface is electrically connected with one first interface.

In one particular embodiment, growing the conductive bump on the redistribution layer includes: one conductive bump is grown on each second interface of the second surface of the redistribution layer.

In a second aspect, the invention further provides a chip fan-out package, which is prepared by any one of the chip fan-out packaging methods described above. In the scheme, the bare chip is directly attached to the radiating carrier, then the bare chip is subjected to plastic package, the rewiring layer and the conductive bumps are grown under the support of the radiating carrier, finally the rewiring layer, the plastic package layer and the radiating carrier are cut, and at least one chip fan-out package is separated, so that the package of the chip fan-out package can be completed. In the process, a bearing sheet in intermediate transition is not needed, the radiating slide is directly used as the bearing sheet, and the temporary bonding is not needed to be removed subsequently, so that the reliability risk of the large-size fan-out chip after the temporary bonding is removed due to warping is avoided, the packaging reliability of the large-size chip is improved, and the radiating capacity of the fan-out package is also improved. Meanwhile, the bare chip can be attached to the radiating carrier by adopting a firmer fixing mode, the chip offset phenomenon in the wafer plastic package process is improved, the dislocation between the rewiring layer and the bare chip is reduced, the high-density rewiring layer is convenient to manufacture, and the difficulty of arranging the radiating fin on the back of the bare chip is also simplified.

Drawings

Fig. 1 is a flowchart of a method for packaging a fan-out of a chip according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional view of a structure for attaching a bare chip to a heat sink chip according to an embodiment of the present invention;

fig. 3 is a schematic cross-sectional view of a structure for plastically packaging and growing a redistribution layer and a conductive bump on a bare chip according to an embodiment of the present invention;

fig. 4 is a schematic structural cross-sectional view of a chip fan-out package prepared by a chip fan-out packaging method according to an embodiment of the present invention.

Reference numerals:

10-heat sink carrier 20-metal brazing material 31-first die

311-first input-output interface 32-second die 321-second input-output interface

40-plastic package layer 50-redistribution layer 60-conductive bump

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

For convenience of understanding the chip fan-out packaging method provided by the embodiment of the present invention, an application scenario of the chip fan-out packaging method provided by the embodiment of the present invention is described below. The chip fan-out packaging method is described in detail below with reference to the accompanying drawings.

Referring to fig. 1 to 4, a chip fan-out packaging method provided by an embodiment of the present invention includes:

step10: attaching at least one group of bare chips to aheat dissipation carrier 10, wherein each group of bare chips comprises at least one bare chip, and each bare chip is in heat conduction connection with theheat dissipation carrier 10;

step20: carrying out plastic package on at least one group of bare chips, and forming aplastic package layer 40 on theheat dissipation slide 10;

step30: growing a rewiringlayer 50 on theplastic packaging layer 40;

step40: growing aconductive bump 60 on theredistribution layer 50;

step50: cutting the rewiringlayer 50, theplastic packaging layer 40 and theheat dissipation slide 10 to separate out at least one chip fan-out packaging piece; wherein each chip fan-out package comprises a group of bare chips.

In the above scheme, the bare chip is directly attached to theheat dissipation carrier 10, then the bare chip is subjected to plastic package and growth of theredistribution layer 50 and theconductive bump 60 under the support of theheat dissipation carrier 10, and finally theredistribution layer 50, theplastic package layer 40 and theheat dissipation carrier 10 are cut, and at least one chip fan-out package is separated, so that the package of the chip fan-out package can be completed. In the process, a bearing sheet in middle transition is not needed, theheat dissipation slide 10 is directly used as the bearing sheet, and the temporary bonding is not needed to be removed subsequently, so that the reliability risk of the large-size fan-out chip after the temporary bonding is removed due to warping is avoided, the packaging reliability of the large-size chip is improved, and the heat dissipation capacity of the fan-out package is also improved. Meanwhile, the bare chip can be attached to theradiating slide 10 in a firmer fixing mode, so that the chip offset phenomenon in the wafer plastic package process is improved, the dislocation between theredistribution layer 50 and the bare chip is reduced, the high-density redistribution layer 50 is convenient to manufacture, and the difficulty in arranging radiating fins on the back of the bare chip is also simplified. The above steps will be described in detail with reference to the accompanying drawings.

First, as shown in fig. 1 and 2, at least one set of dies is attached to aheat sink 10. Each of the at least one group of dies includes at least one die, and each die is a die diced from a wafer. Illustratively, as shown in fig. 2, two sets of dies are included, each set including afirst die 31 and asecond die 32. Of course, the number of groups of dies is not limited to the two groups shown in fig. 2, nor is the number of dies included in each group of dies less than two.

As shown in fig. 2, each die has opposite front and back sides, wherein the front side of the die is provided with an input-output interface. Referring to fig. 2, the front surface of eachfirst die 31 is provided with a first input/output interface 311, and the front surface of eachsecond die 32 is provided with a second input/output interface 321. When each die is attached to theheat sink slide 10, each die is in thermally conductive connection with theheat sink slide 10. Specifically, the back surface of each die in at least one group of dies is attached to theheat dissipation carrier 10, so that the back surface of each die is thermally connected to theheat dissipation carrier 10.

In selecting the material of theheat sink sheet 10, theheat sink sheet 10 may be a material with high heat conduction efficiency. For example, the material of theheat dissipating chip 10 may be a heat sink material, further improving the heat dissipation capability of the fan-out package. The heat sink material may be any type of material having heat sink properties. Illustratively, the heat sink material may be one or more of copper, iron, aluminum, stainless steel, tungsten, and molybdenum, so that a suitable heat sink material is conveniently selected, and theheat dissipation carrier 10 is made of a metal material, so as to improve the stability of the package structure and the reliability of large-size chip package.

In thermally connecting the back side of each die to theheat sink carrier 10, the back side of each die in the at least one group of dies may be secured to theheat sink carrier 10 by ametal solder material 20. I.e., adding ametal solder material 20 between each die and theheat sink carrier 10, the back side of each die is soldered to theheat sink carrier 10. When themetal brazing material 20 is selected, themetal brazing material 20 may specifically be indium, indium-silver alloy, silver, tin-silver alloy, or tin-lead alloy, so that a suitablemetal brazing material 20 is selected. Compared with a bonding connection mode, the bare chip and theheat dissipation carrier 10 are welded by themetal brazing material 20, so that the bare chip moving and shifting phenomena caused by softening of the bonding material in the wafer plastic packaging process can be avoided, the chip shifting phenomenon in the wafer plastic packaging process is improved, the dislocation between theredistribution layer 50 and the bare chip is reduced, and the high-density redistribution layer 50 can be manufactured conveniently.

In addition, the soldering flux can be sprayed between themetal soldering material 20 and theheat dissipation carrier 10 and/or between themetal soldering material 20 and the back of the bare chip, so that the connection firmness between themetal soldering material 20 and theheat dissipation carrier 10 as well as between themetal soldering material 20 and the back of the bare chip is improved, the chip offset phenomenon in the wafer plastic package process is improved, the dislocation between theredistribution layer 50 and the bare chip is reduced, and the high-density redistribution layer 50 can be manufactured conveniently. When the soldering flux is sprayed specifically, the soldering flux can be sprayed only between themetal brazing material 20 and theheat dissipation carrier 10; flux may also be sprayed only between themetal braze material 20 and the die; it is even possible to spray flux between both themetallic brazing material 20 and theheat sink slide 10 and between themetallic brazing material 20 and the die.

Next, referring to fig. 1 and 3, at least one group of dies is subjected to plastic molding, and amolding layer 40 is formed on theheat dissipation carrier 10. As shown in fig. 3, themolding compound layer 40 fills the space between the dies and completely wraps the dies around. When the plastic packaging material is selected specifically, the plastic packaging material may be, for example, but not limited to, a plastic packaging material such as epoxy resin.

Next, referring to fig. 1 and 3, aredistribution layer 50 is grown on themolding layer 40, and the input/output interface on the front side of the die is led out through theredistribution layer 50. Specifically, when theredistribution layer 50 is grown on themolding compound layer 40, themolding compound layer 40 may be polished to expose the input/output interface on the front surface of each die. Then, aredistribution layer 50 is grown on themolding layer 40, so that an input/output interface on the front surface of each die can be conveniently led out. As theredistribution layer 50 shown in fig. 3, theredistribution layer 50 has a first surface and a second surface opposite to each other, and in the cross-sectional view shown in fig. 3, the first surface is a lower surface of theredistribution layer 50, and the second surface is an upper surface of theredistribution layer 50. The first surface has at least one first interface, the first surface of theredistribution layer 50 is attached to the front surface of each die, and each input/output interface on the front surface of the die is electrically connected to one first interface. Theredistribution layer 50 also has at least one second interface on the second surface, and each second interface is conductively connected to the corresponding first interface on the first surface of theredistribution layer 50 through the traces and metal holes in theredistribution layer 50, so as to form a signal transmission path "the input/output interface on the front side of the die → the first interface on the first surface of theredistribution layer 50 → the traces and metal holes in theredistribution layer 50 → the second interface on the second surface of theredistribution layer 50", so as to lead out the input/output interface on the front side of the die.

Next, referring to fig. 1 and fig. 3,conductive bumps 60 are grown on theredistribution layer 50, so as to facilitate the subsequent soldering of the packaged chip fan-out package on a printed circuit board, or facilitate the next system-level packaging of the packaged chip fan-out package. Specifically, when theconductive bump 60 is grown on theredistribution layer 50, oneconductive bump 60 is grown on each second interface of the second surface of theredistribution layer 50, and finally, a signal transmission path of "the input/output interface of the front side of the die → the first interface of the first surface of theredistribution layer 50 → the routing and metal hole in theredistribution layer 50 → the second interface of the second surface of the redistribution layer → theconductive bump 60 grown on the second surface" is formed, so as to lead out the input/output interface of the front side of the die. The shape of theconductive bump 60 may be a cylindrical structure, a solder ball structure, a pin structure, or the like, and is particularly related to an application scenario and a packaging process of the package.

Next, referring to fig. 1, fig. 3 and fig. 4, theredistribution layer 50, themolding compound layer 40 and theheat dissipation carrier 10 are cut to separate at least one chip fan-out package, wherein each chip fan-out package includes a group of dies. During cutting, the plastic package material of theplastic package layer 40, theredistribution layer 50 and the like and theheat dissipation carrier 10 need to be cut and separated at the same time, and after cutting, theheat dissipation carrier 10 is reserved on the fan-out chip package as a heat dissipation fin. A chip fan-out package as shown in fig. 4 contains two chips, afirst die 31 and asecond die 32, in a group of dies contained on the chip fan-out package. It should be noted that the chip fan-out package formed by the above chip fan-out packaging method may be used as a final package to perform a subsequent flip-chip process, or may be directly formed into a ball grid array package.

In the above-described various embodiments, the bare chip is directly attached to theheat dissipation carrier 10, then the bare chip is subjected to plastic package and growth of theredistribution layer 50 and theconductive bumps 60 under the support of theheat dissipation carrier 10, and finally theredistribution layer 50, theplastic package layer 40 and theheat dissipation carrier 10 are cut, and at least one chip fan-out package is separated, so that the package of the chip fan-out package can be completed. In the process, a bearing sheet in middle transition is not needed, theheat dissipation slide 10 is directly used as the bearing sheet, and the temporary bonding is not needed to be removed subsequently, so that the reliability risk of the large-size fan-out chip after the temporary bonding is removed due to warping is avoided, the packaging reliability of the large-size chip is improved, and the heat dissipation capacity of the fan-out package is also improved. Meanwhile, the bare chip can be attached to the radiatingslide 10 in a firmer fixing mode, so that the chip offset phenomenon in the wafer plastic package process is improved, the dislocation between theredistribution layer 50 and the bare chip is reduced, the high-density redistribution layer 50 is convenient to manufacture, and the difficulty in arranging radiating fins on the back of the bare chip is also simplified.

In addition, embodiments of the present invention further provide a chip fan-out package, and referring to fig. 1 to 4, the chip fan-out package is prepared by using any one of the above-described chip fan-out packaging methods. The bare chip is directly attached to theheat dissipation carrier 10, then plastic package is carried out on the bare chip under the support of theheat dissipation carrier 10, therewiring layer 50 and theconductive bumps 60 grow, finally therewiring layer 50, theplastic package layer 40 and theheat dissipation carrier 10 are cut, at least one chip fan-out package piece is separated, and then the package of the chip fan-out package piece can be completed. In the process, a bearing sheet in intermediate transition is not needed, theheat dissipation slide 10 is directly used as the bearing sheet, and the temporary bonding is not needed to be removed subsequently, so that the reliability risk of the large-size fan-out chip after the temporary bonding is removed due to warping is avoided, the packaging reliability of the large-size chip is improved, and the heat dissipation capability of the fan-out package is also improved. Meanwhile, the bare chip can be attached to the radiatingslide 10 in a firmer fixing mode, so that the chip offset phenomenon in the wafer plastic package process is improved, the dislocation between theredistribution layer 50 and the bare chip is reduced, the high-density redistribution layer 50 is convenient to manufacture, and the difficulty in arranging radiating fins on the back of the bare chip is also simplified.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A chip fan-out packaging method is characterized by comprising the following steps:

attaching at least one group of bare chips on a heat dissipation slide; wherein each group of bare chips comprises at least one bare chip, and each bare chip is in heat conduction connection with the heat dissipation slide;

carrying out plastic package on the at least one group of bare chips, and forming a plastic package layer on the heat dissipation carrier;

growing a rewiring layer on the plastic packaging layer;

growing a conductive bump on the redistribution layer;

cutting the rewiring layer, the plastic packaging layer and the heat dissipation carrier, and separating out at least one chip fan-out packaging piece; wherein each chip fan-out package comprises a group of bare chips.

2. The chip fan-out packaging method of claim 1, in which a material of the heat dissipation carrier is a heat sink material.

3. The chip fan-out packaging method of claim 2, wherein the heat sink material is one or any of copper, iron, aluminum, stainless steel, tungsten and molybdenum.

4. The chip fan-out packaging method of claim 1, in which each die has opposing front and back sides, wherein the front side is provided with input-output interfaces;

said attaching at least one set of dies on a heat sink slide comprises: attaching a back side of each die of the at least one group of dies to the heat spreader.

5. The chip fan-out packaging method of claim 4, in which the attaching at least one set of dies on a heat sink carrier further comprises:

and fixing the back surface of each bare chip in the at least one group of bare chips on the heat dissipation carrier through a metal brazing material.

6. The chip fan-out packaging method of claim 5, in which the metal solder material is indium, indium silver alloy, silver, tin silver alloy, or tin lead alloy.

7. The chip fan-out packaging method of claim 5, in which a flux is sprayed between the metal brazing material and the heat dissipation carrier, and/or a flux is sprayed between the metal brazing material and the back side of the die.

8. The chip fan-out packaging method of claim 4, in which the growing a redistribution layer on the molding layer comprises:

grinding the plastic packaging layer to expose the input and output interfaces on the front surface of each bare chip;

growing a rewiring layer on the plastic packaging layer, wherein the rewiring layer is provided with a first surface and a second surface which are opposite, the first surface is provided with at least one first interface, and the second surface is provided with at least one second interface; the first surface is attached to the front surface of each bare chip, and each input/output interface is electrically connected with one first interface.

9. The chip fan-out packaging method of claim 8, in which the growing conductive bumps on the redistribution layer comprises:

and growing a conductive bump on each second interface of the second surface of the redistribution layer.

10. A chip fan-out package prepared using the chip fan-out packaging method of any one of claims 1 to 9.

Images