CN115725410B - A field effect cell culture dish system measurement circuit - Google Patents

Abstract

Translated fromChinese

一种场效应细胞培养皿系统测量电路是由放大器阵、ADC阵、微处理器、USB接口等组成。放大器阵与场效应管阵列的传感器一一对应，ADC阵模拟信号输入与放大器阵一一对应，微处理器不断对ADC阵数字信号输出扫描，并以20kHz扫描速率产生中断。中断期间，微处理器对放大器阵所有信号采集一遍，并在时钟脉冲控制下，将采集的所有数据转换成串行数字信号序列从USB接口输出。该测量电路有益之处在于：将细胞培养皿中一个细胞的动作电位通过所对应的场效应传感器转换为漏极电流，并将该电流从传感器阵列中筛选出来，转换为电压加以放大和模数转换，成为数字信号传递给外接的计算机，解决了细胞膜动作电位检测的数字化问题。

A field effect cell culture dish system measurement circuit is composed of an amplifier array, an ADC array, a microprocessor, a USB interface, etc. The amplifier array corresponds one-to-one to the sensors of the field effect tube array, the ADC array analog signal input corresponds one-to-one to the amplifier array, and the microprocessor continuously scans the ADC array digital signal output and generates interrupts at a scanning rate of 20kHz. During the interruption, the microprocessor collects all the signals of the amplifier array, and under the control of the clock pulse, converts all the collected data into a serial digital signal sequence and outputs it from the USB interface. The measurement circuit is beneficial in that the action potential of a cell in the cell culture dish is converted into a drain current through the corresponding field effect sensor, and the current is screened out from the sensor array, converted into a voltage for amplification and analog-to-digital conversion, and becomes a digital signal and is transmitted to an external computer, solving the problem of digitalization of cell membrane action potential detection.

Description

Measuring circuit of field effect cell culture dish system

Technical Field

The invention belongs to the field of biological instruments, relates to a field effect cell culture dish system, and in particular relates to a measuring circuit of a cell culture dish system for detecting cell membrane potential.

Background

Chinese patent 201210282543.8 discloses a field effect cell culture dish system consisting of a cell culture dish body and a measuring circuit. The bottom of the cell culture dish body was made with n×n Field Effect Transistor (FET) sensor arrays, where N is the number of rows and columns of the sensor array. The cell membrane potential is used as the grid electrode of the field effect tube to control the change of the channel resistance of the field effect tube, and the channel current of the field effect tube is the drain-source current of the field effect tube. When the field effect transistor drain potential is constant, the drain-source current is inversely proportional to the channel resistance according to ohm's law. Thus, by detecting the drain-source current of the field effect transistor, the channel resistance can be detected, and the change in the cell membrane potential can be detected from the transfer characteristic of the field effect transistor. The technical requirements of the system measurement circuit are as follows:

(1) Detecting the drain-source current of the field effect transistor. When cells cover a certain sensor on the sensor array, the cell membrane potential controls the grid potential of the field effect transistor sensor, and a measuring circuit is used for detecting the change of drain-source current of the field effect transistor;

(2) At system initialization, sensors with cell coverage are searched. The cells are distributed on the surface of the culture dish in a dispersing way on the field effect tube sensors, some sensors are covered by the cells, and some sensors are not covered by the cells. System initialization is to find out the sensors with cell coverage. The cells are randomly distributed, the sensors with cell coverage are also randomly distributed, and the measuring circuit is used for searching all the field effect tube sensors with cell coverage in the sensor array;

(3) The system is free to select a sensor of interest in the sensor array and connect an amplifier to the selected sensor during operation. Among all the sensors that were searched for cell coverage, some sensors were of interest in cell membrane potential and some were not. The measuring circuit is to be positioned on the sensor of interest, connecting the amplifier freely to the selected sensor of interest;

(4) The temperature of the bottom of the cell culture dish is reduced. If all field effect transistors on the cell culture dish bottom field effect transistor sensor array are operated, the operation current is large. Thus, the temperature of the bottom of the cell culture dish increases, and the cells are hot, resulting in cell death. The measuring circuit only selects a few interested sensors, and the unselected sensors do not have working current and do not raise the temperature of the cell culture dish.

The measuring circuit of the invention 201210282543.8 of the Chinese patent consists of a power supply, a galvanometer, a reference electrode, an addressing switch and an addressing controller. The Ground (GND) end of the addressing switch is connected with a reference electrode on the base of the culture dish body dish, and meanwhile, the reference electrode is connected with the source electrode of the field effect sensor. The input end of the addressing switch is respectively connected with the drain electrode of each field effect sensor on the sensor array corresponding to the culture dish body. The output and GND terminals of the addressing switch are connected in series with the power supply and the galvanometer. The galvanometer is composed of a detection resistor and an amplifier, and the detection resistor is connected in parallel with the amplifier. The addressing controller outputs two addressing lines, namely radial addressing (LON) and Latitudinal Addressing (LAT), and inputs the two addressing lines to the control end of the addressing switch. The number of bits of the radial addressing and the weft addressing is 10 bits, and 1024×1024 codes can be made to meet the selection requirement of 700×700 field effect sensors. At the same time, only one bit of the outputs of the 10-bit-diameter addressing line and the weft addressing line is 1, and the rest are 0. When the addresses of the radial addressing and the weft addressing of 1 are crossed together, the corresponding switch is gated. The measuring circuit only solves the addressing method for selecting one of the field effect sensors from the field effect transistor sensor array, and does not solve the technical methods of drain-source current detection, amplification, analog-to-digital conversion and data serial output of the field effect transistor sensors.

The invention aims to provide a field effect cell culture dish system measuring circuit which is used for solving the technical problems of drain-source current detection, amplification, analog-to-digital conversion and data serial output of a field effect tube sensor.

Disclosure of Invention

A field effect cell culture dish system measuring circuit 5 is composed of an amplifier array 1, an ADC array 2, a microprocessor 3, a USB interface 4 and the like. The input of the amplifier array 1 comes from the field effect cell culture dish body 6, the output of the amplifier array 1 is connected with the input of the ADC array 2, the output of the ADC array 2 is connected with the input of the microprocessor 3, the output of the microprocessor 3 is connected with the input of the USB interface 4, and the output of the USB interface 4 is the output of the measuring circuit and is connected to the computer system PC.

The amplifier array 1 is an array formed by N multiplied by N amplifiers, the number of each amplifier is A_ij, i represents a row, the value range is 1-N, j represents a column, and the value range is 1-j-N. The number of the field effect transistor is FET_ij, i represents a row, the value range is 1-or-small and is N, j represents a column, and the value range is 1-or-small and is N. Amplifier a_ij is used to amplify the sense signal of FET_ij, which corresponds one-to-one to the sensors of the FET array. The number N of FET_ij can be selected in the range of 10.ltoreq.N.ltoreq.700 according to the cell culture dish specification.

The amplifier a_ij includes an operational amplifier OA₁₁, a resistor R₁₁、R₁₂、R₁₃、R₁₄、R₁₅, a capacitor C₁₁、C₁₂、C₁₃, and the like. Resistor R₁₁ is used to convert the sensor drain-source current I_D to a sense voltage V₁₁ for selection as a range of 1kΩ -R₁₁ -100 kΩ for the detection of the sensor drain current I_D,R₁₁ by the galvo 14. The amplification factor of the amplifier is determined by resistor R₁₂、R₁₃、R₁₄、R₁₅. When (when)The amplifier multiple is:

The current I₁ will affect the detection of I_D, requiring I₁＜＜I_D, typically I₁, to be an order of magnitude less than I_D, i.e., I₁＜I_D/10. To achieve this requirement, R₁₂＞＞R₁₁ is required, typically R₁₂ is an order of magnitude greater than R₁₁, i.e., R₁₂＞10R₁₁. The capacitor C₁₁ plays a role in filtering, and improves the high-frequency interference resistance of the amplifier output. Resistors R₁₆ and R₁₇ form a voltage divider providing a quiescent operating potential for N-type silicon semiconductor substrate 10, typically with R₁₆ and R₁₇ both greater than 100kΩ.

The operational amplifier should be powered by positive power V_DD and negative power V_SS, and capacitor C₁₂、C₁₃ is connected in parallel to improve the stability of the power supply. C₁₂ may be 10. Mu.F and C₁₃ may be 0.1. Mu.F.

The ADC array 2 is composed of a plurality of (n-chip) analog-to-digital converters ADC₁21、ADC₂22、........、ADC_n n. Every 8 amplifiers are allocated 1 ADC until the allocation is finished. The data bus of the ADC array 2 is characterized in that 1 st ADC analog signal input channels AIN 0-AIN 7 are respectively connected with the outputs of the 1 st to 8 th amplifiers, a digital signal output channel DOUT1 is connected with the data bus Out1 of the microprocessor 3,2 nd ADC analog signal input channels AIN 0-AIN 7 are respectively connected with the outputs of the 9 th to 16 th amplifiers, a digital signal output channel DOUT2 is connected with the data bus Out2 of the microprocessor 3, the N-th ADC analog signal input channels AIN 0-AIN 7 are respectively connected with the outputs of the 8 x (N-1) +1 st to NxN th amplifiers, and a digital signal output channel DOUTn is connected with the data bus Outn of the microprocessor 3. The control bus of the ADC array 2 is formed by connecting control lines of a chip selection signal CS, an SPI data input signal DIN, a shutdown and reset signal PD/RET, an SPI clock SCLK, an output BUSY TM_BUSY and the like of all the ADCs in the ADC array 2 in parallel, and is the control bus of the ADC array 2.

The digital power and analog power of the analog-to-digital converter (ADC) may be supplied in common, and the power-off and reset signals PD/RET are directly connected to the digital power. The PD/RET and the DVDD can be connected to a digital power supply 3.3V power supply after being short-circuited. When the temperature information inside the chip is not used, the TM_BUSY can be suspended.

The microprocessor 3 is connected with the USB interface 4, and the output of the USB interface 4 is the output of the measuring circuit.

When the output signal data of each amplifier is 16 bits, the sampling frequency is 20kHz, and the SPI clock frequency of the microprocessor 3 is at least 20 kHz/path×n×n path×16bit. Considering that some instructions take much time for the CPU, the main frequency of the microprocessor 3 should be well above 32MHz. The clock signals SCLK of all the ADCs of the ADC array 2 are connected in parallel to the same control signal, and the chip select signal CS and the SPI data input signal DIN are also connected in parallel to the same control signal. In this way, the 3 control signals cause all ADCs to operate at the same time and remain identical.

The microprocessor 3 controls the program as follows, after the program is started, it is initialized first, then it enters the loop body While (1), the program scans each amplifier continuously, the scanning rate is 20kHz. When 20kHz is satisfied, the program is interrupted, analog-to-digital conversion processing is performed, and stored in a register in the microprocessor 3. The timer times a 20kHz interrupt during which all signals (N x N signals) in the amplifier array 1 are acquired one pass. In controlling the input/output IO ports, the library functions cannot be used, but the input/output IO ports should be controlled in a manner of directly controlling registers.

The interrupt routine and its USB communication are such that the microprocessor 3 detects serial data on the data buses Out 1-Out 21. The effective data amount for 1 detection cycle is 16 bit/track×8 track/slice×n slices. In order to improve the operation efficiency of the microprocessor 3 to meet the 20kHz sampling of the nxn signals, the data collected by the microprocessor 3 is the original data of the input/output IO port, and some parsing is needed to convert the data into real data. The data sent by the microprocessor 3 is specified by a pointer, and all the data collected by the microprocessor 3 from the ADC array 2 are converted into serial digital signal sequences under the control of clock pulses and output from the USB interface.

The invention has the advantages that:

The action potential of a cell in the cell culture dish is converted into drain current through the corresponding field effect sensor, the current is screened out from the sensor array, and the current is converted into voltage for amplification and analog-to-digital conversion, so that a digital signal is transmitted to an external computer, and the digitizing problem of cell membrane action potential detection is solved.

Drawings

FIG. 1 is a diagram of the measuring circuit of a field effect cell culture dish system.

FIG. 2 is a schematic diagram of a field effect cell culture dish system.

Fig. 3 is a schematic diagram of the operation of the cell-field effect sensor.

FIG. 4 is a schematic diagram of cell-field effect sensing characteristics and sensing process.

Fig. 5 is an amplifier array diagram.

Fig. 6 is an amplifier schematic.

Fig. 7 is an ADC array diagram.

Fig. 8 is a block diagram of a microprocessor.

Fig. 9 is a control flow block diagram of the microprocessor 3.

Fig. 10 is a data structure diagram.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

Example 1:

Referring to fig. 1, a field effect cell culture dish system measuring circuit 5 is composed of an amplifier array 1, an ADC array 2, a microprocessor 3, a USB interface 4, and the like. The input of the amplifier array 1 comes from the field effect cell culture dish body 6, the output of the amplifier array 1 is connected with the input of the ADC array 2, the output of the ADC array 2 is connected with the input of the microprocessor 3, the output of the microprocessor 3 is connected with the input of the USB interface 4, and the output of the USB interface 4 is the output of the measuring circuit and is connected with the external computer PC.

Referring to fig. 2, the field effect cell culture dish system consists of a cell culture dish body 6 and a measurement circuit 5. The output of the culture dish body 6 is connected to the input of the measuring circuit 5. The cell culture dish body 6 is composed of a dish base and a dish wall, and forms a U-shaped volume body for storing cells and culture fluid thereof. The dish base is a silicon wafer with a sensor array 7, a reference electrode 8 and the like prepared on an N-type silicon semiconductor substrate, the sensor array 7 comprises no more than 700 multiplied by 700 field effect sensors 9, and each field effect sensor 9 is mutually independent and is used for sensing cell membrane potential. The sensor 9 transmits the sensing signal via a connection wire to a connector at the rim of the dish base for connection to the measuring circuit 5. The reference electrode 8 is exposed on the surface of the dish base inside the U-shaped volume as a reference point for 0 potential and is connected to the edge of the dish base for connection to the measuring circuit 5.

Referring to fig. 3, the field effect sensor 9 is composed of an N-type silicon semiconductor substrate 10, a source electrode 11, a drain electrode 16, and an SiO₂ insulating layer 17. Two highly doped P-type semiconductor regions, one being a source electrode 11 and the other being a drain electrode 16, are manufactured on an N-type silicon semiconductor substrate 10 with lower doping concentration and higher resistivity by using a microelectronic technology. Then, a very thin SiO₂ insulating layer 17 is grown on one side surface of the N-type silicon semiconductor substrate 10. The outside of the SiO₂ insulating layer 17 can be contacted with cell sap, which is suitable for culturing adherent cells 19. The other side of the N-type silicon semiconductor substrate 10 is connected to the rim of the boat base at two P-type semiconductor regions with metal wires, respectively, for cell membrane potential output.

The cell field effect sensor 9 works as follows:

Cells 19 are grown on the surface of SiO₂ insulating layer 17 by adherence and immersed in cell culture solution 18. When the cell 19 is in a resting state, the total intracellular ion count is negative, the cell membrane potential 20 is negative, and a negative-positive-negative-positive electric field is formed between the source 11 and the cell 19. The electric field forms an inversion layer 12 and a depletion layer 15 on the side of the SiO₂ insulating layer 17, wherein the inversion layer 12 is a P-type conduction channel with positive charges (holes) as majority carriers, connecting the source 11 and the drain 16. The depletion layer 15 repels majority carriers (electrons) in the N-type silicon semiconductor substrate 10 to form a space charge isolation band so that positive charges (holes) in the conductive channel do not diffuse to the N-type silicon semiconductor substrate 10. When the cell 19 is in an excited state, the cell membrane potential 20 is negative in one part, which indicates that the total intracellular ion number is decreased negatively, and positive in the other part, which indicates that the total intracellular ion number is positive. For the former case, where the inversion layer 12 is smaller in width, the conduction channel resistance increases and the galvo 14 current I_D will decrease with the voltage of the power supply 13 unchanged. In the latter case, the inversion layer 12 disappears, and the conduction channel also disappears, even when the total number of intracellular ions is deeply positive, and the depletion layer 15 also disappears. At this time, the source 11-N type silicon semiconductor substrate 10 is a reverse PN junction, the drain 16-N type silicon semiconductor substrate 10 is a forward PN junction, which are two back-to-back diodes that are not likely to conduct, i.e., the galvo 14 current I_D is 0. This mode of field effect sensing is known as depletion p-channel field effect sensing.

In summary, the sensing characteristic V_m-I_D of the field effect sensor 9 is shown in fig. 4. When the cell membrane potential 20 changes to V_m (t) with time, the characteristic V_m-I_D is sensed by the field effect sensor 9, the drain 16 current I_D (t) can be obtained in the galvanometer 14, and the purpose that the cell membrane potential 20 is sensed as the galvanometer 14 current I_D (t) by the field effect sensor 9 is realized.

Referring to FIG. 5, the amplifier array 1 is an array of N amplifiers, each of which has a number A_ij, i represents a row, and a value range 1.ltoreq.i.ltoreq.N, and j represents a column, and a value range 1.ltoreq.j.ltoreq.N. The number of the field effect transistor is FET_ij, i represents a row, the value range is 1-or-small and is N, j represents a column, and the value range is 1-or-small and is N. Amplifier a_ij is used to amplify the sense signal I_D of FET_ij, which corresponds one-to-one to the sensors of the FET array. The number N of FET_ij can be selected in the range of 10.ltoreq.N.ltoreq.700 according to the cell culture dish specification.

Example 2:

Referring to fig. 6, an amplifier for sensing a signal I_D (t) by the field effect sensor 9 is composed of an operational amplifier OA₁₁, a resistor R₁₁、R₁₂、R₁₃、R₁₄、R₁₅, a capacitor C₁₁、C₁₂、C₁₃, and the like. Let node 1 potential V₁, node 2 potential V₂. Resistor R₁₁ has the function of galvo 14. When the sensor drain current I_D flows through R₁₁, the sense voltage V₁₁ generated across R₁₁ is:

V₁₁＝V₁-V₂＝R₁₁I_D (2)

The drain-source working current of the field effect transistor does not exceed 1mA, and the sensing voltage V₁₁ does not exceed 1V, so R₁₁ is selected in the range of 1kΩ -R₁₁ -100 kΩ. According to the ideal operational amplifier characteristics, when the current flowing through R₁₂ is the same as the current flowing through R₁₃, the operational amplifier OA₁₁ has a positive terminal potential V₊ and node 1 potentials V₁ and OA₁₁ output potential V_o:

The method comprises the following steps:

similarly, the inverting terminal V_- of the operational amplifier OA₁₁ and the node 2V 2 have:

The method comprises the following steps:

according to the ideal operational amplifier characteristics, there are:

V₊＝V_- (7)

Substituting equation (4) and equation (6) into equation (7), operational amplifier OA₁₁ outputs V_o:

When (when)

The method comprises the following steps:

The amplifier is required to meetThe conditions, magnification were:

At node 1, the presence of shunt currents I_D and I₁.I₁ will affect the detection of I_D, requiring I₁＜＜I_D, typically I₁ an order of magnitude less than I_D, i.e., I₁＜I_D/10. To achieve this requirement, R₁₂＞＞R₁₁ is required, typically R₁₂ is an order of magnitude greater than R₁₁, i.e., R₁₂＞10R₁₁. The capacitor C₁₁ plays a role in filtering, and improves the high-frequency interference resistance of the amplifier output. Resistors R₁₆ and R₁₇ form a voltage divider providing a quiescent operating potential for N-type silicon semiconductor substrate 10, typically with R₁₆ and R₁₇ both greater than 100kΩ.

The operational amplifier should select zero drift, low noise, low power amplifiers, such as AD8628, powered with positive power V_DD and negative power V_SS, and capacitor C₁₂、C₁₃ in parallel to improve the stability of the power supply. C₁₂ may be 10. Mu.F and C₁₃ may be 0.1. Mu.F.

Example 3:

Referring to fig. 7, the ADC array 2 is composed of a plurality of (n-chip) analog-to-digital converters ADC₁21、ADC₂22、........、ADC_n n. Typically, a chip analog-to-digital converter (ADC) has 8 analog signal inputs. When the amplifier array 1 has N×N amplifiers, N is not less than (N×N)/8. When N multiplied by 8, the equal sign is taken, and when the N multiplied by 8 is not, the number is greater than the number. If the amplifier array 1 has 10×10 amplifiers, n=13. Every 8 amplifiers are distributed with 1 ADC, and no numbering configuration is performed until the distribution is completed. The 1 st to 8 th amplifiers are assigned to the 1 st ADC₁ 21, the 9 th to 16 th amplifiers are assigned to the 2 nd ADC₂, &..the.and so on, until the n×n-th amplifiers are assigned to the N-th ADC_n N.

The analog-to-digital converter (ADC) may select the TI company chip ADS8028.ADS8028 is a 12-bit, 1 Million Samples Per Second (MSPS), successive Approximation Register (SAR) digital-to-analog converter (ADC) with 8 channels with internal reference and internal temperature sensor. The chip data and control signals are defined as in table 1.

TABLE 1 ADS8028 data and control pin definitions

The data bus of the ADC array 2 is characterized in that 1 st ADC analog signal input channels AIN 0-AIN 7 are respectively connected with the outputs of the 1 st to 8 th amplifiers, a digital signal output channel DOUT1 is connected with the data bus Out1 of the microprocessor 3,2 nd ADC analog signal input channels AIN 0-AIN 7 are respectively connected with the outputs of the 9 th to 16 th amplifiers, a digital signal output channel DOUT2 is connected with the data bus Out2 of the microprocessor 3, the N-th ADC analog signal input channels AIN 0-AIN 7 are respectively connected with the outputs of the 8 x (N-1) +1 st to NxN th amplifiers, and a digital signal output channel DOUTn is connected with the data bus Outn of the microprocessor 3. For example, when n=10, the 1 st ADC input AIN0 to AIN7 is connected to the 1 st to 8 th amplifiers, the output DOUT1 is connected to the microprocessor 3Out1, the 2 nd ADC input AIN0 to AIN7 is connected to the 9 th to 16 th amplifiers, the output DOUT2 is connected to the microprocessor 3Out 2, the 13 th ADC analog signal input channels AIN0 to AIN7 are connected to the 97 th to 100 th amplifiers, respectively, and the output channel DOUT13 is connected to the microprocessor 3Out13.

The control bus of the ADC array 2 is formed by connecting control lines of a chip selection signal CS, an SPI data input signal DIN, a shutdown and reset signal PD/RET, an SPI clock SCLK, an output BUSY TM_BUSY and the like of all the ADCs in the ADC array 2 in parallel, and is the control bus of the ADC array 2.

The digital power supply and the analog power supply of the analog-to-digital converter (ADC) may be a common power supply, and the shutdown and reset signal PD/RET may be directly connected to the digital power supply, but not to the control terminal of the microprocessor 3. The PD/RET and DV_DD can be short-circuited and then connected to a digital power supply 3.3V power supply. The TM BUSY may be suspended directly when the chip internal temperature information is not used.

Example 4:

referring to fig. 8, a microprocessor 3 is formed by a single chip microcomputer, such as STM32F407, and the microprocessor 3 is connected to a USB interface 4. The output of the USB interface 4 is the output of the measuring circuit. The microprocessor 3 is provided with SPI data buses P0-P15 and D3-D7, wherein 21 signal outputs are connected with the input of the ADC array 2 analog-to-digital converter ADC, and the total number of the SPI data buses is not more than 21 ADCs, namely n is less than or equal to 21. In this way, the microprocessor 3 can measure the sense signals of no more than 8×21=168 amplifiers. And 3 control lines are connected to the ADC array 2 control bus CS, SCLK, DIN. The microprocessor 3 data bus and control bus are defined as in table 2.

Table 2 microprocessor 3 data bus and control bus definitions

SPI protocol signal	Pin name	Data bus	MCU
				CS	D0	Control bus	PD14
SCLK	D1	Control bus	PD15
				DIN	D2	Control bus	PD0
Out1	D3	Data bus	PD1
				Out 2	D4	Data bus	PE7
Out 3	D5	Data bus	PE8
				Out 4	D6	Data bus	PE9
Out 5	D7	Data bus	PE10
				Out 6	P0	Data bus	PB6
Out 7	P1	Data bus	PB7
				Out 8	P2	Data bus	PB8
Out 9	P3	Data bus	PB9
				Out 10	P4	Data bus	PA15
Out 11	P5	Data bus	PC10
				Out 12	P6	Data bus	PC11
Out 13	P7	Data bus	PC12
				Out 14	P8	Data bus	PE7
Out 15	P9	Data bus	PA0
				Out 16	P10	Data bus	PA7
Out 17	P11	Data bus	PA6
				Out 18	P12	Data bus	PB3
Out 19	P13	Data bus	PA4
				Out 20	P14	Data bus	PA8
Out 21	P15	Data bus	PC9

In Table 2, the SPI protocol signal includes CS, SCLK, DIN and DOUT, with DOUT being the outputs Out 1-Out 21 of the ADC array 2 distributed to the data buses P0-P15, D3-D7 of the microprocessor 3.

The microprocessor 3 controls the ADC array 2 by setting the sampling frequency of the output signal of each amplifier to 20kHz and the data of analog-to-digital conversion to 16 bits. Thus, the SPI clock frequency f of the microprocessor 3 is at least:

f=20 kHz/path x N x N-way x 16bit (12)

For example, when n=10, the SPI clock frequency of the microprocessor 3 is at least 20khz×10×10×16 bits=32 MHz. Considering that some instructions take much time for the CPU, the main frequency of the microprocessor 3 should be well above 32MHz. The microprocessor 3 adopted by the system is STM32F407, the main frequency is 168MHz, and the design requirement is met.

Considering that the microprocessor 3 has limited data bus resources, the complexity of the system is reduced, the clock signals SCLK of all the ADCs of the ADC array 2 are connected in parallel with the same control signal, and the chip selection signal CS and the SPI data input signal DIN are also connected in parallel with the same control signal. Thus, the 3 signals cause all ADCs to operate at the same time and remain identical.

Referring to fig. 9, the microprocessor 3 controls the program operation principle that after the program is started, the program is initialized first and then enters the loop body While (1), and the program continuously scans each amplifier with a scanning rate of 20kHz. When 20kHz is satisfied, the program is interrupted, analog-to-digital conversion processing is performed, and stored in a register in the microprocessor 3. The timer times a 20kHz interrupt during which all signals (N x N signals) in the amplifier array 1 are acquired one pass. With particular attention to program optimization, library functions cannot be used when controlling input/output IO ports, but rather the input/output IO ports should be controlled using direct control registers.

The interrupt routine and its USB communication are such that the microprocessor 3 detects serial data on the data buses Out 1-Out 21. The effective data amount for 1 detection cycle is 16 bit/track×8 track/slice×n slices, for example, the 10×10 amplifier array 1 has 13 ADCs, and the effective data amount for 1 detection cycle is 16 bit/track×8 track/slice×13 slices=1664 bit=208 byte. In order to improve the operation efficiency of the microprocessor 3 to meet the 20kHz sampling of the nxn signals, the data collected by the microprocessor 3 is the original data of the input/output IO port, and some parsing is needed to convert the data into real data. The format of these data is as follows:

The microprocessor 3 collects ADC data in clocks, each clock collecting bit data from n ADCs. The number of clocks for 1 ADC full sampling period is 16 per lane x 8 lanes = 128. A16-bit array uint 16D [128] is defined, and D [ i ], i [ E [1,128] stores n bits of data collected by the ith clock microprocessor 3. In particular implementations, the n bits of data are stored in the upper n bits of di, such as n=13. D128 stores all results of one sample, and when the PC receives the data, the data for each channel is parsed according to the description above. Referring to FIG. 10, there is a python script all data structure.

The unit of data that a computer system communicates with a USB is a packet (package). Each communication upper level opportunity determines the number of packets (DataNum) and the size of each packet (PackageSize, bytes) that the microprocessor 3 sends to the computer system. When the host computer successfully sends DataNum and PackageSize data to the microprocessor 3, the microprocessor 3 receives the two data and sends DataNum packets to the computer system in a loop. The data sent by the microprocessor 3 is specified by a pointer. In particular, the data amount of one complete ADC sample is 2byte×128=256 bytes. Using nxn samples as a package, a package size of 256 bytes x nxn, e.g., 100 ADCs with 25.6KByte. Under the control of the clock pulse of the microprocessor 3, the data of the package are converted into serial digital signal sequences and output from the USB interface. This number of packets can be arbitrarily specified and can generally be set to infinity.

When the system is set and used, firstly, a USB driver is installed on Windows, and the corresponding DPINST32.Exe or DPINST64.Exe is selectively installed according to the number of system bits (32 bits or 64 bits). Note that Windows8 and above systems must first disable the driver forcing signature before normal installation. After the installation is completed, the amplifier is powered on, and then the microprocessor 3 is connected by USB for use.

Claims (3)

1. A measuring circuit of a field effect cell culture dish system comprises an amplifier array (1), an ADC array (2), a microprocessor (3), A USB interface (4); the input of the amplifier array (1) is from the field effect cell culture dish body (6), the output of the amplifier array (1) is connected with the input of the ADC array (2), the output of the ADC array (2) is connected with the input of the microprocessor (3), the output of the microprocessor (3) is connected with the input of the USB interface (4), the output of the USB interface (4) is the output of the measuring circuit and is connected with the external computer system PC, the amplifier array (1) is an array formed by a plurality of amplifiers and corresponds to the sensors of the field effect tube array one by one, each amplifier A_ij is formed by an operational amplifier OA₁₁, a resistor R₁₁、R₁₂、R₁₃、R₁₄、R₁₅ and a capacitor C₁₁、C₁₂、C₁₃, the resistor R₁₁ is connected between a power supply V_DD and a drain electrode (16) of the field effect sensor (9) in series, the drain-source current I_D of the sensor is converted into a sensing voltage V₁₁ to realize the function of a galvanometer (14) to detect the sensing current I_D, R₁₂ and R95 are connected between a power supply V_DD and an operational amplifier OA 3443 in series, and a connection point between the output O3432 of the operational amplifier OA and an output OA₁₂ and a positive connection point R5332 and a connection point R5326 and an operational amplifier OA is connected between the drain electrode (R5356) and a connection point R5352 and a positive connection point R5352 of the operational amplifier is determined by the amplifier being connected with the amplifier 5235 and the amplifier (R5256) in series, the connection point is opposite connection point between the amplifier being the connection point and the amplifier being the amplifier is connected with the amplifier₁₁ 1 and the connection point is connected with the amplifier input endWhen the amplifier is amplifying multipleThe capacitor C₁₁ is connected in parallel between the output O₁₁ of the operational amplifier OA₁₁ and circuit ground, and has the filtering function to improve the high-frequency interference resistance of the output of the amplifier, the capacitors C₁₂ and C₁₃ are respectively connected in parallel between the positive power supply V_DD and the negative power supply V_ss of the operational amplifier OA₁₁ and the circuit ground, so as to improve the stability of power supply, the ADC array (2) consists of a plurality of n analog-to-digital converters, 1 ADC is distributed to each 8 amplifiers until the distribution is finished, the ADC analog signal input is connected with the output of each amplifier in the amplifier array (1) in a one-to-one correspondence manner, the ADC digital signal output is connected with the data bus of the microprocessor (3), the chip selection signals CS of all the ADCs in the ADC array (2), the data input signal DIN, SPI clock SCLK, shutdown and reset signals PD/RET, output BUSY TM_BUSY control lines of the serial peripheral interface SPI are connected in parallel and are control buses of the ADC array (2), wherein CS, DIN, SCLK is connected with control bus of microprocessor (3), PD/RET is connected with digital power supply, when it does not use internal temperature information of chip, TM_BUSY is directly suspended; after the program is started, firstly initializing, then entering a circulation body While (1), continuously scanning each amplifier by the program, wherein the scanning rate is 20kHz; when the 20kHz is satisfied, the interrupt program carries Out analog-digital conversion processing and stores data in a register in a microprocessor (3), the timer carries Out the interrupt of 20kHz, during the interrupt period, the microprocessor (3) acquires all signals in an amplifier array (1) by one time, when the input/output IO port is controlled, a library function cannot be used, but a direct register control mode is used for controlling the input/output IO port, the interrupt program is as follows, the microprocessor (3) detects serial data on a data bus Out 1-Out 21, the effective data quantity of 1 detection cycle is 16 bits/channel multiplied by 8 channels multiplied by n pieces, the acquired data is the original data of the input/output IO port, the data can be converted into real data by analysis, the microprocessor (3) acquires ADC data by clocks, each clock acquires data of n ADC bits, 1 ADC complete sampling period needs to take 128 clocks, a 16-bit array D [ i ] (i E1, 128) stores the serial data of the ith bit (i is the data of 3 bits) and the data of n bits [ i ] is stored once, the data of n bits [ D ] are stored, all the data are sampled by one time, when the PC receives the data, the real data of each channel are analyzed according to the description, the data sent by the microprocessor (3) are designated by pointers, and under the control of clock pulses, all the data collected by the microprocessor (3) from the ADC array (2) are converted into serial digital signal sequences and output from the USB interface.

2. The field effect cell culture dish system measurement circuit according to claim 1, wherein the number of rows N and the number of columns N of the amplifier array (1) are selected in a range of 10.ltoreq.N.ltoreq.700 according to the specification of the cell culture dish, the resistor R₁₁ in the amplifier is selected in a range of 1kΩ.ltoreq.R₁₁.ltoreq.100deg.kΩ, the resistor R₁₂ is larger than R₁₁ by one order of magnitude, both R₁₆ and R₁₇ are larger than 100deg.KΩ, the capacitor C₁₂ can be 10 μF, the capacitor C₁₃ can be 0.1 μF, both R₁₆ and R₁₇ are larger than 100deg.KΩ, and the resistors R₁₆ and R₁₇ constitute a voltage divider for providing a static operating potential for the N-type silicon semiconductor substrate (10).

3. The field effect cell culture dish system measuring circuit according to claim 1, wherein the main frequency of the microprocessor 3 is higher than 32MHz.