Disclosure of Invention
The embodiment of the disclosure provides a data conversion circuit, a data conversion method and a memory.
In a first aspect, an embodiment of the present disclosure provides a data conversion circuit, including a conversion module, an adjustment module, and a transmission module, one end of the adjustment module is configured to receive a compensation signal, and the other end of the adjustment module is connected to an output end of the conversion module and an input end of the transmission module respectively, where:
the conversion module is used for receiving an initial data signal, and carrying out parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal;
the adjusting module is used for carrying out compensation processing on the intermediate data signal according to the compensation signal so as to reduce the signal swing of the intermediate data signal;
and the transmission module is used for carrying out driving enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.
In some embodiments, the adjusting module includes a transmission gate module, one end of the transmission gate module is configured to receive the compensation signal, the other end of the transmission gate module is connected to the output end of the converting module and the input end of the transmission module, and the control end of the transmission gate module is configured to receive an enable control signal, where:
And when the enabling control signal is in an effective state, the transmission gate module is turned on to carry out compensation processing on the intermediate data signal according to the compensation signal, or when the enabling control signal is in an ineffective state, the transmission gate module is turned off.
In some embodiments, the enable control signal comprises a first enable control signal and a second enable control signal, wherein:
The transmission gate module comprises an NMOS tube and a PMOS tube, wherein the first end of the NMOS tube is connected with the first end of the PMOS tube to serve as one end of the transmission gate module, and the second end of the NMOS tube is connected with the second end of the PMOS tube to serve as the other end of the transmission gate module;
The control end of the transmission gate module comprises a gate end of the NMOS tube and a gate end of the PMOS tube, the gate end of the NMOS tube is connected with the first enabling control signal, the gate end of the PMOS tube is connected with the second enabling control signal, and the first enabling control signal and the second enabling control signal are mutually opposite signals.
In some embodiments, the adjusting module further includes a first not gate, an input end of the first not gate is connected to the gate end of the NMOS transistor, and an output end of the first not gate is connected to the gate end of the PMOS transistor, wherein:
The first NOT gate is configured to receive the first enable control signal, and perform inversion processing on the first enable control signal to obtain the second enable control signal.
In some embodiments, the adjusting module includes a resistor module, one end of the resistor module is used for receiving the compensation signal, and the other end of the resistor module is connected with the output end of the converting module and the input end of the transmitting module respectively, wherein:
and the resistor module is used for carrying out compensation processing on the intermediate data signal according to the compensation signal so as to reduce the signal swing of the intermediate data signal.
In some embodiments, the transmission module includes a first transmission sub-module and a second transmission sub-module, an input of the first transmission sub-module is connected to an output of the conversion module, and an output of the first transmission sub-module is connected to an input of the second transmission sub-module, wherein:
The first transmission sub-module is used for carrying out reverse phase processing on the intermediate data signal after compensation processing to obtain an initial target data signal;
And the second transmission sub-module is used for carrying out reverse phase processing on the initial target data signal to obtain the target data signal.
In some embodiments, one end of the adjustment module is connected to the output end of the first transmission sub-module, and the other end of the adjustment module is connected to the input end of the first transmission sub-module, wherein:
the first transmission sub-module is further configured to determine the initial target data signal as the compensation signal.
In some embodiments, the first transmission submodule includes a second not gate and a first not gate, the second transmission submodule includes a third not gate, a first input end of the first not gate is used for receiving a transmission control signal, a second input end of the first not gate is connected with an output end of the second not gate and an input end of the third not gate, an output end of the first not gate is connected with an input end of the second not gate, wherein the input end of the second not gate is used as an input end of the first transmission submodule, an output end of the second not gate is used as an output end of the first transmission submodule, an input end of the third not gate is used as an input end of the second transmission submodule, and an output end of the third not gate is used as an output end of the second transmission submodule.
In some embodiments, the conversion module includes a first conversion sub-module, a second conversion sub-module, a third conversion sub-module, and a fourth conversion sub-module, the initial data signal includes first initial data, second initial data, third initial data, and fourth initial data, wherein:
The first conversion sub-module is used for receiving the first initial data and a first clock signal, and sampling the first initial data according to the first clock signal to obtain first intermediate data;
The second conversion sub-module is used for receiving the second initial data and a second clock signal, and sampling the second initial data according to the second clock signal to obtain second intermediate data;
the third conversion sub-module is configured to receive the third initial data and a third clock signal, and sample the third initial data according to the third clock signal to obtain third intermediate data;
The fourth conversion sub-module is configured to receive the fourth initial data and a fourth clock signal, and sample the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;
the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are respectively 0 degree, 90 degrees, 180 degrees and 270 degrees, and the first intermediate data, the second intermediate data, the third intermediate data and the fourth intermediate data form the intermediate data signal.
In some embodiments, the conversion module comprises a first conversion module and a second conversion module, the initial data signal comprises a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, the intermediate data signal comprises a first intermediate data signal and a second intermediate data signal, wherein:
the first conversion module is configured to receive the first initial data signal, and perform parallel-to-serial conversion on the first initial data signal to obtain the first intermediate data signal;
The second conversion module is configured to receive the second initial data signal, and perform parallel-to-serial conversion on the second initial data signal to obtain the second intermediate data signal.
In some embodiments, the compensation signal comprises the first intermediate data signal and the second intermediate data signal, wherein:
the adjusting module is used for performing compensation processing on the second intermediate data signal according to the first intermediate data signal to reduce the signal swing of the second intermediate data signal, and performing compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.
In some embodiments, the target data signal comprises a first target data signal and a second target data signal, and the transmission module comprises a first transmission module and a second transmission module, wherein:
the first transmission module is used for performing driving enhancement processing on the first intermediate data signal after compensation processing to obtain the first target data signal;
And the second transmission module is used for carrying out driving enhancement processing on the second intermediate data signal after compensation processing to obtain the second target data signal.
In some embodiments, one end of the adjusting module is connected to the output end of the first converting module and the input end of the first transmitting module, and the other end of the adjusting module is connected to the output end of the second converting module and the input end of the second transmitting module, respectively.
In some embodiments, the initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are both serial data signals.
In a second aspect, an embodiment of the present disclosure provides a data conversion method, including:
Receiving an initial data signal through a conversion module, and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal;
Receiving a compensation signal through an adjustment module, and carrying out compensation processing on the intermediate data signal according to the compensation signal so as to reduce the signal swing of the intermediate data signal;
And receiving the intermediate data signal after compensation processing through a transmission module, and performing driving enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.
In a third aspect, embodiments of the present disclosure provide a memory comprising a data conversion circuit as claimed in any one of the first aspects.
The embodiment of the disclosure provides a data conversion circuit, a data conversion method and a memory, wherein the circuit comprises a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used for receiving compensation signals, the other end of the adjustment module is respectively connected with an output end of the conversion module and an input end of the transmission module, the conversion module is used for receiving initial data signals, performing parallel-to-serial conversion on the initial data signals to obtain intermediate data signals, the adjustment module is used for performing compensation processing on the intermediate data signals according to the compensation signals so as to reduce signal swing of the intermediate data signals, and the transmission module is used for performing driving enhancement processing on the intermediate data signals after the compensation processing to obtain target data signals. Therefore, the adjustment module is arranged in the data conversion circuit, and performs compensation processing on the intermediate data signal according to the compensation signal, so that the signal swing of the intermediate data signal can be reduced, namely, the signal swing of a connecting node of the conversion module and the transmission module is reduced, the signal bandwidth is increased, the purpose of transmitting high-frequency data is finally achieved, and the high-frequency performance of the circuit is improved.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the related disclosure and not limiting thereof. It should be further noted that, for convenience of description, only the portions related to the disclosure are shown in the drawings.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
It should be noted that the term "first\second\third" in relation to the embodiments of the present disclosure is merely to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first\second\third" may be interchanged in a particular order or sequencing where allowed, so that the embodiments of the present disclosure described herein may be implemented in an order other than that illustrated or described herein.
Before proceeding to further detailed description of the embodiments of the present disclosure, the terms and terms involved in the embodiments of the present disclosure will be described, which are suitable for the following explanation:
A dynamic random access memory (Dynamic Random Access Memory, DRAM);
Double Data Rate (DDR);
P-type metal oxide semiconductor field effect transistor (PMOS transistor) of Positive CHANNEL METAL Oxide Semicond-riser FIELD EFFECT;
an N-type metal oxide semiconductor field effect transistor (NEGATIVE CHANNEL METAL Oxide Semicon-ductor FIELD EFFECT transistor, NMOS transistor);
D flip-flop (DFF).
Fig. 1 is a schematic diagram of a parallel-serial circuit. As shown in fig. 1, the parallel-to-serial circuit 10 is a circuit for converting four parallel data into serial data, and includes four P2S4tol sub-circuits, which respectively receive four parallel data: dataER, dataEF, dataOR and DataOF, and respectively receive four clock signals: sedCKER, sedCKEF, sedCKOR and SedCKOF. The four P2S4tol sub-circuits sample the four parallel data according to the four clock signals and output serial data at PupMid nodes, respectively.
The serial data of PupMid nodes are driven and enhanced by the inverter X1 and the inverter X2, and finally the serial data DataPu is obtained. Meanwhile, the NAND gate Xfb is connected in parallel with the inverter X1 and controls whether the serial data can be normally transmitted according to the DqRstN signal.
With increasing data rates, such as from LPDDR4 4266Mbps to LPDDR5 6400Mbps, the performance of the circuit has encountered bottlenecks due to device performance limitations. The main reason is that the PupMid node is connected not only to the four P2S4to1 sub-circuits, but also to the output devices X1 and Xfb, which results in a large parasitic capacitance at the PupMid node, thus limiting the high frequency performance of the circuit. In order to improve the high-frequency performance of the circuit, one method is to reduce the parasitic capacitance of the PupMid node through a layout, but the parasitic capacitance cannot be reduced infinitely due to structural limitation, so that the circuit can be improved but has a bottleneck.
Based on the above, the embodiment of the disclosure provides a data conversion circuit, which comprises a conversion module, an adjustment module and a transmission module, wherein one end of the adjustment module is used for receiving a compensation signal, the other end of the adjustment module is respectively connected with an output end of the conversion module and an input end of the transmission module, the conversion module is used for receiving an initial data signal, performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal, the adjustment module is used for performing compensation processing on the intermediate data signal according to the compensation signal so as to reduce the signal swing of the intermediate data signal, and the transmission module is used for performing driving enhancement processing on the intermediate data signal after the compensation processing to obtain a target data signal. Therefore, the adjustment module is arranged in the data conversion circuit, and performs compensation processing on the intermediate data signal according to the compensation signal, so that the signal swing of the intermediate data signal can be reduced, namely, the signal swing of a connecting node of the conversion module and the transmission module is reduced, the signal bandwidth is increased, the purpose of transmitting high-frequency data is finally achieved, and the high-frequency performance of the circuit is improved.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
In an embodiment of the present disclosure, referring to fig. 2, a schematic diagram of a composition structure of a data conversion circuit according to an embodiment of the present disclosure is shown. As shown in fig. 2, the data conversion circuit 20 includes a conversion module 201, an adjustment module 202 and a transmission module 203, wherein one end of the adjustment module 202 is used for receiving a compensation signal, and the other end of the adjustment module 202 is connected to an output end of the conversion module 201 and an input end of the transmission module 203, respectively, wherein:
the conversion module 201 is configured to receive an initial data signal, and perform parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal;
The adjustment module 202 is configured to perform compensation processing on the intermediate data signal according to the compensation signal, so as to reduce a signal swing of the intermediate data signal;
and the transmission module 203 is configured to perform driving enhancement processing on the intermediate data signal after the compensation processing, so as to obtain a target data signal.
In the data conversion circuit 20, the conversion module 201 receives the parallel initial data signals, converts the parallel initial data signals into serial intermediate data signals, and the transmission module 203 drives and enhances the serial intermediate data signals to obtain serial target data signals. That is, in the embodiments of the present disclosure, the initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are both serial data signals.
It should be further noted that, as shown in fig. 2, the output end of the conversion module 201, the input end of the transmission module 203, and one end of the adjustment module 202 are connected to the same node, and the signal at the node is an intermediate data signal. Because the node is connected with more devices, the parasitic capacitance of the node is larger, and the high-frequency characteristic of the devices is limited. At this time, the adjustment module 202 may perform compensation processing on the node according to the received compensation signal, so as to reduce the signal swing of the node, that is, perform compensation processing on the intermediate data signal, and reduce the signal swing of the intermediate data signal. Therefore, the signal bandwidth is increased due to the reduction of the signal swing, so that the high-frequency performance of the circuit can be improved, and the purpose of transmitting high-frequency data is achieved.
It should be noted that, the compensation signal is usually a signal opposite to the level state of the intermediate data signal, for example, if the intermediate data signal is at a high level, the compensation signal is at a low level, and the low-level compensation signal affects the voltage of the intermediate data signal through the adjustment module 202, so that the voltage of the intermediate data signal is reduced a little compared to the original high level, and similarly, when the intermediate data signal is at a low level, the compensation signal is pulled up again through the adjustment module 202. Finally, the swing amplitude of the intermediate data signal can be reduced, and further, the transmission of high-frequency data is realized.
For the adjustment module 202, as shown in fig. 3, in one possible implementation manner, the adjustment module 202 may include a transmission gate module 2021 (also called a transmission gate or a transmission pipe), where one end of the transmission gate module 2021 is used to receive the compensation signal, and the other end of the transmission gate module 2021 is connected to the output end of the conversion module 201 and the input end of the transmission module 203, and the control end of the transmission gate module 2021 is used to receive the enable control signal, where:
The transmission gate module 2021 is turned on to perform compensation processing on the intermediate data signal according to the compensation signal when the enable control signal is in an active state, or turned off when the enable control signal is in an inactive state.
It should be noted that, as shown in fig. 3, the adjustment module 202 may be implemented by the transmission gate module 2021. At this time, the compensation signal acts on the intermediate data signal through the transmission gate module 2021, so as to reduce the signal swing of the intermediate data signal.
It should be further noted that, in the embodiment of the present disclosure, the intermediate data signal is mainly compensated when the high frequency signal is transmitted, so as to meet the requirement of the circuit for transmitting the high frequency signal, and the intermediate data signal may not be compensated when the high frequency signal is not required to be transmitted. Therefore, it is also possible to control whether the transmission gate module 2021 is turned on by enabling the control signal, so that the control signal is enabled to be in an active state only when the signal swing of the intermediate data signal needs to be reduced, and the transmission gate module 2021 is enabled to be in an inactive state when the intermediate data signal does not need to be compensated, and the transmission gate module 2021 is not turned on, that is, the intermediate data signal is not compensated.
In this way, the transmission gate module 2021 is controlled by the enabling control signal, so that not only can the signal swing of the intermediate data signal be reduced to meet the requirement of transmitting high-frequency data, but also the transmission gate module 2021 can be turned off in other scenes, the power consumption of a circuit is saved, the use requirement of various scenes is met, and flexible control is realized.
Further, as shown in fig. 4, for the transmission gate module 2021, the transmission gate module 2021 includes an NMOS tube (N1) and a PMOS tube (P1), wherein a first end of the NMOS tube is connected to a first end of the PMOS tube as one end of the transmission gate module 2021, and a second end of the NMOS tube is connected to a second end of the PMOS tube as the other end of the transmission gate module 2021;
the control end of the transmission gate module 2021 includes a gate end of an NMOS transistor and a gate end of a PMOS transistor, where the gate end of the NMOS transistor is connected to the first enable control signal, the gate end of the PMOS transistor is connected to the second enable control signal, and the first enable control signal and the second enable control signal are opposite signals.
It should be noted that, as shown in fig. 4, the transmission gate module 2021 may be formed by connecting an NMOS transistor and a PMOS transistor. At this time, the gate ends of the NMOS and PMOS transistors are respectively used as two control ends of the transmission gate module 2021, and the corresponding enable control signals include a pair of inverted signals, namely a first enable control signal and a second enable control signal, where the first end of the NMOS transistor is connected with the first end of the PMOS transistor to be used as one end of the transmission gate module 2021 for receiving the compensation signal, and the second end of the NMOS transistor is connected with the second end of the PMOS transistor to be used as the other end of the transmission gate module 2021 connected with the output end of the conversion module 201 and the input end of the transmission module 203.
Thus, for the first enable control signal and the second enable control signal, the active state of the first enable control signal may be a high state (logic "1") and the active state of the second enable control signal may be a low state (logic "0"). When the first enabling control signal is in a high level state and/or the second enabling control signal is in a low level state, the NMOS tube and/or the PMOS tube are/is conducted, so that the compensation signal can be transmitted to the node where the intermediate data signal is located, compensation processing of the intermediate data signal is achieved, when the first enabling control signal is in a low level state and the second enabling control signal is in a high level state, the NMOS tube and the PMOS tube are not conducted, the transmission gate module 2021 is turned off, the compensation signal cannot be transmitted to the node where the intermediate data signal is located, and compensation processing of the intermediate data signal cannot be conducted at this time.
Since the first enable control signal and the second enable control signal are inverted signals to each other, the first enable control signal can be inverted to the second enable control signal through the not gate. Thus, in some embodiments, based on the circuit shown in fig. 4, as shown in fig. 5, the adjustment module 202 may further include a first not gate 2022, an input terminal of the first not gate 2022 is connected to a gate terminal of the NMOS transistor, and an output terminal of the first not gate 2022 is connected to a gate terminal of the PMOS transistor, wherein:
The first not gate 2022 is configured to receive the first enable control signal, and perform an inversion process on the first enable control signal to obtain a second enable control signal.
As shown in fig. 5, the input end of the first not gate 2022 is connected to the gate end of the NMOS transistor, and is used for receiving the first enable control signal, and the output end of the first not gate 2022 is connected to the gate end of the PMOS transistor, so that the first not gate 2022 can provide the second enable control signal obtained by inverting the first enable control signal to the gate end of the PMOS transistor.
It should be noted that, as shown in fig. 5, for the transmission gate module 2021, two control terminals (the gate terminal of the PMOS transistor and the gate terminal of the NMOS transistor) respectively receive the first enable control signal and the second enable control signal, and only one first enable control signal needs to be received for the whole adjustment module 202. In this way, the transmission gate module can be turned on only in the high-speed mode of transmitting high-frequency data, so that the level state of the first enabling control signal can be controlled, in the high-speed mode, the first enabling control signal is at a high level (logic "1") and is in an active state, so that the transmission gate module 2021 is turned on, and the signal swing of the intermediate data signal is reduced, and in the non-high-speed mode, the first enabling control signal is at a low level (logic "0") and is in an inactive state, so that the transmission gate module 2021 is not turned on, and power consumption is saved. It can be seen that whether the first Enable control signal is valid is determined according to whether high frequency data is currently transmitted, thereby implementing turning on or off the transmission gate module 2021, and thus the first Enable control signal may also be referred to as a high speed Enable signal (HIGH SPEED Enable, HSEn).
It should be noted that the first NOT 2022 may be further connected in such a manner that an input end of the first NOT 2022 is connected to a gate end of the PMOS transistor, and is used for receiving the second enable control signal, and an output end of the first NOT is connected to a gate end of the NMOS transistor, and is used for outputting the first enable control signal. At this time, the adjustment module 202 only needs to receive a second enable control signal, where the second enable control signal is used as a high-speed enable signal, and the active state is low (logic "0") and the inactive state is high (logic "1"). Control of the transmission gate module 2021 may also be implemented.
For the adjustment module 202, as shown in fig. 6, in another possible implementation manner, the adjustment module 202 may include a resistor module 2023, one end of the resistor module 2023 is used for receiving the compensation signal, and the other end of the resistor module 2023 is connected to the output end of the conversion module 201 and the input end of the transmission module 203, where:
The resistor module 2023 is configured to perform compensation processing on the intermediate data signal according to the compensation signal, so as to reduce a signal swing of the intermediate data signal.
It should be noted that, as shown in fig. 6, the adjustment module 202 may also be implemented by the resistor module 2023. The resistor module 2023 functions in a similar manner to the aforementioned transmission gate module 2021, and the resistor module 2023 transmits the compensation signal to the node where the intermediate data signal is located, where the compensation signal is generally opposite to the intermediate data signal in level state, so that for the intermediate data signal with a high level, the voltage of the intermediate data signal can be pulled down, and for the intermediate data signal with a low level, the voltage of the intermediate data signal can be pulled up, so as to reduce the signal swing of the intermediate data signal and achieve the purpose of transmitting the high-frequency signal.
It should be noted that the resistor module 2023 may be a fixed resistor or a variable resistor, or a combination of a fixed resistor and a variable resistor, which is not limited herein. Thus, the compensation degree of the intermediate data signal can be adjusted by adjusting the resistance value of the variable resistor, and flexible control is realized.
For example, the resistance of the resistor module 2023 may be set to be high so that the compensation signal is hardly passed, corresponding to the off state, and thus the intermediate data signal is hardly compensated, the resistance of the resistor module 2023 may be set to be a first resistance so that the compensation signal is able to pass through but have a certain loss, and the intermediate data signal may be compensated to some extent, in a low frequency scenario in which the resistance of the resistor module 2023 may be set to be a second resistance (the second resistance is smaller than the first resistance) so that the compensation signal is able to pass through and have a low loss, according to the frequency level of the data, in a first-level high frequency scenario in which the compensation signal is able to pass through but have a certain loss, for example.
Further, as shown in fig. 7 for the transmission module 203, in some embodiments, the transmission module 203 includes a first transmission submodule 2031 and a second transmission submodule 2032, wherein an input end of the first transmission submodule 2031 is connected to an output end of the conversion module 201, and an output end of the first transmission submodule 2031 is connected to an input end of the second transmission submodule 2032, wherein:
A first transmission submodule 2031, configured to perform inverse processing on the intermediate data signal after the compensation processing, to obtain an initial target data signal;
The second transmission sub-module 2032 is configured to perform inverse processing on the initial target data signal to obtain a target data signal.
In fig. 7, in the transmission module 203, a first transmission submodule 2031 is connected to the conversion module 201 and the adjustment module 202, and is configured to receive the intermediate data signal after the compensation processing, perform the inversion processing to obtain an initial target data signal, and send the initial target data signal to the second transmission submodule 2032, and after receiving the initial target data signal, the second transmission submodule performs the inversion processing again to invert the initial target data signal into the target data signal. Since the intermediate data signal is serial data, both the initial target data signal and the target data signal are serial data signals.
In this way, the two-stage inversion processing of the first transmission submodule 2031 and the second transmission submodule 2032 makes the level state of the finally obtained target data signal unchanged compared with that of the intermediate data signal, but the driving capability is enhanced, which is more favorable for the transmission of the data signal.
Since the compensation signal is generally a signal having a level opposite to that of the intermediate data signal, and the initial target data signal is obtained by inverting the intermediate data signal, the initial target data signal may be used as the compensation signal in the embodiments of the present disclosure. Thus, as shown in fig. 7, in some embodiments, one end of the adjustment module 202 is connected to the output of the first transmission sub-module 2031 and the other end of the adjustment module 202 is connected to the input of the first transmission sub-module 2032, wherein:
the first transmission submodule 2031 is further configured to determine the initial target data signal as a compensation signal.
It should be noted that, as shown in fig. 7, the output end of the first transmission sub-module 2031 may be connected to one end of the adjustment module 202, the node where the intermediate data signal is located is denoted as PupMid node, the node where the initial target data signal is located is denoted as PupMidN node, and the adjustment module 202 is connected between the nodes PupMid and PupMidN. In this way, for the data conversion circuit 20, the initial data signal is processed into the intermediate data signal by the conversion module 201, the intermediate data signal is processed into the initial target data signal by the first conversion submodule 2031 in an inverted manner, the initial target data signal is used as the compensation signal, the initial target data signal and the intermediate data signal are mutually in an inverted manner, and the adjustment module 202 performs compensation processing on the intermediate data signal according to the initial target data signal, so that the signal swing of the intermediate data signal is reduced, that is, the signal swing of the PupMid node is reduced, and therefore, the high-frequency performance of the circuit can be improved, and the data transmission speed of the circuit is improved.
Further, fig. 8 is a schematic diagram of a specific structure of a data conversion circuit according to an embodiment of the present disclosure on the basis of fig. 5, and fig. 9 is a schematic diagram of a specific structure of a data conversion circuit according to an embodiment of the present disclosure on the basis of fig. 6. The adjustment module 202 in fig. 8 is implemented with a transmission gate module 2021 and a first not gate 2022, and the adjustment module 202 in fig. 9 is implemented with a resistor module 2023.
In fig. 8, the output terminal of the first transmission submodule 2031 is connected to the first ends of the PMOS and NMOS transistors (the first ends of the transmission gate module 2021), and in fig. 9, the output terminal of the first transmission submodule 2031 is connected to one end of the resistor module 2023. In this way, the first transmission submodule 2031 may directly provide the output initial target data signal as a compensation signal to the adjustment module 202 for compensation processing of the intermediate data signal.
As shown in fig. 8 or fig. 9, in some embodiments, the first transmission submodule 2031 includes a second not gate 2033 and a first not gate 2034, the second transmission submodule 2032 includes a third not gate 2035, a first input terminal of the first not gate 2034 is configured to receive a transmission control signal, a second input terminal of the first not gate 2034 is connected to an output terminal of the second not gate 2033 and an input terminal of the third not gate 2035, and an output terminal of the first not gate 2034 is connected to an input terminal of the second not gate 2033, where an input terminal of the second not gate 2033 is configured to serve as an input terminal of the first transmission submodule 2031, an output terminal of the third not gate 2035 is configured to serve as an input terminal of the second transmission submodule 2032, and an output terminal of the third not gate 2035 is configured to serve as an output terminal of the second transmission submodule 2032.
As shown in fig. 8 or fig. 9, in the first transmission submodule 2031, the first nand gate 2034 and the second nand gate 2033 are connected end to end, the second input end of the first nand gate 2034 is connected to the node PupMidN, and the output end is connected to the node PupMid.
The first nand gate 2034 receives a transmission control signal (also referred to as DQ reset N, dqRstN) through the first input terminal in addition to the initial target data signal output from the second nor gate 2033 through the second input terminal, and the transmission control signal may control whether data can be normally transmitted by the first transmission submodule 2031. When the transmission control signal is at a high level (logic "1"), data can be normally transmitted, and when the transmission control signal is at a low level (logic "0"), data cannot be normally transmitted. In this way, the embodiment of the present disclosure may further control whether the intermediate data signal is normally transmitted as the initial target data signal through the first nand gate 2034 and the transmission control signal, which increases flexibility of data conversion, and may further avoid the problem that the data is erroneously transmitted to cause interference of a circuit and the like under the condition that the data is not required to be transmitted.
That is, when the level state of the transfer control signal is high, the first and second nand gates 2034 and 2033 form one latch, latching data without affecting data transfer. When the level state of the transmission control signal is low, the PupMid node is always high, and data cannot be normally transmitted.
As shown in fig. 8 or 9, in some embodiments, for the conversion module 201, the conversion module 201 may include a first conversion sub-module 2011, a second conversion sub-module 2012, a third conversion sub-module 2013, and a fourth conversion sub-module 2014, and the initial data signal may include first initial data, second initial data, third initial data, and fourth initial data, wherein:
The first conversion sub-module 2011 is configured to receive the first initial data and a first clock signal, and sample the first initial data according to the first clock signal to obtain first intermediate data;
a second conversion sub-module 2012, configured to receive the second initial data and the second clock signal, and sample the second initial data according to the second clock signal to obtain second intermediate data;
A third conversion sub-module 2013, configured to receive third initial data and a third clock signal, and sample the third initial data according to the third clock signal to obtain third intermediate data;
a fourth conversion sub-module 2014, configured to receive fourth initial data and a fourth clock signal, and sample the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;
The phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are respectively 0 degree, 90 degrees, 180 degrees and 270 degrees, and the first intermediate data, the second intermediate data, the third intermediate data and the fourth intermediate data form an intermediate data signal.
It should be noted that, as shown in fig. 8 or fig. 9, taking an example that the initial data signal includes four parallel data, in this case, the conversion module 201 correspondingly includes four conversion sub-modules (also referred to as P2S4tol sub-circuits) respectively for sampling the four parallel data to output four intermediate data to form an intermediate data signal. The output end of the first conversion sub-module 2011, the output end of the second conversion sub-module 2012, the output end of the third conversion sub-module 2013, and the output end of the fourth conversion sub-module 2014 are connected to the PupMid node, and are used as the output ends of the conversion modules 201 to output the intermediate data signals.
It should be further noted that, in each conversion sub-module, the clock signal is used to control the sampling time of the corresponding initial data, so as to ensure the timing sequence among the four output intermediate data, so as to form the intermediate data signal. Illustratively, fig. 10 shows a specific schematic structural diagram of a conversion module 201 provided by an embodiment of the present disclosure, where the conversion module 201 may further include a clock signal generator 2015, the clock signal generator 2015 receives a first clock signal (SedCKER), a second clock signal (SedCKEF), a third clock signal (SedCKOR), and a fourth clock signal (SedCKOF), generates the first clock selection signal (SedCKERN) according to a rising edge of the first clock signal (SedCKER), generates the second clock selection signal (SedCKEFN) according to a rising edge of the second clock signal (SedCKEF), generates the third clock selection signal (SedCKORN) according to a rising edge of the third clock signal (SedCKOR), generates the fourth clock selection signal (SedCKOFN) according to a rising edge of the fourth clock signal (SedCKOF), and the pulse width of each clock selection signal is smaller than the pulse width of the corresponding clock signal. The signal timings of the clock signals and the clock selection signals are as shown in fig. 10.
The first conversion sub-module 2011 may include a first flip-flop (DFF 1) and a first switch (S1), the second conversion sub-module 2012 may include a second flip-flop (DFF 2) and a second switch (S2), the third conversion sub-module 2013 may include a third flip-flop (DFF 3) and a third switch (S3), and the fourth conversion sub-module 2014 may include a fourth flip-flop (DFF 4) and a fourth switch (S4).
In the first conversion sub-module 2011, the first flip-flop DFF1 samples the first initial data DataER on the rising edge of the first clock signal SedCKER, and during the high state of the first selection clock signal SedCKERN, the first switch S1 is closed, so that the sampled signal gets the first intermediate data D1' through the first switch S1. Similarly, in the second conversion sub-module 2012, the second flip-flop DFF2 samples the second initial data DataEF at a rising edge of the second clock signal SedCKEF, the second switch S2 is closed during the high state of the second selection clock signal SedCKEFN such that the sampled signal gets the second intermediate data D2' through the second switch S2, in the third conversion sub-module 2013, the third flip-flop DFF3 samples the third initial data DataOR at a rising edge of the third clock signal SedCKOR, the third switch S3 is closed during the high state of the third selection clock signal SedCKORN such that the sampled signal gets the third intermediate data D3' through the third switch S3, the fourth flip-flop DFF4 samples the fourth initial data DataOF at a rising edge of the fourth clock signal SedCKOF, and the fourth switch S4 is closed during the high state of the fourth selection clock signal SedCKOFN such that the sampled signal gets the fourth intermediate data D4' through the fourth switch S4.
As shown in fig. 10 and 11, due to the timing difference between the four clock selection signals, after the first initial data DataER, the second initial data DataEF, the third initial data DataOR and the fourth initial data DataOF are sampled and output in parallel, four intermediate data can be sequentially output, and finally, a serial intermediate data signal is obtained at the PupMid node.
Further, the embodiments of the present disclosure may also be applied in a scenario where a differential exists. As shown in fig. 12, in some embodiments, the conversion module 201 includes a first conversion module 204 and a second conversion module 205, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, and the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, wherein:
A first conversion module 204, configured to receive a first initial data signal, and perform parallel-to-serial conversion on the first initial data signal to obtain a first intermediate data signal;
The second conversion module 205 is configured to receive the second initial data signal, and perform parallel-to-serial conversion on the second initial data signal to obtain a second intermediate data signal.
It should be noted that, in the embodiment of the present disclosure, the initial data signal may be a pair of differential signals (or referred to as inverted signals), including a first initial data signal and a second initial data signal, where the first initial data signal and the second initial data signal are parallel data signals, the first conversion module 204 processes the first initial data signal into a serial first intermediate data signal, and the second conversion module 205 processes the second initial data signal into a serial second intermediate data signal. It will be appreciated that the first intermediate data signal and the second intermediate data signal are also a pair of differential signals, the level states of which are opposite.
At this time, as shown in fig. 12, one end of the adjustment module 202 is connected to the output terminal of the first conversion module 204, and the other end of the adjustment module 202 is connected to the output terminal of the second conversion module 205. The second intermediate data signal is used as a compensation signal for compensating the first intermediate data signal, and the first intermediate data signal is used as a compensation signal for compensating the second intermediate data signal. That is, the compensation signal includes a first intermediate data signal and a second intermediate data signal, wherein:
The adjustment module 202 is configured to perform compensation processing on the second intermediate data signal according to the first intermediate data signal to reduce the signal swing of the second intermediate data signal, and perform compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.
It can be seen that, for an application scenario where a difference exists, the embodiment of the present disclosure may further connect the adjustment module 202 between two differential signals (the first intermediate data signal and the second intermediate data signal), so as to reduce the signal swing of the first intermediate data signal and the second intermediate data signal at the same time.
Accordingly, the target data signal comprises a first target data signal and a second target data signal, the transmission module 203 comprises a first transmission module 206 and a second transmission module 207, wherein:
a first transmission module 206, configured to perform drive enhancement processing on the compensated first intermediate data signal to obtain a first target data signal;
the second transmission module 207 is configured to perform drive enhancement processing on the compensated second intermediate data signal to obtain a second target data signal.
One end of the adjusting module 202 is connected to the output end of the first converting module 204 and the input end of the first transmitting module 206, respectively, and the other end of the adjusting module 202 is connected to the output end of the second converting module 205 and the input end of the second transmitting module 207, respectively.
As shown in fig. 12, the connection node between the first conversion module 204 and the first transmission module 206 is denoted by PupMid node, and the connection node between the second conversion module 205 and the second transmission module 207 is denoted by PupMid node. The adjustment module 202 is connected between the PupMid node and the PupMid node, and is capable of performing compensation processing on the first intermediate data signal according to the second intermediate data signal, reducing the signal swing of the first intermediate data signal, that is, reducing the signal swing of the PupMid node, performing compensation processing on the second intermediate data signal according to the first intermediate data signal, reducing the signal swing of the second intermediate data signal, that is, reducing the signal swing of the PupMid node, then obtaining a first target data signal (also referred to as DataPu) through the first transmission module 206, and obtaining a second target data signal (also referred to as DataPd) through the second transmission module 207, where it can be understood that the first target data signal and the second target data signal are also a pair of differential signals, and are mutually opposite signals. Finally, the first transmission path (the first conversion module 204 and the second transmission module 206) and the second transmission path (the second conversion module 205 and the second transmission module 207) can both transmit high-frequency signals, and the high-frequency performance of the circuit is effectively improved.
Further, for an application scenario where a difference exists, taking the adjustment module 202 including the transmission gate module 2021 and the first not gate 2022 as an example, referring to fig. 13, a specific structure diagram of a data conversion circuit provided in an embodiment of the disclosure is shown. As shown in fig. 13, the structure and function of the first conversion module 204 and the second conversion module 205 are the same as those of the conversion module 201 in fig. 8 or 9, and the specific structure and function thereof can be understood with reference to the descriptions of fig. 10 and 11. Meanwhile, the first conversion module 204 and the second conversion module 205 may also share the same clock signal generator 2015, and the first transmission module 206 and the second transmission module 207 have the same structure and function as the transmission module 203 in fig. 8 or 9. The detailed description of the functions thereof will not be repeated here.
The difference between the differential scenario is that the connection mode of the adjustment module 202 is different, and at this time, the adjustment module 202 is connected between the PupMid node and the PupMid node, so that the signal swing of the PupMid node can be reduced according to the second intermediate data signal, and the signal swing of the PupMid node can be reduced according to the first intermediate data signal.
The four initial data received by the first conversion module 204 are DataER, dataEF, dataOR and DataOF, the four initial data received by the second conversion module 205 are DataERN, dataEFN, dataORN and DataOFN, respectively, it can be understood that DataER and DataERN are a pair of inverted signals, the clock signals for sampling the pair of inverted signals are SedCKER, dataEF and DataEFN are a pair of inverted signals, the clock signals for sampling the pair of inverted signals are SedCKEF, dataOR and DataORN are a pair of inverted signals, the clock signals for sampling the pair of inverted signals are SedCKOR, dataOF and DataOFN are a pair of inverted signals, and the clock signals for sampling the pair of inverted signals are SedCKOF.
Likewise, for the application scenario where there is a difference, the adjustment module 202 may be implemented by the resistor module 2023, where the resistor module 2023 is connected between the PupMid node and the PupMid node. Or according to the connection mode of fig. 8 or fig. 9, two adjusting modules 202 are provided to reduce signal swing of PupMid node and PupMid node, which is also beneficial to transmitting high-frequency data and improving high-frequency performance of the circuit. For a more detailed description of fig. 13, it can be understood with reference to the foregoing fig. 8 to 10, and a detailed description thereof will be omitted herein.
In short, the data conversion circuit provided by the embodiment of the disclosure can increase the conversion rate from parallel data to serial data, and in order to increase the high-frequency performance of the data conversion circuit, the swing of the PupMid node is reduced to increase the high-frequency performance, and for an application scenario without difference, the data conversion circuit is mainly realized by an adjustment module connected between the PupMid node and the PupMidN node in a bridging manner. In the high-speed mode, HSEn signals are high, the transmission tube is conducted, so that the swing amplitude of PupMid nodes is reduced, the signal bandwidth is increased, and the purpose of transmitting high-frequency data is achieved, or the high-speed data transmission is achieved through a resistor module connected between PupMid nodes and PupMidN nodes in a bridging mode. For the scene with difference, as the same data is to be output in a difference way, when the PupMid node is in a High level (High), the PdnMid node is in a Low state, and therefore, the purpose of transmitting High-speed data can be achieved by adding a transmission tube between the PupMid node and the PdnMid node to simultaneously reduce the voltage swing of the PupMid node and the PdnMid node.
The embodiment of the disclosure provides a data conversion circuit, which comprises a conversion module, an adjustment module and a transmission module, wherein one end of the adjustment module is used for receiving compensation signals, the other end of the adjustment module is respectively connected with the output end of the conversion module and the input end of the transmission module, the conversion module is used for receiving initial data signals, carrying out parallel-to-serial conversion on the initial data signals to obtain intermediate data signals, the adjustment module is used for carrying out compensation processing on the intermediate data signals according to the compensation signals so as to reduce signal swing of the intermediate data signals, and the transmission module is used for carrying out driving enhancement processing on the intermediate data signals after the compensation processing to obtain target data signals. Therefore, the adjustment module is arranged in the data conversion circuit, and performs compensation processing on the intermediate data signal according to the compensation signal, so that the signal swing of the intermediate data signal can be reduced, namely, the signal swing of a connecting node of the conversion module and the transmission module is reduced, the signal bandwidth is increased, the purpose of transmitting high-frequency data is finally achieved, and the high-frequency performance of the circuit is improved.
In another embodiment of the present disclosure, referring to fig. 14, a flow chart of a data conversion method provided by an embodiment of the present disclosure is shown. As shown in fig. 14, the method may include:
s1001, receiving an initial data signal through a conversion module, and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal.
And S1002, receiving a compensation signal through an adjustment module, and carrying out compensation processing on the intermediate data signal according to the compensation signal so as to reduce the signal swing of the intermediate data signal.
And S1003, receiving the intermediate data signal after the compensation processing through a transmission module, and performing drive enhancement processing on the intermediate data signal after the compensation processing to obtain a target data signal.
In some embodiments, compensating the intermediate data signal according to the compensation signal includes turning on the transmission gate module to compensate the intermediate data signal according to the compensation signal when the enable control signal is in an active state, or turning off the transmission gate module when the enable control signal is in an inactive state.
In some embodiments, the enable control signal comprises a first enable control signal and a second enable control signal, and the method may further comprise receiving the first enable control signal through a first NOT gate and performing inversion processing on the first enable control signal to obtain the second enable control signal.
In some embodiments, compensating the intermediate data signal according to the compensation signal includes compensating the intermediate data signal according to the compensation signal by a resistor module to reduce a signal swing of the intermediate data signal.
In some embodiments, the driving enhancement processing is performed on the intermediate data signal after the compensation processing to obtain a target data signal, including:
the first transmission sub-module is used for carrying out reverse phase processing on the intermediate data signal after compensation processing to obtain an initial target data signal;
And carrying out reverse phase processing on the initial target data signal through the second transmission sub-module to obtain the target data signal.
In some embodiments, the method may further include determining the initial target data signal as the compensation signal.
In some embodiments, the parallel to serial processing of the initial data signal to obtain an intermediate data signal includes:
Receiving first initial data and a first clock signal through a first conversion sub-module, and sampling the first initial data according to the first clock signal to obtain first intermediate data;
Receiving second initial data and a second clock signal through a second conversion sub-module, and sampling the second initial data according to the second clock signal to obtain second intermediate data;
receiving third initial data and a third clock signal through a third conversion sub-module, and sampling the third initial data according to the third clock signal to obtain third intermediate data;
receiving fourth initial data and a fourth clock signal through a fourth conversion sub-module, and sampling the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;
The phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are respectively 0 degree, 90 degrees, 180 degrees and 270 degrees, and the first intermediate data, the second intermediate data, the third intermediate data and the fourth intermediate data form an intermediate data signal.
In some embodiments, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, and the parallel-to-serial processing is performed on the initial data signals to obtain the intermediate data signal, including:
Receiving a first initial data signal through a first conversion module, and performing parallel-to-serial conversion on the first initial data signal to obtain a first intermediate data signal;
And receiving a second initial data signal through a second conversion module, and performing parallel-to-serial conversion on the second initial data signal to obtain a second intermediate data signal.
In some embodiments, the compensation signal includes a first intermediate data signal and a second intermediate data signal, and the compensation processing for the intermediate data signal according to the compensation signal includes:
the second intermediate data signal is compensated according to the first intermediate data signal by the adjusting module to reduce the signal swing of the second intermediate data signal, and the first intermediate data signal is compensated according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.
In some embodiments, the target data signal includes a first target data signal and a second target data signal, and the driving enhancement processing is performed on the intermediate data signal after the compensation processing to obtain the target data signal, including:
performing driving enhancement processing on the compensated first intermediate data signal through a first transmission module to obtain a first target data signal;
and performing driving enhancement processing on the second intermediate data signal subjected to compensation processing through a second transmission module to obtain a second target data signal.
In some embodiments, the initial data signal is a parallel data signal and the intermediate data signal and the target data signal are both serial data signals.
It should be noted that the data conversion method provided in the embodiments of the present disclosure may be applied to the data conversion circuit 20 described in the foregoing embodiments, and for details not disclosed in the embodiments of the present disclosure, please refer to the description of the foregoing embodiments for understanding.
The embodiment of the disclosure provides a data conversion method, which performs compensation processing on an intermediate data signal according to a compensation signal, and can reduce the signal swing of the intermediate data signal, so that the signal bandwidth is increased, the purpose of transmitting high-frequency data is finally achieved, and the high-frequency performance of a circuit is improved.
In yet another embodiment of the present disclosure, referring to fig. 15, a schematic diagram of a composition structure of a semiconductor memory provided in an embodiment of the present disclosure is shown. As shown in fig. 15, the semiconductor memory 150 may include at least the data conversion circuit 20 according to any one of the foregoing embodiments.
In some embodiments, semiconductor memory 150 is a dynamic random access memory DRAM chip.
In the embodiment of the present disclosure, the DRAM may not only conform to the memory specifications of DDR, DDR2, DDR3, DDR4, DDR5, etc., but also conform to the memory specifications of LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., and is not limited herein.
In the embodiment of the disclosure, for the semiconductor memory 150, since the data conversion circuit 20 described in the foregoing embodiment is included, the signal bandwidth is increased, and finally, the purpose of transmitting high-frequency data is achieved, thereby improving the performance of the memory.
The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the present disclosure.
It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.
The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments.
The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.