Vertical OECT based on porous semiconductor channel and preparation method thereofTechnical Field
The invention belongs to the technical field of organic electrochemical transistors, and particularly relates to a vertical OECT based on a porous semiconductor channel and a preparation method thereof.
Background
The organic electrochemical transistor (organic electrochemical transistor, OECT) can be applied to bioelectrodes, wearable electrons and artificial nerve electrons due to its low driving voltage (< 1V), low power consumption (< μW), high transconductance (> 10 mS) and excellent mechanical flexibility and stretchability. In OECT, the biggest difference from conventional field effect transistors is that the semiconductor constituting the channel has both ion and electron/hole conduction capability. Therefore, when an electrolyte is used as the dielectric layer, ions in the electrolyte can be injected into/precipitated from the semiconductor body by the gate bias, and a unit capacitance of up to μf/cm2 or more is formed, so that extremely high transconductance (> 10 mS) can be realized at extremely low driving voltage (< 1V).
In addition, compared with the traditional transistor, the OECT has the advantages of high sensitivity, miniaturization, high flux sensing, flexibility, biocompatibility and the like, and the advantages of light weight, low cost, flexibility, simple preparation method, multiple types and the like of the organic material, compared with the traditional silicon-based metal oxide semiconductor field effect transistor, the preparation process replaces the complex process of manufacturing devices by the traditional high-temperature vacuum deposition method with simple processes such as low-temperature deposition or solution (ink jet printing, spin coating, dripping coating and the like). Therefore, the method has great application potential in weak signal amplification, biological signal detection/monitoring and brain-like nerve.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a vertical OECT (organic electronic emission computed tomography) preparation method based on a porous semiconductor channel, which further promotes the effective doping of ions in a semiconductor on one hand and ensures that a device has a short channel with a diameter of microns or less on the other hand. The porous semiconductor channel prepared by the solution method is constructed, so that low-cost large-area preparation of vertical OECT is realized, an effective ion transmission path is introduced into a porous structure, and the obstruction of an upper electrode (drain electrode) of the vertical structure to ion transmission is avoided. In addition, the vertical structure can effectively avoid the shape degradation of the semiconductor in repeated doping cycles, and can realize OECT with high cycle stability.
In order to achieve the aim, the OECT based on the porous semiconductor channel is characterized by comprising a substrate, a source electrode, a porous semiconductor layer, a drain electrode, an encapsulation layer, an electrolyte layer and a grid electrode;
The semiconductor device comprises a substrate, a rectangular strip-shaped source electrode, a square porous semiconductor layer, a grid electrode, a packaging layer, an electrolyte layer, a grid electrode and a grid electrode, wherein the rectangular strip-shaped source electrode is arranged at the center of the substrate, the square porous semiconductor layer is arranged at the center of the source electrode, the width of the porous semiconductor layer is larger than that of the source electrode, the porous is in a vertically penetrating structure in the semiconductor layer, the opening of the porous close to the drain electrode is smaller than that of the porous close to the source electrode, the rectangular strip-shaped drain electrode is arranged at the center of the porous semiconductor layer, the width of the drain electrode is smaller than that of the porous semiconductor layer, the packaging layer is arranged at the center of the drain electrode, the square hole is formed at the center of the packaging layer, the size of the opening is required to meet the requirement that the drain electrode is exposed out of all or part of the area overlapped with the source electrode when the packaging layer is seen from the top view, the electrolyte layer is covered above the packaging layer, the square hole is required to be completely covered by the size of the electrolyte layer, the grid electrode is arranged above the electrolyte layer, the grid electrode is fully contacted with the electrolyte layer, or the grid electrode is arranged on the side of the porous semiconductor layer, and the grid electrode is located on the same plane;
and a control signal is applied to the grid electrode, and ions in the electrolyte layer can penetrate into or separate out of the semiconductor layer through the porous holes under the action of source-drain voltage between the drain electrode and the source electrode, so that the conductivity of the semiconductor layer is regulated and controlled.
The invention aims at realizing the following steps:
The invention relates to an OECT based on a porous semiconductor channel and a preparation method thereof, which mainly comprise a substrate, a source electrode, a porous semiconductor layer, a drain electrode, a packaging layer, an electrolyte layer and a grid electrode, wherein in the preparation process, the substrate is prepared firstly in a vertical structure mode, the substrate is cleaned and dried, then the source electrode is prepared on the substrate in sequence, the porous semiconductor layer is prepared on the source electrode, the drain electrode is prepared on the porous semiconductor layer, the packaging layer is prepared on the substrate, the overlapping part of the drain electrode and the source electrode is exposed, the electrolyte layer is prepared above the drain electrode, and finally the grid electrode connected with the electrolyte layer is prepared.
Meanwhile, the OECT based on the porous semiconductor channel and the preparation method thereof have the following beneficial effects:
(1) The vertical structure device is adopted, the channel length can be controllably adjusted within the range of 100 nm-10 mu m, and various indexes of the transistor, such as current density, switching speed, capacitance and the like, can be adjusted according to the channel length;
(2) The porous semiconductor layer is adopted, ions in the electrolyte dielectric layer are doped or separated out of the semiconductor through the multiple holes under the action of gate voltage, so that the doping of the ions in the vertical structure to the semiconductor is prevented from penetrating from the electrolytic edge, the ion transmission path is greatly shortened, the carrier concentration in the semiconductor is further effectively controlled, and the conductivity of the semiconductor is changed;
(3) The porous structure is used in the mode that the diameter of the upper opening is smaller than that of the lower opening, so that the contact between the drain electrode and the source electrode can be effectively avoided when the drain electrode at the top of the porous structure is prepared, and the short circuit of the device is avoided;
(4) The current density and the transconductance of the vertical OECT device based on the porous structure provided by the invention can not be influenced by the dimensional change of the source electrode and the drain electrode, so that the output current and the transconductance can be linearly regulated through the dimensions of the source electrode and the drain electrode, and the vertical OECT device based on the porous structure can be suitable for applications with different requirements on the current density and the transconductance. (ii) a step of (iii) a step of (;
(5) The vertical OECT device preparation method based on the porous structure is compatible with a large-scale solution preparation method, can effectively reduce preparation energy consumption and preparation cost, is compatible with a flexible stretchable substrate, and can realize stable device performance maintenance and output under extreme stress conditions;
(6) The device can change the shape of the opening of the packaging layer to control the ion doping/exudation efficiency, as shown in the effect (2), the size and the mode of the opening can change the ion penetrating efficiency by doping ions into and out of the semiconductor channel through the multiple holes, such as exposing the complete channel layer to the outside, applying the grid voltage for conducting the device, penetrating ions into the channel from all the multiple holes at the same time, and exuding ions from the multiple holes after the voltage is removed, such as exposing only part of the multiple holes to the outside, the ion penetrating/exudation efficiency is reduced, thereby controlling the ion moving distance, changing the time characteristic curve of the device, and simultaneously introducing the storage function.
Drawings
FIG. 1 is a hierarchical structure diagram of a vertical OECT based porous semiconductor layer of the present invention;
FIG. 2 is a transfer characteristic of an output current;
FIG. 3 is a block diagram of a vertical OECT based on a porous semiconductor layer employing a top fully covered gate and a side gate, respectively;
Detailed Description
The following description of the embodiments of the invention is presented in conjunction with the accompanying drawings to provide a better understanding of the invention to those skilled in the art. It is to be expressly noted that in the description below, detailed descriptions of known functions and designs are omitted here as perhaps obscuring the present invention.
Examples
Fig. 1 is a layered structure diagram of a vertical OECT based porous semiconductor layer of the present invention.
In this embodiment, a vertical OECT based on a porous semiconductor layer, as shown in FIG. 1 (a), is a cross-sectional view of OECT, comprising a substrate 1, a source 2, a porous semiconductor layer 3, a drain 4, an encapsulation layer 5, an electrolyte layer 6, and a gate 7;
A rectangular strip-shaped source electrode 2 is arranged at the center of a substrate 1 shown in fig. 1 (b), a square porous semiconductor layer 3 is arranged on the source electrode 2, the width of the porous semiconductor layer 3 is larger than that of the source electrode 2, a rectangular strip-shaped drain electrode 4 is arranged at the center of the porous semiconductor layer 3, the width of the drain electrode 4 is smaller than that of the semiconductor layer 3, the drain electrode 4 does not cover or shield the porous part of the semiconductor, a packaging layer 5 is arranged at the center of the drain electrode 4, a square hole is formed at the center of the packaging layer 5, the size of the square hole is only required to expose the overlapping area of the drain electrode 4 and the source electrode 2 when seen from a top view, the size of the packaging layer 5 is required to cover an electrolyte layer 6 when seen from a top view, the size of the electrolyte layer 6 is required to completely cover the square hole of the packaging layer 5, a grid electrode 7 is arranged above the electrolyte layer 6, and the grid electrode 7 is fully contacted with the electrolyte layer 6, as shown in fig. 1 (f);
The gate electrode 7 may be an electrode sheet directly above the electrolyte layer 6 as in fig. 3 (a), and the gate electrode 7 may be a side surface of the porous semiconductor layer 3 at the same plane as the source electrode 2 as in fig. 3 (b);
Under the action of source-drain voltage between the drain electrode 4 and the source electrode 2, ions in the electrolyte layer 6 can enter or precipitate into the semiconductor layer 3 through porous permeation, so that the conductivity of the semiconductor layer is controlled, and the characteristics of the signals can be influenced by various factors including the porous diameter, the porous density, the thickness of the porous semiconductor, the opening size of the packaging layer and the like, so that the conditions can be controlled according to actual conditions, the migration time of electrons and ions can be effectively regulated, and the OECT performance (including current magnitude, transconductance magnitude and response time) can be effectively regulated.
In this embodiment, the substrate is one of glass, silicon wafer, polyethylene terephthalate PET, polyethylene naphthalate PEN, polydimethylsiloxane PDMS, or polyurethane PU.
In the embodiment, the width of the electrodes of the source electrode and the drain electrode is 1-500 μm, and the electrode is specifically made of an electrochemically stable conductive material, specifically one of gold, platinum, carbon nanotubes or graphene, and the gate electrode is made of a conductive material with electrochemical activity or without electrochemical activity, specifically one of gold, silver, poly-3, 4-ethylenedioxythiophene, polystyrene sulfonate, carbon nanotubes, graphene and graphite alkyne.
In this embodiment, the thickness of the semiconductor layer is 100nm to 1 μm, and the semiconductor layer is specifically made of a composite semiconductor material having both ion conductors and electric conductors.
In this embodiment, the encapsulation layer is made of an electrochemically stable insulating material, and is specifically one of parylene-C, cellulose, photoresist SU-8, polystyrene, polydimethylsiloxane PDMS, and polystyrene-ethylene-butylene SEBS.
In this embodiment, the electrolyte layer is a solid or liquid electrolyte having no conductive properties but having ion-conducting properties.
The following describes in detail a preparation method of vertical OECT based on a porous semiconductor layer according to the present invention by combining the above materials, specifically including the following steps:
(1) The glass substrate shown in FIG. 1 (b) was ultrasonically cleaned using isopropyl alcohol for 15 minutes and oven dried at 80℃for 2 hours.
(2) Sequentially evaporating 3nm chromium and 120nm gold on the cleaned glass substrate as source electrodes, wherein the width is 30-120 mu m, as shown in fig. 1 (c);
(3) Carrying out ultraviolet ozone cleaning treatment on the glass substrate evaporated with the electrode layer for about 10 minutes;
(4) Preparing a spin-coated semiconductor layer having a crosslinking function by controlling the humidity to 85% or more, spin-coating at 5000rpm for 30s (forming a porous semiconductor by vapor condensation due to spin-coating under high humidity conditions), photolithography by exposing the semiconductor film at the channel to light with 365nm ultraviolet light to crosslink it to form a semiconductor layer at the channel region, as shown in FIG. 1 (d);
(5) Preparing 120nm gold as a drain electrode on the semiconductor layer, wherein the width of the electrode is 30-120 mu m, as shown in fig. 1 (e);
(6) Preparing a spin-coating packaging layer with a photocrosslinking function, and exposing by using 365nm ultraviolet light to expose a patterned channel, as shown in fig. 1 (f);
(7) Approximately 1 μl of PBS buffer was added dropwise to the exposed channels as a dielectric layer, and the gate was connected through the dielectric layer, as shown in fig. 1 (g).
Up to this point, the vertical OECT device with the porous semiconductor layer was successfully fabricated, and in this embodiment, the source electrode, the drain electrode, and the gate electrode were fabricated by one of evaporation, magnetron sputtering, spraying, inkjet printing, aerosol printing, and screen printing. The semiconductor layer, the packaging layer and the electrolyte layer are prepared by one method of spin coating, screen printing, ink-jet printing, 3D printing, aerosol printing, electrofluidic printing or knife coating.
The following we performed the test using the vertical OECT prepared as follows:
The constant drain voltage VD =0.1V, the gate source voltage is set between 0.3V and-0.5V to scan forward, the output current is captured to obtain transfer characteristic and graph, as shown in figure 2, the device has extremely large current regulation effect under the test condition, the control of source current (solid line) from 10-8 A to 10-2 A is realized, the gate current always keeps low level (< 10-7 A), the devices with different channel shapes have different hysteresis responses, the rule is that the width of the top electrode is reduced, the ion permeation path is shortened, the hysteresis of the output current is smaller, and the hysteresis is more obvious on the contrary;
While the foregoing describes illustrative embodiments of the present invention to facilitate an understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but is to be construed as protected by the accompanying claims insofar as various changes are within the spirit and scope of the present invention as defined and defined by the appended claims.