Disclosure of Invention
In view of the foregoing, embodiments of the present application provide a method and a system for measuring a semiconductor structure, which are used for characterizing uniformity of an active layer.
In order to achieve the above object, the embodiment of the present application provides the following technical solutions:
a first aspect of an embodiment of the present application provides a method for measuring a semiconductor structure, including the steps of:
providing a first semiconductor structure, wherein the first semiconductor structure comprises a first active layer, a first gate oxide layer and a first gate electrode, wherein the first gate oxide layer and the first gate electrode are stacked on the first active layer, and the projection of the first gate electrode on the first active layer comprises a first central area and a first edge area surrounding the first central area;
providing a second semiconductor structure, wherein the second semiconductor structure and the first semiconductor structure are prepared on the same wafer, the second semiconductor structure comprises a second active layer, a second gate oxide layer and a second gate electrode, the second gate oxide layer and the second gate electrode are stacked on the second active layer, and the second gate electrode projects on the second active layer and comprises a second central region and a second edge region surrounding the second central region;
acquiring a capacitance value C Total (S) 1 of the first semiconductor structure and a capacitance value C Total (S) 2 of the second semiconductor structure;
acquiring a ratio of the capacitance value of the first central region to the capacitance value of the second central region, and acquiring a ratio of the capacitance value of the first edge region to the capacitance value of the second edge region;
And obtaining the ratio of the capacitance value of the first central region to the capacitance value of the first edge region according to the ratio of the capacitance values of the C Total (S) 1, the C Total (S) 2 and the first central region to the capacitance value of the second central region and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region.
The method for measuring a semiconductor structure as described above, wherein the step of obtaining the capacitance value C Total (S) 1 of the first semiconductor structure and the capacitance value C Total (S) 2 of the second semiconductor structure includes:
Acquiring a capacitance value between the first gate and the first active layer in the first semiconductor structure, wherein the capacitance value is marked as C Total (S) 1;
and acquiring a capacitance value between the second grid electrode and the second active layer in the second semiconductor structure, wherein the capacitance value is marked as C Total (S) 2.
The method for measuring a semiconductor structure as described above, wherein the step of obtaining a capacitance value between the first gate and the first active layer in the first semiconductor structure, where the capacitance value is denoted as C Total (S) 1, includes:
Providing a first power module, wherein the first power module is connected with the first grid and is used for providing voltage for the first grid;
Providing a first detection module connected with the first active layer and used for measuring the amplitude and phase offset of current after flowing through the first grid electrode and the first grid oxide layer;
c Total (S) 1 is obtained according to the voltage value, the amplitude and the phase offset of the current.
The measuring method of the semiconductor structure, wherein the first power module is connected with the first grid through a first connecting wire;
The first detection module is connected with the first active layer through a second connecting wire.
The measuring method of the semiconductor structure, as described above, wherein a first bonding pad is provided between the first connection wire and the first gate electrode, and a second bonding pad is provided between the second connection wire and the first active layer.
The method for measuring the semiconductor structure comprises the steps of arranging a plurality of first semiconductor structures in an array;
the number of the first connecting wires is multiple, and each first connecting wire is connected with a first bonding pad of each first semiconductor structure on the same row;
The number of the second connecting wires is multiple, and each second connecting wire is connected with the second bonding pad of each first semiconductor structure on the same row.
The method for measuring a semiconductor structure as described above, wherein when the number of the first semiconductor structures is plural, the step of obtaining the capacitance value C Total (S) 1 of the first semiconductor structure when the plural first semiconductor structures are arranged in an array includes:
Acquiring total capacitance values between the first active layers and the first gates of the plurality of first semiconductor structures;
And obtaining an average value of capacitance values between the first active layer and the first grid electrode of the first semiconductor structure according to the total capacitance values between the first active layer and the first grid electrode of the first semiconductor structure, wherein the average value is used as C Total (S) 1.
The method for measuring a semiconductor structure as described above, wherein the step of acquiring the capacitance value between the second gate and the second active layer in the second semiconductor structure includes:
Providing a second power module, wherein the second power module is connected with the second grid and is used for providing voltage for the second grid;
providing a second detection module connected with the second active layer and used for measuring the amplitude and phase offset of current after flowing through the second grid electrode and the second grid oxide layer;
c Total (S) 2 is obtained according to the voltage value, the amplitude and the phase offset of the current.
The measuring method of the semiconductor structure, wherein the second power module is connected with the second grid through a third connecting wire;
The second detection module is connected with the second active layer through a fourth connecting wire.
The measuring method of the semiconductor structure, wherein a third bonding pad is arranged between the third connecting wire and the second grid electrode, and a fourth bonding pad is arranged between the fourth connecting wire and the second active layer.
The method for measuring the semiconductor structure comprises the steps of arranging a plurality of second semiconductor structures in an array;
The number of the third connecting wires is multiple, and each third connecting wire is connected with a third bonding pad of each second semiconductor structure on the same row;
The number of the fourth connecting wires is multiple, and each fourth connecting wire is connected with a fourth bonding pad of each second semiconductor structure on the same row.
The method for measuring a semiconductor structure as described above, wherein when the number of the second semiconductor structures is plural, and the plural second semiconductor structures are arranged in an array, the step of obtaining the capacitance value between the second gate and the second active layer in the second semiconductor structure includes:
Acquiring total capacitance values between the second active layers and the second grid electrodes of the plurality of second semiconductor structures;
And obtaining an average value of capacitance values between the second active layers and the second gates of the second semiconductor structures according to the total capacitance values between the second active layers and the second gates of the plurality of second semiconductor structures, wherein the average value is used as C Total (S) 2.
The method for measuring a semiconductor structure as described above, wherein the step of obtaining the ratio of the capacitance value of the first central region to the capacitance value of the second central region and the ratio of the capacitance value of the second edge region to the capacitance value of the second edge region includes:
The widths of the first central area and the first edge area are A along the first direction;
In the second direction, the length of the first central region is a, the length of the first edge region is A-a, the area of the first central region is A x a, and the area of the first edge region is A x (A-a);
along the first direction, the widths of the second central region and the second edge region are nA;
Along the second direction, the length of the second central region is (n-1) A+a, the length of the second edge region is A-a, the area of the second central region is [ (n-1) A+a ] ×nA, and the area of the second edge region is nA (A-a);
The ratio of the capacitance value of the first central region to the capacitance value of the second central region is
The ratio of the capacitance value of the first edge region to the capacitance value of the second edge region is
The method for measuring a semiconductor structure as described above, wherein the ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained by the following formula:
wherein Cc1 represents the capacitance of the first center region, C2 represents the capacitance of the first edge region, and m represents the ratio of C Total (S) 1 to C Total (S) 2.
The method for measuring a semiconductor structure as described above, wherein the first central region includes a first edge and a second edge disposed opposite to each other;
the first edge region comprises a first region and a second region, the first region is in fit with the first edge, and the second region is in fit with the second edge;
the capacitance value of the first edge region is equal to the sum of the capacitance value of the first region and the capacitance value of the second region.
A second aspect of an embodiment of the present application provides a measurement system for a semiconductor structure, including:
a first semiconductor structure including a first active layer, and a first gate oxide layer and a first gate electrode stacked on the first active layer, a projection of the first gate electrode on the first active layer including a first central region and a first edge region surrounding the first central region;
a second semiconductor structure including a second active layer, and a second gate oxide layer and a second gate electrode stacked on the second active layer, the second gate electrode projecting on the second active layer including a second center region and a second edge region surrounding the second center region;
The widths of the first central area and the second central area are different, and the widths of the first edge area and the second edge area are the same;
The processor is used for acquiring a capacitance value C Total (S) 1 of the first semiconductor structure and a capacitance value C Total (S) 2 of the second semiconductor structure, acquiring a ratio of the capacitance value of the first central area to the capacitance value of the second central area and a ratio of the capacitance value of the first edge area to the capacitance value of the second edge area, and obtaining a ratio of the capacitance value of the first central area to the capacitance value of the first edge area according to the ratio of the capacitance value of the C Total (S) 1, the capacitance value of the C Total (S) 2, the capacitance value of the first central area to the capacitance value of the second central area and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area.
The measurement system of a semiconductor structure as described above, wherein the processor includes a first power module, a first detection module, a second power module, and a second detection module;
the first power supply module is connected with the first grid and used for providing voltage for the first grid;
The first detection module is connected with the first active layer and is used for measuring the amplitude and phase offset of current after flowing through the first grid electrode and the first grid oxide layer;
the second power supply module is connected with the second grid electrode and used for providing voltage for the second grid electrode;
the second detection module is connected with the second active layer and is used for measuring the amplitude and phase offset of current after flowing through the second grid electrode and the second grid oxide layer.
The measuring system of the semiconductor structure comprises a first power module, a second power module, a first detection module, a second detection module and a first active layer, wherein the first power module is connected with the first grid through a first connecting wire;
The second power module is connected with the second grid electrode through a third connecting wire, and the second detection module is connected with the second active layer through a fourth connecting wire.
The measuring system of the semiconductor structure, wherein the number of the first semiconductor structures is a plurality, and the plurality of the first semiconductor structures are arranged in a rectangular array;
the number of the first connecting wires is multiple, and each first connecting wire is connected with the first grid electrode of each first semiconductor structure on the same row;
The number of the second connecting wires is multiple, and each second connecting wire is connected with the first active layer of the first semiconductor structure on the same row.
The measuring system of the semiconductor structure, wherein the number of the second semiconductor structures is a plurality, and the plurality of the second semiconductor structures are arranged in a rectangular array;
The number of the third connecting wires is multiple, and each third connecting wire is connected with the second grid electrode of each second semiconductor structure on the same row;
The number of the fourth connecting wires is multiple, and each fourth connecting wire is connected with the second active layer of the first semiconductor structure on the same row.
In the measuring method and the measuring system for the semiconductor structure provided by the embodiment of the application, the capacitance values of the first semiconductor structure and the second semiconductor structure are obtained respectively, meanwhile, the ratio of the capacitance value of the first central area to the capacitance value of the second central area and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area are obtained on the premise that the second semiconductor structure and the first semiconductor structure are prepared on the same wafer, and the thickness uniformity of the active layer is judged according to the ratio of the capacitance value of the first central area to the capacitance value of the first edge area.
In addition to the technical problems, technical features constituting the technical solutions, and beneficial effects caused by the technical features of the technical solutions described above, the method for measuring a semiconductor structure and the system for measuring a semiconductor structure provided by the embodiments of the present application, other technical features included in the technical solutions, and beneficial effects caused by the technical features are described in further detail in the detailed description.
Detailed Description
In the related art, a capacitance value between the active layer and the gate is generally measured, and the transistor performance is represented by the capacitance value, but in the above manner, the capacitance value between the central region of the active layer and the gate and the capacitance value between the edge region of the active layer and the gate cannot be measured, so that the thickness uniformity of the active layer cannot be represented.
In view of the above technical problems, in this embodiment, the ratio of the capacitance value of the first central area to the capacitance value of the second central area and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area are obtained by respectively obtaining the capacitance values of the first semiconductor structure and the second semiconductor structure, and meanwhile, on the premise that the second semiconductor structure and the first semiconductor structure are prepared on the same wafer, the thickness uniformity of the active layer is determined by the magnitude of the ratio.
In order to make the above objects, features and advantages of the embodiments of the present application more comprehensible, the technical solutions of the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The semiconductor structure is not limited in this embodiment, and a Dynamic Random Access Memory (DRAM) will be described as an example of the semiconductor structure, but the embodiment is not limited thereto, and the semiconductor structure in this embodiment may be other structures.
As shown in fig. 1, the method for preparing a semiconductor structure provided by the embodiment of the application includes the following steps:
Step S100, providing a first semiconductor structure, wherein the first semiconductor structure comprises a first active layer, a first gate oxide layer and a first gate electrode, wherein the first gate oxide layer and the first gate electrode are stacked on the first active layer, and the projection of the first gate electrode on the first active layer comprises a first central area and a first edge area surrounding the first central area.
As shown in fig. 2, the first semiconductor structure 100 may further include a substrate 110, where the substrate 110 serves as a supporting component of the dynamic random access memory for supporting other components disposed thereon, and the substrate 110 may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound.
As shown in fig. 2, the first active layer 120 is disposed on the substrate 110, where the first active layer 120 is generally formed by an epitaxial growth process, and the first active layer 120 generally has a structure with a thick middle and thin two sides, so that a longitudinal section of the first active layer 120 has a trapezoid structure with a small top and a large bottom, and the material of the first active layer 120 may include silicon germanium.
The first gate oxide layer 130 is disposed on the first active layer 120, where the first gate oxide layer 130 may be a single film layer or a stacked structure, and when the first gate oxide layer 130 may include an oxide layer 131 and a dielectric layer 132, the oxide layer 131 is disposed on a surface of the first active layer 120 facing away from the substrate 110, the dielectric layer 132 is disposed on a surface of the oxide layer 131 facing away from the first active layer 120, and a material of the oxide layer 131 may include an insulating material such as silicon oxide, and the dielectric layer 132 may include HfO2, hfSiO, hfSiON, hfAlO, hfZrO, al2O3, taO2, and the like, where the material has a high dielectric constant.
The first gate electrode 140 is disposed on the first gate oxide layer 130, and the first gate electrode 140 and the first active layer 120 have an overlapping area, and when a voltage difference exists between the first gate electrode 140 and the first active layer 120, an electrostatic field distribution exists between the first gate electrode 140 and the first active layer 120, so that charges are stored under the action of the electrostatic field, the stored charge quantity qalways is in direct proportion to the voltage U thereof, and the ratio is denoted by C.
The projection of the first gate electrode 140 on the first active layer 120 includes a first central region 150 and a first edge region 160, wherein the first edge region 160 is disposed around the first central region 150.
At this time, the capacitance value C Total (S) 1 between the first gate electrode 140 and the first active layer 120 is equal to the sum of the capacitance value of the first center region and the capacitance value of the first edge region, and the formula is as follows:
C Total (S) 1＝Cc1+Ce1 (equation 1.1)
Cc1 represents the capacitance value of the first center region, and Ce1 represents the capacitance value of the first edge region.
As shown in fig. 2, the capacitance value of the first central region refers to the capacitance value of the capacitance formed between the first gate electrode and the first active layer in the middle box, and the capacitance value of the first edge region refers to the capacitance value of the capacitance formed between the first gate electrode and the first active layer in the left and right boxes.
In this embodiment, the first edge area 160 is disposed around the first central area 150, which may be understood that the first edge area 160 semi-surrounds the first central area 150, for example, as shown in fig. 3, along the second direction, that is, the X direction in fig. 3, the first central area 150 has a first edge 151 and a second edge 152 disposed opposite to each other, the first edge area 160 includes a first area 161 and a second area 162, the first area 161 is disposed in a manner of being attached to the first edge 151, and the second area 162 is disposed in a manner of being attached to the second edge 152.
When the first edge region 160 includes the first region 161 and the second region 162, the capacitance value of the first edge region 160 is equal to the sum of the capacitance value of the first region 161 and the capacitance value of the second region 162.
Step 200, providing a second semiconductor structure, wherein the second semiconductor structure and the first semiconductor structure are prepared on the same wafer, the second semiconductor structure comprises a second active layer, a second gate oxide layer and a second gate electrode, the second gate oxide layer and the second gate electrode are stacked on the second active layer, the second gate electrode projects on the second active layer and comprises a second central area and a second edge area surrounding the second central area, the widths of the first central area and the second central area are different, and the lengths of the first edge area and the second edge area are the same.
It should be noted that, since the second semiconductor structure and the first semiconductor structure are prepared on the same wafer, the structure of the second semiconductor structure may be considered similar to that of the first semiconductor structure in the embodiment under the same preparation conditions, that is, the shapes of the first edge region and the second edge region are the same, and only the lengths of the first center region and the second center region are different.
As shown in fig. 4, the second gate electrode 240 projects on the second active layer 220 to include a second center region 250 and a second edge region 260, the second edge region 260 being disposed around the second center region 250.
The capacitance value C Total (S) 2 of the second semiconductor structure is equal to the sum of the capacitance value of the second center region and the capacitance value of the second edge region, and the formula is as follows:
C Total (S) 2＝Cc2+Ce2 (equation 1.2)
Cc2 represents the capacitance value of the second center region, and Ce2 represents the capacitance value of the second edge region.
Step S300 includes obtaining a capacitance value C Total (S) 1 of the first semiconductor structure and a capacitance value C Total (S) 2 of the second semiconductor structure.
Illustratively, as shown in fig. 5, a first power module 300 is provided, the first power module 300 being coupled to the first gate 140 for providing a voltage to the first gate 140, e.g., the first power module 300 may apply a voltage of known amplitude and frequency to the first gate 140.
Providing a first detection module 400, the first detection module 400 being connected to the first active layer 120 for measuring the amplitude and phase shift of the current after flowing through the first gate electrode 140 and the first gate oxide 130;
from the voltage value, the amplitude and the phase shift of the current, C Total (S) 1 is obtained, that is, C Total (S) 1 is calculated based on the voltage, the amplitude and the phase shift of the current, and the calculation formula is as follows:
Wherein V represents the voltage value of the first power supply module, I represents the amplitude of the current,Representing the phase offset.
The first gate 140 may be directly connected to the first power module 300 or indirectly connected to the first power module 300, for example, as shown in fig. 5, a first connection wire 310 is disposed between the first gate 140 and the first power module 300.
In order to facilitate connection between the first connection wire 310 and the first gate 140, a first pad 141 may be disposed on the first gate 140, the first connection wire 310 is connected to the first pad 141, and the first pad 141 transmits an electrical signal on the first gate 140, so that accuracy of detecting the voltage of the first gate 140 may be improved.
A second connection wire 410 is disposed between the first active layer 120 and the first detection module 400, and in order to facilitate connection between the second connection wire 410 and the first active layer 120, a second pad 121 may be disposed on the first active layer 120, and the second connection wire 410 may be connected to the second pad 121.
In some embodiments, the number of the first semiconductor structures 100 may be plural, and the plural first semiconductor structures 100 are arranged in an array, for example, as shown in fig. 5, the number of the first semiconductor structures 100 is nine, and the nine first semiconductor structures 100 are arranged in three rows and three columns.
The number of the first connection wires 310 is plural, and each first connection wire connects the first pads 141 of the respective first semiconductor structures 100 located on the same row.
The number of the second connection wires 410 is plural, and each second connection wire 410 is connected to the second pad 121 of each first semiconductor structure 100 located on the same row.
At this time, the capacitance value of each first semiconductor structure 100 needs to be measured by the above measurement method to obtain the total capacitance value between the first active layers 120 and the first gates 140 of the plurality of first semiconductor structures 100.
Based on the total capacitance between the first active layer 120 and the first gate 140 of the plurality of first semiconductor structures 100, an average value of the capacitance between the first active layer 120 and the first gate 140 of the first semiconductor structure 100 is obtained, and the average value is C Total (S) 1.
In this embodiment, a plurality of first semiconductor structures are provided, and the average value of the capacitance values of the first semiconductor structures is obtained as C Total (S) 1, so that the accuracy of the capacitance value C Total (S) 1 of the first semiconductor structure can be ensured, and further, the ratio of the capacitance values of the first center region and the first edge region, which are accurate, can be obtained later, is ensured.
In this embodiment, the manner of obtaining the capacitance value C Total (S) 2 of the second semiconductor structure may be performed according to the following steps:
Illustratively, as shown in fig. 6, a second power module 500 is provided, the second power module 500 being connected to the second gate 240 for providing a voltage to the second gate 240, a voltage of known amplitude and frequency being applied to the second gate 240 by the second voltage module.
Providing a second detection module 600, the second detection module 600 being connected to the second active layer 220 for measuring the amplitude and phase shift of the current after flowing through the second gate electrode 240 and the second gate oxide layer;
From the voltage value, the amplitude of the current, and the phase offset, C Total (S) 2 is obtained, that is, C Total (S) 2 is calculated based on the voltage, the current, and the phase offset.
It should be noted that, the calculation formula of the capacitance value C Total (S) 2 of the second semiconductor structure is the same as the calculation formula of C Total (S) 1 described above, and the description of this embodiment is omitted here.
The second gate 240 may be directly connected to the second power module 500 or indirectly connected to the second power module 500, for example, as shown in fig. 4, a third connection wire 510 is disposed between the second gate 240 and the second power module 500.
In order to facilitate connection between the third connection wire 510 and the second gate electrode 240, a third pad 241 may be disposed on the second gate electrode 240, and the third connection wire 510 is connected to the third pad 241.
A fourth connection wire 610 is disposed between the second active layer 220 and the second detection module 600, and in order to facilitate connection between the fourth connection wire 610 and the second active layer 220, a fourth pad 221 may be disposed on the second active layer 220, and the fourth connection wire 610 may be connected to the fourth pad 221.
In some embodiments, the number of the second semiconductor structures 200 may be plural, and the plural second semiconductor structures 200 are arranged in an array, for example, as shown in fig. 4, the number of the second semiconductor structures 200 is nine, and the nine second semiconductor structures 200 are arranged in three rows and three columns.
The number of the third connection wires 510 is plural, and each third connection wire 510 is connected to the first pad 141 of each second semiconductor structure 200 located on the same row.
The number of the fourth connection wires 610 is plural, and each fourth connection wire 610 is connected to the second pad 121 of each second semiconductor structure 200 located on the same row.
At this time, the capacitance value of each second semiconductor structure 200 needs to be measured by the above measurement method, so as to obtain the total capacitance value between the second active layers 220 and the second gates 240 of the plurality of second semiconductor structures 200.
Based on the total capacitance value between the second active layer 220 and the second gate 240 of the plurality of second semiconductor structures 200, an average value of the capacitance values between the second active layer 220 and the second gate 240 of the second semiconductor structures 200 is obtained, which is C Total (S) 2.
The embodiment provides a plurality of second semiconductor structures, and the average value of the capacitance values of the second semiconductor structures is obtained as C Total (S) 2, so that the accuracy of the capacitance value C Total (S) 2 of the second semiconductor structures can be ensured, and further, the ratio of the capacitance values of the first central region and the first edge region, which are accurate, can be obtained later.
Step S400, obtaining the ratio of the capacitance value of the first central area to the capacitance value of the second central area, and obtaining the ratio of the capacitance value of the second edge area to the capacitance value of the second edge area.
In the present embodiment, the shape of the projection of the first gate electrode 140 on the first active layer 120 is assumed to be square, while the shape of the projection of the second gate electrode 240 on the second active layer 220 is also assumed to be square.
As shown in fig. 3, the widths of the first center region 150 and the first edge region 160 are both a in the first direction, i.e., the Y direction in fig. 3.
In the second direction, i.e., the X direction in fig. 3, the length of the first central region 150 is a and the length of the first edge region is a-a, and correspondingly, the area of the first central region 150 is axa and the area of the first edge region 160 is axx (a-a).
As shown in fig. 4, the width of the second center region 250 and the width of the second edge region 260 are nA in the first direction, that is, the Y direction in fig. 4.
Since the first semiconductor structure 100 and the second semiconductor structure 200 are prepared on the same wafer, the length of the first edge region 160 and the length of the second edge region 260 are the same on the premise that the epitaxial growth process is the same, and thus the length of the second edge region 260 is a-a, and accordingly, the length of the second central region 250 is equal to nA- (a-a), that is, the length of the second central region 250 is equal to (n-1) a+a.
The area of the second center region 250 is the length of the second center region 250 times the width of the second center region 250, expressed as [ (n-1) a+a ] ×na), and the area of the second edge region 260 is equal to the length of the second edge region 260 times the width of the second edge region 260, expressed as nA (a-a).
Capacitance-based formulaWhere ε is a dielectric constant, S is the facing area of the capacitor plate, d is the distance of the capacitor plate, k is the dielectric constant, and the capacitance and area are proportional under the same dielectric constant.
Thus, the ratio of the capacitance of the first center region 150 to the capacitance of the second center region 250 isThe formula is as follows:
wherein Cc1 represents the capacitance value of the first central region and Cc2 represents the capacitance value of the second central region.
The ratio of the capacitance of the first edge region 160 to the capacitance of the second edge region 260 isThe formula is as follows:
Wherein Ce1 represents the capacitance value of the first edge region, and Ce2 represents the capacitance value of the second edge region.
Dividing equation 1.1 by equation 1.2 yields the following equation:
substituting the above equations 1.3 and 1.4 into equation 1.5 to obtain the ratio of the capacitance values of the first center region and the first edge region is specifically as follows:
Wherein Cc1 represents the capacitance of the first center region, Cc2 represents the capacitance of the first edge region, and m represents the ratio of C Total (S) 1 to C Total (S) 2.
According to the embodiment, the capacitance values of the first semiconductor structure and the second semiconductor structure are obtained respectively in the mode, meanwhile, on the premise that the second semiconductor structure and the first semiconductor structure are prepared on the same wafer, the ratio of the capacitance value of the first central area to the capacitance value of the second central area and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area are obtained, and according to the values, the ratio of the capacitance value of the first central area to the capacitance value of the first edge area is obtained, and the thickness uniformity of the active layer is judged according to the size of the ratio.
Example two
The embodiment of the present application further provides a measurement system of a semiconductor structure, as shown in fig. 2 to 6, where the measurement system includes a first semiconductor structure 100, the first semiconductor structure 100 includes a first active layer 120, and a first gate oxide layer 130 and a first gate 140 stacked on the first active layer 120, and a projection of the first gate 140 on the first active layer 120 includes a first central region 150 and a first edge region 160 surrounding the first central region 150;
the second semiconductor structure 200, and the second semiconductor structure 200 includes a second active layer 220 and a second gate oxide layer and a second gate electrode 240 stacked on the second active layer 220, the second gate electrode 240 projecting on the second active layer 220 including a second central region 250 and a second edge region 260 surrounding the second central region 250.
The widths of the first and second central regions 150 and 250 are different, and the widths of the first and second edge regions 160 and 260 are the same.
The processor is used for acquiring a capacitance value C Total (S) 1 of the first semiconductor structure and a capacitance value C Total (S) 2 of the second semiconductor structure, acquiring a ratio of a capacitance value of the first central area to a capacitance value of the second central area and a ratio of a capacitance value of the first edge area to a capacitance value of the second edge area, and acquiring a ratio of the capacitance value of the first central area to the capacitance value of the first edge area according to C Total (S) 1、C Total (S) 2, the ratio of the capacitance value of the first central area to the capacitance value of the second central area and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area.
According to the embodiment, the ratio of the capacitance value of the first central area and the capacitance value of the first edge area of the first semiconductor structure is obtained through the arrangement of the processor, and the thickness uniformity of the active layer is judged through the ratio, so that a theoretical basis is provided for the preparation of the first semiconductor structure.
In some embodiments, the detection modules may include a first power module 300, a first detection module 400, a second power module 500, and a second detection module 600.
The first power module 300 is connected to the first gate 140 and is used for providing a voltage to the first gate 140.
The first detection module 400 is connected to the first active layer 120 for measuring the amplitude and phase shift of the current after flowing through the first gate electrode and the first gate oxide layer.
The first gate 140 may be directly connected to the first power module 300 or indirectly connected to the first power module 300, for example, as shown in fig. 4, a first connection wire 310 is disposed between the first gate 140 and the first power module 300.
In order to facilitate connection between the first connection wire 310 and the first gate electrode 140, a first pad 141 may be disposed on the first gate electrode 140, and the first connection wire 310 is connected to the first pad 141.
A second connection wire 410 is disposed between the first active layer 120 and the first detection module 400, and in order to facilitate connection between the second connection wire 410 and the first active layer 120, a second pad 121 may be disposed on the first active layer 120, and the second connection wire 410 may be connected to the second pad 121.
Note that, when the number of the first semiconductor structures 100 is plural, the plural first semiconductor structures 100 are arranged in a matrix array, for example, as shown in fig. 5, the number of the first semiconductor structures 100 is nine, and the nine first semiconductor structures 100 are arranged in three rows and three columns.
The number of the first connection wires 310 is plural, and each first connection wire connects the first pads 141 of the respective first semiconductor structures 100 located on the same row.
The number of the second connection wires 410 is plural, and each second connection wire 410 is connected to the second pad 121 of each first semiconductor structure 100 located on the same row.
The second power module 500 is connected to the second gate 240 for providing a voltage to the second gate 240.
The second detection module 600 is connected to the second active layer 220 for measuring the amplitude and phase shift of the current after flowing through the second gate electrode 240 and the second gate oxide layer.
The second gate 240 may be directly connected to the second power module 500 or indirectly connected to the second power module 500, for example, as shown in fig. 4, a third connection wire 510 is disposed between the second gate 240 and the second power module 500.
In order to facilitate connection between the third connection wire 510 and the second gate electrode 240, a third pad 241 may be disposed on the second gate electrode 240, and the third connection wire 510 is connected to the third pad 241.
A fourth connection wire 610 is disposed between the second active layer 220 and the second detection module 600, and in order to facilitate connection between the fourth connection wire 610 and the second active layer 220, a fourth pad 221 may be disposed on the second active layer 220, and the fourth connection wire 610 may be connected to the fourth pad 221.
When the number of the second semiconductor structures 200 may be plural, the plural second semiconductor structures 200 are arranged in an array, for example, as shown in fig. 6, the number of the second semiconductor structures 200 is nine, and the nine second semiconductor structures 200 are arranged in three rows and three columns.
The number of the third connection wires 510 is plural, and each third connection wire 510 is connected to the first pad 141 of each second semiconductor structure 200 located on the same row.
The number of the fourth connection wires 610 is plural, and each fourth connection wire 610 is connected to the second pad 121 of each second semiconductor structure 200 located on the same row.
In forming the active layer, the active layer is easy to form a structure with a thick middle and thin two sides, so the embodiment is based on the technical problem, and a measurement system of a semiconductor structure is designed so as to be convenient for measuring the ratio of the capacitance value of the central area of the active layer to the capacitance value of the edge area, and the thickness uniformity of the active layer is measured by the ratio.
In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application.
In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It should be noted that the above embodiments are merely for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.