Detailed Description
First, the following explanation is made on terms of the present invention:
FPGA, field programmable gate array, preferably Intel corporation AgilexTM, and employing Intel complementDevelopment was performed. MCU (microcontroller unit, microcontrol unit) is based on a soft-core implementation, preferably a Nios II fast-core. Avalon interface, UART, universal asynchronous receiver transmitter, which is used for high-speed data stream transmission, read-write register, memory and control of off-chip equipment. JTAG, test access interface. SDRAM, synchronous dynamic random access memory. "programs" may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. The term "Time Division Multiplexing (TDM)", by employing different time periods of the same physical connection to transmit different signals, can achieve multiplexing purposes. The term in the invention is mainly aimed at dealing with the space domain optimization requirement when more than two modules are needed in the FPGA design, and the space domain optimization is carried out on a plurality of modules which are not used simultaneously and have the same function.
The technical scheme of the invention is described below with reference to the accompanying drawings.
Some hard core interface modules communicate with the MCU through read-write dual-port RAM. The top layer entity of the hard core interface module is shown in figure 1, wherein the input signals comprise clock signals, waveform Data, slave board state, dual-port RAM read-write state, fault signals and notification signals;
Some hard core interface modules include the main underlying modules in fig. 2:
The state monitoring module monitors the dual-port RAM and outputs the read-write state of the dual-port RAM;
The waveform data writing module is used for writing the voltage waveform data and the current waveform data into the dual-port RAM;
A slave board data writing module for writing the slave board data and the slave board data into the dual-port RAM;
The command writing-in and reading module is used for writing the commands sent by the MCU to the hard core into the dual-port RAM;
the parameter transfer module is used for controlling the transfer of configuration parameters between the MCU and the hard core;
The fault signal writing module is used for writing the fault signal into the dual-port RAM and modifying the information of the fault pointer at the same time;
And the time-sharing multiplexing module is used for controlling the time-sharing multiplexing of the read-write of the dual-port RAM by all the bottom layer modules.
The multiplexing module is configured to send a second enabling signal to the state detection module when judging that the dual-port RAM is not occupied, and the state detection module is configured to start working after receiving the second enabling signal.
The principle of some hard core interface modules is as shown in fig. 3, communication between the hard core and the MCU is realized through a dual-port RAM, wherein the dual-port RAM is composed of five RAM blocks with consistent reading and writing, and the dual-port RAM is respectively configured as follows:
The first RAM block is used for storing the read-write state of the dual-port RAM;
A second RAM block for storing a data block including the waveform data, the slave board state;
the third RAM block is used for storing cache data for the MCU to inquire;
a fourth RAM block for storing data exchanged between the hard core and the MCU;
and a fifth RAM block for storing the fault code.
The state detection module of some embodiments is configured to perform state detection on the dual-port RAM at regular intervals;
The state detection module sends the state of the dual-port RAM to any one or more modules of the command writing and reading module, the parameter transfer module, the fault signal writing module and the waveform data writing module;
And after any one or more modules of the command writing and reading module, the parameter transfer module, the fault signal writing module and the waveform data writing module receive the state of the dual-port RAM, sending a RAM request instruction to the time-sharing multiplexing module.
The hard core interface module of some embodiments further performs the step of allowing the time division multiplexing module to write and read the command, the parameter transfer module, the fault signal writing module, the waveform data writing module, and the state detection module in sequence according to the priority from high to low, allowing the request RAM instruction of the corresponding module.
Some of the sub-modules of the parameter delivery module include:
The MCU configuration parameter buffer module is used for reading configuration parameters from an external memory and storing the configuration parameters into an internal memory, wherein the configuration parameters are modified by the MCU;
The updating and initializing module is used for transmitting the index catalog and the numerical value of the configuration parameters to the waveform data writing module for checking whether the numerical value of the transformer is changed after the data of the APF control system is updated, the UART module for informing a slave board of checking whether the numerical value of the configuration parameters is to be modified, the protection module for checking whether the configuration parameters are modified, and the DFT module for checking whether the configuration parameters are required to be modified;
and the issuing configuration data caching module is used for caching configuration parameters issued by the control terminal of the APF control system.
In some more specific embodiments, the waveform data writing module includes a sample writing module and a sample data processing module, wherein:
the detection module detects the read-write state of the dual-port RAM every 400Ms, and if the dual-port RAM is in an idle state, sends out a write signal to the dual-port RAM;
the sampling signal transmitting module is used for transmitting a sampling signal every 7811 clock cycles and controlling the sampling writing module to execute writing;
the sampling writing module is used for collecting the waveform data, generating a writing enabling signal, a writing address and writing data, writing the waveform data into the second RAM block at one time,
The waveform data comprise voltage waveform data and/or current waveform data, and specifically comprise three-phase power grid voltage waveform data, three-phase power grid current waveform data, three-phase load current waveform data and three-phase total compensation current waveform data;
And the sampling data processing module is used for converting the waveform data into actual values.
In some more specific embodiments, the sub-module of the sample writing module comprises:
the second RAM block state monitoring module is used for inquiring the state of the second RAM block at regular intervals and sending a writing instruction to the second RAM block;
The sampling execution module is used for executing the acquisition of the waveform data;
and the auxiliary sampling control module is used for sending sampling commands to the sampling execution module at regular intervals.
The configuration of the MCU of some embodiments is realized by embedding a Nios II architecture on an FPGA, and specifically comprises the following steps:
Loading a soft verification MCU CPU function based on a Nios II architecture on an FPGA;
Based on the Nios II architecture, a plurality of functional modules including an Avalon-MM tri-state bridge, a UART module, a Jtag port debugging module, an SDRAM controller module, a plurality of interval timers, a flash memory interface and a plurality of parallel IO ports are integrated.
Some APFs, constructed as shown in fig. 4, include a motherboard electrically connected to at least three devices, each device including three slave boards, a phase a slave board, a phase B slave board, and a phase C slave board, respectively.
Some APF control systems include a hard core implemented based on an FPGA, an MCU, and a dual port RAM for communication of the hard core with the MCU, the hard core further including a hard core interface module as in any of the embodiments described above.
A dual-port RAM is opened up in the FPGA to realize communication between the MCU and the hard core part. The dual port RAM size in this particular embodiment is 1024 bits by 64 bits. The dual port RAM was divided into 5 blocks, ram#1, rma#2, ram#3, ram#4, ram#5, respectively. Each RAM block holds different data. A 32bit MCU is configured with a 32bit x 32bit multiplier inside. Through practical tests, the MCU works relatively stably at 50M. The interface signals between the hard core and the MCU and the dual-port RAM are fixed, and no signal is directly exchanged between the hard core and the MCU, and the signals are transferred by the dual-port RAM.
The dual-port RAM is a shared multi-port memory which is provided with two sets of completely independent data lines, address lines and read-write control lines on an SRAM memory and allows two independent systems to randomly access the memory at the same time, and can allow an MCU or a hard core to randomly read or write the memory at the same time, but does not allow the MCU to simultaneously read and write one address unit and does not allow the hard core to read and write the same address unit.
The MCU (or FPGA hard core) can send a write command after the address and data to be written are ready on address_a and data_a, the pulse width of the write command is at least 1 global clock length (50M), and the length of a global clock is not allowed to be more than 5, otherwise, the dual-port RAM is written for the second time, and the actual test shows that the command pulse is 10M in width when the main frequency is 50M. The addresses_a and data_a need to be changed after wren_a is low, otherwise erroneous data is written to the erroneous address. The write-once dual-port RAM requires approximately 4 global clocks.
When the MCU reads the address unit which is being written by the hard core, the data read by the MCU is the historical value of the address unit, and when the MCU reads the address unit which is being written by the MCU, the data read by the hard core is also the historical value of the address unit. But when the MCU and the hard core write an address at the same time, the value of the address location is indeterminate. The historical values are saved to a caching module.
The invention is explained below by means of a specific example.
Example 1
1. Design of embedded MCU interface
An MCU interface module was built in the Quartz, and the types and functions of its pins are listed in Table 1.
TABLE 1 MCU interface function List
The MCU interface based on the Nios II soft core processor integrates a plurality of modules, and the description of the main modules is shown in Table 2:
TABLE 2 description of the Main modules of the MCU interface
| Name of the name | Description of the invention |
| CPU | NiosII processor |
| tri_state_bridge_0 | Avalon-MM tri-state bridge |
| Button | Parallel IO port |
| LED | Parallel IO port |
| RS232 | Universal asynchronous serial port (UART) module employing 232 level |
| RS232_485 | Universal asynchronous serial port (UART) module employing 232 level |
| RS232_dis | Universal asynchronous serial port (UART) module employing 232 level |
| jtag_uart_0 | Jtag port debugging module |
| CFI_FLASH | Flash memory interface |
| SDRAM | SDRAM controller |
| PIO_In | Parallel IO port |
| PIO_Out | Parallel IO port |
| sysid | SystemIDPeripheral |
| Timer_1 | Interval timer |
| Timer_2 | Interval timer |
| Sys_State | Parallel IO port |
| RAM_Control | Parallel IO port |
| RAM_Addr | Parallel IO port |
| RAM_Data_A | Parallel IO port |
| RAM_Data_B | Parallel IO port |
| RAM_Byte_En | Parallel IO port |
2. Design of hard core read-write RAM
In order to realize the operation of the hard core read-write RAM, thereby realizing the information communication between the MCU and the hard core, the definition of the input and output signals of the top layer entity of the hard core interface module is shown in the table 3.
TABLE 3 definition of input/output signals for top level entities
The following table gives the interface signals for the hard core and dual port RAM. Byteena _a is a write byte enable signal, which divides 64bit data written into RAM into 8 bytes, corresponding to byteena _a 8 bits, when corresponding bit is high, the bytes can be written into corresponding address unit, and other byte data in the address unit is kept unchanged from last historical value.
The interface signals between the MCU and the dual-port RAM are similar, but an additional clock matching module is added in the middle, so that the dual-port RAM is prevented from being written or read for many times.
TABLE 4 interface signals for hard core and dual port RAM
| Signal signal | Width of (L) | Description of the invention |
| data_a | 64bit | Writing data for dual port RAM |
| address_a | 10bit | Reading or writing addresses of dual port RAM |
| wren_a | 1bit | Request signal for writing dual port RAM |
| rden_a | 1bit | Request signal for reading dual port RAM |
| byteena_a | 8bit | Writing byte enable signals for dual port RAM |
| q_a | 64bit | Dual port RAM output data |
Each of the underlying modules is explained in detail below:
2.1 State monitoring Module
The module corresponds to a control register area, and outputs all RAM read-write states, and table 5 is a definition description of main input-output signals of the module.
TABLE 5 input/output Signal of State monitoring submodule
When the RAM is in the idle state, the state of the RAM block is detected every 1 ms. The signal En comes from the time division multiplexing sub-module, when the time division multiplexing module judges that the current RAM is not occupied, the signal En is in high level, and the RAM state monitoring module is informed to start working.
2.2 Waveform data writing Module
The module is used for controlling the FPGA hard core to write waveform data into the second RAM block for the MCU to read and display, and the table 6 is a definition description of main input and output signals of the module. The module comprises a sampling writing module and a sampling data processing module.
TABLE 6 definition of the Primary input/output Signal of waveform data write Module
Wherein the sampled data processing module is operative to convert the sampled voltage-current data into actual values. It should be noted that, the relationship between the actual value and the sampling value of the grid voltage is:
Wherein Us is the actual value of the grid voltage, and Us' is the sampling value. 2849 in the program is also hereby obtained.
The relation between the actual value and the sampling value of the grid current is:
Where is is the actual value of the grid voltage and is' is the sampled value. N represents the turn ratio of the external current transformer, and the parameter is issued through a screen and is processed and identified by an FPGA_MCU_APF_grid_Cur_Index_Rd module. The APF output side current sampling is the same as the net side current sampling, so the processing is the same.
The sample write module consists of small modules that support parallel computation of multiple small modules.
2.2.1 Second RAM Block status monitoring Module FPGA_MCU_RAM_sample
The function is to detect the state of RAM#2 once every 400ms, if the display MCU is idle, start to send out the signal written into the RAM block, show RAM is being used;
2.2.2 auxiliary sampling Control Module FPGA u MCU_RAM_Volt_Cur Sample Control
The sampling signal is sent out once every 7811 clock cycles (because the voltage and current waveform data are all 128 points/cycle), and the sampling execution module is controlled to collect data of twelve channels.
2.2.3 Sample execution Module FPGA_MCU_RAM Volt_Cur
Data acquisition of twelve channels is executed, wherein the data are respectively ABC three-phase power grid voltage, ABC three-phase power grid current, ABC three-phase load current and ABC three-phase total compensation current, each data is a point, a written enabling signal is generated, addresses are written, data are written, and the like, and the data are written into corresponding positions in the RAM at one time.
2.3 Slave board data write module
The function of the module is to write the data of voltage, current, temperature, protection, etc. sent from the controller into the RAM. The definition of the main input and output signals from the controller data write RAM control submodule is as follows in table 7:
TABLE 7 slave controller data write RAM control submodule
| Signal signal | Type(s) | Meaning of the following description |
| Index_St | Notification signal input | Informing the module that it can start working |
| Slave_Index_1A[63..0] | Data input | Slave plate a phase data |
| Slave_Index_1B[63..0] | Data input | Slave B phase data |
| Slave_Index_1C[63..0] | Data input | Slave plate C phase data |
| Slave_State_1A[7..0] | State input | Slave board a phase protection data |
| Slave_State_1B[7..0] | State input | Slave board B phase protection data |
| Slave_State_1C[7..0] | State input | Slave board C phase protection data |
| Wr_Req | Notification output | Enable signal for writing RAM |
| Addr[9..0] | Address signal output | Writing addresses to RAM |
| Byte_En[7..0] | Byte enable signal output | Byte enabling |
| Wr_Data[63..0] | Write data output | Writing data of RAM |
| RAM_Next | Notification signal output | Notification signal |
2.4 Command write read Module
The function of the module is to write the commands of the MCU interface to the FPGA hard core into the RAM, and then read the commands by the FPGA hard core. The main input/output signals are defined in table 8:
TABLE 8 Main input/output Signal of Command write read submodule
| Signal signal | Type(s) | Meaning of the following description |
| Rd_St | Notification signal input | Informing the module that it can start working |
| RAM_3_W_Ord[15..0] | Command signal input | Write command pointer |
| RAM_3_R_Ord[15..0] | Command signal input | Read command pointer |
| RAM_Data[63..0] | Data input | Data written into RAM |
| RAM_Command | Command signal input | Notification signal after command reading |
| Wr_Req | Notification signal output | Enable signal for writing RAM |
| Addr[9..0] | Address signal output | Writing addresses to RAM |
| Byte_En[7..0] | Byte enable signal output | Byte enabling |
| Wr_Data[63..0] | Write data output | Writing data of RAM |
| Rd_Req | Notification signal output | Enable signal for reading RAM |
| Confi_Rd_St | Notification signal output | Notification signal |
2.5 Parameter transfer Module
The function of the module is to control parameter transfer between MCU and FPGA hard core, the definition of main input and output signals is as shown in Table 9:
TABLE 9 Main input output Signal of parameter transfer submodule
The parameter transmission submodule consists of three small modules, namely:
2.5.1MCU configuration parameter cache module FPGA_MCU_RAM _Config_Rd
The function is that when the MCU modifies the parameters, the module reads the modified parameters from the external RAM, and simultaneously caches the parameters into the internal RAM, thereby facilitating parameter recall. After the MCU requests the parameters of the main controller, the parameters in the internal RAM are read, and then the parameters are written into the external RAM, and finally the parameters are used for screen display.
It should be noted that the external RAM is not located in the main controller of the APF control system.
2.5.2 Update and initialization Module FPGA_RAM_Config RAM Control
When the data update or the power-on signal is detected, the module sends an Index directory (Sys_Index) and a numerical value of system configuration parameters stored in the RAM to a waveform writing module for checking whether the numerical value of a mutual inductor is changed, a UART module for informing a slave board to check whether corresponding data is to be modified, a protection module for checking whether corresponding parameters are to be modified, and a DFT module for checking whether the corresponding parameters are to be modified. The module is mainly used for updating and initializing system data. When the configuration parameters are needed by the main board program, the control terminal judges whether to issue new configuration parameters by detecting three parameters, namely Sys_Config_Ud, sys_Index and cof_RAM_Data, so as to update the parameters. Each time after the configuration data is issued, the module first caches the modified data into the issued configuration data cache module, and then reads all parameters in the RAM all the way around. Every time a parameter is read, sys_Config_Ud is pulled high once, sys_Index outputs the Index corresponding to the currently read configuration parameter, and Cof_RAM_Data outputs the parameter value.
2.5.3 Issue configuration data caching Module FPGA_MCU_Config_RAM
All configuration data issued from the screen of the control terminal is cached.
2.6 Fault Signal writing Module
The function of the module is that when a hard core fails once, fault information is written into the RAM, and meanwhile, the information of a fault pointer in the RAM is modified. The definition of the input/output signals is shown in table 10:
TABLE 10 Primary input output Signal of Fault Signal writing submodule
2.7 Time division multiplexing module
The function of the module is to time-share multiplex the read-write signals of the RAM by each module, so that a plurality of modules can be prevented from simultaneously reading or simultaneously writing the RAM at the same time. The definition of the input/output signals is shown in table 11.
TABLE 11 definition of input/output Signal of time-division multiplexing submodule
3.APF
The APF is structured as in fig. 4, wherein the main controller is implemented based on an FPGA. The method for defining the device ID comprises the step that the main controller automatically distributes the ID through the serial number of the communication interface of the optical fiber.
The three-phase IDs of the device 1 are respectively: 0x010A,0x010B,0x010C;
the three-phase IDs of the device 2 are respectively: 0x020a,0x020b,0x020c;
The three-phase IDs of the device 3 are respectively: 0x030a,0x030b,0x030c;
when the ID is 0x0100,0x0200,0x0300. The description refers to a certain device (including ABC three phases), and 0xAAAA refers to all devices.
4. Hard core and MCU
As shown in fig. 3, the main controller is provided with a hard core part and an MCU.
The hard core mainly comprises a data acquisition sub-module, a power grid voltage phase locking sub-module, a sliding window DFT sub-module, a network side PR regulator sub-module, a reactive DQ extraction sub-module, a harmonic injection reference generation sub-module, an APF working mode selection sub-module, a high-speed optical fiber communication interface sub-module and the like, and also comprises auxiliary sub-modules such as a hardware protection sub-module, a time sequence control sub-module, an MCU data interface sub-module, a contactor control sub-module and the like, wherein the control of direct current side voltage is realized from a controller.
The hard core part is responsible for processing main functions of APF, including harmonic extraction, reference synthesis, high-speed asynchronous serial communication, etc., the part has higher real-time requirements, higher operation speed and more processing by a pipeline, and the MCU is responsible for processing contents with low real-time requirements, mainly comprising user interactive display communication, in the embodiment, a 32-bit MCU is configured, and a 32bit multiplied by 32bit multiplier is arranged inside the MCU. The running clock can work at 100M, but the 100M main frequency has larger pressure on external SDRAM, and through practical test, MCU work at 50M is relatively stable, and 100M is unstable in some cases. And can be properly improved according to actual conditions.
5. Dual port RAM
Preferably, a dual-port RAM is opened up inside the FPGA to realize the communication between the MCU and the hard core.
In a specific embodiment, the dual port RAM is 1024 bits by 64 bits in size, for a total of 64 kbits. The dual port RAM was divided into 5 blocks, ram#1,RMA#2,RAM#3,RAM#4, RAM #5. Each RAM block holds different data, but the read and write to the RAM blocks are consistent.
Some embodiments provide a method for implementing the dual port RAM based on SRAM, comprising the steps of:
Two sets of mutually independent access systems for the MCU and the hard core to access the SRAM are arranged on the SRAM, and each set of access system comprises a data line, an address line and a read-write control line;
the communication between the hard core and the MCU is realized by reading the SRAM, and the method comprises the following steps:
Allowing the hard core and the MCU to randomly read or write the SRAM through respective access systems;
the MCU is not allowed to simultaneously execute reading and writing to an address unit on the SRAM;
the hard check is not allowed to perform both reading and writing to an address location on the SRAM.
In some embodiments, the first RAM block coordinates the hard core and MCU to read or write to the second RAM block based on state information, including RAM2 read-write state, RAM4 read-write state, RAM2 device ID, parameter passing device ID, write failure pointer, read command pointer, write command pointer, MCU passing valid data bits of the parameter.
The communication between the hard core and the MCU is supported through the dual-port RAM, and information such as various electric data, switching states, stability of running lines and the like of the power grid system running in real time are displayed on a display screen, so that the real-time control of the running state of the power grid system is realized, and important data are stored.
When the MCU reads the address unit which is being written by the hard core, the data read by the MCU is the historical value of the address unit, and when the MCU reads the address unit which is being written by the MCU, the data read by the hard core is also the historical value of the address unit. But when the MCU and the hard core write an address at the same time, the value of the address location is indeterminate. The historical values are typically saved to a caching module.
The interface signals between the hard core and the MCU and the dual-port RAM are fixed, as shown in Table 12, and the interface signals between the MCU and the dual-port RAM are similar to the interface signals, but an additional clock matching module is added in the middle, so that the dual-port RAM is prevented from being written or read for many times.
TABLE 12 interface signals for hard core and dual port RAM
Wherein Byteena _a is a writing section enabling signal, 64bit data written into the RAM is divided into 8 bytes, corresponding to the 8 bits of byteena _a, when the corresponding bit is high, the bytes can be written into corresponding address units respectively, and other byte data in the address units are kept unchanged from the last historical value.
The timing of reading and writing to the dual port RAM is further illustrated by the following specific examples, taking the MCU read and write timing as an example (the hard core timing is similar thereto).
5.1 Read Dual port RAM timing
Preferably, the length of the RAM address is 10 bits at the maximum, the upper 6 bits are convenient for expansion, and the upper 0 bit of the 10-bit address is filled into the 16-bit address when the RAM is read. The data read from the dual-port RAM is placed in the array corresponding to the receive_data.
When the address_a of MCU (or hard core) on address line is ready, it can send read command, the pulse width of command is at least 1 global clock length (50M), and it does not allow for more than 5 global clock lengths, otherwise it can twice read dual-port RAM, when the main frequency is 50M, the command pulse is 10M. After a command is issued, data can be read from the q_a signal after an appropriate time. Reading dual port RAM at a time requires approximately 4 global clocks. Address_a is changed after rden_a is low, otherwise erroneous data is read.
5.2 Write Dual port RAM timing
The MCU (or hard core) can send a write command after preparing the address and data to be written on address_a and data_a, the pulse width of the write command is at least 1 global clock length (50M), and the pulse width of the write command is not allowed to exceed 5 global clock lengths, otherwise, the write dual-port RAM is written for the second time, and the actual test shows that the command pulse is 10M width when the main frequency is 50M. The addresses_a and data_a need to be changed after wren_a is low, otherwise erroneous data is written to the erroneous address. The write-once dual-port RAM requires approximately 4 global clocks.
It should be noted that, the speed of reading and writing the dual-port RAM is very fast, and for the MCU with the main frequency of 50M, it takes about 1ns to read or write the dual-port RAM once.
5.3 Data from each RAM Block
1RAM#1 data definition
RAM#1 corresponds to a control register area where all RAM read and write status data is stored, where the hard core and MCU will always query the space to determine the RMA space to operate, the detailed address definitions are as follows:
TABLE 13 Address definition of RAM#1
5.3.2RAM#2 data definition
And storing the related information of the APF system which is required to be displayed on the control terminal. The MCU reads the data and then updates the relevant data of the control terminal. The hard core writes at a rate of 200ms and only after all writes are completed is the MCU allowed to read from it, thus ensuring integrity. The read/write of the hard core and MCU is controlled by the RAM2_state in RAM#1, and other data of the RAM block is refreshed immediately as long as the operation state feedback information from the slave controller is updated. The refresh rate depends on the rate at which the MCU reads the RAM. The hard core only needs to send the compensation current waveform of a certain device required by the MCU, and the hard core judges which device the compensation waveform transmitted by the MCU needs to be transmitted by the hard core by reading the data in the RAM 2_ID. The following table gives detailed data definitions for the RAM block:
Table 14 RAM#2 data definition
The following table gives a detailed definition of the status of the device:
TABLE 15 device State definition
| Command code | Description of the invention |
| 0x0000 | Stop of |
| 0x0001 | Operation |
| 0x0002 | Failure of |
| 0x0003 | Offline |
| 0x0004 | Scram |
| 0x0005 | Standby |
| 0x0006 | Is not present in |
| Others | Standby for use |
Ram#3 data definition
The hard core receives the commands of the MCU and then sequentially executes the commands, and the hard core does not store the commands of the MCU and does not return a status signal, so that the MCU needs to query other related data of the RAM block to determine whether the execution of the commands is completed.
Table 16 RAM#3 data definition
TABLE 17 Command Format
The main controller automatically distributes ID through the serial number of the communication interface of the optical fiber;
ram#4 data definition
The method is used for transferring parameters between the hard core and the MCU, the transfer of the parameters takes pages as units, 9 pieces of data 0x 340-0 x342 are used for storing data transferred from the hard core to the MCU, 0x 343-0 x345 are used for sending MUC to setting of the parameters of the hard core, and the transfer of the data is controlled through the RAM4_ord, the RAM4_ID, the RAM4_addr and the RAM4_ENOB in the RAM # 1.
Table 18 data format for hard-core write and MCU read
Table 19 data format for MCU write, hard core read
The specific parameters are shown in the following table:
TABLE 20 read-write data parameters
5.3.5RAM#5 data definition
The method mainly comprises the steps of accessing fault codes, ensuring that when a plurality of faults happen simultaneously, old faults which are not read by an MCU can not be covered by new faults, and simultaneously writing 32 buffer areas of the fault codes, and when the faults happen, a hard core puts the ID of the fault equipment and the specific fault codes into the 0x3e 0-0 x3fd buffer area according to the pointed position in a write pointer 0x3ff for the MCU to read and store.
Data definition of RAM#5
TABLE 22 event code coding
Embodiments of the subject matter and the functional operations described in this specification can be implemented in computer programs or instructions, digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware, including the structures disclosed in this specification and structural equivalents thereof, or in combinations of one or more of the above. A computer suitable for carrying out the computer program comprises and can be based on a general purpose microprocessor or a special purpose microprocessor or both, or any other kind of central processing unit, as examples.
Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the activities recited in the claims can be executed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying drawings do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multi-tasking and parallel processing may be advantageous.