Disclosure of Invention
The present invention provides a method for acquiring wideband spread spectrum signals in parallel, which can solve at least one of the above problems.
In order to achieve the purpose, the invention adopts the following technical scheme:
a parallel acquisition method of broadband spread spectrum signals comprises the following steps,
step (ii) of1. Radio frequency input signal
After zero intermediate frequency, anti-aliasing filtering, ADC sampling and coding processing, the signals are changed into two paths of mutually orthogonal high-speed digital baseband coding signals which are I branch signals respectively
And Q branch signal
Wherein k represents the kth clock cycle, and the high-speed digital baseband coded signal is converted into a low-speed original bit-spreading signal after being subjected to local decoding deserialization and serial-parallel conversion respectively
And
simultaneously generating a low-speed synchronous channel associated clock signal;
driving a plurality of local carrier Doppler generators by the low-speed synchronous associated clock signal generated in the first step, wherein the carrier signal output by each carrier Doppler generator
And
with fixed phase offset
Wherein i represents the ith carrier Doppler generator, j represents the jth clock cycle, and the carrier Doppler frequency points are searched in a segmented manner under the control of a state machine; carrier signal output by each carrier Doppler generator
And
with the low-speed original bit-spread signal generated in the first step
And
multiplying to obtain multiplied signal
And
for stripping large carrier doppler in the original signal;
driving a plurality of local pseudo-code generators by the low-speed synchronous associated clock signal generated in the first step; local pseudo-code signal output by each pseudo-code generator
With fixed phase offset
Wherein i represents the ith pseudo-code generator, k represents the kth clock cycle, and the local pseudo-code Doppler frequency point is adjusted under the control of the state machine; local pseudo-code signal output by each pseudo-code generator
With the signal generated in the second step
And
carrying out partial matched filtering and coherent integration, and carrying out FFT operation on a coherent integration result;
fourthly, noise floor statistics is carried out on signal segments with correlation peak values appearing in FFT results of the third step, if the correlation peak ratio statistical noise is larger than a Threshold value Threshold, a correct correlation peak is found, carrier Doppler and code phase corresponding to the found correlation peak are calculated at the moment, and the carrier Doppler and the code phase are output backwards and transmitted to a tracking circuit; if no correlation peak is found, the carrier Doppler frequency point is switched through the state machine, and the search is continued.
Further, the step one specifically comprises the following steps,
s11, original radio frequency input signal
After zero intermediate frequency, anti-aliasing filtering, ADC sampling and coding processing, the signals are changed into two paths of mutually orthogonal high-speed digital baseband coding signals which are I branch signals respectively
And Q branch signal
Of a signal
Sum signal
Are equal in code rate, are all
;
S12, high-speed digital baseband coding signal
And
after being processed by local decoding deserializing and deserializing respectively, the signals are changed into low-speed original spread signals
And
simultaneously generating a low-speed synchronous channel clock signal having a frequency of
,
Size and high speed sampling clock
Is related to the serial-to-parallel ratio N in the relationship of
;
wherein
Is the original radio frequency signal of the input,
is Doppler frequency after zero intermediate frequency processing, and the sampling clock frequency of the high-speed digital baseband coding signal is
;
Then
Is a high-speed digital baseband coded signal
The sampled vector after the low-speed extraction is performed,
is a high-speed digital baseband coded signal
Sampling vectors after low-speed extraction, wherein braces are used for representing vector intervals after sampling, and vector elements are represented in the braces.
Further, the second step specifically comprises the steps of,
s21, driving a plurality of local carrier Doppler generators by using the low-speed synchronous associated clock signal generated in the step S12, wherein the carrier signals output by the carrier Doppler generators have fixed phase deviation
Of orthogonal signals
And
;
namely, the carrier amplitude of the ith carrier Doppler generator in the jth clock cycle is recorded as
And
i =1,2, …, N, then:
s22, carrier signals output by each carrier Doppler generator
And
and the low-speed original bit-spread signal generated in S12
And
multiplying to strip off the large carrier doppler in the original signal, the multiplied signal being
And
;
and
i.e. large carrier doppler in the original signal is stripped.
Further, the third step specifically comprises the steps of,
s31, driving a plurality of local pseudo-code generators by using the low-speed synchronous associated clock signal generated in the step S12, wherein each pseudo-code generator outputs a local pseudo-code signal
With fixed phase offset
;
S32, utilizing the on-chip distributed RAM of the FPGA to open up
Block buffer region, starting from the initial address of each block buffer region, storing a local pseudo code signal output by pseudo code generator
While the multiplied signal in S22 is simultaneously processed
And
writing in turn
A block cache region;
s33, read from buffer
And
into the block parallel correlator of the I branch and into the block parallel correlator of the Q branchAnd coherent integration, namely performing FFT (fast Fourier transform) processing on a coherent integration result, and sending the FFT result to a peak value detection circuit to detect a correlation peak.
Further, the fourth step is to perform noise floor statistics on the signal segments with the correlation peak values appearing in the FFT result of the third step, and if the correlation peak ratio statistical noise is greater than a Threshold value Threshold, the correct correlation peak is considered to be found, and at this time, the carrier doppler and code phase corresponding to the found correlation peak are calculated and transmitted to the tracking circuit; if no correlation peak is found, switching the carrier Doppler frequency point through a state machine, and continuing to search, specifically including,
s41, caching the square of the amplitude of the FFT operation result in the step S33, and counting the cached data as
Counting the time period
Max _ point, while calculating the Noise estimate value Noise if
Noise x Threshold, where Threshold represents a Threshold value, then the position where max _ point appears is deemed to be indeed the correlation peak position;
s42, if the correlation peak is found in the step S41, a code phase of the position of the correlation peak is deduced according to the FFT operation times in the step S41, a Doppler frequency shift value is deduced according to the position of the maximum spectrum peak in the FFT result, and then the code phase and the Doppler frequency shift value are transmitted to a tracking circuit;
and S43, if no correlation peak is found in the step S41, switching the carrier Doppler frequency point through the state machine, returning to the step S21, and continuing searching until all Doppler intervals are searched.
In another aspect, the present invention also discloses a computer readable storage medium storing a computer program, which when executed by a processor causes the processor to perform the steps of the above method.
According to the technical scheme, compared with the narrow-band spread spectrum signal, the bandwidth of the wide-band spread spectrum signal is wider, and the AD sampling rate is required to be as high as hundreds of megahertz and exceeds the direct processing capacity of most rear-end devices. At present, the mainstream spread spectrum fast acquisition algorithm aims at narrowband spread spectrum signals below 10Mbps, and no effective acquisition method is found for broadband spread spectrum signals. In order to solve the problem, the invention provides a parallel capturing method and a storage medium for broadband spread spectrum signals, which enable a back-end processing device to realize the rapid capturing of the broadband spread spectrum signals under bearable clock frequency under the condition of not reducing the sampling rate of a front end.
The invention comprises the following steps: the method comprises the following steps: the radio frequency input signal is subjected to radio frequency front end, ADC sampling and coding to obtain a high-speed digital baseband coding signal, then a low-speed original bit expansion signal is obtained through local decoding deserializing and serial-parallel conversion, and a low-speed synchronous channel associated clock signal is generated; step two: the low speed synchronous associated clock signal generated in the first step drives a plurality of local carrier Doppler generators. Multiplying the output carrier signal with fixed phase offset by the low-speed original bit-spread signal generated in the first step, and stripping the carrier Doppler in the original signal; step three: the low speed synchronous associated clock signal generated in the first step drives a plurality of local pseudo-code generators. Carrying out partial matched filtering and coherent integration on the output pseudo code signal with fixed phase offset and the signal generated in the second step, and carrying out FFT operation on a coherent integration result; step four: and performing peak detection on the FFT result of the third step. If the correct correlation peak is found, calculating the corresponding carrier Doppler and code phase; if no relevant peak is found, the carrier Doppler frequency point is switched, and the search is continued. The device of the invention consists of a front-end radio frequency processing circuit, an analog intermediate frequency processing circuit, a digital coding circuit and a baseband processing circuit. The invention utilizes the principle of 'space displacement time' and the principle of partial matched filtering to complete the capture of the broadband spread spectrum signal. Firstly, carrying out local decoding deserializing and serial-parallel conversion processing on two paths of mutually orthogonal high-speed digital baseband coding signals, converting the signals into low-speed original bit extension signals, and generating low-speed synchronous channel associated clock signals; then, a plurality of local carrier Doppler generators with fixed phase difference and a plurality of local pseudo-code generators are driven by a low-speed synchronous associated clock signal, and high-speed local carrier and pseudo-code signals are widened in space (circuit area); then multiplying the bit-spread signal by a plurality of local carriers for stripping larger Doppler, and sending the multiplication result and the local pseudo code signal into a partial matched filter for coherent integration processing; and finally, carrying out FFT operation on the result of coherent integration processing, comparing a peak signal with a noise bottom, if the ratio of the correlation peak to the noise bottom is greater than a threshold value, determining that a correct correlation peak is found, calculating carrier Doppler and code phase positions corresponding to the found correlation peak, outputting the carrier Doppler and code phase positions backwards and transmitting the carrier Doppler and code phase positions to a tracking circuit, and otherwise, switching carrier Doppler frequency points and continuing searching. To this end, parallel acquisition of the entire wideband spread spectrum signal is accomplished.
Through the steps, the broadband spread spectrum signal parallel capturing method and the storage medium realize the rapid capturing of the broadband spread spectrum signal through the space displacement time principle and the partial matching filtering principle. Because the bandwidth of the wideband spread spectrum signal is wider, its acquisition process requires a higher AD sampling rate, which is beyond the capability of most backend devices to directly process. By means of parallel expansion of the local carrier Doppler generator and the local pseudo code generator, the requirement of a system processing clock, namely the principle of space replacement time, is effectively reduced under the condition of utilizing more hardware resources, and the parallel capture algorithm technology is feasible and simple to implement; the partial matched filter and FFT algorithm is a capture algorithm commonly used at present, and a good balance point between hardware resources and time overhead can be obtained by adjusting parameters of the algorithm.
According to the design of the invention, the invention realizes a broadband spread spectrum signal parallel capturing method and a storage medium, the algorithm realization complexity is low, the capturing result is accurate, and the method is particularly suitable for the broadband spread spectrum signal capturing under a large dynamic scene.
According to the design of the invention, the invention realizes a broadband spread spectrum signal parallel capturing method and a storage medium, the algorithm is easy to integrate, and the reconstruction and the upgrade of the capturing algorithm in the existing narrow-band receiver are convenient.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
The embodiment of the invention utilizes the principle of 'space replacement time' and the principle of partial matched filtering to complete the capture of the broadband spread spectrum signal. Because the broadband spread spectrum signal often has the characteristics of high intermediate frequency (> 300 MHz), large bandwidth (> 200 MHz), large Doppler (> 2 MHz), high code rate (> 100 MHz) and the like, and even the clock rate inside a high-end FPGA chip is often difficult to exceed 200MHz, the general narrowband spread spectrum receiving scheme is no longer suitable for receiving the broadband spread spectrum signal. However, we know that a large amount of logic resources (LUT, D flip-flop, distributed RAM, multiplier, etc.) are provided inside a large-capacity FPGA chip, and if an original baseband signal running on a high-speed clock is converted to a low-speed clock in a "space replacement time" manner, the processing of the original signal can be completed by using the large amount of logic resources inside the large-capacity FPGA chip, and meanwhile, the coherent integration is performed on the original signal and a local code division block by using a partial matching filtering principle, so that the capture processing capability with the highest efficiency can be achieved, and the influence of large carrier doppler on code rate deviation can be greatly alleviated. The following is a detailed description:
as shown in fig. 1, the present invention is a hardware frame diagram of a system circuit of the apparatus, an input broadband radio frequency signal sequentially passes through a Low Noise Amplifier (LNA), an anti-mirror filter (SAW), a down converter, an anti-aliasing filter, an analog Automatic Gain Control (AGC), and AD sampling to obtain an intermediate frequency digital signal, the intermediate frequency digital signal is encoded into a high-speed digital code stream by a JESD204B, and then the high-speed digital code stream is sent to an FPGA chip, and baseband signal processing is completed inside the FPGA chip, where the baseband processing mainly refers to a parallel capture algorithm proposed by the present invention. The invention provides a broadband spread spectrum signal parallel capturing method and a storage medium based on FPGA (field programmable gate array), which are shown in figure 2 and are a digital logic framework diagram of the algorithm of the invention. The specific implementation steps are as follows:
the first step is as follows: radio frequency input signal
After zero intermediate frequency, anti-aliasing filtering, ADC sampling and coding processing, the signals are changed into two paths of mutually orthogonal high-speed digital baseband coding signals which are I branch signals respectively
And Q branch signal
Wherein k represents the kth clock cycle, and the high-speed digital baseband coded signal is converted into a low-speed original bit-spreading signal after being subjected to local decoding deserialization and serial-parallel conversion respectively
And
and simultaneously generating a low-speed synchronous channel associated clock signal.
Inputting orthogonal high-speed digital baseband coding signals to be processed by the FPGA as follows:
wherein
Is the original radio frequency signal of the input,
is Doppler frequency after zero intermediate frequency processing, and the sampling clock frequency of the high-speed digital baseband coding signal is
. I branch signal
And Q branch signal
Of a signal
Sum signal
Are equal in code rate, are all
;
To pair
And
after local decoding and deserializing, low-speed original spreading is obtainedBit signal
And
and generating a low speed synchronous channel clock having a frequency of
,
Size of and sampling clock frequency of high-speed digital baseband coding signal
Related to the series-parallel ratio N in the relationship of
. Low speed original bit-spread signal
And
can be expressed as:
is a high-speed digital baseband coded signal
The sampled vector after the low-speed extraction is performed,
is a high-speed digital baseband coded signal
Sampling vectors after low-speed extraction, wherein braces "{ }" represent vector intervals after sampling, and vector elements are represented in the braces { }.
Fig. 3 is a schematic diagram of a baseband signal deserialization timing.
The second step is that: the low-speed synchronous associated clock signal generated in the first step drives a plurality of local carrier Doppler generators, and the carrier signal output by each carrier Doppler generator
And
with fixed phase offset
Wherein i represents the ith carrier Doppler generator, j represents the jth clock cycle, and the carrier Doppler frequency points are searched in a segmented manner under the control of a state machine; carrier signal output by each carrier Doppler generator
And
with the low-speed original bit-spread signal generated in the first step
And
multiplying to obtain multiplied signal
And
for stripping large carrier doppler in the original signal;
the local carrier Doppler generator is mainly composed of NCO in FPGA, driving clock frequency of NCO and sampling clock frequency of high-speed digital baseband coding signal
Is equal to
Driven by a clock of (2), each time a clock cycle passes
A carrier phase point is obtained. If N carrier phase points are obtained, N clock cycles are required, that is, N clock cycles are required
. But of a broadband baseband signal
Often > 300MHz, such high sample rate carrier NCO cannot be implemented on a device, thus requiring parallel spread design of the NCO.
FIG. 4 is a schematic diagram of a parallel spread design of a carrier Doppler NCO. By the first step, a low speed associated clock can be generated
In a
At a sampling rate of (3), where N carrier NCO's are used to operate simultaneously, then in one clock cycle
N carrier phase values may also be obtained. Will each beThe fixed phase offset between the signals generated by the individual carrier NCO is set to
Then, at this time, the sampling result of the N parallel carrier NCO under the low-speed clock can be equivalent to the sampling result of the 1 carrier NCO under the high-speed clock. The carrier amplitude of the ith carrier NCO in the jth clock cycle is recorded as
And
(i =1,2, …, N), then there are:
carrier signal output by each carrier Doppler generator
And
and the low-speed original bit-spread signal generated in the first step
And
multiplying, the multiplied signal being recorded as
And
then, there are:
and
i.e. large carrier doppler in the original signal is stripped.
The third step: the low-speed synchronous associated clock signal generated in the first step drives a plurality of local pseudo-code generators; local pseudo-code signal output by each pseudo-code generator
With fixed phase offset
Wherein i represents the ith pseudo code generator, k represents the kth clock cycle, and the Doppler frequency point of the local pseudo code is adjusted under the control of a state machine; local pseudo-code signal output by each pseudo-code generator
With the signal generated in the second step
And
carrying out partial matched filtering and coherent integration, and carrying out FFT operation on a coherent integration result;
fig. 5 is a schematic diagram of code NCO parallel expansion design. Similar to the second step, the code NCO is also usedAnd (5) designing line expansion. At low speed clock
Then, N code NCO's are used to work simultaneously, and the fixed phase offset between pseudo code signals generated by the code NCO's is set to
The method can be equivalent to the sampling result of 1 code NCO under a high-speed clock. The local pseudo-code signal output by the ith code NCO in the kth clock cycle is recorded as
. Then utilizing on-chip distributed RAM of FPGA to open up
A block buffer for storing an initial phase fixed offset of
Local pseudo code signal of
Simultaneously, the signal in the second step after the large carrier wave Doppler in the original signal is stripped
And
also written in turn
A block buffer.
As shown in fig. 6, a schematic diagram of PMF-FFT processing is shown. To pair
And
coherent integration under PMF (partial matched filtering) can be performed to obtain:
wherein,
is the number of data that are partially coherently integrated (accumulated),
is the number of the sub-blocks,
() The function is a local pseudo-code sequence,
。
to pair
And
performing FFT processing, and obtaining a pseudo code phase point at a correlation peak:
wherein,
is a pseudo code phase point, one pseudo code period has NUM _ PN chips,
is the rate of sampling of the sample to be measured,
is the duration of the coherent integration and,
performing FFT operation times corresponding to the correlation peak; the FFT operation is a fast fourier transform.
Similarly, the carrier doppler value can be obtained as:
wherein, among others,
is the value of the carrier doppler (c) and,
is the down-sampling rate of the sample,
is the number of data accumulated by the partial coherent integration,
is the number of the sub-blocks,
is the number of points of the FFT operation, m is the index value of the FFT,
the function is a local pseudo-code sequence,
the function is a signal stripped of the large carrier doppler in the original signal,
the number of the accumulation ranges is represented,
represents the value of the coherent integration of the pseudo code generated by the ith local pseudo code generator and the original I-path signal,
the value of the coherent integration of the pseudo code generated by the ith local pseudo code generator and the original Q path signal is represented, and n represents the nth sampling of the partial coherent integration;
the fourth step: noise bottom statistics is carried out on signal segments with correlation peak values appearing in the FFT result of the third step, if the correlation peak ratio statistical noise is larger than a Threshold value Threshold, a correct correlation peak is considered to be found, carrier Doppler and code phase corresponding to the found correlation peak are calculated, and the carrier Doppler and code phase are output backwards and transmitted to a tracking circuit; if no correlation peak is found, the carrier Doppler frequency point is switched through the state machine, and the search is continued. The Threshold value Threshold here reflects a multiple relationship, and if the correlation peak-to-peak value is greater than the Threshold multiple of the statistical noise power, it indicates that the correlation peak-to-peak value found is sufficiently high.
After coherent integration in the third step, the expression of the Q branch output is as follows:
the corresponding I branch outputs are as follows:
to eliminate initial phase difference
Will have an influence on
And
add after squaring, and is recorded as
Obtaining:
in the formula,
in order to be a noise term, the noise term,
is the power of the mid-band pass signal,
the function is an auto-correlation function that,
is the difference between the actual intermediate frequency and the nominal intermediate frequency,
is the difference between the true code phase and the local code phase,
representing chi-squared distribution, the above equation illustrates the result after addition
Accord with freedomA non-central chi-square distribution with a degree of 2,
in order to be a non-centering parameter,
is the first coherent integration duration; .
Will be provided with
Caching and counting for a period of time
The maximum value max _ point, and the Noise estimation value Noise is calculated at the same time, the statistics of the Noise can be performed by selecting any branch without the occurrence of the correlation peak, if the statistics is performed, the maximum value max _ point is the maximum value max _ point, and the Noise estimation value Noise is calculated by selecting any branch without the occurrence of the correlation peak
Noise x Threshold, then the position where max _ point appears is considered to be the correlation peak position, i.e. the correct correlation peak is considered to be found; the capture probability can be expressed as:
in the formula,
a class of bessel functions that is of the
order 0,
in order to be a noise term, the noise term,
which is the power of the mid-band pass signal, threshold is the Threshold value,
is the time length of one-time coherent integration, and z is the integration variable. As shown in fig. 7, is a noise floor systemAnd (4) calculating a process schematic diagram.
If the correlation peak is found in the above steps, the code phase of the position of the correlation peak is deduced according to the FFT operation times in the third step, the Doppler frequency shift value is deduced according to the position of the maximum spectrum peak in the FFT result, then the code phase and the Doppler frequency shift value are transmitted to a tracking circuit, and a tracking start signal is synchronously given. If no relevant peak is found in the steps, the carrier Doppler frequency point is switched through the state machine, and the searching is continued until all Doppler intervals are searched.
From the above, the broadband spread spectrum signal parallel acquisition method according to the embodiment of the present invention realizes the fast acquisition of the broadband spread spectrum signal by the "space replacement time" principle and the partial matched filtering principle, and effectively reduces the overall hardware cost of the receiver.
In yet another aspect, the present invention also discloses a computer readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of any of the methods described above.
In yet another aspect, the present invention also discloses a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of any of the methods described above.
In a further embodiment provided by the present application, there is also provided a computer program product comprising instructions which, when run on a computer, cause the computer to perform the steps of any of the methods of the above embodiments.
It can be understood that the system provided by the embodiment of the present invention corresponds to the method provided by the embodiment of the present invention, and for the explanation, examples and beneficial effects of the relevant contents, reference may be made to the corresponding parts in the above method.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by a computer program, which may be stored in a non-volatile computer readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.