CN115483095A - A kind of semiconductor device and its manufacturing method - Google Patents

Abstract

Translated fromChinese

本申请公开了一种半导体器件及其制造方法，应用于半导体器件及其制造技术领域。本申请可以提供衬底，在衬底的栅极区形成栅介质层和栅极，栅介质层包括层叠的氧化铝层和氧化铪层。由于用氧化铝材料和氧化铪材料作为栅介质层材料，代替DMOS中的电介质二氧化硅，即使半导体器件被施加高压，也可以降低漏电。因此，降低了漏电，使得半导体器件双极性、阻变特性更加稳定。

The application discloses a semiconductor device and a manufacturing method thereof, which are applied in the technical field of semiconductor devices and manufacturing thereof. The present application may provide a substrate, a gate dielectric layer and a gate are formed in the gate region of the substrate, and the gate dielectric layer includes a stacked aluminum oxide layer and a hafnium oxide layer. Since the aluminum oxide material and the hafnium oxide material are used as the material of the gate dielectric layer instead of the dielectric silicon dioxide in the DMOS, the leakage current can be reduced even if the semiconductor device is applied with high voltage. Therefore, the electric leakage is reduced, and the bipolar and resistive characteristics of the semiconductor device are more stable.

Description

Translated fromChinese

一种半导体器件及其制造方法A kind of semiconductor device and its manufacturing method

技术领域technical field

本申请涉及半导体器件及其制造技术领域，特别是涉及一种半导体器件及其制造方法。The present application relates to the technical field of semiconductor devices and manufacturing thereof, in particular to a semiconductor device and a manufacturing method thereof.

背景技术Background technique

晶体管是一种固体半导体器件，其中双扩散金属氧化物半导体(Diffused MetalOxide Semiconductor，DMOS)是金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)的一种类型。理想功率的MOSFET应满足器件处于关闭状态是保持非常高的击穿电压，和超低的比导通电阻处于导通状态以最小化传导损耗，两个要求。A transistor is a solid semiconductor device, in which a double diffused metal oxide semiconductor (DMOS) is a type of metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). An ideal power MOSFET should meet the two requirements of maintaining a very high breakdown voltage when the device is in the off state, and ultra-low specific on-resistance in the on state to minimize conduction losses.

一般情况下，采用二氧化硅作为晶体管内的电介质，或采用锆钛酸铅和铋锌铌酸作为High-K(HK)电介质材料，应用于栅介质层。然而，常规功率的MOSFET存在硅限制，限制了功率MOSFET器件在高压领域的应用。会导致增加漏电的问题。Generally, silicon dioxide is used as the dielectric in the transistor, or lead zirconate titanate and bismuth zinc niobate are used as the High-K (HK) dielectric material for the gate dielectric layer. However, there are silicon limitations in conventional power MOSFETs, which limits the application of power MOSFET devices in the high-voltage field. Will lead to increased leakage problems.

发明内容Contents of the invention

基于上述问题，本申请提供了一种半导体器件及其制造方法，降低了漏电，使得半导体器件双极性、阻变特性更加稳定。Based on the above problems, the present application provides a semiconductor device and a manufacturing method thereof, which reduce electric leakage and make the bipolar and resistance-switching characteristics of the semiconductor device more stable.

本申请实施例公开了如下技术方案：The embodiment of the application discloses the following technical solutions:

第一方面，本申请提供一种半导体器件的制造方法，包括：In a first aspect, the present application provides a method for manufacturing a semiconductor device, including:

提供衬底；provide the substrate;

在所述衬底的栅极区形成栅介质层和栅极，所述栅介质层包括层叠的氧化铝层和氧化铪层。A gate dielectric layer and a gate are formed in the gate region of the substrate, and the gate dielectric layer includes a laminated aluminum oxide layer and a hafnium oxide layer.

可选地，所述栅介质层，具体包括：Optionally, the gate dielectric layer specifically includes:

依次层叠氧化铝层、氧化铪层和氧化铝层。An aluminum oxide layer, a hafnium oxide layer, and an aluminum oxide layer are stacked in sequence.

可选地，所述在所述衬底的栅极区形成栅介质层和栅极，具体包括：Optionally, forming a gate dielectric layer and a gate in the gate region of the substrate specifically includes:

在所述栅极区形成沟槽，在所述沟槽底部和侧壁形成所述栅介质层，在所述栅介质层上方形成所述栅极。A trench is formed in the gate region, the gate dielectric layer is formed on the bottom and sidewalls of the trench, and the gate is formed on the gate dielectric layer.

可选地，所述在所述沟槽底部和侧壁形成所述栅介质层，在所述栅介质层上方形成所述栅极，具体包括：Optionally, forming the gate dielectric layer at the bottom and sidewalls of the trench, and forming the gate above the gate dielectric layer specifically includes:

利用沉积工艺在所述沟槽依次形成栅介质材料和栅极材料，所述栅介质材料包括依次层叠的氧化铝材料、氧化铪材料、氧化铝材料，去除所述沟槽外的所述栅介质材料和所述栅极材料。Using a deposition process to sequentially form a gate dielectric material and a gate material in the trench, the gate dielectric material includes sequentially stacked aluminum oxide material, hafnium oxide material, and aluminum oxide material, and remove the gate dielectric outside the trench material and the gate material.

可选地，其特征在于，所述氧化铝层和所述氧化铪层的厚度小于或等于0.5nm。Optionally, it is characterized in that the thickness of the aluminum oxide layer and the hafnium oxide layer is less than or equal to 0.5 nm.

第二方面，本申请提供了一种半导体器件，包括：In a second aspect, the present application provides a semiconductor device, including:

衬底；Substrate;

所述衬底上的栅介质层，所述栅介质层包括层叠的氧化铝层和氧化铪层；a gate dielectric layer on the substrate, the gate dielectric layer comprising a laminated aluminum oxide layer and a hafnium oxide layer;

所述栅介质层表面有栅极。There is a gate on the surface of the gate dielectric layer.

可选地，所述衬底上的栅介质层包括依次层叠的氧化铝层、氧化铪层和氧化铝层。Optionally, the gate dielectric layer on the substrate includes an aluminum oxide layer, a hafnium oxide layer and an aluminum oxide layer stacked in sequence.

可选地，所述栅介质层和所述栅极位于所述衬底的栅极区，在所述栅极区形成沟槽，在所述沟槽底部和侧壁形成所述栅介质层和所述栅极。Optionally, the gate dielectric layer and the gate are located in the gate region of the substrate, a trench is formed in the gate region, and the gate dielectric layer and the gate are formed on the bottom and side walls of the trench. the gate.

可选地，所述形成所述栅介质层和所述栅极是利用沉积工艺在所述沟槽依次形成栅介质材料和栅极材料，所述栅介质材料包括依次层叠的氧化铝材料、氧化铪材料、氧化铝材料，去除所述沟槽外的所述栅介质材料和所述栅极材料。Optionally, the formation of the gate dielectric layer and the gate is to sequentially form a gate dielectric material and a gate material in the trench by using a deposition process, and the gate dielectric material includes sequentially stacked aluminum oxide material, oxide hafnium material, aluminum oxide material, removing the gate dielectric material and the gate material outside the trench.

可选地，其特征在于，所述氧化铝层和所述氧化铪层的厚度小于或等于0.5nm。Optionally, it is characterized in that the thickness of the aluminum oxide layer and the hafnium oxide layer is less than or equal to 0.5 nm.

相较于现有技术，本申请具有以下有益效果：Compared with the prior art, the present application has the following beneficial effects:

本技术申请提供了一种半导体器件及其制造方法，可以提供衬底，在衬底的栅极区形成栅介质层和栅极，栅介质层包括层叠的氧化铝层和氧化铪层。由于用氧化铝材料和氧化铪材料作为栅介质层材料，代替DMOS中的电介质二氧化硅，即使半导体器件被施加高压，也可以降低漏电。因此，降低了漏电，使得半导体器件双极性、阻变特性更加稳定。The technical application provides a semiconductor device and a manufacturing method thereof. A substrate can be provided, and a gate dielectric layer and a gate are formed in the gate region of the substrate. The gate dielectric layer includes a stacked aluminum oxide layer and a hafnium oxide layer. Since the aluminum oxide material and the hafnium oxide material are used as the material of the gate dielectric layer instead of the dielectric silicon dioxide in the DMOS, the leakage current can be reduced even if the semiconductor device is applied with high voltage. Therefore, the leakage current is reduced, and the bipolar and resistive switching characteristics of the semiconductor device are more stable.

附图说明Description of drawings

为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application. Those skilled in the art can also obtain other drawings based on these drawings without any creative effort.

图1为本申请实施例提供的一种半导体器件的制造方法的流程示意图；FIG. 1 is a schematic flow diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

图2-6为根据本申请实施例的制造方法形成半导体器件过程中的结构示意图。2-6 are structural schematic diagrams during the process of forming a semiconductor device according to the manufacturing method of the embodiment of the present application.

具体实施方式detailed description

为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。In order to make the above-mentioned purpose, features and advantages of the present application more obvious and understandable, the specific implementation manners of the present application will be described in detail below in conjunction with the accompanying drawings.

在下面的描述中阐述了很多具体细节以便于充分理解本申请，但是本申请还可以采用其它不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广，因此本申请不受下面公开的具体实施例的限制。In the following description, a lot of specific details are set forth in order to fully understand the application, but the application can also be implemented in other ways different from those described here, and those skilled in the art can do it without violating the content of the application. By analogy, the present application is therefore not limited by the specific embodiments disclosed below.

其次，本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。Secondly, the present application is described in detail in combination with schematic diagrams. When describing the embodiments of the present application in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not be limited here. The protection scope of this application. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

目前，DMOS的栅极区，可以用二氧化硅或HK材料作为栅介质层的材料，其中锆钛酸铅和铋锌铌酸是两种常见的HK材料。HK材料具备良好的绝缘属性，同时可以在栅极和衬底通道之间产生较高的电场效应。然而，常规功率的MOSFET使用二氧化硅作为栅介质层材料，会存在硅限制，在半导体器件被施加高压时，可能会增加漏电风险。使得半导体器件不稳定。At present, the gate region of DMOS can use silicon dioxide or HK material as the material of the gate dielectric layer, among which lead zirconate titanate and bismuth zinc niobate are two common HK materials. The HK material has good insulating properties and can generate a high electric field effect between the gate and the substrate channel. However, conventional power MOSFETs use silicon dioxide as the material of the gate dielectric layer, and there will be silicon confinement, which may increase the risk of leakage when the semiconductor device is applied with high voltage. making semiconductor devices unstable.

基于以上技术问题，本申请实施例提供了一种半导体器件及其制造方法，可以提供衬底，在衬底的栅极区形成栅介质层和栅极，栅介质层包括层叠的氧化铝层和氧化铪层。由于用氧化铝材料和氧化铪材料作为栅介质层材料，代替DMOS中的电介质二氧化硅，即使半导体器件被施加高压，也可以降低漏电。因此，降低了漏电，使得半导体器件双极性、阻变特性更加稳定。Based on the above technical problems, an embodiment of the present application provides a semiconductor device and a manufacturing method thereof. A substrate can be provided, and a gate dielectric layer and a gate are formed in the gate region of the substrate. The gate dielectric layer includes a stacked aluminum oxide layer and hafnium oxide layer. Since the aluminum oxide material and the hafnium oxide material are used as the material of the gate dielectric layer instead of the dielectric silicon dioxide in the DMOS, the leakage current can be reduced even if the semiconductor device is applied with high voltage. Therefore, the leakage current is reduced, and the bipolar and resistive switching characteristics of the semiconductor device are more stable.

为了更好的理解本申请的技术方案和技术效果，以下将结合附图对具体的实施例进行详细的描述。In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below in conjunction with the accompanying drawings.

参考图1所示，为本申请实施例提供的一种半导体器件的制造方法的流程图，该方法可以包括以下步骤：Referring to FIG. 1 , it is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application. The method may include the following steps:

S101：提供衬底100，参考图2。S101: providing asubstrate 100, refer to FIG. 2 .

在本申请实施例中，衬底100可以为半导体衬底，也可以为绝缘衬底，半导体衬底可以为Si衬底、Ge衬底、SiGe衬底等，绝缘衬底例如可以是氧化硅或氮化硅等。在其他实施例中，衬底100还可以为包括其他元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。在本实施例中，衬底100为体硅衬底。In the embodiment of the present application, thesubstrate 100 can be a semiconductor substrate, or an insulating substrate. The semiconductor substrate can be a Si substrate, a Ge substrate, a SiGe substrate, etc., and the insulating substrate can be, for example, silicon oxide or Silicon nitride etc. In other embodiments, thesubstrate 100 may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., and may also be a stacked structure, such as Si/SiGe, etc., or other epitaxial structures, Such as SGOI (silicon germanium on insulator) and so on. In this embodiment, thesubstrate 100 is a bulk silicon substrate.

S102：在所述衬底的栅极区形成栅介质层和栅极，参考图3-6。S102: Forming a gate dielectric layer and a gate in the gate region of the substrate, refer to FIGS. 3-6 .

在半导体器件中，栅介质层是可以形成在衬底100上的绝缘材料，可以用于隔离沟道和栅极，为了实现更好的隔离效果，栅介质层通常会选用高介电常数的材料。本申请实施例中，栅介质层包括氧化铝层和氧化铪层，二者均为HK材料，即使半导体器件处于被施加高压状态，也可以降低漏电。此外，氧化铝层和氧化铪层构成的栅介质层，相比于传统栅介质层使用的锆钛酸铅或铋锌铌酸，在半导体器件的退火过程中不易裂开，保证了器件的性能。In semiconductor devices, the gate dielectric layer is an insulating material that can be formed on thesubstrate 100, and can be used to isolate the channel and the gate. In order to achieve better isolation effect, the gate dielectric layer usually uses a material with a high dielectric constant. . In the embodiment of the present application, the gate dielectric layer includes an aluminum oxide layer and a hafnium oxide layer, both of which are HK materials, which can reduce electric leakage even when the semiconductor device is in a high-voltage state. In addition, the gate dielectric layer composed of aluminum oxide layer and hafnium oxide layer is not easy to crack during the annealing process of the semiconductor device, which ensures the performance of the device .

此外，栅介质层可以位于衬底100的平面上，也可以位于衬底100刻蚀得到的沟槽200中。其中，若栅介质层位于沟槽200内，可以利用沉积工艺将栅介质材料沉积到沟槽200内，再利用刻蚀工艺去除多余的栅介质材料，形成栅介质层。In addition, the gate dielectric layer can be located on the plane of thesubstrate 100 , or can be located in thetrench 200 obtained by etching thesubstrate 100 . Wherein, if the gate dielectric layer is located in thetrench 200, the gate dielectric material can be deposited into thetrench 200 by a deposition process, and then the excess gate dielectric material can be removed by an etching process to form a gate dielectric layer.

栅介质层位于沟槽200中时，如图3所示，可以在栅极区刻蚀形成沟槽200，利用刻蚀工艺，将预先规划的栅极区部分的衬底材料去除，形成沟槽200；之后，如图4和图5所示，在沟槽200的底部和侧壁形成栅介质层和栅极，形成栅介质材料的方法可以是利用沉积工艺和刻蚀工艺，形成栅极的方法可以是利用沉积工艺和刻蚀工艺。具体的，可以沉积栅介质材料，并去除沟槽200外的栅介质材料，得到位于沟槽200底部和侧壁的栅介质层，同样，可以沉积栅极材料，之后去除沟槽200之外的栅极材料，得到位于沟槽200中的栅极。栅介质材料和栅极材料可以一并去除，也可以分别去除。When the gate dielectric layer is located in thetrench 200, as shown in FIG. 3, thetrench 200 can be formed by etching in the gate region, and the substrate material in the pre-planned gate region can be removed by using an etching process to form thetrench 200; Afterwards, as shown in FIGS. 4 and 5, a gate dielectric layer and a gate are formed on the bottom and sidewalls of thetrench 200. The method for forming the gate dielectric material may be to use a deposition process and an etching process to form a gate The method can be by using deposition process and etching process. Specifically, the gate dielectric material can be deposited, and the gate dielectric material outside thetrench 200 can be removed to obtain a gate dielectric layer positioned at the bottom and sidewalls of thetrench 200; similarly, the gate material can be deposited, and then the gate dielectric material outside thetrench 200 can be removed. gate material, resulting in a gate located in thetrench 200. The gate dielectric material and the gate material can be removed together or separately.

沉积工艺例如可以包括化学气相沉积(Chemical Vapor Deposition，CVD)、分子束外延(Molecular Beam Epitaxy，MBE)、原子层沉积(Atomic Layer Deposition，ALD)等中的一种，刻蚀工艺可以包括各向同性的湿法刻蚀或各向异性的干法刻蚀。The deposition process may include, for example, one of chemical vapor deposition (Chemical Vapor Deposition, CVD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE), atomic layer deposition (Atomic Layer Deposition, ALD), etc., and the etching process may include isotropic Isotropic wet etching or anisotropic dry etching.

具体的，栅介质层层叠了氧化铝层和氧化铪层，其中，氧化铝材料和氧化铪材料可以使半导体器件在被施加高压的状态下，降低漏电的情况。此外，依次层叠氧化铝层、氧化铪层和氧化铝层，使得半导体器件在后续的退火过程中，不易裂开。Specifically, the gate dielectric layer is stacked with an aluminum oxide layer and a hafnium oxide layer, wherein the aluminum oxide material and the hafnium oxide material can reduce leakage of the semiconductor device when a high voltage is applied. In addition, the aluminum oxide layer, the hafnium oxide layer and the aluminum oxide layer are sequentially stacked, so that the semiconductor device is not easy to crack during the subsequent annealing process.

如图4所示，首先，在沟槽200内沉积氧化铝材料201、在氧化铝材料201上方沉积氧化铪材料202、在氧化铪材料202上方沉积氧化铝材料203；之后，参考图5所示，可以在氧化铪材料203上沉积栅极材料204；之后，参考图6所示，可以利用刻蚀工艺去除沟槽200外部的栅介质材料和栅极材料，得到位于沟槽200中的栅介质层和栅极。As shown in FIG. 4, first,aluminum oxide material 201 is deposited intrench 200,hafnium oxide material 202 is deposited overaluminum oxide material 201, andaluminum oxide material 203 is deposited overhafnium oxide material 202; after that, refer to FIG. , thegate material 204 can be deposited on thehafnium oxide material 203; then, as shown in FIG. layers and gates.

这样的氧化铝层-氧化铪层-氧化铝层的结构，可以增加半导体器件的电场效应，还可以使得半导体器件双极性、阻变特性更加稳定。对于使得半导体器件双极性、阻变特性更加稳定，举例说明，例如可以用于更好的循环特性、较低的操作电压、较好的保持性能和良好的抗疲劳性。Such an aluminum oxide layer-hafnium oxide layer-alumina layer structure can increase the electric field effect of the semiconductor device, and can also make the bipolar and resistive switching characteristics of the semiconductor device more stable. For making the bipolar and resistive switching characteristics of semiconductor devices more stable, for example, it can be used for better cycle characteristics, lower operating voltage, better retention performance and good fatigue resistance.

此外，氧化铝层201、氧化铪层202和氧化铝层203的厚度接近。例如，氧化铝层201、氧化铪层202和氧化铝层203的厚度可以相等，且厚度小于或等于0.5nm。In addition, thealuminum oxide layer 201 , thehafnium oxide layer 202 and thealuminum oxide layer 203 have similar thicknesses. For example, the thicknesses of thealuminum oxide layer 201 , thehafnium oxide layer 202 and thealuminum oxide layer 203 may be equal and less than or equal to 0.5 nm.

栅极材料可以为金属材料，也可以是其他导体材料，还可以是金属材料和其他导体材料的组合，金属材料例如可以是Ti、TiAlx、TiN、TaNx、HfN、TiCx、TaCx，W，Co等或它们的组合，其他导体材料例如多晶硅等。The gate material can be a metal material, or other conductive materials, or a combination of metal materials and other conductive materials. Metal materials can be Ti, TiAlx, TiN, TaNx, HfN, TiCx, TaCx, W, Co, etc. Or their combination, other conductor materials such as polysilicon etc.

因为本申请的半导体器件为DMOS，根据DMOS的器件特性，半导体器件的源极和漏极具有特殊的放置位置。Because the semiconductor device in this application is a DMOS, according to the device characteristics of the DMOS, the source and drain of the semiconductor device have special placement positions.

当所述半导体器件为横向双扩散金属氧化物半导体晶体管LDMOS时，半导体器件的源极和漏极位于栅极区的同侧。下面进行举例说明，栅极区的左侧为源极，栅极区的右侧为漏极。电子从源极出发，通过栅极区流向漏极。此外，源极与漏极的位置是对称的，所以源极和漏极可以互换位置，即栅极区左侧为漏极，栅极区右侧为源极。When the semiconductor device is a lateral double-diffused metal oxide semiconductor transistor LDMOS, the source and drain of the semiconductor device are located on the same side of the gate region. For example, the left side of the gate region is the source, and the right side of the gate region is the drain. Electrons start from the source and flow through the gate region to the drain. In addition, the positions of the source and the drain are symmetrical, so the source and the drain can be interchanged, that is, the drain is on the left side of the gate region, and the source is on the right side of the gate region.

当所述半导体器件为垂直双扩散金属氧化物半导体晶体管VDMOS时，半导体器件的源极和漏极，分别位于栅极区的同侧和栅极区的对侧。下面进行举例说明，源极位于栅极区的同侧，漏极位于栅极区的对侧。以衬底设置栅极的一侧为上侧，将与该上侧相对的一侧作为下侧，则源极可以位于衬底的上侧，漏极位于衬底的下侧，电子从源极出发，通过栅极区流向位于衬底100下方的漏极。When the semiconductor device is a vertical double-diffused metal oxide semiconductor transistor VDMOS, the source and drain of the semiconductor device are respectively located on the same side of the gate region and on the opposite side of the gate region. An example is given below to illustrate that the source is located on the same side of the gate region, and the drain is located on the opposite side of the gate region. Taking the side of the substrate where the gate is set as the upper side, and the side opposite to the upper side as the lower side, the source can be located on the upper side of the substrate, and the drain can be located on the lower side of the substrate, and electrons flow from the source to Starting from, the flow flows through the gate region to the drain located below thesubstrate 100 .

本实施例提供了一种半导体器件的制造方法，可以提供衬底，在衬底的栅极区形成栅介质层和栅极，栅介质层包括层叠的氧化铝层和氧化铪层。由于用氧化铝材料和氧化铪材料作为栅介质层材料，代替DMOS中的电介质二氧化硅，即使半导体器件被施加高压，也可以降低漏电。因此，降低了漏电，使得半导体器件双极性、阻变特性更加稳定。This embodiment provides a method for manufacturing a semiconductor device. A substrate may be provided, and a gate dielectric layer and a gate are formed in a gate region of the substrate. The gate dielectric layer includes a stacked aluminum oxide layer and a hafnium oxide layer. Since the aluminum oxide material and the hafnium oxide material are used as the material of the gate dielectric layer instead of the dielectric silicon dioxide in the DMOS, the leakage current can be reduced even if the semiconductor device is applied with high voltage. Therefore, the leakage current is reduced, and the bipolar and resistive switching characteristics of the semiconductor device are more stable.

基于以上实施例提供的一种半导体器件结构的制造方法，本申请实施例还提供了一种半导体结构，参考图6所示，半导体结构包括：Based on the manufacturing method of a semiconductor device structure provided in the above embodiments, the embodiment of the present application also provides a semiconductor structure, as shown in FIG. 6, the semiconductor structure includes:

衬底；Substrate;

所述衬底上的栅介质层，所述栅介质层包括层叠的氧化铝层和氧化铪层；a gate dielectric layer on the substrate, the gate dielectric layer comprising a laminated aluminum oxide layer and a hafnium oxide layer;

所述栅介质层表面有栅极。There is a gate on the surface of the gate dielectric layer.

可选地，所述衬底上的栅介质层包括依次层叠的氧化铝层、氧化铪层和氧化铝层。Optionally, the gate dielectric layer on the substrate includes an aluminum oxide layer, a hafnium oxide layer and an aluminum oxide layer stacked in sequence.

可选地，所述栅介质层和所述栅极位于所述衬底的栅极区，在所述栅极区形成沟槽，在所述沟槽底部和侧壁形成所述栅介质层和所述栅极。Optionally, the gate dielectric layer and the gate are located in the gate region of the substrate, a trench is formed in the gate region, and the gate dielectric layer and the gate are formed on the bottom and side walls of the trench. the gate.

可选地，其特征在于，所述氧化铝层和所述氧化铪层的厚度小于或等于0.5nm。Optionally, it is characterized in that the thickness of the aluminum oxide layer and the hafnium oxide layer is less than or equal to 0.5 nm.

可选地，所述形成所述栅介质层和所述栅极是利用沉积工艺在所述沟槽依次形成栅介质材料和栅极材料，所述栅介质材料包括依次层叠的氧化铝材料、氧化铪材料、氧化铝材料，去除所述沟槽外的所述栅介质材料和所述栅极材料。Optionally, the formation of the gate dielectric layer and the gate is to sequentially form a gate dielectric material and a gate material in the trench by using a deposition process, and the gate dielectric material includes sequentially stacked aluminum oxide material, oxide hafnium material, aluminum oxide material, removing the gate dielectric material and the gate material outside the trench.

本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其它实施例的不同之处。尤其，对于器件实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, please refer to part of the description of the method embodiment.

以上所述仅是本申请的优选实施方式，虽然本申请已以较佳实施例披露如上，然而并非用以限定本申请。任何熟悉本领域的技术人员，在不脱离本申请技术方案范围情况下，都可利用上述揭示的方法和技术内容对本申请技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本申请技术方案保护的范围内。The above descriptions are only the preferred embodiments of the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person familiar with the art, without departing from the scope of the technical solution of the application, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the application, or to modify the equivalent of equivalent changes Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application that do not deviate from the content of the technical solution of the present application still fall within the protection scope of the technical solution of the present application.

Claims (10)

1. A method of manufacturing a semiconductor device, wherein the semiconductor device is a double Diffused Metal Oxide Semiconductor (DMOS) transistor, the method comprising:

providing a substrate;

and forming a gate dielectric layer and a gate on a gate region of the substrate, wherein the gate dielectric layer comprises a stacked aluminum oxide layer and a hafnium oxide layer.

2. The method of claim 1, wherein the gate dielectric layer specifically comprises:

an aluminum oxide layer, a hafnium oxide layer, and an aluminum oxide layer are sequentially stacked.

3. The method according to claim 1, wherein the forming of the gate dielectric layer and the gate electrode at the gate region of the substrate specifically comprises:

and forming a groove on the gate region, forming a gate dielectric layer on the bottom and the side wall of the groove, and forming the gate above the gate dielectric layer.

4. The method according to claim 3, wherein the forming the gate dielectric layer on the bottom and the sidewall of the trench and the forming the gate electrode over the gate dielectric layer specifically comprise:

and sequentially forming a gate dielectric material and a gate material in the groove by using a deposition process, wherein the gate dielectric material comprises an aluminum oxide material, a hafnium oxide material and an aluminum oxide material which are sequentially stacked, and removing the gate dielectric material and the gate material outside the groove.

5. The method according to any one of claims 1 or 2, wherein the thickness of said aluminum oxide layer and said hafnium oxide layer is less than or equal to 0.5nm.

6. A semiconductor device characterized by comprising:

a substrate;

the gate dielectric layer comprises an aluminum oxide layer and a hafnium oxide layer which are stacked;

and a grid electrode is arranged on the surface of the grid dielectric layer.

7. The semiconductor device according to claim 6, wherein the gate dielectric layer over the substrate comprises an aluminum oxide layer, a hafnium oxide layer, and an aluminum oxide layer, which are sequentially stacked.

8. The semiconductor device of claim 6, wherein the gate dielectric layer and the gate are located in a gate region of the substrate, a trench is formed in the gate region, and the gate dielectric layer and the gate are formed at the bottom and the side wall of the trench.

9. The semiconductor device of claim 8, wherein the forming of the gate dielectric layer and the gate electrode is performed by sequentially forming a gate dielectric material and a gate electrode material in the trench by a deposition process, wherein the gate dielectric material comprises an aluminum oxide material, a hafnium oxide material and an aluminum oxide material which are sequentially stacked, and removing the gate dielectric material and the gate electrode material outside the trench.

10. The semiconductor device according to any one of claims 6 or 7, wherein a thickness of the aluminum oxide layer and the hafnium oxide layer is less than or equal to 0.5nm.

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