CN115424989A - Filter packaging structure and manufacturing method - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/10—Mounting in enclosures
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
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Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本发明涉及一种封装技术领域，尤其涉及一种滤波器封装结构及制作方法。The invention relates to the technical field of packaging, in particular to a filter packaging structure and a manufacturing method.
背景技术Background technique
在现有技术中，在对滤波器芯片进行封装时，一直会存在以下问题：在将芯片和基板进行封装的时候，通过环氧薄膜将芯片和基板进行压合的过程中，环氧薄膜中的树脂将直接流入芯片底部的空腔内，污染芯片表面的金/焊料凸块和有效区域，因此会降低滤波器产品性能。In the prior art, when the filter chip is packaged, the following problems have always existed: when the chip and the substrate are packaged, during the process of laminating the chip and the substrate through the epoxy film, the epoxy film The resin will flow directly into the cavity at the bottom of the chip and contaminate the gold/solder bumps and active areas on the chip surface, thus degrading the filter product performance.
发明内容Contents of the invention
本发明针对现有技术中的缺点，提供了一种滤波器封装结构及制作方法。Aiming at the shortcomings in the prior art, the present invention provides a filter packaging structure and a manufacturing method.
为了解决上述技术问题，本发明通过下述技术方案得以解决：In order to solve the above technical problems, the present invention is solved through the following technical solutions:
一种滤波器封装结构，包括芯片、基板和环形挡墙；A filter packaging structure, including a chip, a substrate and an annular retaining wall;
所述环形挡墙设置在所述芯片的正面，所述基板表面设有与所述环形挡墙相互配合的环形沟槽；The annular retaining wall is arranged on the front of the chip, and the surface of the substrate is provided with an annular groove that cooperates with the annular retaining wall;
所述芯片通过焊球与所述基板进行焊接，所述环形挡墙嵌入环形沟槽内以使得所述芯片、所述基板和所述环形挡墙之间形成空腔且所述环形挡墙的底部不接触所述环形沟槽的槽底面。The chip is welded to the substrate through solder balls, and the annular retaining wall is embedded in the annular groove so that a cavity is formed between the chip, the substrate and the annular retaining wall, and the annular retaining wall The bottom does not contact the groove bottom surface of the annular groove.
作为一种可实施方式，还包括保护薄膜层；As a possible embodiment, it also includes a protective film layer;
所述保护薄膜层至少包括第一保护区和第二保护区，所述第一保护区覆盖于芯片的背面及侧面以及空腔外侧的基板上方，所述第二保护区设置在所述环形挡墙的外侧及所述环形沟槽内。The protective film layer at least includes a first protection area and a second protection area, the first protection area covers the back and side surfaces of the chip and above the substrate outside the cavity, and the second protection area is arranged on the ring stop The outside of the wall and inside the annular groove.
作为一种可实施方式，所述焊球至少为一个且位于空腔内部。As a possible implementation manner, there is at least one solder ball and it is located inside the cavity.
作为一种可实施方式，所述环形挡墙的高度不小于最终焊接成型的焊球的高度，使得所述空腔与外部的连通区域为U型通道。As a possible implementation manner, the height of the annular retaining wall is not less than the height of the final welded solder balls, so that the communication area between the cavity and the outside is a U-shaped channel.
作为一种可实施方式，所述环形挡墙的高度不大于最初形成的焊球的高度，所述环形沟槽的深度大于二分之一的最初形成的焊球的高度，所述环形沟槽的宽度不小于环形挡墙的厚度。As a possible implementation manner, the height of the annular retaining wall is not greater than the height of the initially formed solder balls, the depth of the annular groove is greater than half of the height of the initially formed solder balls, and the annular groove The width is not less than the thickness of the ring retaining wall.
作为一种可实施方式，所述环形挡墙的材料为PI材料。As a possible implementation manner, the material of the annular retaining wall is PI material.
一种滤波器封装结构的制作方法，包括以下步骤：A method for manufacturing a filter package structure, comprising the following steps:
提供芯片，在所述芯片的正面设置环形挡墙；providing a chip, and setting an annular retaining wall on the front of the chip;
在所述芯片的正面且所述环形挡墙的内侧焊接焊球；Welding solder balls on the front side of the chip and the inner side of the annular retaining wall;
提供基板，所述基板设有与所述环形挡墙相互配合的环形沟槽；providing a base plate, the base plate is provided with an annular groove that cooperates with the annular retaining wall;
所述芯片通过焊球与所述基板进行焊接，所述环形挡墙嵌入环形沟槽内以使得所述芯片、所述基板和所述环形挡墙之间形成空腔且所述环形挡墙的底部不接触所述环形沟槽的槽底面。The chip is welded to the substrate through solder balls, and the annular retaining wall is embedded in the annular groove so that a cavity is formed between the chip, the substrate and the annular retaining wall, and the annular retaining wall The bottom does not contact the groove bottom surface of the annular groove.
作为一种可实施方式，还包括以下步骤：As an implementable mode, the following steps are also included:
在所述基板和芯片表面填充保护薄膜层；Filling the protective film layer on the surface of the substrate and the chip;
所述保护薄膜层至少第一保护区和第二保护区，所述第一保护区覆盖于芯片的背面与侧面以及空腔外侧的基板的上方，所述第二保护区设置在所述环形挡墙的外侧与环形沟槽内。The protective film layer has at least a first protection area and a second protection area, the first protection area covers the back and side surfaces of the chip and above the substrate outside the cavity, and the second protection area is arranged on the ring stop The outer side of the wall and the annular groove.
作为一种可实施方式，所述焊球至少为一个且位于空腔内部。As a possible implementation manner, there is at least one solder ball and it is located inside the cavity.
作为一种可实施方式，所述环形挡墙的高度不小于最终焊接成型的焊球的高度，使得所述空腔与外部的连通区域为U型通道；As a possible implementation, the height of the annular retaining wall is not less than the height of the final welded solder balls, so that the communication area between the cavity and the outside is a U-shaped channel;
所述环形挡墙的高度不大于最初形成的焊球的高度，所述环形沟槽的深度大于二分之一的最初形成的焊球的高度，所述环形沟槽的宽度不小于环形挡墙的厚度。The height of the annular retaining wall is not greater than the height of the initially formed solder ball, the depth of the annular groove is greater than half of the height of the initially formed solder ball, and the width of the annular groove is not less than the annular retaining wall thickness of.
作为一种可实施方式，所述环形挡墙的材料为PI材料。As a possible implementation manner, the material of the annular retaining wall is PI material.
本发明由于采用了以上技术方案，具有显著的技术效果：The present invention has remarkable technical effect owing to adopted above technical scheme:
在本发明中，通过在芯片的正面设置环形挡墙，在基板表面设置相互配合的环形沟槽，可以使得芯片贴装后环形挡墙嵌入基板的环形沟槽中形成空腔,有效阻止芯片和基板在压合时溢出的保护薄膜层的材料进入空腔内污染焊球和芯片的有效区域，从而提高芯片空腔结构的可靠性；另外，由于在焊接过程中，焊球的高度会产生变化，因此如果焊球和环形挡墙都直接焊接在基板的话，一方面焊球的尺寸会变动，但环形挡墙的高度不变，可能导致芯片与基板之间的电性接触不好而影响电性能；另一方面焊球和环形挡墙都采取焊接方式的话，由于焊球高度以及环形挡墙的工艺误差，可能导致环形挡墙与基板之间有缝隙，也会使得腔体内受到污染，本发明通过在基板上设置与环形挡墙相互配合的环形沟槽，在封装的时候，环形挡墙不需要焊接在基板上，只需要嵌入基板的环形沟槽内即可，后续在填充保护薄膜层的材料时，能够充分填充且不会流入空腔内。In the present invention, by setting an annular retaining wall on the front of the chip and providing an annular groove that cooperates with each other on the surface of the substrate, the annular retaining wall can be embedded in the annular groove of the substrate to form a cavity after the chip is mounted, effectively preventing the chip and the The material of the protective film layer overflowed during the pressing of the substrate enters the cavity to pollute the effective area of the solder ball and the chip, thereby improving the reliability of the chip cavity structure; in addition, because the height of the solder ball will change during the soldering process , so if the solder balls and the ring-shaped wall are directly soldered to the substrate, on the one hand, the size of the solder ball will change, but the height of the ring-shaped wall will remain the same, which may lead to poor electrical contact between the chip and the substrate and affect the electrical connection. Performance; on the other hand, if both the solder ball and the annular retaining wall are welded, due to the height of the solder ball and the process error of the annular retaining wall, there may be a gap between the annular retaining wall and the substrate, which will also cause the cavity to be polluted. The invention provides an annular groove that cooperates with the annular retaining wall on the substrate. When packaging, the annular retaining wall does not need to be welded on the substrate, but only needs to be embedded in the annular groove of the substrate, and then filled with a protective film layer When the material is used, it can be fully filled and will not flow into the cavity.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.
图1是本发明实施例的滤波器封装结构的整体结构示意图；FIG. 1 is a schematic diagram of the overall structure of a filter package structure according to an embodiment of the present invention;
图2是本发明实施例中芯片的正面结构设置环形挡墙的结构示意图；Fig. 2 is a schematic structural view of setting an annular retaining wall on the front structure of the chip in an embodiment of the present invention;
图3是本发明实施例中芯片上焊接焊球的结构示意图；Fig. 3 is a schematic structural view of welding solder balls on a chip in an embodiment of the present invention;
图4是本发明实施例中设有环形沟槽的基板的结构示意图；4 is a schematic structural view of a substrate provided with an annular groove in an embodiment of the present invention;
图5是本发明实施例中将芯片与基板通过焊球焊接的结构示意图。FIG. 5 is a schematic structural diagram of bonding a chip and a substrate through solder balls in an embodiment of the present invention.
附图中的标号说明：Explanation of the symbols in the accompanying drawings:
1、芯片；2、环形挡墙；3、焊球；4、基板；41、环形沟槽；5、保护薄膜层；6、空腔；7、第一保护区；8、第二保护区。1. Chip; 2. Ring retaining wall; 3. Solder ball; 4. Substrate; 41. Annular groove; 5. Protective film layer; 6. Cavity; 7. First protection area; 8. Second protection area.
具体实施方式detailed description
下面结合实施例对本发明做进一步的详细说明，以下实施例是对本发明的解释而本发明并不局限于以下实施例。The present invention will be further described in detail below in conjunction with the examples, the following examples are explanations of the present invention and the present invention is not limited to the following examples.
实施例1：Example 1:
一种滤波器封装结构，如图1所示，包括芯片1、基板4和环形挡墙2；环形挡墙2设置在芯片1的正面，基板4表面设有与环形挡墙2相互配合的环形沟槽41；芯片1通过焊球3与基板4进行焊接，环形挡墙2嵌入环形沟槽41内以使得芯片1、基板4和环形挡墙2之间形成空腔6且环形挡墙2的底部不接触环形沟槽41的槽底面。A filter packaging structure, as shown in Figure 1, includes a
本发明解决了传统滤波器封装结构中空腔内容易被灌胶或者污染的问题，为了使得焊球3及芯片1正面的有效区域不被污染，因此，通过在芯片1的正面设置环形挡墙2，在基板4表面设置相互配合的环形沟槽41，可以使得芯片贴装后环形挡墙2嵌入基板4的环形沟槽41中，有效阻止芯片1和基板4在压合时溢出的保护薄膜层5的材料进入空腔6内污染焊球3和芯片1正面的有效区域，从而提高空腔6的可靠性。The invention solves the problem that the cavity in the traditional filter packaging structure is easily filled with glue or polluted. In order to prevent the
另外，由于在焊接过程中，焊球3的高度会产生变化，因此如果焊球3和环形挡墙2都直接焊接在基板4的话，一方面焊球3的高度会变动，但环形挡墙2的高度不变，可能导致芯片1与基板4之间的电性接触不好而影响电性能；另一方面焊球3和环形挡墙2都采取焊接方式的话，由于焊球3的高度以及环形挡墙2的工艺误差，可能导致环形挡墙2与基板4之间有缝隙，也会使得空腔6受到污染，本发明通过在基板4表面设置与环形挡墙2相互配合的环形沟槽41，在封装的时候，环形挡墙2不需要焊接在基板4上，只需要嵌入基板4的环形沟槽41内即可，后续在填充保护薄膜层5的材料时，能够充分填充且不会流入空腔6内。In addition, since the height of the
在本发明中，环形挡墙2的材料为PI材料，环形挡墙2的材料也可以为导电材料，比如可以为铜，以铜为材料在芯片1的正面形成环形挡墙2；还可以铜加锡为材料在芯片1的正面形成环形挡墙2，首先，先用铜材料芯片1的正面形成初始环形挡墙，为了可以增加环形挡墙的高度，则可以继续以锡为材料在初始环形挡墙继续增加高度，最终形成足够高度的环形挡墙2。In the present invention, the material of the annular
将芯片1和基板4通过焊球3焊接好后，在芯片1和基板4覆盖一层保护薄膜层5。保护薄膜层5的材质为环氧树脂，在其他实施例中，保护薄膜层5可以为其他塑封材料。具体地，如图1所示，保护薄膜层5至少包括第一保护区7和第二保护区8，第一保护区7覆盖于芯片1的背面及侧面以及空腔外侧的基板上方，第二保护区8设置在环形挡墙2的侧方外侧及环形沟槽41内。在覆盖保护薄膜层5时，由于基板4上设置有环形沟槽41且环形挡墙2的厚度小于环形沟槽41的宽度，因此会让保护薄膜层5的材料填充入环形沟槽41内，并且由于环形挡墙2的底部不接触环形沟槽41的上表面，所以也会填充到环形挡墙2底部与环形沟槽41的槽底面之间，这样的充分填充能够保护到空腔6内的焊球3以及芯片1的有效区域，并且可以让空腔6更加密闭。After the
在一个实施例中，焊球3的数量至少为一个且位于空腔6内部，焊球为金焊球或锡焊球，当焊球为金焊球，由于金焊球的高度小于50微米，因此对应的环形挡墙2的高度也小于50微米；当焊球为锡焊球，由于锡焊球的高度一般小于100微米，因此对应的环形挡墙2的高度也小于100微米。In one embodiment, the number of
在具体实施例中，为了使得空腔的效果更好，环形挡墙2的高度不小于最终焊接成型的焊球3的高度，使得空腔与外部的连通区域为U型通道；环形挡墙2的高度不大于最初形成的焊球3的高度，环形沟槽41的深度大于二分之一的最初形成的焊球3的高度，环形沟槽41的宽度不小于环形挡墙2的厚度。由于焊球在焊接前后其高度稍微会发生变化，因此依赖于环形沟槽41的设计可以避免焊接的过程中环形挡墙的底部与环形沟槽41的槽底面发生碰撞，同时由于通过设置合适的高度和宽度，环形挡墙2空腔与外部的连通区域为U型通道，即使在压合时溢出的保护薄膜层5材料也很难通过U型通道进入空腔，这样可以提高产品性能。In a specific embodiment, in order to make the effect of the cavity better, the height of the
实施例2：Example 2:
一种滤波器封装结构的制作方法，包括以下步骤：A method for manufacturing a filter package structure, comprising the following steps:
如图2所示，在芯片1的正面设置环形挡墙2；As shown in Figure 2, an
如图3所示，在芯片1的正面且环形挡墙2的内侧焊接焊球3；As shown in FIG. 3 ,
如图4所示，提供基板4，基板4设有与环形挡墙2相互配合的环形沟槽41；As shown in Figure 4, a
如图5所示，芯片1通过焊球3与基板4进行焊接，环形挡墙2嵌入环形沟槽41内以使得芯片1、基板4和环形挡墙2形成空腔6且环形挡墙2的底部不接触环形沟槽41的槽底面。As shown in Figure 5, the
还包括以下步骤：形成保护薄膜层5；The following steps are also included: forming a protective film layer 5;
保护薄膜层5至少包括第一保护区和第二保护区，第一保护区覆盖于芯片1的背面及侧面以及空腔外侧的基板4的上方，第二保护区设置在环形挡墙2的侧方外侧与环形沟槽41内，最终形成的结构如图1所示。The protective film layer 5 includes at least a first protection area and a second protection area, the first protection area covers the back and side surfaces of the
本发明解决了传统滤波器封装结构中空腔内容易被灌胶或者污染的问题，为了使得焊球3及芯片1正面的有效区域不被污染，因此，通过在芯片1的正面设置环形挡墙2，在基板4表面设置相互配合的环形沟槽41，可以使得芯片贴装后环形挡墙2嵌入基板4的环形沟槽41中，有效阻止芯片1和基板4在压合时溢出的保护薄膜层5的材料进入空腔6内污染焊球3和芯片1的有效区域，从而提高空腔6的可靠性。The invention solves the problem that the cavity in the traditional filter packaging structure is easily filled with glue or polluted. In order to prevent the
另外，由于在焊接过程中，焊球3的高度会产生变化，因此如果焊球3和环形挡墙2都直接焊接在基板4的话，一方面焊球3的高度会变动，但环形挡墙2的高度不变，可能导致芯片1与基板4之间的电性接触不好而影响电性能；另一方面焊球3和环形挡墙2都采取焊接方式的话，由于焊球3的高度以及环形挡墙2的工艺误差，可能导致环形挡墙2与基板4之间有缝隙，也会使得空腔6受到污染，本发明通过在基板4表面设置与环形挡墙2相互配合的环形沟槽41，在封装的时候，环形挡墙2不需要焊接在基板4上，只需要嵌入基板4的环形沟槽41内即可，后续在填充保护薄膜层5的材料时，能够充分填充且不会流入空腔6内。In addition, since the height of the
此外，需要说明的是，本说明书中所描述的具体实施例，其零、部件的形状、所取名称等可以不同。凡依本发明专利构思所述的构造、特征及原理所做的等效或简单变化，均包括于本发明专利的保护范围内。本发明所属技术领域的技术人员可以对所描述的具体实施例做各种各样的修改或补充或采用类似的方式替代，只要不偏离本发明的结构或者超越本权利要求书所定义的范围，均应属于本发明的保护范围。In addition, it should be noted that the specific embodiments described in this specification may be different in terms of parts, shapes and names of components. All equivalent or simple changes made according to the structure, features and principles described in the patent concept of the present invention are included in the protection scope of the patent of the present invention. Those skilled in the art to which the present invention belongs can make various modifications or supplements to the described specific embodiments or adopt similar methods to replace them, as long as they do not deviate from the structure of the present invention or exceed the scope defined in the claims. All should belong to the protection scope of the present invention.
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