技术领域Technical Field
本发明涉及一种微处理器多路测频系统及其测频方法，属于电子电路技术领域。The invention relates to a microprocessor multi-channel frequency measuring system and a frequency measuring method thereof, belonging to the technical field of electronic circuits.
背景技术Background technique
惯导系统中，测频通常采用振梁加速度计，振梁加速度计在测频过程中对其输入的加速度用两路TTL方波信号的频率差表示，为真实反应输入的加速度，对两路方波信号的频率测量要同步连续进行，尤其是在大动态条件下，同步、连续、高速的要求更加严格。另外，通过多只振梁加速度计同步测量有利于提高惯导系统解算精度，为此，通常采用大动态高精度FDC(频率数字转换)同时对多只振梁加速度计输出的TTL方波信号进行同步、连续、高速、精确测频，以连续测量同一时间间隔内的多只振梁加速度计的输入加速度，从而确保单只振梁加速度计的测量精度和惯导系统的解算精度。In the inertial navigation system, the frequency measurement usually adopts the vibration beam accelerometer. During the frequency measurement process, the vibration beam accelerometer represents the input acceleration as the frequency difference of two TTL square wave signals. In order to truly reflect the input acceleration, the frequency measurement of the two square wave signals must be performed synchronously and continuously. Especially under large dynamic conditions, the requirements of synchronization, continuity and high speed are more stringent. In addition, synchronous measurement by multiple vibration beam accelerometers is conducive to improving the accuracy of the inertial navigation system. For this reason, large dynamic high-precision FDC (frequency digital conversion) is usually used to synchronously, continuously, high-speed and accurately measure the frequency of the TTL square wave signals output by multiple vibration beam accelerometers at the same time, so as to continuously measure the input acceleration of multiple vibration beam accelerometers in the same time interval, thereby ensuring the measurement accuracy of a single vibration beam accelerometer and the accuracy of the inertial navigation system.
传统的高精度测频通常采用FPGA集成电路完成待测信号滤波模块、锁存和清零信号产生模块、整周期计数器模块、填充脉冲计数器模块和计数锁存模块，实现多路频率信号的测量。随着国产化、小型号、低成本进程的推进，微处理器逐渐替代了FPGA集成电路，传统的测频手段不能满足使用要求。如果能够用微处理器实现高精度测频，满足惯导系统中需求，既可以节省成本，又能降低硬件电路复杂程度。Traditional high-precision frequency measurement usually uses FPGA integrated circuits to complete the signal filtering module to be measured, the latch and clear signal generation module, the full cycle counter module, the fill pulse counter module and the count latch module to achieve the measurement of multiple frequency signals. With the advancement of localization, small models and low costs, microprocessors have gradually replaced FPGA integrated circuits, and traditional frequency measurement methods cannot meet the requirements. If a microprocessor can be used to achieve high-precision frequency measurement to meet the needs of the inertial navigation system, it can save costs and reduce the complexity of the hardware circuit.
发明内容Summary of the invention
本发明的目的是针对发展需求和现有技术存在的问题，提供一种基于微处理器的测频系统及其测频方法，同时测量多路信号的频率，并保障测频结果的准确性。The purpose of the present invention is to provide a frequency measurement system and a frequency measurement method based on a microprocessor in response to development needs and problems existing in the prior art, which can simultaneously measure the frequencies of multiple signals and ensure the accuracy of the frequency measurement results.
为实现本发明目的，本发明提供的微处理器多路测频系统采取技术方案如下：To achieve the purpose of the present invention, the microprocessor multi-channel frequency measurement system provided by the present invention adopts the following technical solutions:
所述测频系统由微处理器、外部晶振及处理器片上定时器实现，包括高频时钟模块、闸门信号定时器、第一整周期脉冲计数器、第二整周期脉冲计数器、第一闸门信号定时器捕获通道、第二闸门信号定时器捕获通道、数据处理模块。The frequency measurement system is implemented by a microprocessor, an external crystal oscillator and a processor on-chip timer, and includes a high-frequency clock module, a gate signal timer, a first full-cycle pulse counter, a second full-cycle pulse counter, a first gate signal timer capture channel, a second gate signal timer capture channel, and a data processing module.
所述高频时钟模块由所述微处理器的时钟控制单元对外部晶振的时钟分频、倍频产生；The high-frequency clock module is generated by the clock control unit of the microprocessor by dividing and multiplying the clock of the external crystal oscillator;
所述闸门信号定时器由所述微处理器片上的第一定时器TIMER1实现，其对高频时钟脉冲进行周期性计数，并将计数结果锁存在第一定时器TIMER1的计数器寄存器，同时第一定时器TIMER1产生周期性中断，上升沿有效，触发第一定时器TIMER1中断服务函数；The gate signal timer is implemented by the first timer TIMER1 on the microprocessor chip, which periodically counts the high-frequency clock pulses and locks the counting result in the counter register of the first timer TIMER1. At the same time, the first timer TIMER1 generates a periodic interrupt, and the rising edge is effective, triggering the first timer TIMER1 interrupt service function;
所述第一整周期脉冲计数器由所述微处理器片上的第二定时器TIMER2实现，触发源为滤波后的外部触发输入待测信号1，上升沿有效，并将计数结果锁存在第二定时器TIMER2的计数器寄存器；The first full cycle pulse counter is implemented by the second timer TIMER2 on the microprocessor chip, the trigger source is the filtered external trigger input test signal 1, the rising edge is valid, and the counting result is locked in the counter register of the second timer TIMER2;
所述第二整周期脉冲计数器由所述微处理器片上的第三定时器TIMER3实现，触发源为滤波后的外部触发输入待测信号2，上升沿有效，并将计数结果锁存在第三定时器TIMER3的计数器寄存器；The second full cycle pulse counter is implemented by the third timer TIMER3 on the microprocessor chip, the trigger source is the filtered external trigger input test signal 2, the rising edge is valid, and the counting result is locked in the counter register of the third timer TIMER3;
所述第一闸门信号定时器捕获通道在所述第一定时器TIMER1的第一通道捕获待测信号1，将在TIMER1的第一通道输入引脚上捕获到上升沿时刻，TIMER1计数器当前的值锁存在TIMER1第一通道捕获寄存器；The first gate signal timer capture channel captures the signal to be tested 1 in the first channel of the first timer TIMER1, captures the rising edge moment on the first channel input pin of TIMER1, and locks the current value of TIMER1 counter in the first channel capture register of TIMER1;
所述第二闸门信号定时器捕获通道在所述第一定时器TIMER1的第二通道捕获待测信号2，将在TIMER1的第二通道输入引脚上捕获到上升沿时刻，TIMER1计数器当前的值锁存在TIMER1第二通道捕获寄存器；The second gate signal timer capture channel captures the signal to be tested 2 in the second channel of the first timer TIMER1, captures the rising edge moment on the second channel input pin of TIMER1, and locks the current value of TIMER1 counter in the second channel capture register of TIMER1;
所述数据处理模块对所述第一整周期脉冲计数器锁存的第二定时器TIMER2计数器寄存器值、第二整周期脉冲计数器锁存的第三定时器TIMER3计数器寄存器值、第一闸门信号定时器捕获通道锁存的第一定时器TIMER1第一通道捕获寄存器值、第二闸门信号定时器捕获通道锁存的第一定时器TIMER1第二通道捕获寄存器值进行计算，获得被测信号的频率。The data processing module calculates the counter register value of the second timer TIMER2 latched by the first full cycle pulse counter, the counter register value of the third timer TIMER3 latched by the second full cycle pulse counter, the first channel capture register value of the first timer TIMER1 latched by the first gate signal timer capture channel, and the second channel capture register value of the first timer TIMER1 latched by the second gate signal timer capture channel to obtain the frequency of the measured signal.
根据本发明又一方面，提供的微处理器多路测频方法采取技术方案如下：According to another aspect of the present invention, the provided microprocessor multi-channel frequency measurement method adopts the following technical solution:
所述第一闸门信号定时器捕获通道在所述第一定时器TIMER1的第一通道捕获待测信号1，将在TIMER1的第一通道输入引脚上捕获到上升沿时刻TIMER1计数器当前的值，锁存在TIMER1第一通道捕获寄存器；所述第二闸门信号定时器捕获通道在所述第一定时器TIMER1的第二通道捕获待测信号2，将在TIMER1的第二通道输入引脚上捕获到上升沿时刻TIMER1计数器当前的值，锁存在TIMER1第二通道捕获寄存器；The first gate signal timer capture channel captures the signal to be tested 1 at the first channel of the first timer TIMER1, captures the current value of the TIMER1 counter at the rising edge moment at the first channel input pin of TIMER1, and locks it in the TIMER1 first channel capture register; the second gate signal timer capture channel captures the signal to be tested 2 at the second channel of the first timer TIMER1, captures the current value of the TIMER1 counter at the rising edge moment at the second channel input pin of TIMER1, and locks it in the TIMER1 second channel capture register;
所述第一整周期脉冲计数器由第二定时器TIMER2对被测信号1上升沿计数，所述第二整周期脉冲计数器由第三定时器TIMER3对被测信号2上升沿计数；The first full cycle pulse counter counts the rising edges of the measured signal 1 by the second timer TIMER2, and the second full cycle pulse counter counts the rising edges of the measured signal 2 by the third timer TIMER3;
所述第一定时器TIMER1中断服务函数中，所述数据处理模块周期性读取所述第二定时器TIMER2、第三定时器TIMER3计数值，记录被测信号1和被测信号2本周期、上周期的脉冲计数个数分别为N1i、N1i-1和N2i、N2i-1；读取所述第一闸门信号定时器第一通道捕获寄存器的值，记录被测信号1本周期、上周期捕获到触发沿时刻第一定时器TIMER1第一通道捕获寄存器值分别为t1i、t1i-1；读取所述第二所述闸门信号定时器第二通道捕获寄存器的值，记录被测信号2本周期、上周期捕获到触发沿时刻第一定时器TIMER1第二通道捕获寄存器值分别为和t2i、t2i-1，则，In the interrupt service function of the first timer TIMER1, the data processing module periodically reads the count values of the second timer TIMER2 and the third timer TIMER3, and records the pulse count numbers of the measured signal 1 and the measured signal 2 in the current cycle and the previous cycle as N1i , N1i-1 and N2i , N2i-1 respectively; reads the value of the first channel capture register of the first gate signal timer, and records the first channel capture register value of the first timer TIMER1 when the measured signal 1 is captured in the current cycle and the previous cycle to the trigger edge as t1i , t1i-1 respectively; reads the value of the second channel capture register of the second gate signal timer, and records the second channel capture register value of the first timer TIMER1 when the measured signal 2 is captured in the current cycle and the previous cycle to the trigger edge as t2i , t2i-1 respectively, then,
被测信号1频率为:被测信号2频率为:The frequency of the measured signal 1 is: The frequency of the measured signal 2 is:
进一步的，所述数据处理模块对所得的数据进一步修正处理，方法如下：Furthermore, the data processing module further corrects and processes the obtained data in the following manner:
以被测信号1为例，所述第一定时器TIMER1中断服务函数中，数据处理模块读取被测信号脉冲计数个数和捕获到触发沿时刻的第一定时器TIMER1通道捕获寄存器的值，获得本周期和上周期有效的脉冲计数个数和捕获计数器值N1i、N1i-1和t1i、t1i-1，则ΔN1i＝N1i-N1i-1、Δt1i＝t1i-t1i-1,Taking the measured signal 1 as an example, in the first timer TIMER1 interrupt service function, the data processing module reads the pulse count of the measured signal and the value of the first timer TIMER1 channel capture register captured at the trigger edge moment, and obtains the effective pulse count number and capture counter value N1i , N1i-1 and t1i , t1i-1 of the current cycle and the previous cycle, then ΔN1i = N1i - N1i-1 , Δt1i = t1i - t1i-1 ,
若ΔN1i＞0，则ΔN1i＝ΔN1i，否则ΔN1i＝ΔN1i+65536；If ΔN1i > 0, then ΔN1i = ΔN1i , otherwise ΔN1i = ΔN1i + 65536;
若Δt1i＜-TG/2,则Δt1i＝Δt1i+TG,若Δt1i＞TG/2,则Δt1i＝Δt1i-TG，否则Δt1i＝Δt1i；If Δt1i ＜-TG /2, then Δt1i ＝Δt1i +TG , if Δt1i ＞TG /2, then Δt1i ＝Δt1i -TG , otherwise Δt1i ＝Δt1i ;
数据处理模块计算被测信号1的频率The data processing module calculates the frequency of the measured signal 1
在中断服务函数中周期性更新ΔN1i、Δt1i，数据处理模块实时计算被测信号1的频率f1i；In the interrupt service function, ΔN1i and Δt1i are periodically updated, and the data processing module calculates the frequency f1i of the measured signal 1 in real time;
采用上述同样方法对被测信号2进行处理，计算被测信号2的频率Use the same method as above to process the measured signal 2 and calculate the frequency of the measured signal 2
本发明采用处理器，应用片内三个通用定时器及一路定时中断，应用等精度测频的方法实现了两路测频，并通过软件对数据进行优化处理。测频方法可推广应用于具有片上定时器的微处理器，被测信号可以同时多路进行，有效降低硬件电路复杂程度，节约成本。The present invention adopts a processor, applies three general timers and one timing interrupt in the chip, and realizes two-way frequency measurement by using the equal-precision frequency measurement method, and optimizes the data through software. The frequency measurement method can be extended to microprocessors with on-chip timers, and the measured signals can be carried out in multiple channels at the same time, effectively reducing the complexity of the hardware circuit and saving costs.
本发明主要特点在于：The main features of the present invention are:
1.本发明提出的多通道测频系统，由微处理器、外部晶振及处理器片上定时器实现，有效降低硬件电路复杂度，易于推广；1. The multi-channel frequency measurement system proposed in the present invention is realized by a microprocessor, an external crystal oscillator and a processor on-chip timer, which effectively reduces the complexity of the hardware circuit and is easy to promote;
2.本发明提出的多通道测频原理，采用上升沿计数及通道捕获功能，避免多路中断的使用及中断嵌套；2. The multi-channel frequency measurement principle proposed in the present invention adopts rising edge counting and channel capture functions to avoid the use of multiple interrupts and interrupt nesting;
3.本发明提出的多通道信号测频具体实现方法、数据处理模块对所得的数据的修正处理方法，排除了数据周期不同步、上升沿冲突、跳数等问题，保证测频精度的准确性。3. The specific implementation method of multi-channel signal frequency measurement proposed in the present invention and the correction processing method of the data processing module on the obtained data eliminate the problems of data cycle asynchrony, rising edge conflict, hop count, etc., and ensure the accuracy of frequency measurement precision.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
所包括的附图用来提供对本发明实施例的进一步的理解，其构成了说明书的一部分，用于例示本发明的实施例，并与文字描述一起来阐释本发明的原理。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。The included drawings are used to provide a further understanding of the embodiments of the present invention, which constitute a part of the specification, are used to illustrate the embodiments of the present invention, and together with the text description, explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
图1示出了根据本发明的具体实施例提供的微处理器多路测频系统结构示意图。FIG1 shows a schematic structural diagram of a microprocessor multi-channel frequency measurement system according to a specific embodiment of the present invention.
图2示出了根据本发明的具体实施例提供的多路测频原理示意图。FIG2 is a schematic diagram showing the principle of multi-channel frequency measurement according to a specific embodiment of the present invention.
图3示出了根据本发明的具体实施例提供的被测信号1数据处理模块识别有效的脉冲计数个数和捕获寄存器值流程示意图。FIG3 shows a schematic diagram of a flow chart of a test signal 1 data processing module identifying a valid pulse count number and a capture register value according to a specific embodiment of the present invention.
具体实施方式Detailed ways
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
本发明提供的微处理器多路测频系统，由微处理器、外部晶振及处理器片上定时器实现，对于两路测频，测频系统包括高频时钟模块、闸门信号定时器、整周期脉冲计数器1、整周期脉冲计数器2、闸门信号定时器捕获通道1、闸门信号定时器捕获通道2、数据处理模块，如图1所示。The microprocessor multi-channel frequency measurement system provided by the present invention is realized by a microprocessor, an external crystal oscillator and a processor on-chip timer. For two-channel frequency measurement, the frequency measurement system includes a high-frequency clock module, a gate signal timer, a whole cycle pulse counter 1, a whole cycle pulse counter 2, a gate signal timer capture channel 1, a gate signal timer capture channel 2, and a data processing module, as shown in Figure 1.
所述高频时钟模块由所述微处理器的时钟控制单元对外部晶振的时钟分频、倍频产生(约1Mhz至200Mhz)。The high-frequency clock module is generated by the clock control unit of the microprocessor by dividing and multiplying the clock of the external crystal oscillator (about 1Mhz to 200Mhz).
所述闸门信号定时器由所述微处理器片上的定时器TIMER1实现，其对高频时钟脉冲进行周期性(周期TG)计数，并将计数结果锁存在定时器TIMER1的计数器寄存器，同时定时器TIMER1产生周期性中断(上升沿有效)，触发TIMER1中断服务函数。The gate signal timer is implemented by the timer TIMER1 on the microprocessor chip, which counts the high-frequency clock pulse periodically (periodTG ) and locks the counting result in the counter register of the timer TIMER1. At the same time, the timer TIMER1 generates a periodic interrupt (rising edge is valid) to trigger the TIMER1 interrupt service function.
所述整周期脉冲计数器1由所述微处理器片上的定时器TIMER2实现，触发源为滤波后的外部触发输入(ETI)待测信号1，上升沿触发，并将计数结果锁存在定时器TIMER2的计数器寄存器。The whole cycle pulse counter 1 is implemented by the timer TIMER2 on the microprocessor chip, the trigger source is the filtered external trigger input (ETI) test signal 1, the rising edge is triggered, and the counting result is locked in the counter register of the timer TIMER2.
所述整周期脉冲计数器2由所述微处理器片上的定时器TIMER3实现，触发源为滤波后的外部触发输入(ETI)待测信号2，上升沿触发，并将计数结果锁存在定时器TIMER3的计数器寄存器。The whole cycle pulse counter 2 is implemented by the timer TIMER3 on the microprocessor chip, the trigger source is the filtered external trigger input (ETI) test signal 2, the rising edge is triggered, and the counting result is locked in the counter register of the timer TIMER3.
所述闸门信号定时器捕获通道1在所述定时器TIMER1的通道1捕获待测信号1，并将在TIMER1通道1的输入引脚上捕获到上升沿时刻，TIMER1计数器当前的值锁存在TIMER1通道1捕获寄存器。The gate signal timer capture channel 1 captures the signal to be measured 1 in channel 1 of the timer TIMER1, and captures the rising edge moment on the input pin of TIMER1 channel 1, and the current value of TIMER1 counter is latched in the TIMER1 channel 1 capture register.
所述闸门信号定时器捕获通道2在所述定时器TIMER1的通道2捕获待测信号2，并将在TIMER1通道2的输入引脚上捕获到上升沿时刻，TIMER1计数器当前的值锁存在TIMER1通道2捕获寄存器。The gate signal timer capture channel 2 captures the signal to be measured 2 in channel 2 of the timer TIMER1, and captures the rising edge moment on the input pin of TIMER1 channel 2, and the current value of TIMER1 counter is latched in the TIMER1 channel 2 capture register.
所述数据处理模块对所述闸门信号定时器捕获通道1锁存的通道1捕获寄存器值、闸门信号定时器捕获通道2锁存的通道2捕获寄存器值、TIMER2计数器寄存器值、TIMER3计数器寄存器值进行计算、处理、修正，计算出被测信号的频率。The data processing module calculates, processes and corrects the channel 1 capture register value latched by the gate signal timer capture channel 1, the channel 2 capture register value latched by the gate signal timer capture channel 2, the TIMER2 counter register value and the TIMER3 counter register value to calculate the frequency of the measured signal.
基于上述微处理器多路测频系统，本发明提供了一种微处理器多路测频方法，方法如下：Based on the above-mentioned microprocessor multi-channel frequency measurement system, the present invention provides a microprocessor multi-channel frequency measurement method, the method is as follows:
如图2所示，闸门信号由所述闸门信号定时器TIMER1产生，定时周期TG(上升沿触发中断)；高频时钟由微处理器的时钟控制单元对外部晶振的时钟分频、倍频产生。所述定时器TIMER1的通道1捕获被测信号1，并将在TIMER1通道1的输入引脚上捕获到上升沿时刻，TIMER1计数器当前的值锁存在TIMER1通道1捕获寄存器。所述定时器TIMER1的通道2捕获被测信号2，并将在TIMER1通道2的输入引脚上捕获到上升沿时刻，TIMER1计数器当前的值锁存在TIMER1通道2捕获寄存器。所述整周期脉冲计数器1的定时器TIMER2对被测信号1上升沿计数，所述整周期脉冲计数器2的TIMER3对被测信号2上升沿计数。所述定时器TIMER1中断服务函数中，所述数据处理模块周期性(周期TG)读取所述定时器TIMER2、TIMER3计数值，记录被测信号1和被测信号2本周期、上周期的脉冲计数个数分别为N1i、N1i-1和N2i、N2i-1；读取所述第一闸门信号定时器第一通道捕获寄存器的值，记录被测信号1本周期、上周期捕获到触发沿时刻第一定时器TIMER1第一通道捕获寄存器值分别为t1i、t1i-1；读取所述第二闸门信号定时器第二通道捕获寄存器的值，记录被测信号2本周期、上周期捕获到触发沿时刻第一定时器TIMER1第二通道捕获寄存器值分别为和t2i、t2i-1。则被测信号1频率为被测信号2频率为As shown in Figure 2, the gate signal is generated by the gate signal timer TIMER1, and the timing period is TG (rising edge triggers interruption); the high-frequency clock is generated by the clock control unit of the microprocessor by dividing and multiplying the clock of the external crystal oscillator. Channel 1 of the timer TIMER1 captures the measured signal 1, and captures the rising edge moment on the input pin of TIMER1 channel 1, and the current value of the TIMER1 counter is locked in the TIMER1 channel 1 capture register. Channel 2 of the timer TIMER1 captures the measured signal 2, and captures the rising edge moment on the input pin of TIMER1 channel 2, and the current value of the TIMER1 counter is locked in the TIMER1 channel 2 capture register. The timer TIMER2 of the full cycle pulse counter 1 counts the rising edge of the measured signal 1, and the TIMER3 of the full cycle pulse counter 2 counts the rising edge of the measured signal 2. In the interrupt service function of the timer TIMER1, the data processing module periodically (period TG ) reads the count values of the timers TIMER2 and TIMER3, and records the pulse count numbers of the measured signal 1 and the measured signal 2 in the current cycle and the previous cycle as N1i , N1i-1 and N2i , N2i-1 respectively; reads the value of the first channel capture register of the first gate signal timer, and records the first channel capture register value of the first timer TIMER1 when the measured signal 1 is captured in the current cycle and the previous cycle to the trigger edge as t1i , t1i-1 respectively; reads the value of the second channel capture register of the second gate signal timer, and records the second channel capture register value of the first timer TIMER1 when the measured signal 2 is captured in the current cycle and the previous cycle to the trigger edge as t2i , t2i-1 respectively. Then the frequency of the measured signal 1 is The frequency of the measured signal 2 is
在本发明一实施例中，数据处理模块对所得的数据ΔN1i、Δt1i进一步修正处理，排除数据周期不同步、上升沿冲突、跳数等问题，方法如下：In one embodiment of the present invention, the data processing module further corrects and processes the obtained data ΔN1i and Δt1i to eliminate problems such as data cycle asynchrony, rising edge conflict, and hop count. The method is as follows:
以被测信号1为例，TIMER1中断服务函数中的数据处理模块读取被测信号脉冲计数个数和通道1捕获到信号1上升沿时刻通道1捕获寄存器的值，获得本周期和上周期有效的脉冲计数个数和捕获寄存器值N1i、N1i-1和t1i、t1i-1，则ΔN1i＝N1i-N1i-1、Δt1i＝t1i-t1i-1。Taking the measured signal 1 as an example, the data processing module in the TIMER1 interrupt service function reads the pulse count number of the measured signal and the value of the channel 1 capture register when channel 1 captures the rising edge of signal 1, and obtains the valid pulse count number and capture register valuesN1i , N1i-1 andt1i , t1i-1 in this cycle and the previous cycle, thenΔN1i =N1i -N1i-1 ,Δt1i =t1i -t1i-1 .
若ΔN1i＞0，则ΔN1i＝ΔN1i，否则ΔN1i＝ΔN1i+65536；若Δt1i＜-TG/2,则Δt1i＝Δt1i+TG,若Δt1i＞TG/2,则Δt1i＝Δt1i-TG，否则Δt1i＝Δt1i。数据处理模块计算被测信号1的频率在中断服务函数中周期性更新ΔN1i、Δt1i，数据处理模块实时计算被测信号1的频率f1i。If ΔN1i > 0, then ΔN1i = ΔN1i , otherwise ΔN1i = ΔN1i + 65536; if Δt1i < -TG /2, then Δt1i = Δt1i +TG , if Δt1i > TG /2, then Δt1i = Δt1i -TG , otherwise Δt1i = Δt1i . The data processing module calculates the frequency of the measured signal 1 In the interrupt service function, ΔN1i and Δt1i are updated periodically, and the data processing module calculates the frequency f1i of the measured signal 1 in real time.
采用上述同样方法对被测信号2进行处理，计算被测信号2的频率Use the same method as above to process the measured signal 2 and calculate the frequency of the measured signal 2
在本发明一实施例中，如图3所示，获得本周期脉冲计数个数和捕获到上升沿时刻通道捕获寄存器方法如下：In one embodiment of the present invention, as shown in FIG3 , the method for obtaining the number of pulse counts in this cycle and the channel capture register at the moment of capturing the rising edge is as follows:
以被测信号1为例，所述整周期脉冲计数器1的TIMER2对被测信号1上升沿计数，读取脉冲个数Sig1L1；Taking the measured signal 1 as an example, TIMER2 of the full cycle pulse counter 1 counts the rising edges of the measured signal 1 and reads the pulse number Sig1L1;
所述闸门信号定时器捕获通道1在所述定时器TIMER1的通道1捕获待测信号1，并将在TIMER1通道1的输入引脚上捕获到上升沿时刻，TIMER1计数器当前的值锁存在TIMER1通道1捕获寄存器，读取捕获值Sig1H1；The gate signal timer capture channel 1 captures the signal to be tested 1 in channel 1 of the timer TIMER1, and captures the rising edge moment on the input pin of TIMER1 channel 1, the current value of TIMER1 counter is latched in the TIMER1 channel 1 capture register, and the capture value Sig1H1 is read;
等待200ns后(等待时间由高频时钟脉冲频率决定)，所述整周期脉冲计数器1、闸门信号定时器捕获通道1分别读取到脉冲个数Sig1L2、捕获值Sig1H2；After waiting for 200ns (the waiting time is determined by the high-frequency clock pulse frequency), the full cycle pulse counter 1 and the gate signal timer capture channel 1 read the pulse number Sig1L2 and the capture value Sig1H2 respectively;
判断两次捕获值是否相等，若Sig1H1＝Sig1H2，则有效捕获值Sig1H＝Sig1H1，有效计数值Sig1L＝Sig1L1；若Sig1H1≠Sig1H2，且Sig1L1＝Sig1L2，则有效捕获值Sig1H＝Sig1H2，有效计数值Sig1L＝Sig1L1；若Sig1H1≠Sig1H2，且Sig1L1≠Sig1L2，则有效捕获值Sig1H＝Sig1H2，有效计数值Sig1L＝Sig1L2。则，当前有效捕获值t1i＝Sig1H，当前有效脉冲个数N1i＝Sig1L。Determine whether the two capture values are equal. If Sig1H1＝Sig1H2, then the effective capture value Sig1H＝Sig1H1, and the effective count value Sig1L＝Sig1L1; if Sig1H1≠Sig1H2, and Sig1L1＝Sig1L2, then the effective capture value Sig1H＝Sig1H2, and the effective count value Sig1L＝Sig1L1; if Sig1H1≠Sig1H2, and Sig1L1≠Sig1L2, then the effective capture value Sig1H＝Sig1H2, and the effective count value Sig1L＝Sig1L2. Then, the current effective capture value t1i＝Sig1H, and the current effective pulse number N1i＝Sig1L.
对被测信号2，采用上述同样方法，所述第一定时器TIMER1中断服务函数中，数据处理模块读取第三定时器TIMER3被测信号脉冲计数个数和TIMER1通道2的输入引脚上捕获到上升沿时刻，TIMER1通道2捕获寄存器值，获得本周期脉冲计数个数和捕获到上升沿时刻时刻的捕获寄存器值。For the measured signal 2, the same method as above is adopted. In the interrupt service function of the first timer TIMER1, the data processing module reads the pulse count number of the measured signal of the third timer TIMER3 and the rising edge moment captured on the input pin of TIMER1 channel 2, the capture register value of TIMER1 channel 2, and obtains the pulse count number of this cycle and the capture register value at the moment of capturing the rising edge.
此种测频方法应用片内三个通用定时器及一路定时中断，实现了两路测频，并通过软件对数据进行优化处理，有效修正、完善了数据周期不同步、上升沿冲突、跳数等问题。可推广应用于具有片上定时器的微处理器，进行多路信号测频，有效降低硬件电路复杂程度，节约成本。This frequency measurement method uses three general timers and one timing interrupt on the chip to achieve two-way frequency measurement, and optimizes the data through software, effectively correcting and improving problems such as data cycle asynchrony, rising edge conflict, and jump count. It can be widely used in microprocessors with on-chip timers to perform multi-channel signal frequency measurement, effectively reducing the complexity of hardware circuits and saving costs.
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
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