CN115327344A - Be applied to inside TC module and integrated chip of ATE test - Google Patents

Abstract

Translated fromChinese

本公开提供一种应用于ATE测试的芯片内部的TC模块和集成芯片，其中，应用于ATE测试的芯片内部的TC模块包括：逻辑控制电路，用于将指定测试指令通过本地的AHB master协议转换为测试程序；JTAG接口，连接至逻辑控制电路的输入端，用于接收基于JTAG协议传输的指定测试指令，并将指定测试指令传输至输入端；AHB总线接口，连接至逻辑控制电路的输出端，AHB总线接口还连接至芯片的总线矩阵，用于将指定测试程序发送至总线矩阵进行测试。通过本公开实施例，降低了ATE测试的时间支出，另外，也实现了专用测试指令对芯片的高效测试，进一步地提升了芯片测试的可靠性和效率。

The present disclosure provides an internal TC module and an integrated chip applied to an ATE test chip, wherein the internal TC module applied to the ATE test chip includes: a logic control circuit for converting a designated test command through a local AHB master protocol It is the test program; JTAG interface, connected to the input end of the logic control circuit, used to receive the specified test command transmitted based on the JTAG protocol, and transmit the specified test command to the input end; AHB bus interface, connected to the output end of the logic control circuit , the AHB bus interface is also connected to the bus matrix of the chip for sending the specified test program to the bus matrix for testing. Through the embodiments of the present disclosure, the time expenditure of the ATE test is reduced, and in addition, the efficient test of the chip by the dedicated test instruction is also realized, which further improves the reliability and efficiency of the chip test.

Description

Translated fromChinese

应用于ATE测试的芯片内部的TC模块和集成芯片TC module and integrated chip inside the chip applied to ATE test

技术领域technical field

本公开涉及芯片测试技术领域，具体而言，涉及一种应用于ATE测试的芯片内部的TC模块和集成芯片。The present disclosure relates to the technical field of chip testing, and in particular, relates to a TC module and an integrated chip inside a chip applied to ATE testing.

背景技术Background technique

目前，在所有的电子元器件(Device)的制造工艺里面，存在着去伪存真的需要，这种需要实际上是一个试验的过程。为了实现这种过程，就需要各种试验设备，这类设备就是所谓的ATE(Automatic Test Equipment)设备。这里所说的电子元器件DUT(Device UnderTest)，包括IC、分立的元件和半导体器件。At present, in the manufacturing process of all electronic components (Device), there is a need to remove the false and preserve the true, and this need is actually an experimental process. In order to realize this process, various test equipment are needed, such equipment is the so-called ATE (Automatic Test Equipment) equipment. The electronic components DUT (Device Under Test) mentioned here include IC, discrete components and semiconductor devices.

在相关技术中，ATE测试存在于前道工序(Front End)和后道工序(Back End)的各个环节，具体的取决于工艺(Process)设计的要求。In related technologies, the ATE test exists in each link of the front end process (Front End) and the back end process (Back End), depending on the requirements of the design of the process (Process).

但是，传统的ATE测试由于需要测试者手动输入CPU执行，从而会浪费大量时间在CPU指令录入这个过程中。另外，传统的ATE测试没有专门定制的测试指令，需要将ATE测试行为转换为CPU通用指令，转换完成后通过CPU来访问相关模块才能完成整个测试。However, because the traditional ATE test requires the tester to manually input the CPU for execution, a lot of time is wasted in the process of CPU instruction input. In addition, the traditional ATE test does not have specially customized test instructions. It is necessary to convert the ATE test behavior into CPU general instructions. After the conversion is completed, the CPU can access the relevant modules to complete the entire test.

需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。It should be noted that the information disclosed in the above background section is only for enhancing the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.

发明内容Contents of the invention

本公开的目的在于提供一种应用于ATE测试的芯片内部的TC模块和集成芯片，用于至少在一定程度上克服由于相关技术的限制和缺陷而导致的测试效率低下的问题。The purpose of the present disclosure is to provide a TC module and an integrated chip used in an ATE test chip to overcome the problem of low test efficiency caused by limitations and defects of related technologies at least to a certain extent.

根据本公开实施例的第一方面，提供一种应用于ATE测试的芯片内部的TC模块，包括：逻辑控制电路，用于将指定测试指令通过本地的AHB master协议转换为测试程序；JTAG接口，连接至所述逻辑控制电路的输入端，用于接收基于JTAG协议传输的所述指定测试指令，并将所述指定测试指令传输至所述输入端；AHB总线接口，连接至所述逻辑控制电路的输出端，所述AHB总线接口还连接至芯片的总线矩阵，用于将所述指定测试程序发送至所述总线矩阵进行测试。According to the first aspect of an embodiment of the present disclosure, there is provided a TC module applied to an ATE test chip, including: a logic control circuit for converting a specified test instruction into a test program through a local AHB master protocol; a JTAG interface, Connected to the input terminal of the logic control circuit, used to receive the specified test instruction transmitted based on the JTAG protocol, and transmit the specified test instruction to the input terminal; AHB bus interface, connected to the logic control circuit The output terminal of the AHB bus interface is also connected to the bus matrix of the chip, and is used to send the specified test program to the bus matrix for testing.

在本公开的一种示例性实施例中，所述逻辑控制电路包括：指令命令单元，所述指令命令单元的第一端连接至所述JTAG接口，所述指令命令单元的第二端连接至所述AHB总线接口，所述指令命令单元预定义有对应的指令名称和指令代码。In an exemplary embodiment of the present disclosure, the logic control circuit includes: an instruction command unit, the first end of the instruction command unit is connected to the JTAG interface, and the second end of the instruction command unit is connected to For the AHB bus interface, the instruction command unit is predefined with a corresponding instruction name and instruction code.

在本公开的一种示例性实施例中，所述逻辑控制电路还包括：专用控制命令单元，所述专用控制命令单元的第一端连接至所述JTAG接口，所述专用控制命令单元的第二端连接至所述AHB总线接口，所述专用控制命令单元预定义有ATE测试专用协议，所述ATE测试专用协议用于基于输入的控制信号定义测试向量的输入方式。In an exemplary embodiment of the present disclosure, the logic control circuit further includes: a dedicated control command unit, the first end of the dedicated control command unit is connected to the JTAG interface, and the first end of the dedicated control command unit The two ends are connected to the AHB bus interface, and the dedicated control command unit is predefined with a special protocol for ATE testing, and the special protocol for testing ATE is used to define the input mode of the test vector based on the input control signal.

在本公开的一种示例性实施例中，所述逻辑控制电路还包括：指令执行数据单元，所述指令执行数据单元的第一端连接至所述JTAG接口，所述指令执行数据单元的第二端连接至所述AHB总线接口，所述指令执行数据单元存储有用于执行所述指定测试指令的数据。In an exemplary embodiment of the present disclosure, the logic control circuit further includes: an instruction execution data unit, the first end of the instruction execution data unit is connected to the JTAG interface, and the first end of the instruction execution data unit Two ends are connected to the AHB bus interface, and the instruction execution data unit stores data for executing the specified test instruction.

在本公开的一种示例性实施例中，所述逻辑控制电路还包括：控制逻辑状态机，所述控制逻辑状态机的第一端连接至所述指令命令单元，所述控制逻辑状态机的第二端连接至所述专用控制命令单元，所述控制逻辑状态机的第三端连接至所述指令执行数据单元，所述控制逻辑状态机的第四端连接至所述AHB总线接口，所述控制逻辑状态机用于根据所述TC模块的输入变量、输出变量和状态数进行测试控制所述测试程序执行。In an exemplary embodiment of the present disclosure, the logic control circuit further includes: a control logic state machine, the first terminal of the control logic state machine is connected to the instruction command unit, and the control logic state machine The second end is connected to the dedicated control command unit, the third end of the control logic state machine is connected to the instruction execution data unit, and the fourth end of the control logic state machine is connected to the AHB bus interface, so The control logic state machine is used for testing and controlling the execution of the test program according to the input variable, output variable and state number of the TC module.

在本公开的一种示例性实施例中，所述JTAG接口连接至所述输入变量的相关接口，所述输入变量的相关接口包括TCK接口、TDI接口、TMS接口、TRST_N接口和TDO接口中的至少一种。In an exemplary embodiment of the present disclosure, the JTAG interface is connected to the relevant interface of the input variable, and the relevant interface of the input variable includes TCK interface, TDI interface, TMS interface, TRST_N interface and TDO interface. at least one.

在本公开的一种示例性实施例中，所述AHB总线接口连接至所述输出变量的相关接口，所述输出变量的相关接口包括HSEL接口、HADDR接口、HTRANS接口、HWRITE接口、HSIZE接口、HBURST接口、HWDATA接口、HRDATA接口和HRESP接口中的至少一种。In an exemplary embodiment of the present disclosure, the AHB bus interface is connected to the relevant interfaces of the output variables, and the relevant interfaces of the output variables include HSEL interfaces, HADDR interfaces, HTRANS interfaces, HWRITE interfaces, HSIZE interfaces, At least one of HBURST interface, HWDATA interface, HRDATA interface and HRESP interface.

根据本公开实施例的第二方面，提供一种集成芯片，包括：功能模块，用于对数据执行运算处理；总线矩阵，所述总线矩阵的输入端能够接入上述应用于ATE测试的芯片内部的TC模块，所述TC模块能够经所述总线矩阵访问所述功能模块。According to the second aspect of the embodiments of the present disclosure, an integrated chip is provided, including: a functional module for performing calculation processing on data; a bus matrix, the input end of the bus matrix can be connected to the inside of the above-mentioned chip for ATE testing A TC module, the TC module can access the functional module via the bus matrix.

在本公开的一种示例性实施例中，所述TC模块与所述总线矩阵之间通过AHB总线接口进行数据交互。In an exemplary embodiment of the present disclosure, data interaction is performed between the TC module and the bus matrix through an AHB bus interface.

在本公开的一种示例性实施例中，所述功能模块包括system sub-modules、nand_phy、pcie、efuse中的至少一种模块。In an exemplary embodiment of the present disclosure, the functional modules include at least one of system sub-modules, nand_phy, pcie, and efuse.

本公开实施例，通过设置TC模块包括逻辑控制电路、JTAG接口和AHB总线接口，并且通过逻辑控制电路将指定测试指令通过本地的AHB master协议转换为测试程序，另外，通过JTAG接口于接收基于JTAG协议传输的所述指定测试指令，并将所述指定测试指令传输至所述输入端，以及通过AHB总线接口将所述指定测试程序发送至所述总线矩阵进行测试，降低了ATE测试的时间支出，另外，也实现了专用测试指令对芯片的高效测试，进一步地提升了芯片测试的可靠性和效率。In the embodiment of the present disclosure, by setting the TC module to include a logic control circuit, a JTAG interface and an AHB bus interface, and through the logic control circuit, the designated test instruction is converted into a test program through the local AHB master protocol. The specified test instruction transmitted by the protocol, and the specified test instruction is transmitted to the input terminal, and the specified test program is sent to the bus matrix through the AHB bus interface for testing, which reduces the time expenditure of the ATE test , In addition, it also realizes the efficient testing of chips by special test instructions, further improving the reliability and efficiency of chip testing.

应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

附图说明Description of drawings

此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure. Apparently, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without creative efforts.

图1是本公开示例性实施例中一种应用于ATE测试的芯片内部的TC模块的示意图；FIG. 1 is a schematic diagram of a TC module inside a chip applied to ATE testing in an exemplary embodiment of the present disclosure;

图2是本公开示例性实施例中另一种应用于ATE测试的芯片内部的TC模块的示意图；2 is a schematic diagram of another TC module inside a chip applied to ATE testing in an exemplary embodiment of the present disclosure;

图3是本公开示例性实施例中另一种应用于ATE测试的芯片内部的TC模块的示意图；3 is a schematic diagram of another TC module inside a chip applied to ATE testing in an exemplary embodiment of the present disclosure;

图4是本公开示例性实施例中一种集成芯片的示意图；FIG. 4 is a schematic diagram of an integrated chip in an exemplary embodiment of the present disclosure;

图5是本公开示例性实施例中另一种集成芯片的示意图Fig. 5 is a schematic diagram of another integrated chip in an exemplary embodiment of the present disclosure

图6是本公开示例性实施例中另一种集成芯片的示意图。FIG. 6 is a schematic diagram of another integrated chip in an exemplary embodiment of the present disclosure.

具体实施方式Detailed ways

现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details being omitted, or other methods, components, devices, steps, etc. may be adopted. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。In addition, the drawings are only schematic illustrations of the present disclosure, the same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different network and/or processor means and/or microcontroller means.

下面结合附图对本公开示例实施方式进行详细说明。Exemplary implementations of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

图1至图3是本公开示例性实施例的应用于ATE测试的芯片内部的TC模块的示意图。1 to 3 are schematic diagrams of a TC module inside a chip applied to an ATE test according to an exemplary embodiment of the present disclosure.

参考图1，应用于ATE测试的芯片内部的TC模块100可以包括：Referring to Fig. 1, the TC module 100 inside the chip applied to ATE testing may include:

逻辑控制电路102，用于将指定测试指令通过本地的AHB master协议转换为测试程序。Thelogic control circuit 102 is used to convert the specified test instruction into a test program through the local AHB master protocol.

其中，AHB总线协议(AHB master协议)被大多数SoC(System-on-a-Chip，集成芯片)设计采用，它规定了AHB(Advanced High-performance Bus)、ASB(Advanced SystemBus)、APB(Advanced Peripheral Bus)等，用于高性能、高时钟频率的系统结构。Among them, the AHB bus protocol (AHB master protocol) is adopted by most SoC (System-on-a-Chip, integrated chip) designs, which stipulates AHB (Advanced High-performance Bus), ASB (Advanced SystemBus), APB (Advanced Peripheral Bus), etc., for high performance, high clock frequency system structure.

JTAG接口104，连接至所述逻辑控制电路102的输入端，用于接收基于JTAG协议传输的所述指定测试指令，并将所述指定测试指令传输至所述输入端。TheJTAG interface 104 is connected to the input terminal of thelogic control circuit 102, and is used for receiving the specified test instruction transmitted based on the JTAG protocol, and transmitting the specified test instruction to the input terminal.

其中，JTAG(Joint Test Action Group，联合测试工作组)是在器件内部定义一个TAP(Test Access Port，测试访问口)通过专用的JTAG测试工具对内部节点进行测试。JTAG测试允许多个器件通过JTAG接口串联在一起，形成一个JTAG链，能实现对各个器件分别测试。JTAG接口还常用于实现ISP(In-System Programmer，在线系统编程)，对FLASH等器件进行编程。Among them, JTAG (Joint Test Action Group, joint test working group) defines a TAP (Test Access Port, test access port) inside the device to test internal nodes through a dedicated JTAG test tool. The JTAG test allows multiple devices to be connected in series through the JTAG interface to form a JTAG chain, which can test each device separately. The JTAG interface is also often used to implement ISP (In-System Programmer, online system programming) and program devices such as FLASH.

AHB总线接口106，连接至所述逻辑控制电路102的输出端，所述AHB总线接口106还连接至芯片的总线矩阵，用于将所述指定测试程序发送至所述总线矩阵进行测试。TheAHB bus interface 106 is connected to the output terminal of thelogic control circuit 102, and theAHB bus interface 106 is also connected to the bus matrix of the chip, and is used for sending the specified test program to the bus matrix for testing.

本公开实施例，通过设置TC模块100包括逻辑控制电路102、JTAG接口104和AHB总线接口106，并且通过逻辑控制电路102将指定测试指令通过本地的AHB master协议转换为测试程序，另外，通过JTAG接口104于接收基于JTAG协议传输的所述指定测试指令，并将所述指定测试指令传输至所述输入端，以及通过AHB总线接口106将所述指定测试程序发送至所述总线矩阵进行测试，降低了ATE测试的时间支出，另外，也实现了专用测试指令对芯片的高效测试，进一步地提升了芯片测试的可靠性和效率。In the embodiment of the present disclosure, by setting the TC module 100 to include alogic control circuit 102, aJTAG interface 104, and anAHB bus interface 106, and through thelogic control circuit 102, the designated test instruction is converted into a test program through the local AHB master protocol. In addition, through the JTAG Theinterface 104 receives the specified test instruction transmitted based on the JTAG protocol, transmits the specified test instruction to the input terminal, and sends the specified test program to the bus matrix through theAHB bus interface 106 for testing, The time expenditure of ATE testing is reduced, and in addition, the efficient testing of chips by special test instructions is also realized, which further improves the reliability and efficiency of chip testing.

具体地，TC模块100是专门应用于ATE测试的芯片内部模块。它能够接收来自于JTAG接口104传输的用户自定义指令并且TC模块100内部的控制器能够对外产生AHB传输协议。由于TC模块100的AHB master(即AHB总线接口106)已经连接到了芯片内部的busmatrix(总线矩阵)，因为TC模块100能够轻松访问诸如PCIE、NAND_PHY和EFUSE这些芯片内部的重要模块。由于TC模块100内部有用户自定义的ATE测试指令，这些指令能够快速通过TC模块100内部的AHB master来完成对相关高速接口模块的ATE测试程序，在保证测试完成度的情况下最大限度的降低了测试时间，节省了大量ATE测试开支，TC模块100在保持最低硬件开销的情况下，能够从芯片外部接收JTAG接口104的指令，并且在内部的逻辑控制电路102产生相应的AHB master协议来访问芯片内部的相关模块。Specifically, the TC module 100 is a chip internal module specially applied to ATE testing. It can receive user-defined instructions transmitted from theJTAG interface 104 and the controller inside the TC module 100 can generate the AHB transmission protocol externally. Since the AHB master (namely the AHB bus interface 106) of the TC module 100 has been connected to the busmatrix (bus matrix) inside the chip, the TC module 100 can easily access important modules inside the chip such as PCIE, NAND_PHY and EFUSE. Since there are user-defined ATE test instructions inside the TC module 100, these instructions can quickly complete the ATE test program for the relevant high-speed interface module through the AHB master inside the TC module 100, and minimize the The test time is shortened, and a lot of ATE test expenses are saved. The TC module 100 can receive the instructions of theJTAG interface 104 from the outside of the chip while maintaining the minimum hardware overhead, and the internallogic control circuit 102 generates the corresponding AHB master protocol to access Related modules inside the chip.

下面，对应用于ATE测试的芯片内部的TC模块100的各部分进行详细说明。Next, each part of the TC module 100 inside the chip applied to the ATE test will be described in detail.

在本公开的一种示例性实施例中，如图2所示，所述逻辑控制电路102包括：In an exemplary embodiment of the present disclosure, as shown in FIG. 2 , thelogic control circuit 102 includes:

指令命令单元1022(CMD INSTRUCTION)，所述指令命令单元1022的第一端连接至所述JTAG接口104，所述指令命令单元1022的第二端连接至所述AHB总线接口106，所述指令命令单元1022预定义有对应的指令名称和指令代码。Instruction command unit 1022 (CMD INSTRUCTION), the first end of theinstruction command unit 1022 is connected to theJTAG interface 104, the second end of theinstruction command unit 1022 is connected to theAHB bus interface 106, theinstruction command Unit 1022 is predefined with corresponding instruction names and instruction codes.

在本公开的一种示例性实施例中，如图2所示，所述逻辑控制电路102还包括：In an exemplary embodiment of the present disclosure, as shown in FIG. 2 , thelogic control circuit 102 further includes:

专用控制命令单元1024(TMS INSTRUCTION)，所述专用控制命令单元1024的第一端连接至所述JTAG接口104，所述专用控制命令单元1024的第二端连接至所述AHB总线接口106，所述专用控制命令单元1024预定义有ATE测试专用协议，所述ATE测试专用协议用于基于输入的控制信号定义测试向量的输入方式。Dedicated control command unit 1024 (TMS INSTRUCTION), the first end of the dedicatedcontrol command unit 1024 is connected to theJTAG interface 104, the second end of the dedicatedcontrol command unit 1024 is connected to theAHB bus interface 106, the The dedicatedcontrol command unit 1024 is pre-defined with a dedicated ATE test protocol, and the dedicated ATE test protocol is used to define the input mode of the test vector based on the input control signal.

在本公开的一种示例性实施例中，如图2所示，所述逻辑控制电路102还包括：In an exemplary embodiment of the present disclosure, as shown in FIG. 2 , thelogic control circuit 102 further includes:

指令执行数据单元1026，所述指令执行数据单元1026的第一端连接至所述JTAG接口104，所述指令执行数据单元1026的第二端连接至所述AHB总线接口106，所述指令执行数据单元1026存储有用于执行所述指定测试指令的数据。Instructionexecution data unit 1026, the first end of the instructionexecution data unit 1026 is connected to theJTAG interface 104, the second end of the instructionexecution data unit 1026 is connected to theAHB bus interface 106, the instructionexecution data Unit 1026 stores data for executing the specified test instructions.

在本公开的一种示例性实施例中，基于JTAG协议定义了一个ATE测试专用协议，通过TMS的输入定义了以下一些测试向量的输入方式如表1所示。In an exemplary embodiment of the present disclosure, an ATE test-specific protocol is defined based on the JTAG protocol, and the following input methods of some test vectors are defined through the input of the TMS, as shown in Table 1.

表1Table 1

tms 100001:cmd starttms 100001: cmd starttms 111111:cmd endtms 111111: cmd endtms 100011:cmd instructiontms 100011: cmd instructiontms 100101:cmd d0tms 100101: cmd d0tms 100111:cmd d1tms 100111: cmd d1tms 101001:cmd d2tms 101001: cmd d2tms 101011:cmd d3tms 101011: cmd d3tms 101101:cmd d4tms 101101: cmd d4tms 101111:cmd d5tms 101111: cmd d5tms 110001:cmd d6tms 110001: cmd d6tms 110011:cmd d7tms 110011: cmd d7

在本公开的一种示例性实施例中，如图2所示，所述逻辑控制电路102还包括：In an exemplary embodiment of the present disclosure, as shown in FIG. 2 , thelogic control circuit 102 further includes:

控制逻辑状态机1028(control logic FSM)，所述控制逻辑状态机1028的第一端连接至所述指令命令单元，所述控制逻辑状态机1028的第二端连接至所述专用控制命令单元，所述控制逻辑状态机1028的第三端连接至所述指令执行数据单元，所述控制逻辑状态机1028的第四端连接至所述AHB总线接口106，所述控制逻辑状态机1028用于根据所述TC模块100的输入变量、输出变量和状态数进行测试控制所述测试程序执行。A control logic state machine 1028 (control logic FSM), the first end of the controllogic state machine 1028 is connected to the instruction command unit, and the second end of the controllogic state machine 1028 is connected to the dedicated control command unit, The third end of the controllogic state machine 1028 is connected to the instruction execution data unit, the fourth end of the controllogic state machine 1028 is connected to theAHB bus interface 106, and the controllogic state machine 1028 is used for The input variables, output variables and state numbers of the TC module 100 are tested to control the execution of the test program.

在本公开的一种示例性实施例中，如图3所示，所述JTAG接口104连接至所述输入变量的相关接口，所述输入变量的相关接口包括TCK接口、TDI接口、TMS接口、TRST_N接口和TDO接口中的至少一种。In an exemplary embodiment of the present disclosure, as shown in FIG. 3 , theJTAG interface 104 is connected to the relevant interfaces of the input variables, and the relevant interfaces of the input variables include a TCK interface, a TDI interface, a TMS interface, At least one of TRST_N interface and TDO interface.

其中，TCK接口是JTAG接口对应的外部输入时钟的接口，TDI接口是JTAG接口对应的外部数据输入信号的接口，TDO接口是JTAG接口对应的外部输出信号的接口，TMS接口是JTAG接口对应的模式选择信号的接口，TRST_N接口通常连接至音频设备连接插头，用于平衡信号的传输(此时功能与卡农插头一样)，或者用于不平衡的立体声信号的传输。Among them, the TCK interface is the interface of the external input clock corresponding to the JTAG interface, the TDI interface is the interface of the external data input signal corresponding to the JTAG interface, the TDO interface is the interface of the external output signal corresponding to the JTAG interface, and the TMS interface is the mode corresponding to the JTAG interface Select the interface of the signal. The TRST_N interface is usually connected to the audio equipment connection plug for the transmission of balanced signals (the function is the same as that of the Canon plug at this time), or for the transmission of unbalanced stereo signals.

在本公开的一种示例性实施例中，对于内部的测试命令定义了指令名称和指令代码如表2所示。In an exemplary embodiment of the present disclosure, an instruction name and an instruction code are defined for internal test commands as shown in Table 2.

表2Table 2

在本公开的一种示例性实施例中，如图3所示，所述AHB总线接口106连接至所述输出变量的相关接口，所述输出变量的相关接口包括HSEL接口、HADDR接口、HTRANS接口、HWRITE接口、HSIZE接口、HBURST接口、HWDATA接口、HRDATA接口和HRESP接口中的至少一种。In an exemplary embodiment of the present disclosure, as shown in FIG. 3 , theAHB bus interface 106 is connected to the relevant interfaces of the output variables, and the relevant interfaces of the output variables include HSEL interfaces, HADDR interfaces, and HTRANS interfaces , at least one of HWRITE interface, HSIZE interface, HBURST interface, HWDATA interface, HRDATA interface and HRESP interface.

图4至图6是本公开示例性实施例的集成芯片的示意图。4 to 6 are schematic diagrams of an integrated chip of an exemplary embodiment of the present disclosure.

参考图4，本公开示例性实施例的集成芯片，包括：Referring to FIG. 4, the integrated chip of an exemplary embodiment of the present disclosure includes:

功能模块202，用于对数据执行运算处理。Afunction module 202, configured to perform calculation processing on data.

总线矩阵204(System bus matrix)，所述总线矩阵204的输入端能够接入如上述的应用于ATE测试的芯片内部的TC模块100，所述TC模块100能够经所述总线矩阵204访问所述功能模块202。Bus matrix 204 (System bus matrix), the input end of described bus matrix 204 can access the TC module 100 inside the chip that is applied to ATE test as above-mentioned, and described TC module 100 can visit described bus matrix 204function module 202 .

在本公开的一种示例性实施例中，如图5所示，所述TC模块100与所述总线矩阵之间通过AHB总线接口106进行数据交互。在集成芯片内部的SOC互联结构中，TC模块100可以视作一个简易小CPU来访问SOC互联结构中的大多数模块，TC模块100通过自身的AHBmaster连接到了集成芯片内部的system bus matrix(即总线矩阵204)，system busmatrix(即总线矩阵204)还可以连接N个CPU，记作CPU 0、……、CPU N，N为大于或等于0的整数。In an exemplary embodiment of the present disclosure, as shown in FIG. 5 , data interaction is performed between the TC module 100 and the bus matrix through anAHB bus interface 106 . In the SOC interconnection structure inside the integrated chip, the TC module 100 can be regarded as a simple small CPU to access most modules in the SOC interconnection structure, and the TC module 100 is connected to the system bus matrix inside the integrated chip (ie, the bus matrix 204), system busmatrix (that is, bus matrix 204) can also connect N CPUs, denoted asCPU 0, . . . , CPU N, where N is an integer greater than or equal to 0.

在本公开的一种示例性实施例中，如图6所示，所述功能模块202包括system sub-modules(系统子模块)、nand_phy(nand闪存物理层)、pcie(peripheral componentinterconnect express，高速串行计算机扩展总线)、efuse(电编程熔丝一次性可编程存储器)中的至少一种模块。In an exemplary embodiment of the present disclosure, as shown in FIG. 6 , thefunctional module 202 includes system sub-modules (system sub-module), nand_phy (nand flash memory physical layer), pcie (peripheral component interconnect express, high-speed serial Line computer expansion bus), efuse (electric programming fuse one-time programmable memory) at least one module.

应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. Actually, according to the embodiment of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided to be embodied by a plurality of modules or units.

在本公开的示例性实施例中，还提供了一种能够实现上述方法的电子设备。In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

所属技术领域的技术人员能够理解，本发明的各个方面可以实现为系统、方法或程序产品。因此，本发明的各个方面可以具体实现为以下形式，即：完全的硬件实施方式、完全的软件实施方式(包括固件、微代码等)，或硬件和软件方面结合的实施方式，这里可以统称为“电路”、“模块”或“系统”。Those skilled in the art can understand that various aspects of the present invention can be implemented as systems, methods or program products. Therefore, various aspects of the present invention can be embodied in the following forms, that is: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which can be collectively referred to herein as "circuit", "module" or "system".

通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、终端装置、或者网络设备等)执行根据本公开实施方式的方法。Through the description of the above implementations, those skilled in the art can easily understand that the example implementations described here can be implemented by software, or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of software products, and the software products can be stored in a non-volatile storage medium (which can be CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to make a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) execute the method according to the embodiments of the present disclosure.

在本公开的示例性实施例中，还提供了一种计算机可读存储介质，其上存储有能够实现本说明书上述方法的程序产品。在一些可能的实施方式中，本发明的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当所述程序产品在终端设备上运行时，所述程序代码用于使所述终端设备执行本说明书上述“示例性方法”部分中描述的根据本发明各种示例性实施方式的步骤。In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium on which a program product capable of implementing the above-mentioned method in this specification is stored. In some possible implementations, various aspects of the present invention can also be implemented in the form of a program product, which includes program code, and when the program product is run on a terminal device, the program code is used to make the The terminal device executes the steps according to various exemplary embodiments of the present invention described in the "Exemplary Method" section above in this specification.

根据本发明的实施方式的用于实现上述方法的程序产品可以采用便携式紧凑盘只读存储器(CD-ROM)并包括程序代码，并可以在终端设备，例如个人电脑上运行。然而，本发明的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。The program product for implementing the above method according to the embodiment of the present invention may adopt a portable compact disk read-only memory (CD-ROM) and include program codes, and may run on a terminal device such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program, and the program may be used by or in combination with an instruction execution system, apparatus or device.

所述程序产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以为但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。The program product may reside on any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。A computer readable signal medium may include a data signal carrying readable program code in baseband or as part of a carrier wave. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

可以以一种或多种程序设计语言的任意组合来编写用于执行本发明操作的程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。Program code for carrying out the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages—such as Java, C++, etc., as well as conventional procedural programming languages. Programming language - such as "C" or a similar programming language. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server to execute. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., using an Internet service provider). business to connect via the Internet).

此外，上述附图仅是根据本发明示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above figures do not imply or limit the chronological order of these processes. In addition, it is also easy to understand that these processes may be executed synchronously or asynchronously in multiple modules, for example.

本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。Other embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, and these modifications, uses or adaptations follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field not disclosed in the present disclosure . The specification and examples are to be considered exemplary only, with the true scope and concept of the disclosure indicated by the appended claims.

Claims (10)

Translated fromChinese

1.一种应用于ATE测试的芯片内部的TC模块，其特征在于，包括：1. a kind of TC module that is applied to the chip interior of ATE test, is characterized in that, comprises:逻辑控制电路，用于将指定测试指令通过本地的AHB master协议转换为测试程序；The logic control circuit is used to convert the specified test instruction into a test program through the local AHB master protocol;JTAG接口，连接至所述逻辑控制电路的输入端，用于接收基于JTAG协议传输的所述指定测试指令，并将所述指定测试指令传输至所述输入端；JTAG interface, connected to the input terminal of the logic control circuit, for receiving the specified test instruction transmitted based on the JTAG protocol, and transmitting the specified test instruction to the input terminal;AHB总线接口，连接至所述逻辑控制电路的输出端，所述AHB总线接口还连接至芯片的总线矩阵，用于将所述指定测试程序发送至所述总线矩阵进行测试。The AHB bus interface is connected to the output terminal of the logic control circuit, the AHB bus interface is also connected to the bus matrix of the chip, and is used to send the specified test program to the bus matrix for testing.2.如权利要求1所述的应用于ATE测试的芯片内部的TC模块，其特征在于，所述逻辑控制电路包括：2. the TC module that is applied to the chip interior of ATE test as claimed in claim 1, is characterized in that, described logic control circuit comprises:指令命令单元，所述指令命令单元的第一端连接至所述JTAG接口，所述指令命令单元的第二端连接至所述AHB总线接口，所述指令命令单元预定义有对应的指令名称和指令代码。Instruction command unit, the first end of the instruction command unit is connected to the JTAG interface, the second end of the instruction command unit is connected to the AHB bus interface, and the instruction command unit is predefined with a corresponding instruction name and instruction code.3.如权利要求1所述的应用于ATE测试的芯片内部的TC模块，其特征在于，所述逻辑控制电路还包括：3. the TC module that is applied to the chip interior of ATE test as claimed in claim 1, is characterized in that, described logic control circuit also comprises:专用控制命令单元，所述专用控制命令单元的第一端连接至所述JTAG接口，所述专用控制命令单元的第二端连接至所述AHB总线接口，所述专用控制命令单元预定义有ATE测试专用协议，所述ATE测试专用协议用于基于输入的控制信号定义测试向量的输入方式。A dedicated control command unit, the first end of the dedicated control command unit is connected to the JTAG interface, the second end of the dedicated control command unit is connected to the AHB bus interface, and the dedicated control command unit is predefined with ATE A test-specific protocol, the ATE test-specific protocol is used to define the input mode of the test vector based on the input control signal.4.如权利要求1所述的应用于ATE测试的芯片内部的TC模块，其特征在于，所述逻辑控制电路还包括：4. the TC module that is applied to the chip interior of ATE test as claimed in claim 1, is characterized in that, described logic control circuit also comprises:指令执行数据单元，所述指令执行数据单元的第一端连接至所述JTAG接口，所述指令执行数据单元的第二端连接至所述AHB总线接口，所述指令执行数据单元存储有用于执行所述指定测试指令的数据。An instruction execution data unit, the first end of the instruction execution data unit is connected to the JTAG interface, the second end of the instruction execution data unit is connected to the AHB bus interface, and the instruction execution data unit is stored for execution The data specifying the test instruction.5.如权利要求1-4中任一项所述的应用于ATE测试的芯片内部的TC模块，其特征在于，所述逻辑控制电路还包括：5. the TC module that is applied to the chip interior of ATE test as described in any one of claim 1-4, it is characterized in that, described logic control circuit also comprises:控制逻辑状态机，所述控制逻辑状态机的第一端连接至所述指令命令单元，所述控制逻辑状态机的第二端连接至所述专用控制命令单元，所述控制逻辑状态机的第三端连接至所述指令执行数据单元，所述控制逻辑状态机的第四端连接至所述AHB总线接口，所述控制逻辑状态机用于根据所述TC模块的输入变量、输出变量和状态数进行测试控制所述测试程序执行。A control logic state machine, the first end of the control logic state machine is connected to the instruction command unit, the second end of the control logic state machine is connected to the special control command unit, the first end of the control logic state machine Three terminals are connected to the instruction execution data unit, the fourth terminal of the control logic state machine is connected to the AHB bus interface, and the control logic state machine is used for input variable, output variable and state according to the TC module The number of tests performed controls the execution of the test program.6.如权利要求5所述的应用于ATE测试的芯片内部的TC模块，其特征在于，所述JTAG接口连接至所述输入变量的相关接口，所述输入变量的相关接口包括TCK接口、TDI接口、TMS接口、TRST_N接口和TDO接口中的至少一种。6. the TC module that is applied to the chip interior of ATE test as claimed in claim 5 is characterized in that, described JTAG interface is connected to the relevant interface of described input variable, and the relevant interface of described input variable comprises TCK interface, TDI At least one of interface, TMS interface, TRST_N interface and TDO interface.7.如权利要求5所述的应用于ATE测试的芯片内部的TC模块，其特征在于，所述AHB总线接口连接至所述输出变量的相关接口，所述输出变量的相关接口包括HSEL接口、HADDR接口、HTRANS接口、HWRITE接口、HSIZE接口、HBURST接口、HWDATA接口、HRDATA接口和HRESP接口中的至少一种。7. the TC module that is applied to the chip interior of ATE test as claimed in claim 5 is characterized in that, described AHB bus interface is connected to the relevant interface of described output variable, and the relevant interface of described output variable comprises HSEL interface, At least one of HADDR interface, HTRANS interface, HWRITE interface, HSIZE interface, HBURST interface, HWDATA interface, HRDATA interface and HRESP interface.8.一种集成芯片，其特征在于，包括：8. An integrated chip, characterized in that it comprises:功能模块，用于对数据执行运算处理；A function module, used to perform calculation processing on data;总线矩阵，所述总线矩阵的输入端能够接入如权利要求1-7中任一项所述的应用于ATE测试的芯片内部的TC模块，所述TC模块能够经所述总线矩阵访问所述功能模块。A bus matrix, the input end of the bus matrix can be connected to the TC module inside the chip applied to the ATE test according to any one of claims 1-7, and the TC module can access the described bus matrix through the bus matrix functional module.9.如权利要求8所述的应用于ATE测试的芯片内部的TC模块，其特征在于，所述TC模块与所述总线矩阵之间通过AHB总线接口进行数据交互。9. The TC module applied to the chip for ATE testing according to claim 8, wherein the data interaction between the TC module and the bus matrix is performed through an AHB bus interface.10.如权利要求8或9所述的应用于ATE测试的芯片内部的TC模块，其特征在于，所述功能模块包括system sub-modules、nand_phy、pcie、efuse中的至少一种模块。10. The internal TC module applied to the ATE test chip according to claim 8 or 9, wherein the functional modules include at least one module of system sub-modules, nand_phy, pcie, and efuse.

Images