CN115274894A - GeSn and Ge avalanche photodiode on Si substrate and manufacturing method thereof - Google Patents

Abstract

The invention relates to a GeSn/Ge avalanche photodiode on a Si substrate and a manufacturing method thereof. A GeSn/Ge avalanche photodiode on a Si substrate comprises the following components which are stacked in sequence from bottom to top: the lower doped silicon region, the intrinsic silicon multiplication layer, the middle doped silicon layer, the intrinsic germanium absorption layer, the intrinsic germanium tin absorption layer and the upper doped germanium tin layer, wherein at least the upper doped germanium tin layer in the intrinsic germanium absorption layer, the intrinsic germanium tin absorption layer and the upper doped germanium tin layer is black germanium tin; the lower doped silicon layer and the upper doped germanium tin layer are also respectively connected with electrodes. The invention solves the problem that the conventional APDs have low absorptivity to wavelengths of more than 2 mu m.

Description

Translated fromChinese

Si衬底上GeSn及Ge雪崩光电二极管及其制造方法GeSn and Ge avalanche photodiode on Si substrate and its manufacturing method

技术领域technical field

本发明涉及半导体领域，特别涉及一种Si衬底上GeSn及Ge雪崩光电二极管及其制造方法。The invention relates to the field of semiconductors, in particular to a GeSn and Ge avalanche photodiode on a Si substrate and a manufacturing method thereof.

背景技术Background technique

短波红外(SWIR，λ＝1-3μm)成像技术在夜视、无损伤检测、光通信、激光雷达、测距、相干传感、医疗诊断、高端监控、铁路、天文等领域具有鲜明的不可替代的优势。作为一种极其灵敏的光电探测器，雪崩光电二极管(Avalanche Photodiodes,APDs)可通过碰撞电离使电荷载流子倍增，从而器件的性能得到显著提升。商业化的InGaAs/InP SWIR APDs存在制造工艺昂贵、晶圆尺寸小、后脉冲效应高、死区时间长、暗计数率高等问题，导致器件性能问题主要原因是InP倍增区域的空穴与电子碰撞电离系数比较大(0.4-0.5)。尽管低成本Si材料的空穴与电子碰撞电离系数比(0.1)优于InP材料，但其截止波长为1.1μm，不适用于SWIR成像应用。Short-wave infrared (SWIR, λ=1-3μm) imaging technology is irreplaceable in night vision, non-destructive detection, optical communication, laser radar, ranging, coherent sensing, medical diagnosis, high-end monitoring, railway, astronomy and other fields The advantages. As an extremely sensitive photodetector, avalanche photodiodes (Avalanche Photodiodes, APDs) can multiply the charge carriers through impact ionization, so that the performance of the device can be significantly improved. Commercial InGaAs/InP SWIR APDs have problems such as expensive manufacturing process, small wafer size, high after-pulse effect, long dead time, and high dark count rate. The main cause of device performance problems is the collision of holes and electrons in the InP multiplication region. The ionization coefficient is relatively large (0.4-0.5). Although the hole-to-electron impact ionization coefficient ratio (0.1) of the low-cost Si material is better than that of the InP material, its cutoff wavelength of 1.1 μm is not suitable for SWIR imaging applications.

同为四族的Ge半导体材料在波长大于1.6μm时的吸收系数极低，这使得Ge不适合1.6-3μm波长范围的SWIR成像。为提升Ge在1.6-3μm波长范围的吸收系数，研究人员提出在Ge半导体材料中掺入Sn元素形成GeSn合金。理论与实验研究均表明：GeSn合金是非常重要的SWIR半导体材料，有望实现低成本、高性能的SWIR APDs。常规的GeSn/Si SWIR APDs以Si层和GeSn层作为倍增区域和吸收区域。此外，研究人员还采用GeSn/Ge多量子阱结构作为吸收区域。受到GeSn材料生长技术与本征吸收特性的限制，目前报道的GeSn/Si SWIR APDs对大于2μm的波吸收率差，导致器件性能差，不能满足实际应用的要求。因此，突破相关技术瓶颈对于低成本、高性能GeSn/Si SWIR APDs的大规模生产和商业化来说至关重要。为此，提出本发明。Ge semiconductor materials belonging to the same group IV have extremely low absorption coefficients when the wavelength is greater than 1.6 μm, which makes Ge unsuitable for SWIR imaging in the wavelength range of 1.6-3 μm. In order to increase the absorption coefficient of Ge in the wavelength range of 1.6-3 μm, researchers proposed to dope Ge semiconductor material with Sn element to form GeSn alloy. Both theoretical and experimental studies have shown that GeSn alloy is a very important SWIR semiconductor material, which is expected to realize low-cost and high-performance SWIR APDs. Conventional GeSn/Si SWIR APDs use Si layer and GeSn layer as multiplication region and absorption region. In addition, the researchers also used the GeSn/Ge multiple quantum well structure as the absorption region. Due to the limitations of GeSn material growth technology and intrinsic absorption characteristics, the currently reported GeSn/Si SWIR APDs have poor absorption rates for waves larger than 2 μm, resulting in poor device performance and cannot meet the requirements of practical applications. Therefore, breaking through the related technical bottleneck is crucial for the mass production and commercialization of low-cost, high-performance GeSn/Si SWIR APDs. For this reason, the present invention is proposed.

发明内容Contents of the invention

本发明的主要目的在于一种Si衬底上GeSn及Ge雪崩光电二极管及其制造方法，解决了现有APDs对2μm以上的波长吸收率低的问题。The main purpose of the invention is a GeSn and Ge avalanche photodiode on a Si substrate and its manufacturing method, which solves the problem of low absorption rate of the existing APDs for wavelengths above 2 μm.

为了实现以上目的，本发明提供了以下技术方案。In order to achieve the above objectives, the present invention provides the following technical solutions.

本发明的第一方面提供了一种Si衬底上GeSn及Ge雪崩光电二极管，包括由下至上依次堆叠的：The first aspect of the present invention provides a GeSn and Ge avalanche photodiode on a Si substrate, including stacking sequentially from bottom to top:

下部掺杂硅区，The lower doped silicon region,

本征硅倍增层，Intrinsic silicon multiplication layer,

中间掺杂硅层，middle doped silicon layer,

本征锗吸收层，Intrinsic germanium absorber layer,

本征锗锡吸收层，Intrinsic GeSn absorber layer,

上部掺杂锗锡层，The upper part is doped with germanium tin layer,

其中，所述本征锗吸收层、本征锗锡吸收层和上部掺杂锗锡层中的至少上部掺杂锗锡层为黑锗锡；Wherein, at least the upper germanium-tin doped layer among the intrinsic germanium absorbing layer, the intrinsic germanium-tin absorbing layer and the upper germanium-tin-doped layer is black germanium-tin;

所述下部掺杂硅层和所述上部掺杂锗锡层还分别连接有电极。The lower doped silicon layer and the upper doped germanium tin layer are also respectively connected with electrodes.

本发明对雪崩光电二极管最上方的掺杂锗锡层的结构改进，使其下方的锗及锗锡吸收层具有了“黑色效应”，对1.6μm及以上甚至2μm的光波吸收率达到90％以上，甚至99％以上，显著提升了低反射特性，因此，本发明的雪崩光电二极管亦可称之为“Si衬底上黑GeSn及黑Ge雪崩光电二极管”。其中，本发明所述的“黑锗锡”是指具有粗糙表面的材料，包括但不限于纳米尺寸的毛刺状、随机锥形尖刺、草状、金字塔状、纳米线、多孔结构等，这些形状可以深入到本征锗锡吸收层甚至深入至本征锗吸收层。The invention improves the structure of the doped germanium-tin layer on the top of the avalanche photodiode, so that the germanium and germanium-tin absorption layer below it has a "black effect", and the light wave absorption rate of 1.6 μm and above or even 2 μm reaches more than 90%. , even more than 99%, significantly improved the low reflection characteristics, therefore, the avalanche photodiode of the present invention can also be called "black GeSn and black Ge avalanche photodiode on Si substrate". Among them, "black germanium tin" in the present invention refers to materials with rough surfaces, including but not limited to nano-sized burrs, random cone-shaped spikes, grass-like, pyramid-like, nanowires, porous structures, etc., these The shape can go deep into the intrinsic germanium tin absorber layer or even into the intrinsic germanium absorber layer.

另外，与商业化的InGaAs/InP SWIR APDs相比，本发明的黑GeSn/黑Ge/Si SWIRAPDs具有低成本、与硅工艺兼容、大晶圆尺寸、宽频谱范围、可大批量生产、可在室温下工作等优势，是变革SWIR探测领域的关键技术，其实现有助于推动红外夜视、量子计算、量子通信、激光雷达、医疗成像、无人驾驶、污染监测、航行安全等高科技技术领域的快速发展。In addition, compared with the commercialized InGaAs/InP SWIR APDs, the black GeSn/black Ge/Si SWIRAPDs of the present invention are low cost, compatible with silicon process, large wafer size, wide spectrum range, mass production, available in The advantages of working at room temperature are the key technologies to change the field of SWIR detection. Its realization will help promote high-tech technologies such as infrared night vision, quantum computing, quantum communication, laser radar, medical imaging, unmanned driving, pollution monitoring, and navigation safety. rapid development of the field.

对于各区域和各层的掺杂类型则根据二极管的用途而定，例如根据电子倍增或空穴倍增不同类型而定，目前应用比较广泛的是电子倍增。The doping type of each region and layer depends on the application of the diode, for example, according to the different types of electron multiplication or hole multiplication, and electron multiplication is widely used at present.

当采用电子倍增的二极管时，所述下部掺杂硅区的掺杂为n掺杂，且所述中间掺杂硅层和所述上部掺杂锗锡层的掺杂为p掺杂。When an electron-multiplied diode is used, the doping of the lower doped silicon region is n-doped, and the doping of the middle doped silicon layer and the upper doped germanium-tin layer is p-doped.

当采用空穴倍增的二极管时，将电子倍增的二极管各掺杂层的类型替换即可，具体为n掺杂改为p掺杂，p掺杂改为n掺杂。When the hole-multiplied diode is used, the type of each doped layer of the electron-multiplied diode can be replaced, specifically, n-doped is changed to p-doped, and p-doped is changed to n-doped.

在一些实施方式中，所述本征硅倍增层的上表面设有凹陷区域，所述中间掺杂硅层位于所述凹陷区域。In some embodiments, the upper surface of the intrinsic silicon multiplication layer is provided with a recessed region, and the intermediate doped silicon layer is located in the recessed region.

采用这种结构可以有效降低边缘漏电或边缘击穿问题。Adopting this structure can effectively reduce the problem of edge leakage or edge breakdown.

在一些实施方式中，所述黑锗锡的深度为0.01～4μm，直径为0.01～1μm，以显著提高对1.6～2.0μm范围波长的吸收率。In some embodiments, the black germanium tin has a depth of 0.01-4 μm and a diameter of 0.01-1 μm, so as to significantly increase the absorption rate of wavelengths in the range of 1.6-2.0 μm.

在一些实施方式中，所述下部掺杂硅区采用掺杂的硅衬底，或者在未掺杂的硅衬底上设有掺杂硅层的结构。两种形成的二极管各有优势，前者成本低，后者掺杂硅层的厚度可控。In some embodiments, the lower doped silicon region adopts a doped silicon substrate, or a structure in which a doped silicon layer is provided on an undoped silicon substrate. The two kinds of diodes have their own advantages, the former has low cost, and the latter has controllable thickness of the doped silicon layer.

另外，上述未掺杂的硅衬底也可以替换为其他衬底，包括但不限于SOI(绝缘体上硅)，蓝宝石，SOS(蓝宝石上硅)，SGOI(绝缘体上硅锗)，SGOS(蓝宝石上硅锗)，GOI(绝缘体上锗)，GOS(蓝宝石上锗)，GaAsOI(绝缘体上GaAs)和GaAsOS(蓝宝石上GaAs)衬底等。In addition, the aforementioned undoped silicon substrate can also be replaced with other substrates, including but not limited to SOI (silicon-on-insulator), sapphire, SOS (silicon-on-sapphire), SGOI (silicon-germanium-on-insulator), SGOS (silicon-on-sapphire Silicon germanium), GOI (germanium on insulator), GOS (germanium on sapphire), GaAsOI (GaAs on insulator) and GaAsOS (GaAs on sapphire) substrates, etc.

在一些实施方式中在一些实施方式中，所述电极为透明电极。In some embodiments, the electrode is a transparent electrode.

在一些实施方式中，所述本征硅倍增层的厚度、中间掺杂硅层的厚度、本征锗吸收层与本征锗锡吸收层总厚、上部掺杂锗锡层的厚度分别为0.5～2μm、80～120nm、0.5～3μm、80～120nm。In some embodiments, the thickness of the intrinsic silicon multiplication layer, the thickness of the middle doped silicon layer, the total thickness of the intrinsic germanium absorption layer and the intrinsic germanium-tin absorption layer, and the thickness of the upper doped germanium-tin layer are respectively 0.5 ～2μm, 80～120nm, 0.5～3μm, 80～120nm.

在一些实施方式中，所述下部掺杂硅区采用在未掺杂的硅衬底上设有掺杂硅层的结构，所述掺杂硅层的厚度为0.5～2μm。In some embodiments, the lower doped silicon region adopts a structure in which a doped silicon layer is provided on an undoped silicon substrate, and the thickness of the doped silicon layer is 0.5-2 μm.

本发明的第二方面提供了上文所述的Si衬底上GeSn及Ge雪崩光电二极管的制造方法，包括下列步骤：A second aspect of the present invention provides a method for manufacturing GeSn and Ge avalanche photodiodes on the Si substrate as described above, comprising the following steps:

先形成由下至上依次堆叠的以下结构：下部掺杂硅区、本征硅倍增层、中间掺杂硅层、外延锗层、外延锗锡层，First form the following structures stacked from bottom to top: lower doped silicon region, intrinsic silicon multiplication layer, middle doped silicon layer, epitaxial germanium layer, epitaxial germanium tin layer,

对所述外延锗锡层的浅表层进行掺杂，形成上部掺杂锗锡层，下方剩余锗层为本征锗锡吸收层；Doping the shallow surface layer of the epitaxial germanium-tin layer to form an upper doped germanium-tin layer, and the remaining germanium layer below is an intrinsic germanium-tin absorbing layer;

再刻蚀所述本征锗吸收层、本征锗锡吸收层和上部掺杂锗锡层中的至少上部掺杂锗锡层，使其形成黑锗锡；Etching at least the upper germanium-tin layer among the intrinsic germanium absorber layer, intrinsic germanium-tin absorber layer and upper germanium-tin-doped layer to form black germanium-tin;

从所述下部掺杂硅层和所述上部掺杂锗锡层引出电极。Electrodes are drawn out from the lower doped silicon layer and the upper doped germanium tin layer.

以上工艺与现有的APDs兼容性好，降低了产品升级难度。The above process has good compatibility with existing APDs, which reduces the difficulty of product upgrading.

在一些实施例中，采用如下方法形成所述本征硅倍增层和中间掺杂硅层：In some embodiments, the intrinsic silicon multiplication layer and the intermediate doped silicon layer are formed by the following method:

在下部掺杂硅区上方形成硅膜，然后将硅膜浅表层的中心区域进行掺杂以形成中间掺杂硅层，其余硅膜作为本征硅倍增层。A silicon film is formed above the lower doped silicon region, and then the central region of the shallow surface layer of the silicon film is doped to form an intermediate doped silicon layer, and the rest of the silicon film is used as an intrinsic silicon multiplication layer.

或者，采用如下方法形成所述本征硅倍增层和中间掺杂硅层：Alternatively, the intrinsic silicon multiplication layer and the intermediate doped silicon layer are formed by the following method:

在下部掺杂硅区上方形成硅膜，作为本征硅倍增层；forming a silicon film over the lower doped silicon region as an intrinsic silicon multiplication layer;

然后在本征硅倍增层上方沉积掺杂硅层，作为中间掺杂硅层。A doped silicon layer is then deposited over the intrinsic silicon multiplication layer as an intermediate doped silicon layer.

在一些实施例中，采用如下方法形成所述外延锗层和所述外延锗锡层：In some embodiments, the epitaxial germanium layer and the epitaxial germanium tin layer are formed by the following method:

先外延一层锡，然后再异质外延一层锗锡；Epitaxial layer of tin first, and then heteroepitaxial layer of germanium tin;

或者，or,

先外延一层锗，然后对锗的浅表层进行锡离子注入，使其表层形成外延锗锡层。在一些实施例中，所述刻蚀所述上部掺杂锗锡层的手段为以下中的一种或多种结合：A layer of germanium is epitaxial first, and then tin ions are implanted on the shallow surface layer of germanium to form an epitaxial germanium tin layer on the surface layer. In some embodiments, the means for etching the upper doped germanium-tin layer is one or more of the following combinations:

SF₆中的飞秒激光照射，基于SF₆的电感耦合等离子体蚀刻，Cl₂基反应离子刻蚀，基于SF₆的ICP-RIE工艺，金属辅助化学蚀刻。Femtosecond laser irradiation in_SF6 ,_SF6 -based inductively coupled plasma etching, Cl2_- based reactive ion etching,_SF6 -based ICP-RIE process, metal-assisted chemical etching.

在一些实施例中，在所述引出电极之前还包括：In some embodiments, before the extraction electrode, it also includes:

形成使所述下部掺杂硅区的至少部分表面和上部掺杂锗锡层的至少表面裸露的台面；forming a mesa exposing at least part of the surface of the lower doped silicon region and at least a surface of the upper doped germanium tin layer;

然后形成覆盖所述台面表面的钝化层；then forming a passivation layer covering the surface of the mesa;

刻蚀所述钝化层，形成用于引出电极的接触孔。Etching the passivation layer to form a contact hole for drawing out electrodes.

综上，与现有技术相比，本发明达到了以下技术效果：In summary, compared with the prior art, the present invention achieves the following technical effects:

(1)提供Si衬底上黑GeSn/黑Ge异质材料的结构及制备方法，旨在提升GeSn吸收层在大于2μm时的吸收效率；(1) Provide the structure and preparation method of black GeSn/black Ge heterogeneous material on Si substrate, aiming to improve the absorption efficiency of GeSn absorption layer when it is larger than 2 μm;

(2)提供Si衬底上黑GeSn/黑Ge/Si SWIR APDs的结构及制备方法，采用黑GeSn/黑Ge异质材料作为吸收层，降低反射对GeSn层吸收效率的影响，旨在提升黑GeSn/黑Ge/SiSWIR APDs的关键性能参数。(2) Provide the structure and preparation method of black GeSn/black Ge/Si SWIR APDs on Si substrate, use black GeSn/black Ge heterogeneous material as the absorption layer, reduce the influence of reflection on the absorption efficiency of GeSn layer, and aim to improve the black Key performance parameters of GeSn/black Ge/SiSWIR APDs.

附图说明Description of drawings

通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention.

图1-5为本发明实施例1提供的Si衬底上GeSn/Ge雪崩光电二极管的制造方法各步骤得到的结构示意图；1-5 are structural schematic diagrams obtained in each step of the manufacturing method of a GeSn/Ge avalanche photodiode on a Si substrate provided in Embodiment 1 of the present invention;

图6-10为本发明实施例2提供的Si衬底上GeSn/Ge雪崩光电二极管的制造方法各步骤得到的结构示意图；6-10 are structural schematic diagrams obtained in each step of the manufacturing method of a GeSn/Ge avalanche photodiode on a Si substrate provided in Embodiment 2 of the present invention;

图11-15为本发明实施例3提供的Si衬底上GeSn/Ge雪崩光电二极管的制造方法各步骤得到的结构示意图；11-15 are structural schematic diagrams obtained in each step of the manufacturing method of a GeSn/Ge avalanche photodiode on a Si substrate provided in Embodiment 3 of the present invention;

图16-20为本发明实施例4提供的Si衬底上GeSn/Ge雪崩光电二极管的制造方法各步骤得到的结构示意图。16-20 are schematic structural diagrams obtained in each step of the method for manufacturing a GeSn/Ge avalanche photodiode on a Si substrate according to Embodiment 4 of the present invention.

具体实施方式Detailed ways

以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on" another layer/element in one orientation, the layer/element can be located "below" the other layer/element when the orientation is reversed.

如背景技术所述，现有APDs的GeSn及吸收层在工作波长大于2μm时的吸收系数与吸收效率低，器件性能差。为此，本发明对锗锡吸收层及其上部的接触层的形状进行改进，以提高对2μm以上波长的吸收率，以期提高器件性能。As mentioned in the background art, the absorption coefficient and absorption efficiency of GeSn and the absorption layer of the existing APDs are low when the operating wavelength is greater than 2 μm, and the device performance is poor. For this reason, the present invention improves the shape of the germanium-tin absorption layer and the contact layer on it, so as to increase the absorption rate for wavelengths above 2 μm, in order to improve device performance.

本发明提供的Si衬底上GeSn/Ge雪崩光电二极管中锗锡/锗具有“黑锗锡/黑锗”结构特点，具体如下。The germanium tin/germanium in the GeSn/Ge avalanche photodiode on the Si substrate provided by the present invention has the structural characteristics of "black germanium tin/black germanium", as follows.

一种Si衬底上GeSn/Ge雪崩光电二极管，包括由下至上依次堆叠的：A GeSn/Ge avalanche photodiode on a Si substrate, including sequentially stacked from bottom to top:

下部掺杂硅区，The lower doped silicon region,

本征硅倍增层，Intrinsic silicon multiplication layer,

中间掺杂硅层，middle doped silicon layer,

本征锗吸收层，Intrinsic germanium absorber layer,

本征锗锡吸收层，Intrinsic GeSn absorber layer,

上部掺杂锗锡层，The upper part is doped with germanium tin layer,

其中，所述本征锗吸收层、本征锗锡吸收层和上部掺杂锗锡层中的至少上部掺杂锗锡层为黑锗锡；Wherein, at least the upper germanium-tin doped layer among the intrinsic germanium absorbing layer, the intrinsic germanium-tin absorbing layer and the upper germanium-tin-doped layer is black germanium-tin;

所述下部掺杂硅层和所述上部掺杂锗锡层还分别连接有电极。The lower doped silicon layer and the upper doped germanium tin layer are also respectively connected with electrodes.

本发明正是利用上述“黑锗锡”提高吸收率和拓宽波长范围，实验证明其对2μm以上波长的吸收率达到90％以上，甚至99％以上。The present invention utilizes the above-mentioned "black germanium tin" to increase the absorption rate and broaden the wavelength range. Experiments have proved that its absorption rate for wavelengths above 2 μm reaches more than 90%, or even more than 99%.

在此基础上还可以优化二极管的材料类型、各层形状及厚度等参数，以进一步提高光吸收率或者灵敏度等。On this basis, parameters such as the material type of the diode, the shape and thickness of each layer can be optimized to further improve the light absorption rate or sensitivity.

例如，优化本征硅倍增层和中间掺杂硅层的关系：所述本征硅倍增层的上表面设有凹陷区域，所述中间掺杂硅层位于所述凹陷区域。这样减少边缘漏电或击穿问题。For example, optimizing the relationship between the intrinsic silicon multiplication layer and the intermediate doped silicon layer: the upper surface of the intrinsic silicon multiplication layer is provided with a recessed area, and the intermediate doped silicon layer is located in the recessed area. This reduces edge leakage or shoot-through problems.

优化黑锗锡的尺寸，所述黑锗锡的深度为0.01～4μm，直径为0.01～1μm。The size of the black germanium tin is optimized, the depth of the black germanium tin is 0.01-4 μm, and the diameter is 0.01-1 μm.

优化电极的材料，采用透明电极。Optimize the material of the electrode and use a transparent electrode.

优化各层的厚度，所述本征硅倍增层、中间掺杂硅层、本征锗吸收层与本征锗锡吸收层总厚、上部掺杂锗锡层的厚度优选分别为0.5～2μm、80～120nm、0.5～3μm、80～120nm。进一步地，所述下部掺杂硅区采用在未掺杂的硅衬底上设有掺杂硅层的结构，所述掺杂硅层的厚度优选为0.5～2μm。Optimizing the thickness of each layer, the total thickness of the intrinsic silicon multiplication layer, intermediate doped silicon layer, intrinsic germanium absorption layer and intrinsic germanium-tin absorption layer, and the thickness of the upper doped germanium-tin layer are preferably 0.5 to 2 μm, respectively. 80~120nm, 0.5~3μm, 80~120nm. Further, the lower doped silicon region adopts a structure in which a doped silicon layer is provided on an undoped silicon substrate, and the thickness of the doped silicon layer is preferably 0.5-2 μm.

优化掺杂类型，所述下部掺杂硅区的掺杂为n掺杂，且所述中间掺杂硅层和所述上部掺杂锗锡层的掺杂为p掺杂。The doping type is optimized, the doping of the lower doped silicon region is n-doped, and the doping of the middle doped silicon layer and the upper doped germanium-tin layer is p-doped.

本发明还提供了上述Si衬底上Ge雪崩光电二极管的制造方法，主要包括衬底制作、黑GeSn及黑Ge形成、台面及电极制作等三个主要阶段。The present invention also provides a method for manufacturing the above-mentioned Ge avalanche photodiode on the Si substrate, which mainly includes three main stages: substrate fabrication, black GeSn and black Ge formation, and mesa and electrode fabrication.

下文以电子倍增的雪崩光电二极管为例介绍本发明的制造工艺。The manufacturing process of the present invention will be described below taking an electron-multiplied avalanche photodiode as an example.

实施例1Example 1

(1)GeSn及Ge/Si衬底制作：(1) Fabrication of GeSn and Ge/Si substrates:

提供n+-Si衬底101作为初始材料，形成0.5-2μm厚的i-Si雪崩层，即i-Si倍增层102，在i-Si倍增层102上外延100nm厚p-Si电荷层103。在p-Si电荷层103上外延Ge吸收层104和GeSn吸收层111，两个吸收层总厚0.5-3μm，GeSn吸收层111可采用先形成0.5-3μm的锗层后对浅表层进行Sn离子注入的方式形成。之后对GeSn吸收层111浅层掺杂形成100nm厚p+-GeSn接触层105，得到如图1所示的结构。以上尺寸仅为列举，并不限制本发明的应用范围，例如p+-Ge层的厚度可以在80nm～120nm之间调整。另外，各层的形成手段，除外延外，其余可采用PECVD、LPCVD、ALD、CVD等各种典型沉积方法。掺杂的元素类型也不受限制，同种类型的掺杂优选采用相同元素。掺杂浓度和锗锡的比例根据需要调整。Provide an n+-Si substrate 101 as an initial material, form a 0.5-2 μm thick i-Si avalanche layer, that is, an i-Si multiplication layer 102 , and epitaxially 100 nm thick p-Si charge layer 103 on the i-Si multiplication layer 102 . EpitaxialGe absorbing layer 104 andGeSn absorbing layer 111 on the p-Si charge layer 103, the total thickness of the two absorbing layers is 0.5-3 μm,GeSn absorbing layer 111 can be formed by first forming a germanium layer of 0.5-3 μm and then performing Sn ions on the shallow surface layer formed by injection. Afterwards, theGeSn absorption layer 111 is shallowly doped to form a 100 nm thick p+-GeSn contact layer 105, and the structure shown in FIG. 1 is obtained. The above dimensions are just examples and do not limit the scope of application of the present invention. For example, the thickness of the p+-Ge layer can be adjusted between 80nm and 120nm. In addition, the formation methods of each layer include epitaxy and other typical deposition methods such as PECVD, LPCVD, ALD, and CVD. The type of doping element is also not limited, and the doping of the same type preferably uses the same element. The doping concentration and the ratio of germanium to tin are adjusted as needed.

(2)黑GeSn及黑Ge衬底制作：(2) Fabrication of black GeSn and black Ge substrates:

刻蚀图1所示的p+-GeSn接触层105，形成如图2所示的纳米尺寸的毛刺107。刻蚀的手段为以下中的一种或多种结合：The p+-GeSn contact layer 105 shown in FIG. 1 is etched to form nanometer-sized burrs 107 as shown in FIG. 2 . The means of etching is one or more combinations of the following:

SF₆中的飞秒激光照射，基于SF₆的电感耦合等离子体蚀刻，Cl₂基反应离子刻蚀，基于SF₆的ICP-RIE工艺，金属辅助化学蚀刻。Femtosecond laser irradiation in_SF6 ,_SF6 -based inductively coupled plasma etching, Cl2_- based reactive ion etching,_SF6 -based ICP-RIE process, metal-assisted chemical etching.

毛刺的尺寸可控制在深度为0.01～4μm，直径为0.01～1μm。毛刺也可以深入至Ge吸收层或GeSn吸收层。The size of the burrs can be controlled at a depth of 0.01-4 μm and a diameter of 0.01-1 μm. The burrs may also penetrate deep into the Ge absorbing layer or the GeSn absorbing layer.

本实施例的毛刺状仅为列举，实际上其也可以替换为随机锥形尖刺、草状、金字塔状、纳米线、多孔结构等。The burr shape in this embodiment is just an example, and in fact, it can also be replaced by random cone-shaped spikes, grass-like, pyramid-like, nanowire, porous structure, and the like.

(3)引出电极：(3) lead out electrode:

形成台面：使所述p+-GeSn接触层105的至少部分表面和n+-Si衬底的至少上表面裸露的，如图3所示；这一步可以接触掩膜版和刻蚀等手段实现。Forming a mesa: exposing at least part of the surface of the p+-GeSn contact layer 105 and at least the upper surface of the n+-Si substrate, as shown in FIG. 3 ; this step can be achieved by contacting a mask and etching.

形成钝化层108：在上一步形成台面的表面形成氧化硅等绝缘材料钝化层，如图4所示。Forming a passivation layer 108: forming a passivation layer of insulating material such as silicon oxide on the surface of the mesa formed in the previous step, as shown in FIG. 4 .

刻蚀接触孔及填充电极：在钝化层上刻蚀接触孔，填充电极材料，以形成n型欧姆接触109、p型欧姆接触110，如图5所示。Etching contact holes and filling electrodes: etching contact holes on the passivation layer and filling electrode materials to form n-type ohmic contacts 109 and p-type ohmic contacts 110 , as shown in FIG. 5 .

在其他实施例中，台面形状并不仅限于图3所示，只要能引出电极同时满足集成度高、电阻小等实用要求即可。In other embodiments, the shape of the mesa is not limited to that shown in FIG. 3 , as long as the electrodes can be drawn out and meet practical requirements such as high integration and low resistance.

实施例2Example 2

(1)GeSn及Ge/Si衬底制作(1) Fabrication of GeSn and Ge/Si substrates

提供i-Si衬底206作为初始材料，在i-Si衬底206上外延0.5-2μm厚n+-Si层201，形成0.5-2μm厚的i-Si倍增层202，在i-Si倍增层202上外延100nm厚p-Si电荷层203。在p-Si电荷层203上外延Ge吸收层204和GeSn吸收层211，两个吸收层总厚0.5-3μm，GeSn吸收层211可采用先形成0.5-3μm的锗层后对浅表层进行Sn离子注入的方式形成。之后对GeSn吸收层211浅层掺杂形成100nm厚p+-GeSn接触层205，得到如图6所示的结构。在其他实施例中，各层的厚度、形成手段和掺杂元素类型及浓度都可以调整。An i-Si substrate 206 is provided as an initial material, and a 0.5-2 μm thick n+-Si layer 201 is epitaxially formed on the i-Si substrate 206 to form a 0.5-2 μm thick i-Si multiplication layer 202. In the i-Si multiplication layer 202 A p-Si charge layer 203 with a thickness of 100nm is epitaxially formed thereon. EpitaxialGe absorbing layer 204 andGeSn absorbing layer 211 on p-Si charge layer 203, the total thickness of the two absorbing layers is 0.5-3 μm,GeSn absorbing layer 211 can be formed by first forming a germanium layer of 0.5-3 μm and then performing Sn ions on the shallow surface layer formed by injection. After that, theGeSn absorption layer 211 is shallowly doped to form a 100 nm thick p+-GeSn contact layer 205, and the structure shown in FIG. 6 is obtained. In other embodiments, the thickness, formation method, and type and concentration of doping elements of each layer can be adjusted.

(2)黑GeSn及黑Ge/Si衬底制作：(2) Fabrication of black GeSn and black Ge/Si substrates:

刻蚀图6所示的p+-GeSn接触层205，形成如图7所示的纳米尺寸的毛刺207形状。刻蚀的手段为以下中的一种或多种结合：The p+-GeSn contact layer 205 shown in FIG. 6 is etched to form nanometer-sized burrs 207 as shown in FIG. 7 . The means of etching is one or more combinations of the following:

SF₆中的飞秒激光照射，基于SF₆的电感耦合等离子体蚀刻，Cl₂基反应离子刻蚀，基于SF₆的ICP-RIE工艺，金属辅助化学蚀刻。Femtosecond laser irradiation in_SF6 ,_SF6 -based inductively coupled plasma etching, Cl2_- based reactive ion etching,_SF6 -based ICP-RIE process, metal-assisted chemical etching.

毛刺的尺寸可控制在深度为0.01～4μm，直径为0.01～1μm。毛刺也可以深入至Ge吸收层或GeSn吸收层。The size of the burrs can be controlled at a depth of 0.01-4 μm and a diameter of 0.01-1 μm. The burrs may also penetrate deep into the Ge absorbing layer or the GeSn absorbing layer.

本实施例的毛刺状仅为列举，实际上其也可以替换为随机锥形尖刺、草状、金字塔状、纳米线、多孔结构等。The burr shape in this embodiment is just an example, and in fact, it can also be replaced by random cone-shaped spikes, grass-like, pyramid-like, nanowire, porous structure, and the like.

(3)引出电极：(3) lead out electrode:

形成台面：使所述p+-GeSn接触层205的至少部分表面和n+-Si层201的至少上表面裸露的，如图8所示；这一步可以接触掩膜版和刻蚀等手段实现。Forming a mesa: exposing at least part of the surface of the p+-GeSn contact layer 205 and at least the upper surface of the n+-Si layer 201, as shown in FIG. 8; this step can be achieved by contacting a mask and etching.

形成钝化层208：在上一步形成台面的表面形成氧化硅等绝缘材料钝化层，如图9所示。Forming a passivation layer 208: forming a passivation layer of insulating material such as silicon oxide on the surface of the mesa formed in the previous step, as shown in FIG. 9 .

刻蚀接触孔及填充电极：在钝化层208上刻蚀接触孔，填充电极材料，以形成n型欧姆接触209、p型欧姆接触210，如图10所示。Etching contact holes and filling electrodes: etching contact holes on thepassivation layer 208 and filling electrode materials to form n-type ohmic contacts 209 and p-type ohmic contacts 210 , as shown in FIG. 10 .

在其他实施例中，台面形状并不仅限于图8所示，只要能引出电极同时满足集成度高、电阻小等实用要求即可。In other embodiments, the shape of the mesa is not limited to that shown in FIG. 8 , as long as the electrodes can be drawn out and meet practical requirements such as high integration and low resistance.

实施例3Example 3

(1)GeSn及Ge/Si衬底制作(1) Fabrication of GeSn and Ge/Si substrates

提供i-Si衬底306作为初始材料，在i-Si衬底306上外延0.5-2μm厚n+-Si层301，形成0.5-2μm厚的i-Si倍增层302，在i-Si倍增层302内形成100nm厚p-Si电荷层303。Ge吸收层304和GeSn吸收层311，两个吸收层总厚0.5-3μm，GeSn吸收层311可采用先形成0.5-3μm的锗层后对浅表层进行Sn离子注入的方式形成。之后对GeSn吸收层311浅层掺杂形成100nm厚p+-GeSn接触层305，得到如图11所示的结构。An i-Si substrate 306 is provided as an initial material, and a 0.5-2 μm thick n+-Si layer 301 is epitaxially formed on the i-Si substrate 306 to form a 0.5-2 μm thick i-Si multiplication layer 302. In the i-Si multiplication layer 302 A 100nm-thick p-Si charge layer 303 is formed therein. TheGe absorbing layer 304 and theGeSn absorbing layer 311 have a total thickness of 0.5-3 μm. TheGeSn absorbing layer 311 can be formed by first forming a germanium layer of 0.5-3 μm and then implanting Sn ions into the shallow surface layer. After that, theGeSn absorption layer 311 is shallowly doped to form a 100 nm thick p+-GeSn contact layer 305, and the structure shown in FIG. 11 is obtained.

(2)黑GeSn及黑Ge/Si衬底制作：(2) Fabrication of black GeSn and black Ge/Si substrates:

刻蚀图11所示的p+-GeSn接触层305，形成如图12所示的纳米尺寸的毛刺307形状。刻蚀的手段为以下中的一种或多种结合：The p+-GeSn contact layer 305 shown in FIG. 11 is etched to form nanometer-sized burrs 307 as shown in FIG. 12 . The means of etching is one or more combinations of the following:

SF₆中的飞秒激光照射，基于SF₆的电感耦合等离子体蚀刻，Cl₂基反应离子刻蚀，基于SF₆的ICP-RIE工艺，金属辅助化学蚀刻。Femtosecond laser irradiation in_SF6 ,_SF6 -based inductively coupled plasma etching, Cl2_- based reactive ion etching,_SF6 -based ICP-RIE process, metal-assisted chemical etching.

毛刺的尺寸可控制在深度为0.01～4μm，直径为0.01～1μm。毛刺也可以深入至Ge吸收层或GeSn吸收层。The size of the burrs can be controlled at a depth of 0.01-4 μm and a diameter of 0.01-1 μm. The burrs may also penetrate deep into the Ge absorbing layer or the GeSn absorbing layer.

本实施例的毛刺状仅为列举，实际上其也可以替换为随机锥形尖刺、草状、金字塔状、纳米线、多孔结构等。The burr shape in this embodiment is just an example, and in fact, it can also be replaced by random cone-shaped spikes, grass-like, pyramid-like, nanowire, porous structure, and the like.

(3)引出电极：(3) lead out electrode:

形成台面：使所述p+-GeSn接触层305的至少部分表面和n+-Si层301的至少上表面裸露的，如图13所示；这一步可以接触掩膜版和刻蚀等手段实现。Forming a mesa: exposing at least part of the surface of the p+-GeSn contact layer 305 and at least the upper surface of the n+-Si layer 301, as shown in FIG. 13; this step can be achieved by contacting a mask and etching.

形成钝化层308：在上一步形成台面的表面形成氧化硅等绝缘材料钝化层，如图14所示。Forming a passivation layer 308: forming a passivation layer of insulating material such as silicon oxide on the surface of the mesa formed in the previous step, as shown in FIG. 14 .

刻蚀接触孔及填充电极：在钝化层308上刻蚀接触孔，填充电极材料，以形成n型欧姆接触309、p型欧姆接触310，如图15所示。Etching contact holes and filling electrodes: etching contact holes on thepassivation layer 308 and filling electrode materials to form n-type ohmic contacts 309 and p-type ohmic contacts 310 , as shown in FIG. 15 .

在其他实施例中，台面形状并不仅限于图13所示，只要能引出电极同时满足集成度高、电阻小等实用要求即可。In other embodiments, the shape of the mesa is not limited to that shown in FIG. 13 , as long as the electrodes can be drawn out and meet practical requirements such as high integration and low resistance.

实施例4Example 4

(1)GeSn及Ge/Si衬底制作(1) Fabrication of GeSn and Ge/Si substrates

提供n+-Si衬底401作为初始材料，外延0.5-2μm厚的i-Si倍增层402，在i-Si倍增层402内形成100nm厚p-Si电荷层403。Ge吸收层404和GeSn吸收层411，两个吸收层总厚0.5-3μm，GeSn吸收层411可采用先形成0.5-3μm的锗层后对浅表层进行Sn离子注入的方式形成。之后对GeSn吸收层411掺杂形成100nm厚p+-GeSn接触层405，得到如图16所示的结构。An n+-Si substrate 401 is provided as an initial material, an i-Si multiplication layer 402 with a thickness of 0.5-2 μm is epitaxially formed, and a p-Si charge layer 403 with a thickness of 100 nm is formed in the i-Si multiplication layer 402 . TheGe absorbing layer 404 and theGeSn absorbing layer 411 have a total thickness of 0.5-3 μm. TheGeSn absorbing layer 411 can be formed by first forming a germanium layer of 0.5-3 μm and then implanting Sn ions into the shallow surface layer. Afterwards, theGeSn absorption layer 411 is doped to form a p+-GeSn contact layer 405 with a thickness of 100 nm, and the structure shown in FIG. 16 is obtained.

(2)黑GeSn及黑Ge/Si衬底制作：(2) Fabrication of black GeSn and black Ge/Si substrates:

刻蚀图16所示的p+-GeSn接触层405，形成如图17所示的纳米尺寸的毛刺407形状。刻蚀的手段为以下中的一种或多种结合：The p+-GeSn contact layer 405 shown in FIG. 16 is etched to form nanometer-sized burrs 407 as shown in FIG. 17 . The means of etching is one or more combinations of the following:

SF₆中的飞秒激光照射，基于SF₆的电感耦合等离子体蚀刻，Cl₂基反应离子刻蚀，基于SF₆的ICP-RIE工艺，金属辅助化学蚀刻。Femtosecond laser irradiation in_SF6 ,_SF6 -based inductively coupled plasma etching, Cl2_- based reactive ion etching,_SF6 -based ICP-RIE process, metal-assisted chemical etching.

毛刺的尺寸可控制在深度为0.01～4μm，直径为0.01～1μm。毛刺也可以深入至Ge吸收层或GeSn吸收层。The size of the burrs can be controlled at a depth of 0.01-4 μm and a diameter of 0.01-1 μm. The burrs may also penetrate deep into the Ge absorbing layer or the GeSn absorbing layer.

本实施例的毛刺状仅为列举，实际上其也可以替换为随机锥形尖刺、草状、金字塔状、纳米线、多孔结构等。The burr shape in this embodiment is just an example, and in fact, it can also be replaced by random cone-shaped spikes, grass-like, pyramid-like, nanowire, porous structure, and the like.

(3)引出电极：(3) lead out electrode:

形成台面：使所述p+-GeSn接触层405的至少部分表面裸露，如图18所示；这一步可以接触掩膜版和刻蚀等手段实现。Forming a mesa: exposing at least part of the surface of the p+-GeSn contact layer 405, as shown in FIG. 18; this step can be achieved by contacting a mask, etching and other means.

形成钝化层408：在上一步形成台面的表面形成氧化硅等绝缘材料钝化层，如图19所示。Forming a passivation layer 408: forming a passivation layer of insulating material such as silicon oxide on the surface of the mesa formed in the previous step, as shown in FIG. 19 .

刻蚀接触孔及填充电极：在钝化层408上刻蚀接触孔，填充电极材料，以形成p型欧姆接触410，同时在n+-Si衬底401背面金属化，形成n型欧姆接触409，如图20所示。Etching the contact hole and filling the electrode: etching the contact hole on thepassivation layer 408, filling the electrode material to form a p-typeohmic contact 410, and metallizing the back of the n+-Si substrate 401 to form an n-typeohmic contact 409, As shown in Figure 20.

在其他实施例中，台面形状并不仅限于图18所示，只要能引出电极同时满足集成度高、电阻小等实用要求即可。In other embodiments, the shape of the mesa is not limited to that shown in FIG. 18 , as long as the electrodes can be drawn out and meet practical requirements such as high integration and low resistance.

以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (13)

1. A GeSn/Ge avalanche photodiode on a Si substrate is characterized by comprising the following components which are stacked from bottom to top in sequence:

a lower region of doped silicon is provided,

an intrinsic silicon multiplication layer is formed on the silicon substrate,

a middle doped silicon layer is arranged between the silicon substrate and the silicon substrate,

an intrinsic germanium-absorbing layer is provided,

an intrinsic germanium-tin (Ge-Sn) absorption layer,

the upper part is doped with a germanium-tin layer,

at least one upper germanium-doped tin layer of the intrinsic germanium absorption layer, the intrinsic germanium-tin absorption layer and the upper germanium-doped tin layer is black germanium tin;

the lower doped silicon layer and the upper doped germanium tin layer are also respectively connected with electrodes.

2. The GeSn/Ge avalanche photodiode on a Si substrate of claim 1, wherein an upper surface of the intrinsic silicon multiplication layer is provided with a recess region, the intermediate doped silicon layer being located in the recess region.

3. The GeSn/Ge avalanche photodiode on a Si substrate of claim 1, wherein the black germanium tin has a depth of 0.01 to 4 μm and a diameter of 0.01 to 1 μm.

4. The GeSn/Ge avalanche photodiode on a Si substrate of claim 1, wherein the lower doped silicon region is a doped silicon substrate or a structure having a doped silicon layer provided on an undoped silicon substrate.

5. A GeSn/Ge avalanche photodiode on a Si substrate according to any one of claims 1 to 4, characterized in that the doping of the lower doped silicon region is n-doped and the doping of the intermediate doped silicon layer and the upper doped germanium tin layer is p-doped.

6. The GeSn/Ge avalanche photodiode on a Si substrate of claim 1, wherein the electrode is a transparent electrode.

7. The GeSn/Ge avalanche photodiode on a Si substrate according to claim 1, wherein the thickness of the intrinsic silicon multiplication layer, the thickness of the middle doped silicon layer, the total thickness of the intrinsic germanium absorption layer and the intrinsic germanium tin absorption layer, and the thickness of the upper germanium tin doped layer are 0.5 to 2 μm, 80 to 120nm, 0.5 to 3 μm, and 80 to 120nm, respectively;

preferably, the ratio of the thickness of the intrinsic germanium absorber layer to the thickness of the intrinsic germanium tin absorber layer is greater than 1:1.

8. the GeSn/Ge avalanche photodiode on a Si substrate of claim 7 wherein the lower doped silicon region is of a structure having a doped silicon layer on an undoped silicon substrate, the doped silicon layer having a thickness of 0.5 to 2 μm.

9. The method of fabricating GeSn and Ge avalanche photodiodes on Si substrates as claimed in any one of claims 1 to 8, comprising the steps of:

firstly, the following structures are formed and stacked from bottom to top in sequence: a lower doped Si region, an intrinsic Si multiplication layer, a middle doped Si layer, an epitaxial Ge-Sn layer,

doping the shallow surface layer of the epitaxial germanium-tin layer to form an upper doped germanium-tin layer, wherein the residual germanium-tin layer below is an intrinsic germanium-tin absorption layer;

etching at least the upper germanium-doped tin layer in the intrinsic germanium absorption layer, the intrinsic germanium-tin absorption layer and the upper germanium-doped tin layer to form black germanium-tin;

and leading out an electrode from the lower doped silicon layer and the upper doped germanium tin layer.

10. The method of manufacturing of claim 9 wherein the intrinsic silicon multiplication layer and the intermediate doped silicon layer are formed by:

a silicon film is formed over the lower doped silicon region, and then the central region of the shallow surface of the silicon film is doped to form a middle doped silicon layer, with the remaining silicon film acting as an intrinsic silicon multiplication layer.

Or, the intrinsic silicon multiplication layer and the middle doped silicon layer are formed by adopting the following method:

forming a silicon film as an intrinsic silicon multiplication layer over the lower doped silicon region;

a doped silicon layer is then deposited over the intrinsic silicon multiplication layer as an intermediate doped silicon layer.

11. The method of manufacturing of claim 9, wherein the epitaxial germanium layer and the epitaxial germanium tin layer are formed by:

firstly, extending a layer of tin, and then heteroepitaxially extending a layer of germanium tin;

or,

and then carrying out tin ion implantation on the shallow surface layer of the germanium to form an epitaxial germanium tin layer on the surface layer.

12. The method of manufacturing of claim 9, wherein the means of etching the upper doped germanium layer is one or more of the following in combination:

SF₆in femtosecond laser irradiation based on SF₆Inductively coupled plasma etching of (Cl)₂Radical reactive ion etching based on SF₆The ICP-RIE process of (1), metal assisted chemical etching.

13. The manufacturing method according to claim 9, further comprising, before the extraction electrode:

forming a mesa that exposes at least a portion of a surface of the lower doped silicon region and at least a surface of an upper doped germanium tin layer;

then forming a passivation layer covering the surface of the mesa;

and etching the passivation layer to form a contact hole for leading out an electrode.

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