Disclosure of Invention
The application provides a passive buzzer control integrated circuit which is used for realizing the circuit integration effect, reducing the PCB area and getting rid of the restriction of factors such as precision, reliability grade and the like of discrete devices.
In one aspect, the application provides a passive buzzer control integrated circuit, which comprises an enabling circuit, a biasing circuit, a charge-discharge circuit, a level conversion circuit and a driving circuit, wherein,
The bias circuit is connected with the enabling circuit and the charging and discharging circuit and is used for outputting a discharging current according to the starting current;
The charging and discharging circuit is connected with the enabling circuit and is used for outputting an initial voltage based on the charging current and the discharging current; the level conversion circuit is connected with the charge-discharge circuit and is used for outputting a power supply voltage after the initial voltage is subjected to transformation treatment;
And the driving circuit is connected with the level conversion circuit and the loudspeaker and is used for outputting a driving signal to the loudspeaker based on the power supply voltage and the modulation control signal so as to drive the loudspeaker to work.
In one embodiment, the enabling circuit includes a first transistor, a first resistor, a second resistor, and a bias current module;
The first end of the first resistor is used for receiving the enabling signal, and the second end of the first resistor is connected with the base electrode of the first transistor;
The emitter of the first transistor is connected with the first end of the second resistor, and the second end of the second resistor is grounded;
And the bias current module is connected with the base electrode of the first transistor and is used for generating the starting current.
In one embodiment, the bias current module comprises a second transistor, a third transistor, a fourth transistor and a third resistor;
The base electrode of the second transistor is connected with the collector electrode of the second transistor and the base electrode of the first transistor, and the emitter electrode of the second transistor is connected with the first end of the third resistor and the base electrode of the third transistor;
The second end of the third resistor is connected with the collector electrode of the third transistor, and the emitter electrode of the third transistor is grounded;
the base electrode of the fourth transistor is connected with the collector electrode of the third transistor, the collector electrode of the fourth transistor is connected with the bias circuit and used for outputting the starting current, and the emitter electrode of the fourth transistor is grounded.
In one embodiment, the bias circuit includes a self-biasing current mirror circuit.
In one embodiment, the self-bias current mirror circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a fourth resistor;
The emitter of the fifth transistor is connected with the emitter of the sixth transistor and the emitter of the ninth transistor and is connected to a power supply, the base of the fifth transistor is connected with the collector of the fifth transistor, and the collector of the fifth transistor is connected with the collector of the seventh transistor and the enabling circuit and is used for receiving the starting current;
The base electrode of the seventh transistor is connected with the base electrode of the eighth transistor, the emitter electrode of the seventh transistor is connected with the first end of the fourth resistor, and the second end of the fourth resistor is grounded;
The base electrode of the sixth transistor is connected with the base electrode of the fifth transistor, and the collector electrode of the sixth transistor is connected with the collector electrode of the eighth transistor;
the base of the ninth transistor is connected with the base of the fifth transistor, and the collector of the ninth transistor is connected with the charge-discharge circuit and is used for outputting discharge current.
In one embodiment, the charge-discharge circuit comprises a capacitor, a discharge module and a charge module, wherein the charge module comprises a tenth transistor and an eleventh transistor;
an emitter of the tenth transistor is connected to an emitter of the eleventh transistor and to a power supply, a base of the tenth transistor is connected to a collector of the tenth transistor and the enable circuit for receiving a charging current;
the base electrode of the eleventh transistor is connected with the base electrode of the tenth transistor, the collector electrode of the eleventh transistor is connected with the first end of the capacitor, and the second end of the capacitor is grounded;
the collector of the twelfth transistor is connected with the first end of the capacitor, the emitter of the twelfth transistor is grounded, the base of the twelfth transistor is connected with the base of the thirteenth transistor, the base of the thirteenth transistor is connected with the collector of the thirteenth transistor and the bias circuit and used for receiving discharge current, and the emitter of the thirteenth transistor is grounded.
In one embodiment, the charge-discharge circuit further comprises a voltage dividing module and a ladder mirror branch:
the voltage dividing module is used for outputting step voltages, and the step voltages correspond to the step mirror image branches one by one;
The step mirror image branch is connected to the corresponding step voltage and is used for starting or stopping discharging the capacitor according to the relation between the current energy storage of the capacitor and the step voltage.
In one embodiment, the number of the step mirror branches is two, and the number of the step voltages is also two, and the step voltages corresponding to different step mirror branches are different.
In one embodiment, the first ladder mirror leg includes a fourteenth transistor and a fifteenth transistor, and the second ladder mirror leg includes a sixteenth transistor and a seventeenth transistor;
the fourteenth transistor and the sixteenth transistor are mirror images of each other, and the fifteenth transistor and the seventeenth transistor are mirror images of each other.
The base electrode of the fourteenth transistor is connected with the collector electrode of the fourteenth transistor, the collector electrode of the fourteenth transistor is connected with the collector electrode of the fifteenth transistor and the voltage dividing circuit and is used for receiving corresponding step voltage, and the emitter electrode of the fourteenth transistor is connected with the first end of the capacitor;
the base of the fifteenth transistor is connected with the base of the thirteenth transistor, and the emitter of the fifteenth transistor is grounded;
the fourteenth transistor and the sixteenth transistor are mirror images of each other, and the fifteenth transistor and the seventeenth transistor are mirror images of each other.
In one embodiment, a unidirectional conductive element is disposed between the collector of the fourteenth transistor and the voltage divider circuit;
The first end of the unidirectional conduction element is connected with the voltage dividing circuit, and the second end of the unidirectional conduction element is connected with the collector electrode of the fourteenth transistor and is used for unidirectional transmission of the step voltage provided by the voltage dividing circuit to the fourteenth transistor.
In one embodiment, the unidirectional-conduction element includes an eighteenth transistor and a nineteenth transistor;
An emitter of the eighteenth transistor is connected with the voltage dividing circuit, a base of the eighteenth transistor is connected with a collector of the eighteenth transistor, and a collector of the eighteenth transistor is connected with a collector of the fourteenth transistor;
The eighteenth transistor and the nineteenth transistor are mirror images of each other.
In one embodiment, the unidirectional conductive element includes a diode;
The positive electrode of the diode is connected with the voltage dividing circuit, and the negative electrode of the diode is connected with the collector electrode of the fourteenth transistor.
In one embodiment, the voltage dividing module comprises a twentieth transistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor;
The second end of the fifth resistor is used for outputting a first ladder voltage, and the second end of the fifth resistor is connected with the first end of the sixth resistor and the collector electrode of a fourteenth transistor in a ladder mirror branch corresponding to the first ladder voltage;
The second end of the sixth resistor is used for outputting a second ladder voltage, and the second end of the sixth resistor is connected with the first end of the seventh resistor and the collector electrode of a fourteenth transistor in the ladder mirror image branch corresponding to the second ladder voltage;
The second end of the seventh resistor is connected with the collector electrode of the twentieth transistor, the second end of the twentieth transistor is grounded, the first end of the eighth resistor is connected with the level conversion circuit and is used for receiving the power supply voltage, and the second end of the eighth resistor is connected with the base electrode of the twentieth transistor.
In one embodiment, the driving circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor;
The emitter of the twenty-first transistor is connected with the first end of the ninth resistor and the emitter of the twenty-fourth transistor and is connected to the power supply voltage, the base of the twenty-first transistor is connected with the second end of the ninth resistor, the collector of the twenty-first transistor is connected with the collector of the twenty-fourth transistor and is used for outputting the driving signal, and the emitter of the twenty-fourth transistor is grounded;
the emitter of the twenty-third transistor is connected with the first end of the tenth resistor, the base of the twenty-third transistor is connected with the second end of the tenth resistor, the collector of the twenty-third transistor is connected with the collector of the twenty-third transistor and is used for outputting the driving signal, and the emitter of the twenty-third transistor is grounded;
The first end of the eleventh resistor is connected with the base electrode of the twenty-fifth transistor and is used for receiving the modulation control signal, the second end of the eleventh resistor is connected with the base electrode of the twenty-third transistor, the collector electrode of the twenty-fifth transistor is connected with the second end of the ninth resistor, and the emitter electrode of the twenty-fifth transistor is grounded;
The first end of the twelfth resistor is connected with the base electrode of the twenty-fourth transistor, the second end of the twelfth resistor is connected with the base electrode of the twenty-sixth transistor and used for receiving the inverted signal of the modulation control signal, the collector electrode of the twenty-sixth transistor is connected with the second end of the tenth resistor, and the emitter electrode of the twenty-sixth transistor is grounded.
In one embodiment, the driving circuit further includes an inverter;
an input end of the inverter is connected to the modulation control signal, and an output end of the inverter is connected to a base of the twenty-sixth transistor.
The application provides a passive buzzer control integrated circuit which comprises an enabling circuit, a biasing circuit, a charging and discharging circuit, a level conversion circuit and a driving circuit. The system comprises an enabling circuit, a bias circuit, a charge-discharge circuit, a level conversion circuit and a loudspeaker, wherein the enabling circuit is used for outputting charging current and starting current according to an enabling signal, the bias circuit is connected with the enabling circuit and the charge-discharge circuit and used for outputting discharging current according to the starting current, the charge-discharge circuit is connected with the enabling circuit and used for outputting initial voltage based on the charging current and the discharging current, the level conversion circuit is connected with the charge-discharge circuit and used for outputting power supply voltage after the initial voltage is subjected to transformation treatment, and the drive circuit is connected with the level conversion circuit and the loudspeaker and used for outputting a drive signal to the loudspeaker to drive the loudspeaker to work based on the power supply voltage and a modulation control signal. The scheme provided by the application adopts the design thought of the integrated circuit, and the music passive buzzer control circuit achieves the integration effect, so that the PCB area is reduced, and the restrictions of factors such as precision, reliability level and the like of discrete devices are eliminated.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic diagram of a passive buzzer control integrated circuit controlling the operation of a speaker;
fig. 2 is a schematic structural diagram of a passive buzzer control integrated circuit according to a first embodiment of the present application;
FIG. 3 is a schematic diagram of an enabling circuit according to a first embodiment of the present application;
FIG. 4 is a schematic diagram of another configuration of an enabling circuit according to a first embodiment of the present application;
FIG. 5 is a schematic diagram of a bias circuit according to a first embodiment of the present application;
FIG. 6 is a schematic diagram of another structure of a bias circuit according to a first embodiment of the present application;
Fig. 7 is a schematic structural diagram of a charge-discharge circuit according to a first embodiment of the present application;
fig. 8 is a schematic diagram of another structure of a charge-discharge circuit according to a first embodiment of the present application;
fig. 9 is a schematic diagram of a charge-discharge circuit according to a first embodiment of the present application;
fig. 10 is a schematic diagram of a charge-discharge circuit according to a first embodiment of the present application;
fig. 11 is a schematic diagram of a charge-discharge circuit according to a first embodiment of the present application;
fig. 12 is a schematic diagram of a charge-discharge circuit according to a first embodiment of the present application;
fig. 13 is a schematic diagram of a charge-discharge circuit according to a first embodiment of the present application;
fig. 14 is a schematic structural diagram of a driving circuit according to a first embodiment of the present application;
fig. 15 is a schematic diagram of another structure of a driving circuit according to an embodiment of the application.
Reference numerals illustrate:
an enable circuit 21;
a bias circuit 22;
23, a charge-discharge circuit;
24, a level conversion circuit;
25, a driving circuit;
Q1 is a first transistor;
Q2 is a second transistor;
q3 is a third transistor;
q4 is a fourth transistor;
a fifth transistor Q5;
Q6: a sixth transistor;
q7: a seventh transistor;
q8 is an eighth transistor;
a ninth transistor Q9;
Q10 is a tenth transistor;
Q11 is an eleventh transistor;
Q12, twelfth transistor;
q13 is thirteenth transistor;
q14, fourteenth transistor;
a fifteenth transistor;
q16, sixteenth transistor;
Q17 seventeenth transistor;
q18 eighteenth transistor;
a nineteenth transistor Q19;
q20 is a twentieth transistor;
q21 is a twenty-first transistor;
a twenty-second transistor Q22;
q23, twenty-third transistor;
a twenty-fourth transistor Q24;
A twenty-fifth transistor Q25;
Q26, twenty-sixth transistor;
r1 is a first resistor;
R2 is a second resistor;
r3 is a third resistor;
R4 is a fourth resistor;
R5 is a fifth resistor;
R6 is a sixth resistor;
R7 is a seventh resistor;
R8 is an eighth resistor;
r9 is a ninth resistor;
R10 is a tenth resistor;
r11 is an eleventh resistor;
and R12 is a twelfth resistor.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
It should be noted that the brief description of the terminology in the present application is for the purpose of facilitating understanding of the embodiments described below only and is not intended to limit the embodiments of the present application. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.
In practical applications, the buzzer integrated circuit is mainly a circuit for realizing a music function by using a speaker, as shown in fig. 1, fig. 1 is a schematic diagram of a passive buzzer control integrated circuit for controlling the speaker to work, and is generally widely applied to washing machines, refrigerators, water heaters, coffee machines, and the like. As can be seen from the figure, the passive buzzer control integrated circuit converts an input signal into an output signal and sends the output signal to the loudspeaker, so that the loudspeaker can work by sounding.
The technical scheme of the present application and the technical scheme of the present application will be described in detail with specific examples. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. In describing the present application, the terms should be construed broadly in the art unless explicitly stated and limited otherwise. Embodiments of the present application will be described below with reference to the accompanying drawings.
Example 1
Fig. 2 is a schematic structural diagram of a passive buzzer control integrated circuit according to an embodiment of the present application, as shown in fig. 2, the passive buzzer control integrated circuit includes an enabling circuit 21, a bias circuit 22, a charge-discharge circuit 23, a level conversion circuit 24, and a driving circuit 25, wherein,
An enable circuit 21 for outputting a charging current and a starting current according to an enable signal, a bias circuit 22 connected to the enable circuit 21 and the charging and discharging circuit 23 for outputting a discharging current according to the starting current;
A charge/discharge circuit 23 connected to the enable circuit 21 for outputting an initial voltage based on the charge current and the discharge current, a level conversion circuit 24 connected to the charge/discharge circuit 23 for transforming the initial voltage and outputting a power supply voltage;
and a driving circuit 25 connected to the level conversion circuit 24 and the speaker for outputting a driving signal to the speaker based on the power supply voltage and the modulation control signal to drive the speaker to operate.
In combination with the scenario example, the passive buzzer control integrated circuit starts to operate after the enable signal is accessed, the enable circuit 21 receives the enable signal and then outputs a starting current to the bias circuit 22, and simultaneously outputs a charging current to the charge-discharge circuit 23. The bias circuit 22 receives the start-up current, and outputs a discharge current to the charge/discharge circuit 23. After receiving the charging current and the discharging current, the charging and discharging circuit outputs an initial voltage to the level conversion circuit 24, and the level conversion circuit 24 performs level conversion on the received initial voltage to generate a supply voltage VREG, which is provided to the driving circuit 25. The driving circuit 25 receives the power supply voltage, and generates a driving signal based on a modulation control signal, which is a pulse width modulation PWM signal and is a speaker frequency input signal, to be supplied to the speaker, thereby controlling the speaker to operate. As an example, the supply voltage VREG may also be returned to the charge-discharge circuit 23.
In one example, fig. 3 is a schematic structural diagram of an enabling circuit according to a first embodiment of the present application, where the enabling circuit 21 includes a first transistor Q1, a first resistor R1, a second resistor R2, and a bias current module;
The first end of the first resistor R1 is used for receiving the enabling signal, and the second end of the first resistor R1 is connected with the base electrode of the first transistor Q1;
The collector of the first transistor Q1 is connected with the charge-discharge circuit 23 and is used for outputting the charge current, the emitter of the first transistor Q1 is connected with the first end of the second resistor R2, and the second end of the second resistor R2 is grounded;
and the bias current module is connected with the base electrode of the first transistor Q1 and is used for generating the starting current.
The enabling circuit 21 is composed of a first resistor R1, a second resistor R2, a first transistor and a first mirror circuit. The enable signal is connected with the base electrode of the first transistor Q1 after passing through the first resistor R1, and the enable signal enables the first transistor to be turned on to generate a charging current, and the charging current is transmitted to the charging and discharging circuit 23 after being output from the collector electrode of the first transistor Q1. The emitter of the first transistor Q1 is grounded after passing through the second resistor, so that the emitter voltage of the first transistor Q1 is set to 0, and thus, the first transistor Q1 is turned on to generate a charging current as soon as the enable signal reaches the first transistor Q1. The bias current module operates on the principle that a signal, which is a start-up current, is generated based on the down-current (reduced current) processed enable signal, which is transmitted to the bias circuit 22. By down-flowing the enable signal, the transistor can be prevented from being burned out.
In another example, fig. 4 is a schematic diagram of another structure of an enabling circuit according to the first embodiment of the present application, where the bias current module includes a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and a third resistor R3;
The base electrode of the second transistor Q2 is connected with the collector electrode of the second transistor Q2 and the base electrode of the first transistor Q1, and the emitter electrode of the second transistor Q2 is connected with the first end of the third resistor R3 and the base electrode of the third transistor Q3;
The second end of the third resistor R3 is connected with the collector of the third transistor Q3, and the emitter of the third transistor Q3 is grounded;
The base of the fourth transistor Q4 is connected to the collector of the third transistor Q3, the collector of the fourth transistor Q4 is connected to the bias circuit 22 for outputting the start-up current, and the emitter of the fourth transistor Q4 is grounded.
For example, when the enable signal is transmitted to the first transistor Q1, the enable signal is also transmitted to the second transistor Q2, and after the current is reduced by the structure formed by the second transistor Q2, the third resistor R3 and the third transistor Q3, the enable signal is input to the fourth transistor Q4, so that the fourth transistor Q4 outputs the start current.
In one example, fig. 5 is a schematic diagram of a bias circuit according to a first embodiment of the present application, where the bias circuit 22 includes a self-bias current mirror circuit.
The self-bias current mirror circuit of the bias circuit 22 generates a discharge current based mainly on the received start-up current, which is supplied to the charge-discharge circuit 23.
In one example, fig. 6 is a schematic diagram of another structure of a bias circuit according to the first embodiment of the present application, where the self-bias current mirror circuit includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, and a fourth resistor R4;
An emitter of the fifth transistor Q5 is connected to an emitter of the sixth transistor Q6 and an emitter of the ninth transistor Q9 and to a power supply, a base of the fifth transistor Q5 is connected to a collector of the fifth transistor Q5, a collector of the fifth transistor Q5 is connected to a collector of the seventh transistor Q7 and to the enabling circuit 21 for receiving the start-up current;
The base electrode of the seventh transistor Q7 is connected with the base electrode of the eighth transistor Q8, the emitter electrode of the seventh transistor Q7 is connected with the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded;
The base of the sixth transistor Q6 is connected with the base of the fifth transistor Q5, the collector of the sixth transistor Q6 is connected with the collector of the eighth transistor Q8, the base of the eighth transistor Q8 is connected with the collector of the eighth transistor Q8, and the emitter of the eighth transistor Q8 is grounded;
The base of the ninth transistor Q9 is connected to the base of the fifth transistor Q5, and the collector of the ninth transistor Q9 is connected to the charge-discharge circuit 23 for outputting a discharge current.
Specifically, in the bias circuit 22, the sixth transistor Q6 mirrors the current in the fifth transistor Q5, and the loop gain is attenuated due to the addition of the resistor R4, and the gain of the positive feedback of the circuit is less than 1, so that the circuit remains stable.
In one example, fig. 7 is a schematic structural diagram of a charge-discharge circuit according to a first embodiment of the present application, wherein the charge-discharge circuit 23 includes a capacitor C1, a discharge module and a charge module, the charge module includes a tenth transistor Q10 and an eleventh transistor Q11, and the discharge module includes a twelfth transistor Q12 and a thirteenth transistor Q13;
An emitter of the tenth transistor Q10 is connected to an emitter of the eleventh transistor Q11 and to a power supply, a base of the tenth transistor Q10 is connected to a collector of the tenth transistor Q10 and the enable circuit for receiving a charging current;
the base of the eleventh transistor Q11 is connected with the base of the tenth transistor Q10, the collector of the eleventh transistor Q11 is connected with the first end of the capacitor C1, and the second end of the capacitor C1 is grounded;
The collector of the twelfth transistor Q12 is connected with the first end of the capacitor C1, the emitter of the twelfth transistor Q12 is grounded, the base of the twelfth transistor Q12 is connected with the base of the thirteenth transistor Q13, the base of the thirteenth transistor Q13 is connected with the collector terminal of the thirteenth transistor Q13 and the bias circuit and used for receiving discharge current, and the emitter of the thirteenth transistor Q13 is grounded.
When the charge-discharge circuit 23 receives the charge current, the eleventh transistor Q11 mirrors the current in the tenth transistor Q10, and the mirrored current charges the capacitor C1, and the discharge current also works simultaneously when the capacitor C1 is charged, but since the charge current is much larger than the discharge current, the voltage on the capacitor C1 is not affected by the discharge current. When the charge-discharge circuit receives the discharge current, the twelfth transistor Q12 mirrors the discharge current in the thirteenth transistor Q13, thereby providing a discharge path of the capacitor C1 to the ground, and realizing the discharge of the capacitor C1.
In one example, fig. 8 is a schematic diagram of another structure of a charge-discharge circuit according to the first embodiment of the present application, where the charge-discharge circuit 23 further includes a voltage dividing module and a step mirror branch:
the voltage dividing module is used for outputting step voltages, and the step voltages correspond to the step mirror image branches one by one;
The step mirror image branch is connected to the corresponding step voltage and is used for starting or stopping discharging the capacitor according to the relation between the current energy storage of the capacitor and the step voltage.
In the figure, the signal VREG is derived from the charging current to charge the capacitor C1 built in the charge-discharge circuit 23, so that the voltage on C1 is raised, then the voltage on C1 is provided for the level conversion circuit 24, so that the level conversion circuit 24 outputs VREG, and the level conversion circuit 24 outputs VREG and then acts on the voltage division module of the charge-discharge circuit 23, so that the voltage division module works.
In one example, the voltage divider circuit outputs different step voltages corresponding to different step mirror circuits, the step mirror branch being used to provide a discharge path of the capacitor C1 to ground.
Optionally, the number of the step mirror image branches is two, the number of the step voltages is also two, and the step voltages corresponding to different step mirror image branches are different. By adjusting the number of the step mirror branches, step discharge at different stages can be realized, so that the voltage of the VREG is slowly stepped down, and the sound is more pleasant.
In one example, fig. 9 is a schematic diagram of still another structure of a charge-discharge circuit according to the first embodiment of the present application, where the first ladder mirror circuit includes a fourteenth transistor Q14 and a fifteenth transistor Q15, and the second ladder mirror circuit includes a sixteenth transistor Q16 and a seventeenth transistor Q17;
The base electrode of the fourteenth transistor Q14 is connected with the collector electrode of the fourteenth transistor Q14, the collector electrode of the fourteenth transistor Q14 is connected with the collector electrode of the fifteenth transistor Q15 and the voltage dividing circuit for receiving corresponding step voltage, and the emitter electrode of the fourteenth transistor Q14 is connected with the first end of the capacitor C1;
the base of the fifteenth transistor Q15 is connected to the base of the thirteenth transistor Q13, and the emitter of the fifteenth transistor Q15 is grounded;
The fourteenth transistor Q14 and the sixteenth transistor Q16 are mirror images of each other, and the fifteenth transistor Q15 and the seventeenth transistor Q17 are mirror images of each other.
The charge-discharge circuit 23 is illustrated with two ladder image branches, a first ladder image branch and a second ladder image branch, respectively. Wherein each ladder mirror leg comprises two transistors, wherein a first ladder mirror leg comprises a fourteenth transistor Q14 and a fifteenth transistor Q15 and a second ladder mirror leg comprises a sixteenth transistor Q16 and a seventeenth transistor Q17. The fourteenth transistor Q14 in the first ladder mirror branch and the sixteenth transistor Q16 in the second ladder mirror branch are in mirror structures, and the connection modes in the circuits are the same. Similarly, the fifteenth transistor Q15 and the seventeenth transistor Q17 are mirror image structures.
In an example, fig. 10 is a schematic diagram of still another structure of a charge-discharge circuit according to the first embodiment of the present application, where a unidirectional conductive element is disposed between a collector of a fourteenth transistor Q14 and the voltage dividing circuit;
The first end of the unidirectional conduction element is connected with the voltage dividing circuit, and the second end of the unidirectional conduction element is connected with the collector electrode of the fourteenth transistor Q14 and is used for unidirectional transmission of the step voltage provided by the voltage dividing circuit to the fourteenth transistor Q14.
Specifically, the unidirectional conducting element is arranged on the step mirror branch, so that the transmission direction of a current signal can be guaranteed to flow from the voltage dividing module to the fourteenth transistor Q14 only, and reverse transmission can not be realized, and signal backflow is prevented. Since the first step mirror branch and the second step mirror branch are mirror branches, a unidirectional conductive element is also disposed between the sixteenth transistor Q16 and the voltage divider circuit.
In one example, fig. 11 is a schematic diagram of a charge-discharge circuit according to a first embodiment of the present application, where the unidirectional-conduction device includes an eighteenth transistor Q18 and a nineteenth transistor Q19;
an emitter of the eighteenth transistor Q18 is connected to the voltage dividing circuit, a base of the eighteenth transistor Q18 is connected to a collector of the eighteenth transistor Q18, and a collector of the eighteenth transistor Q18 is connected to a collector of the fourteenth transistor Q14;
the eighteenth transistor Q18 and the nineteenth transistor Q19 are mirror images of each other.
In particular, the unidirectional conducting element in a single stepped mirror leg may be implemented as a transistor. For example, an eighteenth transistor Q18 in the first step mirror leg in the figure serves as a unidirectional conducting element in the first step mirror leg, and a nineteenth transistor Q19 in the second step mirror leg serves as a unidirectional conducting element in the second step mirror leg.
In one example, fig. 12 is a schematic diagram of still another structure of a charge-discharge circuit according to the first embodiment of the present application, where the unidirectional conductive element includes a diode;
The positive electrode of the diode is connected with the voltage dividing circuit, and the negative electrode of the diode is connected with the collector of the fourteenth transistor Q14.
Specifically, the unidirectional conductive element on the step mirror branch may be a diode. For example, in fig. 12, the diode corresponding to the first step mirror branch is D1, and the negative electrode of D1 is connected to the collector of the fourteenth transistor Q14. The diode corresponding to the second step mirror branch is D2, and the cathode of D2 is connected to the first end of the sixteenth transistor Q16.
In one example, fig. 13 is a schematic diagram of a charge-discharge circuit according to a first embodiment of the present application, where the voltage dividing module includes a twentieth transistor Q20, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8;
The second end of the fifth resistor R5 is used for outputting a first ladder voltage, and the second end of the fifth resistor R5 is connected with the first end of the sixth resistor R6 and the collector electrode of a fourteenth transistor in a ladder mirror branch corresponding to the first ladder voltage;
The second end of the sixth resistor R6 is used for outputting a second step voltage, and the second end of the sixth resistor R6 is connected with the first end of the seventh resistor R7 and the collector electrode of the fourteenth transistor in the step mirror branch corresponding to the second step voltage;
the second end of the seventh resistor R7 is connected to the collector of the twentieth transistor Q20, the emitter of the twentieth transistor Q20 is grounded, the first end of the eighth resistor R8 is connected to the level shift circuit 24 for receiving the supply voltage, and the second end of the eighth resistor R8 is connected to the base of the twentieth transistor Q20.
In the charge-discharge circuit, a first end of a fifth resistor R5 is connected to a power supply VCC, a second end of the fifth resistor R5 outputs a first step voltage, a first step mirror branch corresponding to the first step voltage is connected with the second end of the fifth resistor R5, and similarly, a second end of a sixth resistor R6 outputs a second step voltage, and a second step mirror branch corresponding to the second step voltage is connected with the second end of the sixth resistor R6.
From the illustrated situation, it can be seen that in this example, the first step voltage V1 is higher than the second step voltage V2. In connection with the example of a discharge scenario, when the capacitor C1 just begins to discharge, the voltage at the first end of the capacitor C1 is greater, and the voltages at the right ends of the fourteenth transistor Q14 of the first ladder image branch and the sixteenth transistor Q16 of the second ladder image branch (here, "left/right" is merely by way of reference to the example, but not by way of limitation to the structure) are higher than the voltages at the left ends thereof, so that both Q14 and Q16 are on. Accordingly, the stored energy on capacitor C1 is discharged to ground through the first stepped mirror leg formed by Q14 and Q15 and the second stepped mirror leg formed by Q16 and Q17. That is, the discharging path of the capacitor C1 includes the path in which the twelfth transistor Q12 is located and the two-step mirror branches and the three paths.
When the capacitor C1 discharges for a period of time, the voltage on the capacitor C1 decreases, and accordingly, the voltages on the right ends of the fourteenth transistor Q14 and the sixteenth transistor Q16 decrease, and when the voltage decreases between the first step voltage and the second step voltage, the voltage on the right end of the fourteenth transistor Q14 is lower than the voltage on the left end thereof, and the voltage on the right end of the sixteenth transistor Q16 is still higher than the voltage on the left end thereof. The fourteenth transistor Q14 is turned off, but the sixteenth transistor Q16 is still turned on. Therefore, the discharge path at this time includes a path in which the twelfth transistor Q12 is located and a second step mirror branch, two paths.
The subsequent capacitor C1 continues to discharge, the voltage on the capacitor C1 continues to decrease, and when the voltage decreases below the second step voltage, the sixteenth transistor Q16 is turned off, and the discharge path only includes the path along which the twelfth transistor Q12 is located until the discharge of the capacitor C1 ends.
In this example, the charge-discharge circuit 23 achieves the effect of step-discharging the capacitor C1 by setting the voltage dividing module and the step mirror branch, so that the sound controlled by the passive buzzer is more gentle. In addition, when the voltage on C1 is discharged so that the supply voltage VREG is smaller than the on voltage of the twentieth transistor Q20, the voltage dividing circuit stops operating, thereby reducing power consumption.
In one example, fig. 14 is a schematic diagram of a driving circuit according to the first embodiment of the present application, wherein the driving circuit 25 includes a twenty-first transistor Q21, a twenty-second transistor Q22, a twenty-third transistor Q23, a twenty-fourth transistor Q24, a twenty-fifth transistor Q25, a twenty-sixth transistor Q26, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12;
an emitter of the twenty-first transistor Q21 is connected to a first end of the ninth resistor R9 and an emitter of the twenty-fourth transistor Q22 and to the power supply voltage, a base of the twenty-first transistor Q21 is connected to a second end of the ninth resistor R9, a collector of the twenty-first transistor Q21 is connected to a collector of the twenty-fourth transistor Q24 for outputting the driving signal, and an emitter of the twenty-fourth transistor Q24 is grounded;
an emitter of the twenty-second transistor Q22 is connected with a first end of the tenth resistor R10, a base electrode of the twenty-second transistor Q22 is connected with a second end of the tenth resistor R10, a collector of the twenty-second transistor Q22 is connected with a collector of the twenty-third transistor Q23 for outputting the driving signal, and an emitter of the twenty-third transistor Q23 is grounded;
The first end of the eleventh resistor R11 is connected with the base electrode of the twenty-fifth transistor Q25 and is used for receiving the modulation control signal, the second end of the eleventh resistor R11 is connected with the base electrode of the twenty-third transistor Q23, the collector electrode of the twenty-fifth transistor Q25 is connected with the second end of the ninth resistor R9, and the emitter electrode of the twenty-fifth transistor Q25 is grounded;
the first end of the twelfth resistor R12 is connected with the base electrode of the twenty-fourth transistor Q24, the second end of the twelfth resistor R12 is connected with the base electrode of the twenty-sixth transistor Q26 and used for receiving the inverted signal of the modulation control signal, the collector electrode of the twenty-sixth transistor Q26 is connected with the second end of the tenth resistor R10, and the emitter electrode of the twenty-sixth transistor Q26 is grounded.
The VREG signal output from the level shifter 24 is transmitted to the driver circuit 25 as a power supply for the driver circuit. In the drive circuit 25, the PWM signal is a modulation control signal PWM for providing the frequency input signal to the speaker. The driving circuit 25 outputs driving signals BUZZ _a and BUZZ _b for driving the speaker based on the modulation control signal. Adjusting the frequency of the PWM signal may cause the speaker to emit different tones.
In one example, in order to provide an inverse signal of the modulation control signal, fig. 15 is a schematic diagram of another structure of the driving circuit provided in the first embodiment of the present application, where the driving circuit 25 further includes an inverter;
the input of the inverter is connected to the modulation control signal and the output of the inverter is connected to the base of the twenty-sixth transistor Q26.
In the passive buzzer control integrated circuit provided by the embodiment, the enabling circuit is used for outputting charging current and starting current according to the enabling signal, the biasing circuit is used for outputting discharging current based on the starting current, the charging and discharging circuit is used for outputting initial voltage based on the charging current and the discharging current, the level conversion circuit is used for outputting power supply voltage after performing voltage transformation processing on the initial voltage, and the driving circuit is used for outputting driving signals to the loudspeaker based on the power supply voltage and the modulation control signal so as to drive the loudspeaker to work. The scheme provided by the application adopts the design thought of the integrated circuit, and the music passive buzzer control circuit achieves the integration effect, so that the PCB area is reduced, and the restriction of discrete device factors is eliminated.