Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms referred to in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are merely directions referring to the attached drawings, and thus, directional terms are used for better, more clear description and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context. It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprises," "comprising," "includes," "including," "may be" or "including" as used in this application mean the presence of the corresponding function, operation, element, etc. disclosed, but not limited to other one or more additional functions, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. It will also be understood that the meaning of "at least one" as described herein is one and more, such as one, two or three, etc., and the meaning of "a plurality" is at least two, such as two or three, etc., unless specifically defined otherwise. The terms "step 1", "step 2", and the like in the description and claims of the present application and in the drawings, are used for distinguishing between different objects and not for describing a particular sequential order.
In the field of display technology, a display device may generally include a display panel mounted to a light emitting side of a backlight assembly for providing backlight to the display panel to adjust the display panel to display different pictures. In a thin film transistor liquid crystal display (Thin Film Transistor-Liquid Crystal Display, TFT-LCD), a common electrode, a pixel electrode, a data line and liquid crystal molecules are disposed in the backlight assembly, wherein the common electrode voltage is a reference voltage, and changing the data signal of the data line causes the pixel electrode to release capacitance in different degrees, so that electric fields of different magnitudes are formed between the common electrode and the pixel electrode, and the electric fields of different magnitudes control the liquid crystal molecules in the backlight assembly to deflect in different degrees, so that the display panel displays different gray-scale pictures.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device according to an embodiment of the disclosure. As shown in fig. 1, the display device 100 provided in this embodiment of the present application may at least include a display module 10, a power module 20 and a supporting frame 30, wherein the display module 10 is fixed on the supporting frame 30, and the power module 20 is disposed on the back of the display module 10, that is, on the non-display surface of the display module 10, that is, on the side of the display module 10 opposite to the user. The display module 10 is configured to display an image, the power module 20 is electrically connected to the display module 10, and is configured to provide a power supply voltage for displaying the image on the display module 10, and the support frame 30 provides support and protection for the display module 10 and the power module 20.
It will be appreciated that the display module 10 further has a display surface disposed opposite to the non-display surface, i.e. the front surface of the display module 10, i.e. the side of the display module 10 facing the user. The display surface is for facing a user using the display device 100 to display an image.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a structure of the display module 10 in the display device 100 shown in fig. 1. In this embodiment, the display Module 10 may at least include a display panel 13 and a Backlight Module (BM) 17, where the display panel 13 is disposed on a light emitting side of the Backlight Module 17, the Backlight Module 17 is configured to provide light for display to the display panel 13, and the display panel 13 emits corresponding light according to image data to be displayed to perform image display.
In the exemplary embodiment of the present application, the display module 10 may further include other elements or components, such as a signal processor module, a signal sensing module, and the like.
AS shown in fig. 2, the display panel 13 at least includes an Array Substrate (AS) 131, a color film Substrate 133, and a liquid crystal layer 132 interposed between the Array Substrate 131 and the color film Substrate 133. A corresponding electric field is generated between the array substrate 131 and the color film substrate 133 according to the image data to be displayed, so as to control the liquid crystal molecules in the liquid crystal layer 132 to deflect by a corresponding angle to emit light with a corresponding brightness, so as to execute image display. In this embodiment, the display panel 13 may be a Micro-LED display panel, an OLED display panel, a Mini-LED display panel, or the like, which adopts a passive addressing (PM) driving mode.
Referring to fig. 3, fig. 3 is a schematic circuit diagram illustrating a driving circuit 11 of the display module 10 in the display device 100 shown in fig. 1. In this embodiment, the display module 10 further includes a driving circuit 11, where the driving circuit 11 may be disposed in a peripheral area of the display panel 13, and the driving circuit 11 is electrically connected to the display panel 13 and is configured to supply power to the display panel 13 and provide driving signals. The driving circuit 11 is electrically connected with the backlight module 17, and the driving circuit 11 and the backlight module 17 cooperate to enable the display panel 13 to display images.
In the embodiment of the present application, the driving circuit 11 may include at least one signal control unit 40, a switching unit 50, a pixel array unit 60, and a charge discharging unit 70. Each signal control unit comprises an output signal end and a plurality of scanning input ends, the scanning input ends receive scanning signals, and the signal control units output control signals from the output signal ends according to the scanning signals.
The switch unit comprises a switch input end, a plurality of first switch output ends and a plurality of second switch output ends, wherein the switch input end is electrically connected with the output signal end and receives the control signals.
The pixel array unit comprises a plurality of scanning signal input ends and a plurality of charge output ends, wherein the plurality of scanning signal input ends are electrically connected to the plurality of first switch output ends and the plurality of second switch output ends at the same time, and the first switch output ends or the second switch output ends are selectively conducted with the scanning signal input ends according to the control signals, so that the scanning signals are selectively transmitted to the pixel array unit.
The charge discharging unit includes a plurality of charge discharging terminals, each of which is electrically connected to each of the charge outputting terminals, and the charge discharging unit discharges at least part of charges of parasitic capacitances generated by the pixel array unit.
In order to clearly illustrate the port number relationship of each unit, the number of each port and each component, for example, k scan inputs, n scan signal inputs, k-1 second transistors, etc., will be set in the following, and the technical solution of the present application will be further described. Wherein k is an integer greater than 1 and less than or equal to n, n is an integer greater than or equal to 2, and the number of the integers is the same as the number of the integers which are 'a plurality' and the number of the integers which are 'a plurality', so the limitation of the number of k or n does not form a limitation on the technical scheme, and only the technical scheme is clearer.
In the present embodiment, each of the signal control units 40 includes k scan inputs 42 and an output signal 44.k scan inputs 42 receive k scan signals, i.e., each scan input 42 receives a corresponding scan signal. The signal control unit 40 outputs control signals at a first potential or a second potential from the output signal terminal 44 according to k scan signals. It will be appreciated that the scan input 42 may receive the scan signal with a scan drive circuit or a row drive circuit.
Each of the switching units 50 comprises a switching input 51, k first switching outputs 52 and k second switching outputs 53. The switch input terminal 51 is electrically connected to the output signal terminal 44.
The pixel array unit 60 includes n scan signal inputs 61 and n charge outputs 63. The charge output terminal 63 is electrically connected to the charge discharging unit 70. Wherein k of said scanning signal inputs 61 are electrically connected to k of said first switch outputs 52 and k of said second switch outputs 53 simultaneously. The switching unit 50 selectively turns on the scan signal input terminal 61 and the first switching output terminal 52 or the second switching output terminal 53 according to the control signal. Further, the scan signal input terminal 61 is selectively turned on to transmit a corresponding scan signal to the pixel array unit 60 through the scan signal input terminal 61. The scan signal is generated for other circuit structures of the driving circuit 11 and can be transmitted to the scan signal input terminal 61.
The charge discharging unit 70 includes n charge discharging terminals 73, each of the charge discharging terminals 73 is electrically connected to each of the charge outputting terminals 63, and the charge discharging unit 70 is configured to discharge a part of the parasitic capacitance generated by the pixel array unit 60. Specifically, each of the charge discharging terminals 73 is configured to guide discharging of the charge of the parasitic capacitance generated by the corresponding scan line.
In the embodiment of the present application, k is an integer greater than 1 and equal to or less than n, and n is an integer greater than or equal to 2. It is understood that the signal control unit 40 and the switching unit 50 may adjust only a portion of the scan signal input terminals 61 of the pixel array unit 60 to selectively receive the scan signal. For example, the scan lines which may affect each other may be adjusted by the signal control unit 40 and the switching unit 50 according to the actual situation.
In this embodiment, the signal control unit 40 and the switching unit 50 are added to the driving circuit 11, so that the transmission of the scanning signal to the light emitting unit 65 of the pixel array unit 60 through the scanning signal input terminal 61 is stopped during the time of switching the scanning line. Thus, the problem that the parasitic capacitance of the pixel array unit 60 increases during the switching scan line time, which results in that the charge releasing unit 70 cannot fully release the charge on the parasitic capacitance during the interval time, thereby causing abnormal light emission of the pixel array unit 60 can be effectively avoided. Therefore, the driving accuracy of the driving circuit 11 is effectively improved, so that the afterglow phenomenon is eliminated, and the display effect of the display module 10 is ensured.
Referring to fig. 4, fig. 4 is a schematic circuit diagram illustrating a specific circuit configuration of the driving circuit 11 according to the first embodiment shown in fig. 3. In the embodiment of the present application, the pixel array unit 60 includes n Scan lines (Scan lines) S1 to Sn disposed in a grid shape and extending along the first direction F1, and m Data lines (Data lines) D1 to Dm extending along the second direction F2. The first direction F1 and the second direction F2 are perpendicular to each other, and the scan lines S1 to Sn, the data lines D1 to Dm, and the scan lines S1 to Sn and the data lines D1 to Dm are insulated from each other. That is, the plurality of scan lines S1 to Sn are arranged at intervals along the second direction F2 and are insulated from each other, the plurality of data lines D1 to Dm are arranged at intervals along the first direction F1 and are insulated from each other, and the plurality of scan lines S1 to Sn are insulated from the plurality of data lines D1 to Dm. Wherein each of the scan lines is for transmitting the scan signal to the light emitting unit 65 through the scan signal input terminal 61. Wherein m is a positive integer.
Light emitting units 65 are provided at intersections of the plurality of scan lines S1 to Sn and the data lines D1 to Dm, respectively. Specifically, the light emitting units 65 are disposed between any two adjacent scan lines and any two adjacent data lines, the light emitting units 65 located in the same column are all electrically connected to the same data line, and the light emitting units 65 located in the same row are all electrically connected to the same scan line. In this embodiment, a plurality of the light emitting units 65 are distributed in an array. In this embodiment of the present application, each of the data lines is electrically connected to a data signal input terminal, and each of the scan lines is electrically connected to a scan signal input terminal.
As shown in fig. 4, in the embodiment of the present application, the pixel array unit 60 includes m data signal input terminals 62, n scan signal input terminals 61, and n×m light emitting units 65, each of the scan signal input terminals 61 is electrically connected to a first electrode of the m light emitting units 65, each of the data signal input terminals 62 is electrically connected to a second electrode of the n light emitting units 65, and the scan signals are transmitted to the light emitting units through the scan signal input terminals to control the on and off of the light emitting units. That is, each of the scan signal input terminals 61 is electrically connected to the first poles of the m light emitting cells 65 corresponding to one row, and each of the data signal input terminals 62 is electrically connected to the second poles of the n light emitting cells 65 corresponding to one column. That is, the first and second poles of each of the light emitting units 65 are electrically connected to the scan signal input terminal 61 and the data signal input terminal 62, respectively.
In the exemplary embodiment of the present application, the first pole of the light emitting unit 65 may be an anode, and the second pole of the light emitting unit 65 may be a cathode.
Referring to fig. 5 and fig. 6 together, fig. 5 is a schematic circuit diagram of a driving circuit 12 of the second embodiment shown in fig. 3, and fig. 6 is a schematic circuit diagram of a driving circuit 14 of the third embodiment shown in fig. 3.
In this embodiment, each of the signal control units 40 may be an or circuit, where the or circuit includes k scan inputs 42 and output signal inputs 44, and k scan inputs 42 receive k scan signals. The signal control unit 40 outputs a control signal having a first potential or a second potential from the output signal terminal 44 according to the potential conditions of the received k scan signals. Wherein k is a positive integer greater than 1 and less than or equal to n.
The scan signal may be at a first potential or a second potential. The scanning signals which need to be transmitted when the scanning lines perform line scanning are at a first potential, and the scanning signals corresponding to the other scanning lines which do not perform line scanning are at a second potential. The first potential may be a high potential and the second potential may be a low potential. Specifically, in the signal control unit 40, if the scan signals are all at the second potential, the output signal terminal 44 outputs a control signal having the second potential to the switching unit 50.
If at least one of the scan signals is at the first potential, the output signal terminal 44 outputs a control signal having the first potential to the switching unit 50.
As shown in fig. 5, in other embodiments of the present application, the number of the signal control units 40 may be 1, 2, 3 or other numbers, which is not particularly limited in the present application. It will be appreciated that the number of the k scan lines for selectively transmitting the scan signal, which are controlled by the signal control unit 40, may be determined according to the influence of a specific driving circuit.
For example, if the scan lines S1 and S2 are susceptible to each other, the signal control unit 40 may be provided between the scan lines S1 and S2, and the number of the adjusted scan lines k=2.
If there is an influence between the scan line Sn and the scan line Sn-1, the signal control unit 40 may be provided between the scan line Sn and the scan line Sn-1, and the number of the adjusted scan lines k=2.
If the influence is easily generated between the scan lines S1 and S2 and between the scan lines Sn and Sn-1, one signal control unit 40 may be disposed between the scan lines S1 and S2 and between the scan lines Sn and Sn-1, respectively, that is, one signal control unit 40 is disposed as a group of the scan lines S1 and S2, another signal control unit 40 is disposed as a group of the scan lines Sn and Sn-1, and at this time, the number k=2 of each group of the scan lines being adjusted. One of the signal control units 40 may also be provided between the scan line S1, the scan line S2, the scan line Sn, and the scan line Sn-1, where k=4.
Further, the transmission of the scanning signals of the plurality of scanning lines which may affect each other is adjusted in a targeted manner.
In the embodiment of the present application, the switching unit 50 includes a switching input terminal 51, k first switching output terminals 52, and k second switching output terminals 53. The switch input 51 is electrically connected to the output signal 44, the switch input 51 receiving a control signal at a first potential or a second potential from the output signal 44. k first switch output terminals 52 are electrically connected to k scan signal input terminals 61, and k second switch output terminals 53 are electrically connected to k scan signal input terminals 61.
Specifically, when the switch input terminal 51 receives the control signal at the first potential, the k first switch output terminals 52 are electrically connected to the k scan signal input terminals 61, and at this time, the k scan signal input terminals 61 receive the k scan signals, and the k scan signals scan the plurality of light emitting units 65 of the corresponding row.
When the switch input terminal 51 receives the control signal at the second potential, the k second switch output terminals 53 are electrically connected to the k scan signal input terminals 61, and at this time, the k scan signal input terminals 61 are electrically connected, i.e. the k scan lines are shorted, and the k scan signal input terminals 61 stop receiving the k scan signals, i.e. the k scan lines corresponding to the k scan signal input terminals 61 stop charging.
It will be appreciated that the output signal terminal 44 outputs the control signal at the second potential to the switch input terminal 51, indicating that it is time to switch scan lines at this time. By electrically conducting the k scan signal input terminals 61, the corresponding scan line is not charged continuously in the time of switching the scan line, and the parasitic capacitance on the scan line is not increased continuously, which is beneficial to improving the efficiency of discharging the charge on the parasitic capacitance in the time of switching the scan line, and effectively avoiding the phenomenon of afterglow generated by abnormal light emission of the light emitting unit 65 due to the influence between the scan lines.
It will be appreciated that k scan lines controlled to selectively transmit the scan signals are controlled by one signal control unit 40, and k-1 second transistors 57 are electrically connected between k scan signal input terminals 61. Further, k of the scan signal inputs 61 are shorted by k-1 of the second transistors 57 during the switching row scan interval. In the driving circuit, a plurality of the signal control units 40 may be included in combination with the switching unit 50 for controlling a plurality of scan lines to selectively transmit a plurality of scan signals. Each of the signal control units 40 is combined with the switching unit 50 to control k scan lines to selectively transmit k scan signals.
In the present embodiment, the switching unit 50 includes k first transistors 56 and k-1 second transistors 57. Specifically, each of the first transistors 56 includes a control terminal, a first terminal, and a second terminal, and the control terminal of the first transistor 56 is electrically connected to the switch input terminal 51, for receiving the control signal at the first potential or the second potential, and the control signal may control the first transistor 56 to be in an on or off state. A first terminal of the first transistor 56 is for receiving the scan signal. A second terminal of the first transistor 56 is correspondingly electrically connected to the first switch output 52.
When the control signal is at the first potential, the control terminal of the first transistor 56 receives the control signal at the first potential, and the first transistor 56 is in a conductive state. The first and second terminals of the first transistor 56 are electrically conductive. Further, the scan signal input terminal 61 is turned on with the second terminal of the first transistor 56, and the scan signal input terminal 61 receives the scan signal.
When the control signal is at the second potential, the control terminal of the first transistor 56 receives the control signal having the second potential, and the first transistor 56 is in an off state. The first and second terminals of the first transistor 56 are electrically off. Further, the scan signal input terminal 61 is electrically disconnected from the second terminal of the first transistor 56, and the scan signal input terminal 61 cannot receive the scan signal, so that the scan line does not continue to generate parasitic capacitance.
Wherein the first potential is a high potential and the second potential is a low potential. This is not particularly limited in this application.
Each of the second transistors 57 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second transistor 57 is electrically connected to the switch input terminal 51, i.e. the control terminal of the first transistor 56 and the control terminal of the second transistor 57 are both electrically connected to the switch input terminal 51. The control terminal of the second transistor 57 is configured to receive a control signal at the first potential or the second potential, where the control signal may control the second transistor 57 to be in an on or off state.
The first and second terminals of each of the second transistors 57 are electrically connected to the adjacent two of the second switch output terminals 53, respectively. Specifically, the first terminal of the ith second transistor 57 is electrically connected to the ith second switch output terminal 53, and the second terminal of the ith second transistor 57 is electrically connected to the i+1 th second switch output terminal 53. Wherein i is an integer of 1 or more and k or less. For example, a first terminal of the second transistor 57 of 1 st is electrically connected to the second switch output 53 of 1 st, and a second terminal of the second transistor 57 of 1 st is electrically connected to the second switch output 53 of 2 nd; the first terminal of the second transistor 57 of fig. 2 is electrically connected to the second switch output 53 of fig. 2, the second terminal of the second transistor 57 of fig. 2 is electrically connected to the second switch output 53 of fig. 3, and so on. Where i is an integer greater than 1 and less than k.
When the control signal is at the first potential (i.e., when high), the control terminal of the second transistor 57 receives the control signal at the first potential, and the second transistor 57 is in an off state.
When the control signal is at the second potential (i.e., at a low potential), the control terminal of the second transistor 57 receives the control signal at the second potential, and the second transistor 57 is in an on state. The first and second terminals of the ith second transistor 57 are electrically conductive, so that the ith second switch output 53 is electrically conductive with the (i+1) th second switch output 53. And k scan signal input terminals 61 are electrically connected, and k scan lines are short-circuited, so that the discharge rate of the charge release unit 70 is multiplied, and the problem of afterglow abnormality caused by charge accumulation on parasitic capacitance is effectively avoided.
In the embodiment of the present application, when at least one of the k scan signals has the first potential, the k scan input terminals 42 receive the k scan signals. Since the output signal terminal 44 of the signal control unit 40 outputs the control signal at the first potential when at least one of the k scan signals received by the scan input terminals 42 is at the first potential. The control signal at the first potential is transmitted to the switching unit 50, the control terminal of the first transistor 56 receives the control signal at the first potential, the first transistor 56 is in a conductive state, the first terminal and the second terminal of the first transistor 56 are electrically conductive, and the scan signal is transmitted from the scan signal input terminal 61 to the pixel array unit 60. At this time, when the second transistor 57 is turned off, each scanning line independently outputs a waveform required for the own line, and the short-circuit function of each scanning line is disabled.
When k scan signals are at the second potential, k scan inputs 42 receive k scan signals at the second potential. Since the output signal terminal 44 of the signal control unit 40 outputs the control signal having the second potential when the scan signals received by the k scan input terminals 42 are all at the second potential. The control signal with the second potential is transmitted to the switch unit 50, the control signal at the second potential controls the k second switch output terminals 53 to be electrically conducted, that is, the k Scan signal input terminals 61 to be electrically conducted, and the Scan signal cannot be transmitted to the corresponding Scan line, that is, the Scan line cannot continuously receive the residual Scan signal to generate parasitic capacitance, so that each Scan independently outputs the waveform function required by the Scan, and the Scan lines are short-circuited.
In the embodiment of the present application, the first transistor 56 may be an N-Metal-Oxide-Semiconductor (NMOS) transistor, and the second transistor 57 may be a P-Metal-Oxide-Semiconductor (PMOS) transistor.
In the embodiment of the present application, the charge discharging unit 70 may include a plurality of capacitors 71. In the embodiment of the present application, the number of the capacitors 71 is n. Wherein one end of each of the capacitors 71 is electrically connected to the corresponding charge discharging terminal 73, and the other end of each of the capacitors is electrically connected to the ground GND. The capacitor 71 is used to discharge the charge on the parasitic capacitance generated during the row driving scanning of the corresponding scanning line.
In this embodiment, by adding the signal control unit 40 and the switch unit 50, k scan signal input terminals 61 are controlled to stop receiving k scan signals in the time of line scan switching, and k scan lines are shorted at the same time, so that parasitic capacitance will not increase continuously in the switching time. Further, the efficiency of the capacitor 71 to discharge the charge on the parasitic capacitor is effectively improved. Specifically, when k=4, the efficiency of the capacitor 71 to release parasitic capacitance will be improved by a factor of 4.
In this embodiment of the present application, when the driving circuit performs a line scan, a scan signal corresponding to a scan line scanned by the line is at a first potential, and in a time of switching the scan line, the potential on the scan line is switched from the first potential to a second potential. At this time, the signals of all the scan lines are at the second potential, but parasitic capacitance is generated due to the charge residue of the first potential on the scan lines during the scan. In the embodiment of the present application, in the time of switching the scan lines, by adding the signal control unit 40 and the switch unit 50, the scan lines that may affect each other are disconnected by using the characteristics that the scan signals have the second potential in the switching time, so that the problem that the parasitic capacitance is continuously increased due to the fact that the residual charges continuously charge the scan lines in the time of switching the scan lines is avoided, and the accuracy of the driving circuit to drive the light emitting unit 65 to emit light is effectively improved. In addition, by setting the switch unit 50, the scan lines which may be mutually affected are shorted by utilizing the characteristic that the switching time scan signals have the second potential, so that the charge release rate of the charge release unit 70 is multiplied, and the problem of afterglow abnormality caused by slower charge release on the parasitic capacitance is effectively avoided.
An exemplary circuit configuration of the driving circuit will be described below by taking specific circuit configuration diagrams of different embodiments of the driving circuit shown in fig. 4, 5 and 6 as an example.
As shown in fig. 4, in one embodiment of the present application, the driving circuit 11 includes 1 signal control unit 40 and 1 switching unit 50 for controlling 4 scan lines to selectively receive the scan signals. The 4 controlled scanning lines may be the scanning line S1, the scanning line S2, the scanning line Sn-1, and the scanning line Sn illustrated in the drawing, which is not particularly limited in this application.
At this time, the signal control unit 40 includes 4 scan input terminals 42,4 scan input terminals 42 that receive 4 scan signals along scan lines S1, S2, sn-1 and Sn. The switching unit 50 includes four first transistors 56 and three second transistors 57.
When at least one of the 4 scan signals is at the first potential, the output signal terminal 44 outputs a control signal at the first potential to the switching unit 50. The switch input end 51 is electrically connected to 4 of the first switch output ends 52, the scan signal input end 61 is electrically connected to 4 of the first switch output ends 52, and the scan signal is transmitted to the corresponding 4 rows of the pixel array unit 60, so as to further control the plurality of light emitting units 65 corresponding to the 4 rows.
When the 4 scan signals are at the second potential, the output signal terminal 44 outputs the control signal at the second potential to the switching unit 50. In the switch unit 50, the switch input end 51 is electrically connected to the 4 second switch output ends 53, and the 4 scan signal input ends 61 are electrically connected, i.e. the 4 scan lines are short-circuited, the scan signals are stopped from being transmitted to the corresponding 4 rows of the pixel array unit 60, further, the charge discharging efficiency of the charge discharging unit 70 is correspondingly improved by 4 times, the charge discharging efficiency of the parasitic capacitor is effectively improved, and the phenomenon that the parasitic capacitor is not timely and sufficiently discharged to cause afterglow is abnormal due to the fact that the parasitic capacitor is not timely discharged is eliminated.
As shown in fig. 5, in one embodiment of the present application, the driving circuit 12 includes 1 signal control unit 40 and 1 switching unit 50 for controlling 2 scan lines to selectively receive the scan signals. The 2 controlled scanning lines may be the scanning line S1 and the scanning line Sn illustrated in the drawing, which is not particularly limited in this application.
At this time, the signal control unit 40 includes 2 scan inputs 42,2, and the scan inputs 42 receive 2 scan signals along the scan lines S1 and Sn. The switching unit 50 includes 2 first transistors 56 and 1 second transistor 57.
When at least one of the 2 scan signals is at the first potential, the output signal terminal 44 outputs a control signal at the first potential to the switching unit 50. The switch input end 51 is electrically connected to 2 of the first switch output ends 52, 2 of the first switch output ends 52 are electrically connected to 2 of the scan signal input ends 61, and the scan signal is transmitted to the corresponding 2 rows of the pixel array unit 60, so that the plurality of light emitting units 65 corresponding to 2 rows can be further controlled.
When the 2 scan signals are at the second potential, the output signal terminal 44 outputs the control signal at the second potential to the switching unit 50. In the switch unit 50, the switch input end 51 is electrically connected to 2 second switch output ends 53, and 2 scan signal input ends 61 are electrically connected, i.e. 2 scan lines are short-circuited, the scan signals are stopped from being transmitted to the corresponding 2 rows of the pixel array unit 60, further, the charge discharging efficiency of the charge discharging unit 70 is correspondingly improved by 2 times, the charge discharging efficiency of the parasitic capacitor is effectively improved, and the phenomenon that the parasitic capacitor is abnormal due to the fact that the charge is not discharged timely enough is eliminated, so that afterglow is caused is eliminated.
As shown in fig. 6, in one embodiment of the present application, the driving circuit 14 includes 2 signal control units 40 and 2 switch units 50, where each signal control unit 40 and each switch unit 50 are combined to control 2 scan lines to selectively receive the scan signals. I.e. 4 scan lines in total. The 4 controlled scanning lines may be the scanning line S1, the scanning line S2, the scanning line Sn-1, and the scanning line Sn-2 illustrated in the drawing, which is not particularly limited in this application.
At this time, each of the signal control units 40 includes 2 of the scan input terminals 42, and one of the signal control units 40 receives 2 scan signals along the scan lines S1 and S2. The switching unit 50 used in conjunction with the signal control unit 40 includes 2 first transistors 56 and 1 second transistor 57.
The other signal control unit 40 receives two scan signals along the scan line Sn-1 and the scan line Sn. The switching unit 50 used in conjunction with the signal control unit 40 includes 2 first transistors 56 and 1 second transistor 57.
When at least one of the 2 scan signals is at the first potential, the output signal terminal 44 outputs a control signal at the first potential to the switching unit 50. In the switch unit 50, the switch input end 51 is electrically connected to 2 first switch output ends 52, 2 first switch output ends 52 are electrically connected to 2 scan signal input ends 61, and the scan signal is transmitted to the corresponding 2 rows of the pixel array unit 60, so that a plurality of light emitting units 65 corresponding to 2 rows can be further controlled. When the 2 scan signals are at the second potential, the output signal terminal 44 outputs the control signal at the second potential to the switching unit 50. In the switch unit 50, the switch input end 51 is electrically connected to 2 second switch output ends 53, and 2 scan signal input ends 61 are electrically connected, i.e. two scan lines are short-circuited, the scan signals are stopped from being transmitted to two corresponding rows of the pixel array unit 60, further, the charge discharging efficiency of the charge discharging unit 70 is correspondingly improved by 2 times, the charge discharging efficiency of the parasitic capacitor is effectively improved, and the phenomenon that the parasitic capacitor is abnormal due to residual afterglow caused by that the charge is not discharged timely enough is eliminated.
Based on the same inventive concept, the present application further provides a display module 10, where the display module 10 includes the above driving circuit and a display panel 13, the driving circuit is electrically connected to the display panel 13, and the driving circuit is used to drive the display panel 13 to display different pictures.
Based on the same inventive concept, the present application further provides a display device 100, where the display device 100 includes a display module 10 and a power module 20, the power module 20 is disposed on a non-display surface of the display module 10, and the power module 20 is configured to provide a power supply voltage for performing image display on the display module 10.
It is understood that the display device 100 provided in the embodiments of the present application may be any product or component having a display function, such as a display screen of a notebook computer, a liquid crystal display, a liquid crystal television, a mobile phone, a tablet computer, and the like.
In one embodiment, the display device 100 further includes other necessary components and components such as a high-voltage board and a key control board, which can be correspondingly supplemented by those skilled in the art according to the specific type and actual function of the display device 100, and will not be described herein.
It will be appreciated that the display apparatus 100 may also be used in electronic devices that include functionality such as personal digital assistants (Personal Digital Assistant, PDAs) and/or music players, such as cell phones, tablet computers, wearable electronic devices with wireless communication functionality (e.g., smart watches), etc. The electronic device may also be other electronic means, such as a Laptop computer (Laptop) or the like having a touch sensitive surface, e.g. a touch panel.
In summary, in the driving circuit, the display module 10 and the display device 100 provided in the present application, the signal control unit 40 and the switch unit 50 are provided to selectively control k scan signal input ends 61 to receive or stop receiving the scan signal, so as to effectively control the driving circuit to normally transmit the scan signal to the pixel array unit 60 during the row scanning, and stop transmitting the scan signal to the pixel array unit 60 during the row scanning switching time, thereby avoiding the parasitic capacitance generated by the scan signal charges remaining during the row scanning switching time, effectively avoiding the problem that the parasitic capacitance of the switching time increases continuously, aggravates the discharge workload of the charge release unit 70, and the problem of the abnormal afterglow caused by the insufficient discharge capability of the charge release unit 70. In addition, the signal control unit 40 and the switching unit 50 cooperate to control the shorting of k scan lines at the switching time, thereby improving the discharging rate of the charges on the capacitor 71 electrically connected to the corresponding scan line. Specifically, when the k scan lines are shorted, the charge drain rate on the capacitor 71 corresponding to the scan line is increased by k times as compared with the case where the capacitor is not shorted. The problem of afterglow abnormality caused by unclean charge discharge or insufficient timely release of parasitic capacitance is greatly reduced, thereby effectively improving the driving accuracy of the driving circuit and ensuring the display effect of the display module 10.
All possible combinations of the technical features in the above embodiments are described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It is to be understood that the above examples represent only a few embodiments of the present application, which are described in more detail and detail, but are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.