CN115116871A - Bump package structure and preparation method of bump package structure - Google Patents
Bump package structure and preparation method of bump package structureDownload PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H—ELECTRICITY
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
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Abstract
Description
Translated fromChinese技术领域technical field
本发明涉及半导体封装技术领域，具体而言，涉及一种凸块封装结构和凸块封装结构的制备方法。The present invention relates to the technical field of semiconductor packaging, and in particular, to a bump packaging structure and a preparation method of the bump packaging structure.
背景技术Background technique
随着半导体行业的快速发展，倒装封装结构广泛应用于半导体行业中，倒装芯片封装利用凸块进行芯片与基板之间的电性连接。凸块包括了铜柱、金属层(UBM：under bumpmetalization)、保护层(聚酰亚胺Polyimide)，锡帽(Sn Cap)，在制作金属层UBM后，需要针对多余的金属层进行蚀刻去除，由于聚酰亚胺Polyimide材质极其容易吸水，金属柱底部UBM侧壁蚀刻液残留，导致铜柱凸块底部存在过度腐蚀底切开口，进而使得凸块芯片在进可靠性测试时，铜柱凸块容易出现掉落的问题。采用现有技术铜柱凸块底部完全与芯片电极相连，并通常采用平坦化结构，导致铜柱凸块上的应力直接作用在芯片电极上，存在芯片电极裂开问题，其中各金属层之间的接触面积较小，结合力较差。并且其铜柱凸块受电流情况下，由于焦耳热效应,铜柱底部连接处的金属原子同时承受电场和热场的影响，互联界面的电迁移和热迁移会因异常活跃而使其寿命显著降低，造成潜在的失效隐患。With the rapid development of the semiconductor industry, the flip-chip package structure is widely used in the semiconductor industry, and the flip-chip package uses bumps for electrical connection between the chip and the substrate. The bump includes a copper pillar, a metal layer (UBM: under bump metalization), a protective layer (Polyimide), and a tin cap (Sn Cap). After making the metal layer UBM, it is necessary to etch and remove the excess metal layer. Because the polyimide material is extremely easy to absorb water, the etching solution on the sidewall of the UBM at the bottom of the metal pillars remains, resulting in excessive corrosion and undercut openings at the bottom of the copper pillar bumps, which makes the copper pillars protrude when the bump chip is tested for reliability. Blocks are prone to falling problems. The bottom of the copper pillar bump in the prior art is completely connected to the chip electrode, and the planarization structure is usually adopted, so that the stress on the copper pillar bump directly acts on the chip electrode, and the chip electrode is cracked. The contact area is small and the bonding force is poor. And when the copper pillar bump is subjected to current, due to the Joule heating effect, the metal atoms at the bottom of the copper pillar are affected by both electric and thermal fields, and the electromigration and thermal migration of the interconnect interface will be abnormally active and its life will be significantly reduced. , resulting in potential failure hazards.
发明内容SUMMARY OF THE INVENTION
本发明的目的包括，例如，提供了一种凸块封装结构和凸块封装结构的制备方法，其能够避免出现过度腐蚀形成的底切开口，同时结构更加稳定，底部结构结合力更好，且散热、导电性能均较佳，有效缓解了电迁移和热迁移带来的失效隐患。The objects of the present invention include, for example, to provide a bump package structure and a method for manufacturing the bump package structure, which can avoid the occurrence of undercut openings formed by excessive corrosion, and at the same time, the structure is more stable, and the bottom structure has better bonding force, And the heat dissipation and electrical conductivity are good, which effectively alleviates the hidden danger of failure caused by electromigration and thermal migration.
本发明的实施例可以这样实现：Embodiments of the present invention can be implemented as follows:
第一方面，本发明提供一种凸块封装结构，包括：In a first aspect, the present invention provides a bump package structure, comprising:
芯片，所述芯片的正面设置有焊垫；a chip, the front side of the chip is provided with a solder pad;
设置在所述芯片的正面的保护层，所述保护层上设置有与所述焊垫对应的保护开口；a protective layer disposed on the front side of the chip, and a protective opening corresponding to the pad is disposed on the protective layer;
设置在所述保护开口内的基底粘接层；a base adhesive layer disposed in the protective opening;
设置在所述基底粘接层上的导电组合层；a conductive composite layer disposed on the base adhesive layer;
设置在所述导电组合层上的电性凸柱；electrical bumps arranged on the conductive composite layer;
设置在所述电性凸柱上的帽层；a cap layer disposed on the electrical bumps;
其中，所述基底粘接层包括多层石墨烯材料，所述基底粘接层的顶部边缘向外延伸至所述保护层上，并覆盖所述保护开口的边缘，且所述基底粘接层远离所述芯片的一侧表面设置有弧形凹槽，所述导电组合层至少部分容置在所述弧形凹槽内。Wherein, the base adhesive layer includes multiple layers of graphene materials, the top edge of the base adhesive layer extends outward to the protective layer, and covers the edge of the protective opening, and the base adhesive layer An arc-shaped groove is provided on the surface of one side away from the chip, and the conductive composite layer is at least partially accommodated in the arc-shaped groove.
在可选的实施方式中，所述导电组合层包括阻挡层和润湿层，所述阻挡层覆盖在所述基底粘接层上，所述润湿层覆盖在所述阻挡层上。In an optional embodiment, the conductive composite layer includes a barrier layer and a wetting layer, the barrier layer covers the base adhesive layer, and the wetting layer covers the barrier layer.
在可选的实施方式中，所述基底粘接层延伸至所述保护层的部分的厚度H1为4-8μm；所述阻挡层的厚度H2为4-6μm；所述润湿层的厚度H3为2-4μm。In an optional embodiment, the thickness H1 of the portion of the base adhesive layer extending to the protective layer is 4-8 μm; the thickness H2 of the barrier layer is 4-6 μm; the thickness H3 of the wetting layer 2-4 μm.
在可选的实施方式中，所述基底粘接层延伸至所述保护层的部分、所述阻挡层以及所述润湿层的厚度相同。In an optional embodiment, the thickness of the portion of the base adhesive layer extending to the protective layer, the barrier layer and the wetting layer is the same.
在可选的实施方式中，所述基底粘接层延伸至所述保护层的部分的宽度L1为4-8μm，且所述基底粘接层在所述芯片的正面上的投影、所述阻挡层在所述芯片的正面上的投影、所述润湿层在所述芯片的正面上的投影相重叠。In an optional embodiment, the width L1 of the portion of the base adhesive layer extending to the protective layer is 4-8 μm, and the projection of the base adhesive layer on the front surface of the chip, the blocking The projection of the layer on the front side of the chip and the projection of the wetting layer on the front side of the chip overlap.
在可选的实施方式中，所述基底粘接层远离所述芯片的一侧表面至少部分呈内凹弧面，并形成所述弧形凹槽，以使所述阻挡层和所述润湿层均向着靠近所述芯片的方向拱起，并使得所述电性凸柱靠近所述芯片的一侧表面至少部分呈外凸弧面。In an optional embodiment, a surface of the base adhesive layer on one side away from the chip at least partially has a concave arc surface, and the arc-shaped groove is formed, so that the barrier layer and the wetting layer are formed. The layers are all arched toward the direction close to the chip, so that the surface of one side of the electrical bump close to the chip is at least partially convex.
在可选的实施方式中，所述弧形凹槽延伸至所述基底粘接层的边缘，以使所述基底粘接层远离所述芯片的一侧表面呈内凹弧面。In an optional embodiment, the arc-shaped groove extends to the edge of the base adhesive layer, so that the side surface of the base adhesive layer away from the chip is a concave arc surface.
在可选的实施方式中，所述电性凸柱远离所述芯片的一侧还设置有止挡层，所述止挡层设置在所述帽层和所述电性凸柱之间，用于阻挡所述帽层和所述电性凸柱之间的扩散原子。In an optional implementation manner, a stopper layer is further provided on the side of the electrical bumps away from the chip, and the stopper layer is arranged between the cap layer and the electrical bumps. for blocking diffusion atoms between the cap layer and the electrical bump.
在可选的实施方式中，所述电性凸柱远离所述芯片的一侧还设置有导电粘接层，所述导电粘接层设置在所述止挡层和所述电性凸柱之间，且所述导电粘接层为石墨烯层。In an optional embodiment, a conductive adhesive layer is further provided on the side of the electrical bump away from the chip, and the conductive adhesive layer is disposed between the stop layer and the electrical bump and the conductive adhesive layer is a graphene layer.
在可选的实施方式中，所述电性凸柱远离所述芯片的一侧表面至少部分呈内凹弧面，以使所述止挡层和所述导电粘接层均向着靠近所述芯片的方向拱起，并使得所述帽层靠近所述芯片的一侧表面至少部分呈外凸弧面。In an optional implementation manner, a surface of one side of the electrical bump away from the chip is at least partially concave, so that both the stopper layer and the conductive adhesive layer are close to the chip The direction of the cap layer is arched, and the surface of one side of the cap layer close to the chip is at least partially convex.
第二方面，本发明提供一种凸块封装结构的制备方法，用于制备如前述实施方式任一项所述的凸块封装结构，包括：In a second aspect, the present invention provides a method for fabricating a bump package structure for fabricating the bump package structure according to any one of the foregoing embodiments, including:
提供一正面设置有焊垫的芯片；providing a chip with solder pads disposed on the front side;
在所述芯片的正面形成保护层；forming a protective layer on the front side of the chip;
在所述保护层上与所述焊垫对应的位置开槽，以形成保护开口；A groove is formed on the protective layer at a position corresponding to the solder pad to form a protective opening;
在所述保护开口内形成基底粘接层；forming a base adhesive layer in the protective opening;
在所述基底粘接层上形成导电组合层；forming a conductive composite layer on the base adhesive layer;
在所述导电组合层上形成电性凸柱；forming electrical bumps on the conductive composite layer;
在所述电性凸柱上形成帽层；forming a cap layer on the electrical bump;
其中，所述基底粘接层包括多层石墨烯材料，所述基底粘接层的顶部边缘向外延伸至所述保护层上，并覆盖所述保护开口的边缘，且所述基底粘接层远离所述芯片的一侧表面设置有弧形凹槽，所述导电组合层至少部分容置在所述弧形凹槽内。Wherein, the base adhesive layer includes multiple layers of graphene materials, the top edge of the base adhesive layer extends outward to the protective layer, and covers the edge of the protective opening, and the base adhesive layer An arc-shaped groove is provided on the surface of one side away from the chip, and the conductive composite layer is at least partially accommodated in the arc-shaped groove.
本发明实施例的有益效果包括，例如：The beneficial effects of the embodiments of the present invention include, for example:
本发明实施例提供了一种凸块封装结构，通过在芯片的正面设置保护层，并在保护层上设置有保护开口，在保护开口内设置基底粘接层，在基底粘接层上设置导电组合层，同时在导电组合层上依次设置电性凸柱和帽层，其中基底粘接层包括多层石墨烯材料，基底粘接层的顶部边缘向外延伸到保护层上，通过采用多层石墨烯材料，能够增强底部结构的稳定性以及疏水性。而基底粘接层的顶部边缘向外延伸到保护层上并覆盖保护开口的边缘，在进行微蚀刻工艺处理时，无论采用化学蚀刻方式还是等离子蚀刻方式，基底粘接层都可以避免传统微蚀刻工艺去除UBM层时带来的底切问题。并且，石墨烯材料的热膨胀系数CTE仅仅是铜和铝的1/10-1/20，可以更好的避免导电柱底部UBM层变形，能够保护底部的焊垫以及导电柱底部的金属结构。石墨烯材料的导电性能远远高于金属，并且导热性能优越，随着石墨烯体积增大而形成的多层石墨烯结构，其热导率以及导热性进一步提升，大幅提升了其导电性能和散热性能，避免电迁移和热迁移会因异常活跃而使铜柱凸块的寿命显著降低，并造成潜在的失效隐患的问题。同时，利用石墨烯的稳定性，解决传统技术中铜柱会在封装体内引起较大的应力导致脆性材料层损坏的问题，如与铜柱底部芯片焊盘破裂、UBM金属层分层或者降低焊点疲劳寿命，从而保证了结构的稳定性。此外，基底粘接层的表面设置有弧形凹槽，导电组合层部分容置在弧形凹槽内，能够提升导电组合层和基底粘接层之间的接触面积，从而提升二者的结合力，进一步提升结构的稳定性，避免电性凸柱脱落。相较于现有技术，本发明提供的凸块封装结构，能够避免出现过度腐蚀形成的底切开口，同时结构更加稳定，底部结构结合力更好，且散热、导电性能均较佳，有效缓解了电迁移和热迁移带来的失效隐患。An embodiment of the present invention provides a bump package structure. By arranging a protective layer on the front side of the chip, a protective opening is arranged on the protective layer, a base adhesive layer is arranged in the protective opening, and a conductive layer is arranged on the base adhesive layer. Combined layer, and at the same time, electrical convex pillars and cap layers are sequentially arranged on the conductive combined layer, wherein the base adhesive layer comprises a multi-layer graphene material, and the top edge of the base adhesive layer extends outward to the protective layer. The graphene material can enhance the stability and hydrophobicity of the bottom structure. The top edge of the base adhesive layer extends outward to the protective layer and covers the edge of the protective opening. During the micro-etching process, whether chemical etching or plasma etching is used, the base adhesive layer can avoid traditional micro-etching. The undercut problem caused by the process removing the UBM layer. Moreover, the thermal expansion coefficient CTE of graphene material is only 1/10-1/20 of that of copper and aluminum, which can better avoid the deformation of the UBM layer at the bottom of the conductive column, and can protect the bottom pad and the metal structure at the bottom of the conductive column. The electrical conductivity of graphene materials is much higher than that of metals, and the thermal conductivity is superior. The multi-layer graphene structure formed as the volume of graphene increases, its thermal conductivity and thermal conductivity are further improved, and its electrical conductivity and thermal conductivity are greatly improved. Thermal performance to avoid electromigration and thermal migration, which can significantly reduce the life of copper pillar bumps due to abnormal activity, and cause potential failure problems. At the same time, the stability of graphene is used to solve the problem that the copper pillar will cause large stress in the package and cause damage to the brittle material layer in the traditional technology, such as cracking with the chip pad at the bottom of the copper pillar, delamination of the UBM metal layer or reducing the soldering effect. point fatigue life, thus ensuring the stability of the structure. In addition, the surface of the base adhesive layer is provided with an arc-shaped groove, and the conductive composite layer is partially accommodated in the arc-shaped groove, which can increase the contact area between the conductive composite layer and the base adhesive layer, thereby improving the combination of the two. force to further improve the stability of the structure and prevent the electrical bumps from falling off. Compared with the prior art, the bump package structure provided by the present invention can avoid undercut openings formed by excessive corrosion, and at the same time, the structure is more stable, the bonding force of the bottom structure is better, and the heat dissipation and electrical conductivity are both better, and it is effective. It alleviates the hidden danger of failure caused by electromigration and thermal migration.
附图说明Description of drawings
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.
图1为本发明第一实施例提供的凸块封装结构的示意图；FIG. 1 is a schematic diagram of a bump package structure provided by a first embodiment of the present invention;
图2为图1中Ⅱ的局部放大示意图；Fig. 2 is the partial enlarged schematic diagram of II in Fig. 1;
图3至图8为本发明第一实施例提供的凸块封装结构的制备方法的工艺流程图；3 to 8 are process flow diagrams of a method for fabricating a bump package structure according to a first embodiment of the present invention;
图9为本发明第二实施例提供的凸块封装结构的示意图；9 is a schematic diagram of a bump package structure according to a second embodiment of the present invention;
图10为本发明第三实施例提供的凸块封装结构的示意图；10 is a schematic diagram of a bump package structure provided by a third embodiment of the present invention;
图11为图10中Ⅺ的局部放大示意图。FIG. 11 is a partial enlarged schematic view of XI in FIG. 10 .
图标：100-凸块封装结构；110-芯片；120-保护层；121-保护开口；130-基底粘接层；140-导电组合层；141-阻挡层；143-润湿层；150-电性凸柱；160-帽层；170-止挡层；180-导电粘接层。Icon: 100-bump package structure; 110-chip; 120-protective layer; 121-protective opening; 130-substrate adhesive layer; 140-conductive combination layer; 141-barrier layer; 143-wetting layer; 150-electrical 160-cap layer; 170-stop layer; 180-conductive adhesive layer.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.
因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。Thus, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.
在本发明的描述中，需要说明的是，若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings, or It is the orientation or positional relationship that the product of the invention is usually placed in use, only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation , so it should not be construed as a limitation of the present invention.
此外，若出现术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。In addition, where the terms "first", "second" and the like appear, they are only used to differentiate the description, and should not be construed as indicating or implying relative importance.
正如背景技术中所公开的，现有技术中存在以下客观缺点：As disclosed in the background art, the following objective disadvantages exist in the prior art:
1、保护层通常采用聚酰亚胺Polyimide材质，由于聚酰亚胺Polyimide材质极其容易吸水，导致金属柱底部UBM侧壁容易出现蚀刻液残留，进而导致铜柱凸块底部存在过度腐蚀底切开口，凸块芯片在进可靠性测试时，铜柱凸块存在掉落的问题。1. The protective layer is usually made of polyimide polyimide material. Because polyimide polyimide material is extremely easy to absorb water, it is easy to have etchant residue on the sidewall of the UBM at the bottom of the metal pillar, which in turn leads to excessive corrosion at the bottom of the copper pillar bump. Undercut When the bump chip enters the reliability test, the copper pillar bumps have the problem of falling.
2.现有机组中铜柱凸块底部直接完全与芯片电极相连，缓冲能力差，导致铜柱凸块上的应力直接作用在芯片电极上，存在芯片电极裂开问题。2. In the existing unit, the bottom of the copper pillar bump is directly and completely connected to the chip electrode, and the buffering capacity is poor, so that the stress on the copper pillar bump directly acts on the chip electrode, and the chip electrode is cracked.
为了解决上述问题，本发明提供了一种新型的凸块封装结构和凸块封装结构的制备方法，需要说明的是，在不冲突的情况下，本发明的实施例中的特征可以相互结合。In order to solve the above problems, the present invention provides a novel bump package structure and a method for manufacturing the bump package structure. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.
第一实施例first embodiment
参见图1和图2，本实施例提供了一种凸块封装结构100，其能够避免出现过度腐蚀形成的底切开口，同时结构更加稳定，底部结构结合力更好，且散热、导电性能均较佳，有效缓解了电迁移和热迁移带来的失效隐患。Referring to FIG. 1 and FIG. 2 , the present embodiment provides a
本实施例提供的凸块封装结构100，包括芯片110、保护层120、基底粘接层130、导电组合层140、电性凸柱150和帽层160，芯片110的正面设置有焊垫，保护层120设置在芯片110的正面，且保护层120上设置有与焊垫对应的保护开口121，保护开口121的尺寸略小于焊垫的尺寸，从而能够使得焊垫暴露于保护层120。基底粘接层130设置在保护开口121内，并覆盖保护开口121，导电组合层140设置在基底粘接层130上，电性凸柱150设置在导电组合层140上，帽层160设置在电性凸柱150上。其中，基底粘接层130包括多层石墨烯材料，基底粘接层130的顶部边缘向外延伸至保护层120上，并覆盖保护开口121的边缘，且基底粘接层130远离芯片110的一侧表面设置有弧形凹槽，导电组合层140至少部分容置在弧形凹槽内。The
在本实施例中，通过在芯片110的正面设置保护层120，并在保护层120上设置有保护开口121，在保护开口121内设置基底粘接层130，在基底粘接层130上设置导电组合层140，同时在导电组合层140上依次设置电性凸柱150和帽层160，其中基底粘接层130包括多层石墨烯材料，基底粘接层130的顶部边缘向外延伸到保护层120上，通过采用多层石墨烯材料，能够增强底部结构的稳定性以及疏水性。而基底粘接层130的顶部边缘向外延伸到保护层120上并覆盖保护开口121的边缘，在进行微蚀刻工艺处理时，无论采用化学蚀刻方式还是等离子蚀刻方式，基底粘接层130都可以避免传统微蚀刻工艺去除UBM层时带来的底切问题。并且，石墨烯材料的热膨胀系数CTE仅仅是铜和铝的1/10-1/20，可以更好的避免导电柱底部UBM层变形，能够保护底部的焊垫以及导电柱底部的金属结构。石墨烯材料的导电性能远远高于金属，并且导热性能优越，随着石墨烯体积增大而形成的多层石墨烯结构，其热导率以及导热性进一步提升，大幅提升了其导电性能和散热性能，避免电迁移和热迁移会因异常活跃而使铜柱凸块的寿命显著降低，并造成潜在的失效隐患的问题。同时，利用石墨烯的稳定性，解决传统技术中铜柱会在封装体内引起较大的应力导致脆性材料层损坏的问题，如与铜柱底部芯片110焊盘破裂、UBM金属层分层或者降低焊点疲劳寿命，从而保证了结构的稳定性。此外，基底粘接层130的表面设置有弧形凹槽，导电组合层140部分容置在弧形凹槽内，能够提升导电组合层140和基底粘接层130之间的接触面积，从而提升二者的结合力，进一步提升结构的稳定性，避免电性凸柱150脱落。In this embodiment, the
在本实施例中，弧形凹槽的深度小于基底粘接层130的厚度，使得弧形凹槽不会贯通至焊垫，导电组合层140铺设在基底粘接层130上，使得导电组合层140容置在弧形凹槽内，并朝着靠近芯片110的方向形成拱形，能够进一步提升其结构强度。In this embodiment, the depth of the arc-shaped groove is smaller than the thickness of the base
在本实施例中，导电组合层140包括阻挡层141和润湿层143，阻挡层141覆盖在基底粘接层130上，润湿层143覆盖在阻挡层141上。具体地，阻挡层141和润湿层143均采用导电金属材料，例如，阻挡层141可以采用镍、钒、铬中的至少一种材料，润湿层143与导电凸柱均采用铜材料，阻挡层141能够阻挡导电凸柱与底部基底粘接层130之间的原子扩散，润湿层143能够提升导电凸柱底部的浸润性，从而提升结合强度。In this embodiment, the
在本实施例中，基底粘接层130延伸至保护层120的部分的厚度H1为4-8μm；阻挡层141的厚度H2为4-6μm；润湿层143的厚度H3为2-4μm。具体地，基底粘接层130高出保护层120的厚度H1为4-8μm，优选为4μm，能够完全避免蚀刻残留液进入到保护开口121边缘，从而进一步避免底切现象。同时，阻挡层141为等厚层，其厚度为4μm，润湿层143也为等厚层，其厚度为4μm。通过合理设置基底粘接层130、阻挡层141和润湿层143的厚度，能够在保证导电性能的同时，保证连接处具有足够的结构强度。In this embodiment, the thickness H1 of the portion of the base
在本实施例中，基底粘接层130延伸至保护层120的部分、阻挡层141以及润湿层143的厚度相同。即基底粘接层130延伸至保护层120的部分、阻挡层141以及润湿层143的厚度均为4μm，能够保证结构强度和功能特性(如导电性、阻挡性和浸润性)的同时，尽可能地降低整体凸块结构的高度，有利于降低焊接结构的高度。In this embodiment, the portion of the base
在本实施例中，基底粘接层130延伸至保护层120的部分的宽度L1为4-8μm，且基底粘接层130在芯片110的正面上的投影、阻挡层141在芯片110的正面上的投影、润湿层143在芯片110的正面上的投影相重叠。优选地，基底粘接层130延伸至保护层120的部分的宽度L1为6μm，阻挡层141的边缘、润湿层143的边缘以及基底粘接层130的边缘相平齐，从而在制备时可以采用同一掩膜一并蚀刻，简化了工艺步骤。In this embodiment, the width L1 of the portion of the base
在本实施例中，基底粘接层130远离芯片110的一侧表面至少部分呈内凹弧面，并形成弧形凹槽，以使阻挡层141和润湿层143均向着靠近芯片110的方向拱起，并使得电性凸柱150靠近芯片110的一侧表面至少部分呈外凸弧面。具体地，基底粘接层130的边缘保持水平状态，并搭接在保护层120上，基底粘接层130的中心位置下凹形成内凹弧面，从而形成弧形凹槽，能够进一步提升阻挡层141与基底粘接层130之间的接触面积，从而提升结合力。In this embodiment, the side surface of the base
在本实施例中，弧形凹槽的宽度与保护开口121的宽度相同，具体地，基底粘接层130的边缘呈水平状并覆盖在保护层120的表面，从而使得基底粘接层130的边缘平坦化，能够完全覆盖在保护开口121的边缘，以进一步防止底切现象的发生，并且能够更好地实现基底粘接层130延伸至保护层120的部分、阻挡层141以及润湿层143的厚度相同。进一步地，由于阻挡层141和润湿层143均为等厚层，故阻挡层141和润湿层143的中部均向着靠近芯片110的方向拱起，从而增加各层之间的接触面积，以增强结合力。同时阻挡层141和润湿层143的边缘均呈水平状，使得边缘处的基底粘接层130、阻挡层141和润湿层143受力更均匀。In this embodiment, the width of the arc-shaped groove is the same as the width of the
在本实施例中，电性凸柱150远离芯片110的一侧还设置有止挡层170，止挡层170设置在帽层160和电性凸柱150之间，用于阻挡帽层160和电性凸柱150之间的扩散原子。具体地，止挡层170可以是镍、钒、铬中的至少一种，电性凸柱150远离芯片110的端面呈水平状，从而使得止挡层170水平铺设在电性凸柱150的端面，帽层160铺设在止挡层170上。In this embodiment, a
本实施例还提供了一种凸块封装结构100的制备方法，用于制备前述的凸块封装结构100，其中，该制备方法包括以下步骤：The present embodiment also provides a method for manufacturing the
S1：提供一正面设置有焊垫的芯片110。S1: Provide a
参见图3，具体而言，首先提供一正面带有焊垫的芯片110，芯片110内部有布线层，焊垫与布线层电连接。Referring to FIG. 3 , specifically, a
S2：在芯片110的正面形成保护层120。S2 : forming the
参见图4，具体而言，可以在芯片110的正面均匀旋涂液态的保护材料，例如聚酰亚胺，然后再由热盘进行软烤，定型成膜并形成一层保护层120。Referring to FIG. 4 , specifically, a liquid protective material, such as polyimide, can be uniformly spin-coated on the front surface of the
S3：在保护层120上与焊垫对应的位置开槽，以形成保护开口121。S3: A groove is formed on the
参见图5，具体而言，可以在保护层120上通过光罩将保护层120预定开孔的位置遮住，然后通过显影方式利用显影液以喷洒方式进行去除未曝光的区域，漏出铝焊垫开孔位置，然后再次使用烤箱加热将保护层120固化至稳定状态。并利用电浆去残胶机清除保护层120表面的污染物或残留物。当然，此处保护层120也可以是氮化硅材料。Referring to FIG. 5 , specifically, the position of the predetermined opening of the
S4：在保护开口121内形成基底粘接层130。S4: The base
参见图6，具体而言，基底粘接层130包括多层石墨烯材料，基底粘接层130的顶部边缘向外延伸至保护层120上，并覆盖保护开口121的边缘，且基底粘接层130远离芯片110的一侧表面设置有弧形凹槽。6 , specifically, the base
在完成保护开口121的制备后，在保护层120上涂覆石墨烯材料，从而形成多层的石墨烯结构，其中石墨烯材料填充保护开口121并覆盖在保护层120表面的厚度在4-8μm之间，然后再次利用烤箱加热将石墨烯材料加速固化至稳定状态，形成基底粘接层130。然后利用蚀刻工艺，对保护开口121内的石墨烯进行蚀刻，以使基底粘接层130上形成内凹弧面，并形成弧形凹槽。After the preparation of the
S5：在基底粘接层130上形成导电组合层140。S5 : forming the
参见图7，具体而言，在完成弧形凹槽的制备后，可以在内凹弧面上电镀金属形成阻挡层141，阻挡层141的材料可以是镍、钒、铬中的至少一种，厚度在4-6μm之间，然后再次电镀形成润湿层143，润湿层143可以是铜层，厚度为2-4μm。Referring to FIG. 7 , specifically, after the preparation of the arc-shaped grooves is completed, the inner concave arc surface can be electroplated with metal to form a
S6：在导电组合层140上形成电性凸柱150。S6 : forming
参见图8，具体而言，在形成润湿层143后，然后在表面涂布保护胶，然后利用光刻工艺开口出铜柱开口，再次利用电镀工艺在圆弧状的润湿层143上溅射铜层，形成铜柱，即形成了电性凸柱150，电性凸柱150的底部呈弧形凸块状，能够提升其与下部结构之间的结合力。Referring to FIG. 8 , specifically, after the
在形成电芯凸柱后，可以在电性凸柱150上形成止挡层170。After the cell bumps are formed, a
S7：在电性凸柱150上形成帽层160。S7 : forming a
请继续参见图1，具体地，可以利用电镀或植球工艺，在止挡层170上形成焊料层，并在回流后形成帽层160。其中帽层160可以是锡帽层160。Please continue to refer to FIG. 1 , specifically, a solder layer may be formed on the
综上所述，本实施例提供的凸块封装结构100和凸块封装结构100的制备方法，通过在芯片110的正面设置保护层120，并在保护层120上设置有保护开口121，在保护开口121内设置基底粘接层130，在基底粘接层130上设置导电组合层140，同时在导电组合层140上依次设置电性凸柱150和帽层160，其中基底粘接层130包括多层石墨烯材料，基底粘接层130的顶部边缘向外延伸到保护层120上，通过采用多层石墨烯材料，能够增强底部结构的稳定性以及疏水性。而基底粘接层130的顶部边缘向外延伸到保护层120上并覆盖保护开口121的边缘，在进行微蚀刻工艺处理时，无论采用化学蚀刻方式还是等离子蚀刻方式，基底粘接层130都可以避免传统微蚀刻工艺去除UBM层时带来的底切问题。并且，石墨烯材料的热膨胀系数CTE仅仅是铜和铝的1/10-1/20，可以更好的避免导电柱底部UBM层变形，能够保护底部的焊垫以及导电柱底部的金属结构。石墨烯材料的导电性能远远高于金属，并且导热性能优越，随着石墨烯体积增大而形成的多层石墨烯结构，其热导率以及导热性进一步提升，大幅提升了其导电性能和散热性能，避免电迁移和热迁移会因异常活跃而使铜柱凸块的寿命显著降低，并造成潜在的失效隐患的问题。同时，利用石墨烯的稳定性，解决传统技术中铜柱会在封装体内引起较大的应力导致脆性材料层损坏的问题，如与铜柱底部芯片110焊盘破裂、UBM金属层分层或者降低焊点疲劳寿命，从而保证了结构的稳定性。此外，基底粘接层130的表面设置有弧形凹槽，导电组合层140部分容置在弧形凹槽内，能够提升导电组合层140和基底粘接层130之间的接触面积，从而提升二者的结合力，进一步提升结构的稳定性，避免电性凸柱150脱落。To sum up, in the
第二实施例Second Embodiment
参见图9，本实施例提供了一种凸块封装结构100，其基本结构和原理及产生的技术效果和第一实施例相同，为简要描述，本实施例部分未提及之处，可参考第一实施例中相应内容。Referring to FIG. 9 , this embodiment provides a
在本实施例中，电性凸柱150远离芯片110的一侧还设置有止挡层170，止挡层170设置在帽层160和电性凸柱150之间，用于阻挡帽层160和电性凸柱150之间的扩散原子，进一步地，电性凸柱150远离芯片110的一侧还设置有导电粘接层180，导电粘接层180设置在止挡层170和电性凸柱150之间，且导电粘接层180为石墨烯层。In this embodiment, a
需要说明的是，此处导电粘接层180采用石墨烯材料，能够更好地实现散热以及导电。It should be noted that the conductive
在本实施例中，电性凸柱150远离芯片110的一侧表面至少部分呈内凹弧面，以使止挡层170和导电粘接层180均向着靠近芯片110的方向拱起，并使得帽层160靠近芯片110的一侧表面至少部分呈外凸弧面。具体地，电性凸柱150远离芯片110的端面呈内凹弧面，可以通过蚀刻方式形成圆弧形结构，配合下部的弧形凹槽，形成改了双圆弧结构，将电性凸柱150顶端成型为凹槽形状，底部为带有凸起和平坦边缘的结构，从而使得电性凸柱150底部可以起到更好的支撑作用。同时导电粘接层180和止挡层170为等厚层，能够形成向着芯片110方向凸起的拱形结构，提升接触面积并提升结合力。In this embodiment, the side surface of the
本实施例提供的凸块封装结构100，在止挡层170和电性凸柱150之间还设置有石墨烯材料的导电粘接层180，配合下方的基底粘接层130，能够实现双层石墨烯结构，从而实现更好地散热特性和导电特性。并且，采用了圆弧结构，能够提升导电粘接层180与电性凸柱150之间、止挡层170与导电粘接层180之间以及帽层160与止挡层170之间接触面积，从而提升结合力，保证整体的结构强度。同时，止挡层170能够很好地阻止帽层160向下的原子扩散问题。并且，采用了向下凹陷的圆弧结构，使得电性凸柱150远离芯片110的一端能够更好地锁住焊料，防止焊料溢出。同时采用双层圆弧结构，双层圆弧结构的凹陷方向相同，能够实现更好地应力释放，以缓冲结构应力，避免电极裂开。In the
第三实施例Third Embodiment
参见图10和图11，本实施例提供了一种凸块封装结构100，其基本结构和原理及产生的技术效果和第一实施例相同，为简要描述，本实施例部分未提及之处，可参考第一实施例中相应内容。Referring to FIG. 10 and FIG. 11 , this embodiment provides a
在本实施例中，弧形凹槽延伸至基底粘接层130的边缘，以使基底粘接层130远离芯片110的一侧表面呈内凹弧面。具体地，弧形凹槽的宽度大于保护开口121的宽度，从而使得基底粘接层130的边缘不存在平坦结构，内凹弧面直接延伸至基底粘接层130的边缘。In this embodiment, the arc-shaped groove extends to the edge of the base
在本实施例中，阻挡层141和润湿层143也均为等厚层，故阻挡层141和润湿层143的边缘也为形成有平坦结构，阻挡层141和润湿层143整体呈拱形朝向靠近芯片110的方向拱起。In this embodiment, the
在本实施例中，电性凸柱150远离芯片110的一侧还设置有止挡层170，止挡层170设置在帽层160和电性凸柱150之间，用于阻挡帽层160和电性凸柱150之间的扩散原子，进一步地，电性凸柱150远离芯片110的一侧还设置有导电粘接层180，导电粘接层180设置在止挡层170和电性凸柱150之间，且导电粘接层180为石墨烯层。其中，导电粘接层180和止挡层170均为平面结构，即电性凸柱150远离芯片110的端面为平面。In this embodiment, a
在本实施例中，基底粘接层130的边缘厚度H1可以是阻挡层141的厚度H2以及润湿层143的厚度H3之和，即H1＝H2+H3，从而能够防止蚀刻后残留化学药剂收到毛细作用而侧爬至阻挡层141、润湿层143以及电性导电柱。而基底粘接层130为石墨烯材料，利用石墨烯的疏水性和稳定性，能够防止底切问题。In this embodiment, the edge thickness H1 of the base
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims (11)
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