CN1150694C - Modulation system and method including oversampling and DC offset compensation of narrow bandwidth signals - Google Patents
Modulation system and method including oversampling and DC offset compensation of narrow bandwidth signalsDownload PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/71—Interference-related aspects the interference being narrowband interference
- H04B1/7101—Interference-related aspects the interference being narrowband interference with estimation filters
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/42—Systems providing special services or facilities to subscribers
- H04M3/487—Arrangements for providing information services, e.g. recorded voice services or time announcements
- H04M3/493—Interactive information services, e.g. directory enquiries ; Arrangements therefor, e.g. interactive voice response [IVR] systems or voice portals
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/38—Angle modulation by converting amplitude modulation to angle modulation
- H03C3/40—Angle modulation by converting amplitude modulation to angle modulation using two signal paths the outputs of which have a predetermined phase difference and at least one output being amplitude-modulated
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
- H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
- H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
- H04L27/2067—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers with more than two phase states
- H04L27/2071—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers with more than two phase states in which the data are represented by the carrier phase, e.g. systems with differential coding
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/7097—Direct sequence modulation interference
- H04B2201/709709—Methods of preventing interference
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
Translated fromChinese
Description
Invention field
The present invention relates to modulating system and method, relate in particular to the modulating system and the method for modulation digital input signal.
Background of invention
Modulating system and method are widely used in the information input that comes in the reflector comprising sound and/or data and are modulated on the carrier wave.Carrier wave can be final carrier wave or mean carrier.Carrier frequency can be UHF, VHF, RF, microwave or any other frequency band.Modulator is also referred to as " frequency mixer " or " multiplexer ".For example, in mobile radiotelephone, modulator is used to the radio telephone reflector.
Those skilled in the art are known, and the modulating system and the method that are used for digital input signals generally include the digital to analog converter (DAC) that digital input signals is converted to analog signal.Low pass filter, filtering produces filtered analog signal to analog signal to be also referred to as " anti-aliasing filter ".Modulator is modulated to filtered analog signal on the carrier wave.Modulator comprises multiplexer local oscillator and that be coupled in filtered analog signal that is coupled in such as voltage controlled oscillator (VCO).The carrier wave that comprises filtered analog signal then can be launched by antenna.
In Modern Communication System, double mode modulating system and method need be provided usually, it can modulate two types signal of communication.For example, in mobile radiotelephone, it is normally important to be provided at the modulator of operating in arrowband FM pattern and wideband code division multiple access (CDMA) pattern.Especially, for the mobile radiotelephone that can use IS-19 AMPS analogue system and IS-95 direct sequence spread spectrum (DSSS) wideband CDMA system is provided, need provide double mode modulating system and method.
Unfortunately be that it is difficult that the AMPS that can handle diverse bandwidth and the double mode modulating system and the method for CDMA signal are provided.Especially, arrowband AMPS FM signal has the bandwidth of about 12.5KHz, and the wideband CDMA signal has the bandwidth of about 615KHz or roomy about 1 order of magnitude.
In modern radiotelephone communication, mobile radiotelephone is continuing to reduce aspect size, cost and the power consumption.For satisfying these targets, need to share the circuit in the dual-mode wireless phone usually.The circuit of sharing can reduce the component count that is used in the modulator, thereby allows reducing of its size.The assembly of sharing also can reduce the power consumption of double mode modulation system, and it makes battery lengthening service time.At last, the shared assembly cost that makes of assembly reduces, thereby wireless telephonic whole cost is reduced.
Fig. 1 illustrates first kind of traditional double mode modulation device.As shown in Figure 1, IQ modulator 10 is also referred to as " quadrature phase modulator " or " quadrature modulator " and comprises that also known is the quadrature splitter 20 and a pair of multiplexer 16a, the 16b that is coupled in the quadrature splitter of 90 ° phase shifter.Local oscillator 15 such as voltage controlled oscillator (VCO) is coupled in quadrature splitter 20, to produce 90 ° phase shift to oscillation signals according.I data 11a and Q data 11b are coupled in each multiplexer or frequency mixer 16a, 16b respectively.Digital input signals is converted to analogue data by I digital to analog converter (DAC) 14a and Q DAC 14b respectively.The output of DAC14a and 14b is applied to low pass filter respectively so that I and Q data input 11a and 11b to be provided respectively.Modulator is by the multiplexer 16a at summingjunction 218 places, the output phase Calais of 16b the input data-modulated to carrier wave 13, and the carrier wave 13 after the antenna emission is modulated.
DAC 14a and 14b, low pass filter 12a and 12b and IQ modulator 10 can be used to the high bandwidth CDMA signal such as direct sequence spread spectrum (DSSS) signal is modulated on the carrier wave.Produce because signal is digitlization, it is low pass filtering device 12a and the 12b low-pass filtering allows information pass through, and removes burr (spur) and noise that digitized landed property is given birth to.
Be the IQ modulator 10 of use Fig. 1 in double mode, as be used for narrow bandwidth FM signal, independent F M DAC 19 and independent F M low pass filter 17 can be provided.Baseband circuit produces the FM voltage signal that is added in the tuning circuit of VCO, FM information is modulated to the carrier wave that is used to transmit according to the AMPS standard.Produce because the FM voltage signal is digitlization, it passed through by to be allowed information by FM low pass filter 17 low-pass filtering, removes burr and noise that digitized landed property is given birth to simultaneously.
Because the very different bandwidth of FM and CDMA signal, low pass filter 17 have and the low pass filter 12a bandpass characteristics different with 12b as the part of CDMA modulator usually.Therefore, in this double mode embodiment, can provide independent F M DAC 19 and independent F M low pass filter 17.Modulating system according to Fig. 1 can be designed into in the many integrated circuit (IC) chip groups that also comprise the functional CDMA exploitation of AMPS.Unfortunately be, this technology is used independently DAC and low pass filter, its can increase modulator size, improve its cost and/or increase its power consumption.
Second kind of double mode modulating system represented in Fig. 2.In the figure, provide to comprisequadrature splitter 220, one-to-many path multiplexer 216a, 216b, add the carrier wave that produces modulation with theIQ modulator 210 ofnode 218 and VCO215.But compared to Figure 1, DAC and low pass filter are shared for dual-mode operation.Especially, I DAC andQ DAC Low pass filter
Unfortunately be that because the very different bandwidth of CDMA signal and FM signal,low pass filter 212a should have different bandpass characteristics with 212b in different patterns the time.For sharing low pass filter, the logical frequency of band is switched according to pattern.Therefore, although thefilter 212a of these switchings can be used in the different patterns with 212b, they implement is expensive, and consumes excessive electric energy and/or take excessive area in mobile phone.
In high performance communication system, also need to provide high carrier suppressed.For high carrier suppressed is provided, should in modulating system, produce low direct current offset.For example, modulating desired carrier suppressed for FM in IS-19 AMPS analogue system approximately is-35dBc.For acceptable critical design is provided, nominal carrier suppressed is preferably-40dBc, and when the difference information signal of the peak-peak that produces 2V in balance sysmte, it can be converted into the difference direct-flow shifted signal of 14mV.
Can use traditional technology low direct current offset in the digital input signals is provided.But, unfortunately be that modulating system can produce its direct current offset.Especially, digital to analog converter and/or low pass filter can produce direct current offset.
Can use the high-performance digital to analog converter and be reduced in the direct current offset that produces in the digital to analog converter.Unfortunately be that these digital to analog converter costs are high and complicated.By providing outer (off-chip) filter of the passive chip that has the tight tolerance assembly to reduce direct current offset.Unfortunately be that this passive chip outer filter cost is high and complicated, and takies too much space in the portable radiotelephone phone.
Regardless of the maximum frequency of operation of the digital to analog converter in the modulator how EPO application 0359609A1 disclose a kind of being intended to the digital signal with the variable bit rate that can reach several megabit per seconds that arrives is carried out filter filtering.Oversample factor FA is inversely proportional to variable speed basically, so that be applied to the sample frequency substantially constant of transducer.In response to the position of each arrival, logic device circulation produces FA sampling sequence number, and it is selected and be recycled by the sampling sequence number and read by the factor of selecting that sequence number equals one of several sampling address quantum memory of possible oversample factor.The position of the signal that arrives is converted into each symbol word, and each comprises one and the position adjacent with this from the signal that arrives.Relevant and impulse response storage separately of several with possible symbol word is selected by each symbol word select in one of sampling quantum memory of described filter that may the factor, to read with the FA digital sampling of packing into by the address of reading from the selected address of the factor quantum memory of selecting.Modulator also comprises the cycle low pass filter of non-switching.
Disclosed PCT application WO96/20540 has described a kind of dual mode digital communication system that is used at frequency modulation(FM) and multiple access pattern operating period communication information signal.Digital communication system is included in that FM pattern operating period is used the FM signal of communication and launches information signal and uses the multiple access signal of communication and the dual-mode transmitter of launching information signal in multiple access pattern operating period, and communication system also is included in FM pattern operating period and receives the FM signal of communication and dual-mode receiver receive the multiple access signal of communication in multiple access pattern operating period.Be combined in the dual-mode receiver be used for FM pattern operating period the FM signal recovering information signal that receives and multiple access pattern operating period the digital demodulator of the multiple access signal recovering information signal that receives.
At last, U.S. patent 5,248,970 has been described a kind of digital to analog converter (DAC) that comprises the demarcation of the DAC with interpolating circuit and ∑ δ transducer.The output of ∑ δ transducer is imported into a DAC and its output simulated the filtering of low-pass filtering part.During calibration process, use the analog to digital converter of the demarcation of the simulation output of operating the DAC that imports through " 0 " of the oriented there of multiplexer receiving belt value.The intrinsic error in ∑ δ transducer and the analog filter part is represented in the output of A direct current.This is stored in the register.In second step of operation, interpolating circuit and the memory of offset register/latch circuit and be transfused to of the content of register through being used for interpolation.The content of latch is imported into one and adds and node, and in normal operation, the output addition of these contents and interpolating circuit is used to be input to ∑ δ transducer.Add and node by being provided with between interpolating circuit and ∑ δ modulator, the position load of interpolation can be lowered.By utilizing the interpolating circuit of calibration process, its gain can be used to compensate the value that is stored in the register/latch.
Summary of the invention
Therefore an object of the present invention is to provide a kind of improved modulating system and method.
Another object of the present invention provides a kind of double mode modulation System and method for that is used for first signal and has the secondary signal of the bandwidth narrower than first signal.
A further object of the invention provides a kind of first signal and double mode modulation System and method for secondary signal of the bandwidth narrower than first signal of being used for, and the assembly that these signals can be shared modulating system is to provide the compact low cost and/or the double mode modulation of low power consumption.
A further object of the invention provides a kind of modulating system and method that can produce low direct current offset.
According to the present invention, provide these and other objects by modulation such as the narrow bandwidth signal of arrowband FM signal in modulator, this modulator is modulated wide bandwidth signals such as the CDMA signal by the over-sampling narrow bandwidth signal with the narrow bandwidth signal application of over-sampling in modulator.By the over-sampling narrow bandwidth signal, same fixed low-pass filters can be used to the narrow bandwidth signal of wide bandwidth signals and over-sampling.Therefore, do not need the different low pass filters or the low pass filter of switching.
In a particular aspects of the present invention, the CDMA modulator that comprises sampler is by being used to double mode modulation to narrow bandwidth FM signal application in the CDMA modulator, thus CDMA modulator over-sampling FM signal and modulate the FM signal of over-sampling.The CDMA modulator comprises the fixed low-pass filters of the passband with the FM signal that comprises CDMA signal and sampling, thereby same fixed low-pass filters can be used to the filtering to CDMA signal and FM signal.CDMA modulator CDMA signal therein is that direct sequence spread spectrum signal and FM signal are to be particularly useful in the radio telephone of analog cellular telephone signal.
Comprise according to double mode modulation of the present invention system being used for a signal of using being modulated to the device on the carrier wave and being used for, thereby first signal is modulated on the carrier wave the device of first signal application in modulating device.Comprise the over-sampling device come to have than first signal more the secondary signal of narrow bandwidth carry out over-sampling.System also comprise be used for over-sampling second more the signal of narrow bandwidth be added to the device of modulating device, thereby second more the signal of narrow bandwidth be modulated on the carrier wave.
Modulating device preferably includes the simulation of digital to analog converter and logarithmic mode transducer and exports the low pass filter that carries out filtering, wherein low pass filter has second passband of narrow bandwidth signal more that comprises first signal and over-sampling, thereby same fixed low-pass filters is used to the second more filtering of narrow bandwidth signal to first signal and over-sampling.When modulating device comprised the IQ modulator with I and Q input, the over-sampling device preferably included first and second samplers.
According to double mode modulation of the present invention system also comprise the device that is used for the signal sampling of using, be used for the conversion of signals of sampling be analog signal device, be used for analog signal is carried out the device of low-pass filtering and is used for the analog signal of low-pass filtering is modulated to device on the carrier wave.Thereby thereby double mode modulation system also comprise be used for first signal application in sampling apparatus use sampling apparatus, conversion equipment and low-pass filter first signal be modulated on the carrier wave and be used for secondary signal that handle has the bandwidth narrower than first signal and be applied to sampling apparatus over-sampling secondary signal and use sampling apparatus, conversion equipment and low-pass filter that secondary signal is modulated to device on the carrier wave.Therefore, the same filter that does not switch can be used to the wide and narrow strip bandwidth signals, thereby makes cost, take up room and/or power consumption reduces.
Double mode modulation System and method for according to the present invention also compensates the direct current offset of being introduced by digital to analog converter and/or low pass filter.Preferably afford redress, thereby reduce direct current offset in the acceptable limit range of the modulation of just using at numeric field.More preferably, the digital value by the direct current offset in the analog signal that deducts the representative filtering of being introduced by digital to analog converter and/or low pass filter from the signal of sampling affords redress.
Modulating system according to the present invention comprises that be the digital to analog converter of analog signal to the conversion of signals of sampling.Analog signal is low pass filtering the analog signal that device filtering produces filtering.Digital to analog converter and/or low pass filter are introduced direct current offset in the analog signal of filtering.Modulator is modulated to the analog signal of filtering on the carrier wave.Direct current offset in the analog signal of DC-offset compensation device compensation filter by digital to analog converter and/or low pass filter introducing.
DC-offset compensation device according to the present invention preferably includes the detector of the direct current offset of the analog signal that is used for detection filter.Analog to digital converter in response to detector so that detected direct current offset is converted to the digimigration signal.Subtracter deducts the digital DC shifted signal and the signal of sampling is removed (deducting) digital DC shifted signal and is applied to digital to analog converter from the signal of sampling in response to analog to digital converter.Therefore, detected skew is deducted in numeric field.Can comprise that also the scaler in response to analog to digital converter is the digital DC shifted signal of calibration so that the digital DC shifted signal is calibrated.Then subtracter in response to scaler from the signal of sampling, to deduct the digital DC shifted signal of calibration.
Direct current offset in the analog signal of the unnecessary continuous detecting filtering of subtracter, but off and on and preferably by carrying out periodically.For example, the DC-offset compensation device can comprise the latch in response to analog to digital converter, also a digital DC shifted signal that latchs is applied to subtracter to latch the digital DC shifted signal off and on, thereby the digital DC shifted signal that latchs is deducted from the signal of sampling.When analog to digital converter with first clock frequency during by timing, latch can with than the lower second clock frequency of first clock frequency by timing.
Detector can comprise the low pass filter of the direct current offset in the analog signal of detection filter.In one embodiment, analog to digital converter is one a ∑ δ analog to digital converter.In another embodiment, polarity inverter is in response to detector, with periodically the polarity paraphase of detected direct-flow shifted signal.Analog to digital converter is converted to the digimigration signal to the detected direct-flow shifted signal of cycle paraphase, thereby reduces the effect of the inside direct current offset of analog to digital converter.
DC-offset compensation can advantageously use the wide modulator of biobelt, and wherein Cai Yang signal comprises from first digital input signals and has one that selects second digital input signals of the bandwidth narrower than first digital input signals.For example, the present invention can use first digital input signals of CDMA signal and second digital input signals of FM signal.Especially, the CDMA signal can be the direct sequence spread spectrum signal, and the FM signal can be the analog cellular telephone signal.The present invention also can be used in the IQ modulator that is also referred to as " quadrature phase modulator " or " quadrature modulator ", and the analog signal of its homophase and quadrature filtering is modulated on the carrier.Also can provide analog modulation method.
Therefore, the modulating system and the method that are used for digital input signals can provide low direct current offset, although introduced direct current offset by digital to analog converter and/or low pass filter.Unnecessary use high-performance and expensive digital to analog converter.The outer low pass filter of the high performance chip of also unnecessary use.
Brief Description Of Drawings
Fig. 1 is the block diagram of first kind of traditional double mode modulation System and method for.
Fig. 2 is the block diagram of second kind of traditional double mode modulation System and method for.
Fig. 3 is the block diagram that comprises the double mode modulation System and method for of DC-offset compensation according to of the present invention.
Fig. 4 A and 4B, it is placed on together, as shown in Figure 4, is the block diagram according to second embodiment of the double mode modulation System and method for that comprises DC-offset compensation of the present invention.
Fig. 5 is the block diagram that is used to one ∑ δ analog to digital converter of compensating DC offset according to of the present invention.
Fig. 6 is according to another of the analog to digital converter that is used to compensating DC offset of the present invention
The block diagram of embodiment.
Fig. 7 represents to be used for the operation of the polarity inverter of Fig. 6.
Fig. 8 is the block diagram according to modulating system of the present invention and method.
Fig. 9 A and 9B, it is placed on together, as shown in Figure 9, is double mode IQ modulating system and the method according to the first embodiment of the present invention.
Figure 10 is double mode IQ modulating system and a method according to a second embodiment of the present invention.
Figure 11 A and 11B, it is placed on together, as shown in figure 11, is monotype IQ modulating system according to an embodiment of the invention and method.
The specific descriptions of preferred embodiment
Describe the present invention more fully referring now to accompanying drawing, wherein show the preferred embodiments of the present invention.But this invention can be with multi-form realization, and the embodiment that is not restricted to here to be proposed.On the contrary, provide these embodiment to make this scheme complete and thorough, will pass on scope of invention fully those of ordinary skill in the art.Mark same in the whole explanation is represented components identical.
Refer now to Fig. 3, it is the block diagram according to double mode modulation system and method for the present invention.As shown in Figure 3, double mode modulation System and method for comprises and comprisesVCO 315, one-to-many path multiplexer 316a and 316b, quadrature splitter 320 and add IQ modulator 310 with contact 318.Interconnecting of these elements and the quadrature modulator that forms are known to those skilled in the art and do not need here to further describe.Go out as shown like that, IQ modulator 310 receives I input 311a and Q input 311b and produces these inputs are modulated to output 313 on the carrier wave.
Still with reference to figure 3, double mode modulation system and method according to the present invention comprises a pair of fixed low-pass filters 312a and 312b.Fixed low-pass filters comprises the passband that can pass through such as the wide bandwidth signals of CDMA DSSS signal.Also comprise I DAC 314a andQ DAC 314b.
Still with reference to figure 3, also comprise a pair ofsampler 330a and 330b, it also is hereinafter referred to as I sampler and Q sampler.According to the present invention, as shown in Figure 3, all be added tosampler 330a and 330b such as the wide bandwidth signals source ofDSSS signal source 350 with such as the narrow bandwidth signal source of FM signal source 340.DSSS signal source 350 can produce DSSS-I signal and the DSSS-Q signal that is added tosampler 330a and 330b respectively.FM signal source 330 can produce FM I signal and the FM Q signal that is added tosampler 330a and 330b respectively.Be appreciated thatDSSS signal source 350 and FM signal source 340 can be used as baseband signal and produce in the dual-mode wireless phone.The generation of DSSS signal and FM signal is known to those skilled in the art and does not need here to further describe in the dual-mode wireless phone.
Still, can see thatsampler 330a and 330b andDAC 314a and 314b are with sample rate T with reference to figure 3SampleOperation.Sample rate TSampleCan be by the signal controlling that is applied to control circuit 335.Sample rate is provided with by the sample rate that is used forwide bandwidth signals 350 usually.Therefore, when narrow bandwidth signal 340 was applied tosampler 330a and 330b, sampler was used for the over-sampling narrow bandwidth signal.By the over-sampling narrow bandwidth signal, same DAC is applied to wide bandwidth signals and narrow bandwidth signal with low pass filter 314 and 312 respectively.
Be appreciated that wide bandwidth signals also can be sampleddevice 330a and 330b over-sampling as the part of wide bandwidth signals modulation.Under the sort of situation, narrow bandwidth signal is sampled more highland over-sampling of device 330a and 330b.Also can understand for wide and narrow strip bandwidth signals sample rate unnecessary identical.But, common sample rate TSampleBeing maintained at one makes same fixed low-pass filters 312a and 312b can be used to the sample rate of wide and narrow strip bandwidth signals.Therefore, double mode modulation device can use the same low pass filter that does not switch, the narrow bandwidth signal that is used to modulate wide bandwidth signals and over-sampling, thus save cost, space and/or electric energy.
The present invention can use same fixed low-pass filters (not switching) to be used to supply with the FM signal and the spread spectrum signal of IQ modulator.Need be such as the variable low pass filter of the low pass filter that switches.For using same fixed low-pass filters, the FM signal in DAC by over-sampling excessively, preferably with identical sample rate TSample, the same with spread spectrum signal.For in DAC with the sampling of this speed, it is sampled/in be inserted into the speed of this excessive over-sampling.
For the IS-95 signal, sample rate can be 8X or 4.9152MHz.For simplicity, FM signals sampling rate can be the mark (19.2MHz/4.8MHz) near the reference clock frequency of IS-95 sample rate.The sampling burr (～5MHz) can be low pass filtering the burr property specification that device reduces to satisfy the reflector that is used for AMPS and CDMA.
By over-sampling FM signal excessively, rise a sampling noise bottom line from DAC can be lowered to AMPS launch acceptable level (＜-60dBc).Spread spectrum signal is by over-sampling excessively, and over-sampling (8X) normally.The sampling noise bottom line that is used for the DAC of this pattern can be lowered to IS-95 launch acceptable level (＜-45dBc).The free dynamic range of the parasitism of any pattern (spurious) is poor (for AMPS＞60B and for CDMA＞45dB) more preferably greater than peak signal and noise bottom line.Thereby the quality optimization of IQ modulator is enough to satisfy the modulation specification in the AMPS pattern, and it is stricter than CDMA pattern usually.This legacy system for Fig. 2 also is a kind of situation, and the IQ modulator is shared here, and low pass filter is switched.
The present invention can be applied to sharing the modulating system and the method for the IQ modulator that has FM signal (narrow bandwidth) and direct sequence spread spectrum signal (wide bandwidth).Simulation FM signal is converted into digital signal with a certain speed.If switching rate is low, it can be sampled so/in be inserted into the speed Tsample of final requirement.In the A/D transition period, speed that it can finally require is by over-sampling to heavens at once.The present invention also can be applied to sharing the modulating system and the method for the IQ modulator of the digital signal (narrow bandwidth) have not expansion and direct sequence spread spectrum signal (wide bandwidth).Thereby in the radio telephone of the AMPS/CDMA radio telephone (IS-95) that the present invention can be used to mix, the GSM/WCDMA radio telephone (third generation broadband cellular standard) that mixes and other combination broadband and narrow band signal.
Still, will describe according to DC-offset compensation of the present invention with reference to figure 3.Although I and Q signal 333a and the 333b of sampling can have low direct current offset, can produce unacceptable high direct current offset by the direct current offset of at least one introducing among digital toanalog converter 314a and 314b and low pass filter 312a and the 312b.Digital toanalog converter 314a and 314b andlow pass filter 312a and 312b 324a and 324b concentrated area by dashed box are designated the direct current offset source.
According to the present invention, provide DC-offset compensation device 322a and 322b, the direct current offset among the analog signal 311a of its compensation filter and the 311b by at least one introducing among digital toanalog converter 314a and 314b and low pass filter 312a and the 312b.As illustrated, do in order to the analog signal 311a of compensation filter and the direct current offset among the 311b on the signal 333a of DC-offset compensation device 322a and the 322b sampling in numeric field and the 333b, thereby direct current offset is reduced in the acceptable limit of the modulating mode that is used by at least one introducing among digital toanalog converter 314a and 314b and low pass filter 312a and the 312b.
Especially, as shown in Figure 3, each DC-offsetcompensation device 322a and 322b preferably include the analog signal 311a of detection filter and the DC detector 321a and the 321b of the direct current offset among the 311b.Analog to digital converter (A direct current) 323a and 323b are converted to digital DC shifted signal 331a and 331b to detected direct current offset 329a and 329b.Subtracter 326a and 326b deduct digital DC shifted signal 331a and 331b and the signal of sampling are removed (deducting) direct-flow shiftedsignal 327a and 327b is applied to digital toanalog converter 314a and 314b from the signal 333a of sampling and 333b.Therefore, the direct current offset that produces in path forward is detected and be converted into digital value.From the sampled signal 333a that arrives and 333b, deduct the digital value of representing direct current offset then.
Be still as shown in Figure 3, be compensating DC offset, the digital DC shifted signal is unnecessary to be calculated with the identical frequency of the digital-to-analogue conversion of carrying out with digital to analog converter 314a and 314b.On the contrary, can preferably determine direct current offset periodically off and on.Therefore, as shown in Figure 1, latch 325a and 325b can be used to latch off and on and periodically digital DC shifted signal 311a and 311b, thereby deduct digital DC shifted signal 332a and the 332b that latchs from sampled signal 333a and 333b.Like this, as described below, latch 325a and 325b and/or analog todigital converter 323a and 323b can be than the lower frequency of digital toanalog converter 314a and 314b by timing, and be rapid because direct current offset does not resemble sampled signal 333a and the 333b with changing usually.In certain embodiments, but the detection of direct current offset per second once, or detect at interval with other.
Be appreciated that in Fig. 3 and provide two independently DC-offsetcompensation device 322a and 322b two input signal paths.But, be appreciated that and can use single DC-offset compensation device to be used for I input signal path and Q input signal path.
Refer now to Fig. 4, with another embodiment that describes according to double mode IQ modulator of the present invention.In Fig. 4, between the analog to digital converter 323a of correspondence and 323b andcorresponding latch 325a and 325b, use optional scaler 460a and 460b.Scaler is digital DC shifted signal 329a ' and the 329b ' for calibrating digital DC shiftedsignal 329a and 329b calibration.Using calibration is for scaling factor being applied to the digital signal that analog todigital converter 323a and 323b produce.For example, when the difference direct voltage is detected by the DC detector 321a among Fig. 4 and 321b, need to use scaling factor.And in Fig. 4, optional amplifier 461a and 461b are used between correspondinglow pass filter 312a and 312b and corresponding modulators 316a and the 316b so that amplification to be provided where necessary.As shown in Figure 4, but the also direct current offset among compensated amplifier 461a and the 461b of DC-offsetcompensation device 322a and 322b.
And as shown in Figure 4, also be provided for the sequential of analog todigital converter 323a and 323b, digital toanalog converter 314a and 314b and latch 325a and 325b from shared clock 462.Be appreciated that preferably voltage controlledoscillator 315 can be locked to identical normative reference as shared clock 462.As shown in Figure 4, digital toanalog converter 314a and 314b are preferably locked by clock 462.It is preferably locked with first clock rate of the speed that is lower thanclock 462 that analog todigital converter 323a and 323b use M parallel circuit (÷ M) 463a and 463b.And latch 325a and 325b application N parallel circuit (÷ N) 464a and 464b are locked with the second clock speed that is lower than first clock rate.Can use first clock rate and the second clock speed of the speed that is lower thanclock 462, because direct current offset does not need to be converted into numeral continually as sampledsignal 333a and 333b, this be since direct current offset to change ground than sampled signal self usually slower.
The direct current offset finished is offset the restriction of the direct current offset that the analog to digital converter 323a that is subjected among DC-offset compensation device 322a and the 322b and 323b introduce.Therefore, preferably use low direct current offset analog to digital converter 323a and 323b.Preferred analog todigital converter 323a and 323b are ∑ δ transducers.Thereby feedback connects and does not need intermediate module just can obtain the feedback path of ∑ δ converter inside to use a bit pad to use directly.
Fig. 5 represents the block diagram of a ∑ δ analog to digital converter 323 '.As shown in Figure 5, analog to digital converter 323 ' comprises that integrator 70, comparator 71 and ten select an extraction/low pass filter 72.The output of comparator 71 is fed to input through adding with node 73.The design of a ∑ δ analog to digital converter is known to being familiar with those skilled in the art, in the textbook that Candy and Temes showed that IEEE1992 for example publishes at exercise question for being described in the article of " Oversampling Delta-sigma Data Converters " at exercise question in the chapters and sections of " Oversampling Methods for A/D and D/A Converters ", this article is introduced into as a reference here.
Therefore, the direct current offset of being introduced by the element in the path forward of ∑ δ transducer can be translated into null value.Thereby it is the analog differential amplifier of being represented by summing junction 73 that unique direct current offset provides device.Direct current offset is lowered in this differential amplifier 73, for example by selecting ten to get one low pass filter 72 with the 10Hz corner.Thereby differential amplifier 73 can very low frequencies operations, for example 10KHz.Therefore differential amplifier 73 can be made by big geometry, low frequency transistor, and it is being used in the digital to analog converter 314a that also comprises high frequency, has good assembly coupling in the time of in the processing of 314b.This good coupling can produce low direct current offset in ∑ δ transducer.
Preferably, can select the corner frequency of detector 321 that it is enough hanged down and slip over modulation, thereby keep feedback loop not modulate.Preferably select the frequency of a ∑ δ transducer to eliminate this modulation and do not bring aliasing error.
The locking rate of latch 325 is preferably enough low to make the open-loop system be fixed.The resolution of feedback is preferably in the least important position of digital to analog converter 314.This resolution can be determined by the over-sampling rate between the input and output of extracting one/low pass filter 72 in ten.
It is available that worst error is corrected for first subtraction.This correction can be finished in a step.Another kind of situation is that this correction can become more smooth by the digital filter that is arranged between latch 325 and the subtracter 326.Another kind of situation is, latchs moment by the restriction latch at each and only moves a least important position and make transformation more level and smooth.Speed as required selects setting compensation initially.After this, the DC-offset compensation device can and can use same technology in the tracing mode operation.
Fig. 6 represents to use another embodiment of analog-to-digital converter 80 of the analog to digital converter 323 of arbitrary type.As shown in Figure 6, comprise periodically thepolarity phase inverter 81 of the polarity paraphase of detected direct-flow shifted signal.Operating among Fig. 7 ofpolarity phase inverter 81 simply described.
With reference to figure 6, analog to digital converter 323 is converted to the digimigration signal to the detected direct-flow shifted signal 82 of polarity paraphase periodically again.Because the sampling that replaces is by paraphase, idol sampling and strange sampling are latched among the first and second latch 82a and the 82b then.Before subtracter 83 carries out subtraction, be delayed 84 as the sampling of the strange sampling among the latch 82b and postpone.
The subtraction of the polarity paraphase sampling in the piece 85 can useclock 462 to come clock, and whereinclock 462 is removed by R and is applied topolarity phase inverter 81 and analog to digital converter 323 by the first and second R parallel circuits 86 and 87.Take advantage of the slower clock of P circuit 88 generations can be used to by removing R to subtracter 83 timing.
The analog-to-digital converter 80 of Fig. 6 is because following relational expression can produce low direct current offset:
M0=direct currentOffset+ EMeasurement,
M1=direct currentOffset+ EMeasurement,
Direct currentOffset=(M0-M1)/2,
M wherein0Be the error of in a state ofphase inverter 81, measuring, M1Be the error of in another state ofphase inverter 81, measuring, direct currentOffsetBe direct-flow shifted signal 311, EMeasurementBe the dc error of the measuring system of Fig. 6, it is assumed to be between measuring is constant.
When polarity is changed or during paraphase, the sign modification of the direct current offset of measurement, but the dc error in the measuring system does not change.Error is at a state M of phase inverter0In measured, at another state M1In measured once more.These two measurements are subtracted each other and are calibrated by the scaler 460 of after 80s of the analog to digital converter in the numeric field.Any dc error of the removable analog to digital converter 80 of this subtraction.For sampling of alignment even number and odd number sampling, use to postpone 84.Thereby the dc error in the analog to digital converter can be lowered.
Refer now to Fig. 8, be used for the modulating system of digital input signals and the block diagram of method is expressed out according to of the present invention.As shown in Figure 8, comprise the digital to analog converter (DAC) 814 that digital input signals 833 is converted to analog signal 828 according to modulating system of the present invention and method.812 pairs of analog signal 828 filtering of low pass filter that are also referred to as " anti-aliasing filter " produce filtered analogsignal 811.Modulator 816 is modulated to filteredanalog signal 811 on the carrier wave that is produced by the controllable source such as voltage controlled oscillator (VCO) 815.Theinput signal 813 of modulation is launched by transmittingantenna 834 then.The radiating circuit that also can comprise other, this is known to those skilled in the art.
Modulating system of describing in the earlier paragraphs and method are known to those skilled in the art.But unfortunately be, can produce unacceptable high direct current offset by the direct current offset of at least one introducing of digital toanalog converter 814 andlow pass filter 812 although digital input signals 833 can have low direct current offset.Digital toanalog converter 814 andlow pass filter 812 are the direct current offset source by frame ofbroken lines 824 centralised identity.
According to the present invention, the DC-offsetcompensation device 822 in the filteredanalog signal 811 that affords redress by the direct current offset of at least one introducing of digital toanalog converter 814 and low pass filter 812.As illustrated, do on the digital input signals 833 of DC-offsetcompensation device 822 in numeric field in order to the direct current offset in the analog signal behind thecompensation filter 811, thereby direct current offset is reduced in the acceptable scope of employed modulation scheme by at least one introducing of digital toanalog converter 814 andlow pass filter 812.
More particularly, as shown in Figure 8, DC-offsetcompensation device 822 preferably includes theDC detector 821 of the direct current offset in theanalog signal 811 after the detection filter.Analog to digital converter (A direct current) 823 is converted to digital DC shiftedsignal 831 to detected direct current offset 829.Subtracter 826 deducts digital DC shiftedsignal 831 and digital input signals is removed (deducting) digital DC shiftedsignal 827 and is added to digital toanalog converter 814 from digital input signals 833.Therefore, the direct current offset that produces in path forward is detected and be converted into digital value.Represent the digital value of direct current offset from import next digital input signals 833, to be deducted then.
And as shown in Figure 8, being compensating DC offset, the digital DC shifted signal is unnecessary to be calculated with the identical frequency of the digital-to-analogue conversion of carrying out with digital to analog converter 814.On the contrary, can preferably determine direct current offset periodically off and on.Therefore, as shown in Figure 8, latch 825 can be used to latch off and on and periodically digital DC shiftedsignal 831, thereby deducts the digital DC shifted signal 832 that latchs from digital input signals 833.Like this, as described below,latch 825 and/or analog todigital converter 823 can be than the lower frequency of digital toanalog converter 814 by timing because direct current offset change usually do not resemble thedigital input signals 833 rapid.Under a certain embodiments, but the detection of direct current offset per second once, or detect at interval with other.
Fig. 9 represents according to double mode IQ modulating system of the present invention.What go out as shown is such, and IQ modulator 910 is included as quadrature splitter 920 and a pair of multiplexer 916a that is coupled in the quadrature splitter that carries out 90 ° of phase shifters, 916b.VCO 915 is coupled in quadrature splitter 920, to produce 90 ° phase shift to local oscillator signal.Numeral I input signal 933a and digital Q input signal 933b are offered the I and the Q path of IQ modulating system respectively.Element in the I path is by parameter characteristic a design, and the element in the Q path is by parameter characteristic b design.IQ modulator 910 passes through the multiplexer 916a at summing junction 918 places, and the output phase Calais of 916b is modulated to the analog signal 911a and the 911b of I and Q filtering on the carrier wave respectively.The input signal of modulation is launched through antenna 934.
Digital to analog converter 914a and 914b, low pass filter 912a and 912b and IQ modulator 910 can be used to the high bandwidth CDMA signal such as direct sequence spread spectrum (DSSS) signal is modulated on the carrier wave.Produce because signal is digitlization, its filtered device 912a and 912b low-pass filtering to be allowing information pass through, but remove burr and noise that digitized landed property is given birth to.
Be IQ modulator 910, as be used for narrow bandwidth FM signal, independent F M digital toanalog converter 914c and independent F Mlow pass filter 912c can be provided at double mode Fig. 9 of use down.Assembly in the modulation path of numeralFM input signal 933c is put on reference marker c.Baseband circuit produces the digitalFM input signal 933c that is added on the VCO 915 tuning circuits, FM information is modulated to the carrier wave that is used to transmit according to the AMPS standard.Because FM has very different bandwidth with the CDMA signal,low pass filter 912c has and low pass filter 912a as the part of CDMA modulator usually, the bandpass characteristics that 912b is different.
Being appreciated that in Fig. 9 provides three independently DC-offsetcompensation device 922a, 922b and 922c to three input signal paths.But, be appreciated that single DC-offset compensation device also can be used to digital I input signal path and digital Q input signal path.And single DC-offset compensation device can be used for three whole input signal paths of Fig. 9.
Second kind of double mode modulation system shown in Figure 10.In the figure, digital to analog converter and low pass filter are shared by double mode.Especially, I DAC 1014a and Q DAC 1014b can be used to wide bandwidth CDMA and narrow bandwidth FM operation.Low pass filter 1012a ' and 1012b ' also are used to wide bandwidth CDMA and narrow bandwidth FM operation.Because the very different bandwidth of CDMA signal and FM signal, low pass filter 1012a ' should have different bandpass characteristics with 1012b ' in different mode.For sharing low pass filter, the logical frequency of band is according to mode switch.
Refer now to Figure 11, describe a embodiment according to single-mode IQ modulator of the present invention.In Figure 11,optional scaler digital converter corresponding latch 1125a and 1125b.Scaler is digital DC shiftedsignal 1129a ' and the 1129b ' for calibrating digital DC shiftedsignal digital converter DC detector 1121a among Figure 11 and 1121b, need to use scaling factor.And in Fig. 4,optional amplifier low pass filter amplifier 1161a and the 1161b of DC-offsetcompensation device
And as shown in figure 11, also be provided for the sequential of analog todigital converter analog converter analog converter digital converter input signal
The direct current offset finished is offset the restriction of the direct current offset that the analog todigital converter 1123a that is subjected among DC-offsetcompensation device 1122a and the 1122b and 1123b introduce.Therefore, preferably use low direct current offset analog todigital converter 1123a and 1123b.Preferred analog todigital converter
In accompanying drawing and explanation, disclose typical preferred embodiment of the present invention, although used specific term, their use be general meaning and for the description needs, and do not play the restriction purpose, scope of the present invention is proposed by appended claim.
Claims (38)
1. dual-mode wireless phone comprises:
Be used for device (330) that added signal is sampled;
Being used for the conversion of signals of sampling is the device (314) of analog signal;
Be used for thereby analog signal is carried out the device (312) that low-pass filtering produces filtered analog signal;
Be used for the analog signal of low-pass filtering is modulated to device (310) on the radio telephone carrier wave, and
Be used to the device of second radiophone signal (340) that produces first radiophone signal (350) and have the bandwidth narrower than first radiophone signal, wherein at least one is a nonbinary signal of representing the variable time waveform in first and second radiophone signals; With
Thereby thereby be used for first radiophone signal be added to sampling apparatus use sampling apparatus, conversion equipment and low-pass filter first radiophone signal be modulated on the carrier wave and be used for that second radiophone signal with bandwidth narrower than first radiophone signal is added to sampling apparatus the sampling of second radiophone signal and use sampling apparatus, conversion equipment and low-pass filter be modulated to device on the carrier wave to second radiophone signal.
2. according to the dual-mode wireless phone of claim 1, it is characterized in that:
Direct current offset is introduced the device that is used for changing in the analog signal of filtering and be used at least one device of the device of low-pass filtering;
The dual-mode wireless phone also comprise the analog signal that is used for compensation filter periodically by the device that is used for changing in its operating period and be used for the device (322) of direct current offset of at least one introducing of the device of low-pass filtering.
3. according to the dual-mode wireless phone of claim 1, it is characterized in that low-pass filter is second fixed low-pass filters of the passband of narrow bandwidth signal more with first signal that comprises sampling and sampling, thereby fixed low-pass filters is used to more narrow bandwidth radiophone signal filtering of first radiophone signal and second.
4. according to the dual-mode wireless phone of claim 1, it is characterized in that first signal is a direct sequence spread spectrum CDMA signal, secondary signal is a FM analog mobile telephone signal.
5. according to the dual-mode wireless phone of claim 1, it is characterized in that:
Modulating device comprises the IQ modulator with I and Q input;
Wherein sampling apparatus comprise first and second samplers (330a, 330b), first sampler is imported in response to I, second sampler is imported in response to Q.
6. according to the dual-mode wireless phone of claim 2, it is characterized in that the device that is used for compensating periodically comprise periodically from the signal of sampling deduct the analog signal of representing filtering by the device that is used to change and be used for the device (326) of digital value of direct current offset of at least one introducing of the device of low-pass filtering.
7. according to the dual-mode wireless phone of claim 2, it is characterized in that the device that is used for compensating periodically comprises:
The device (321) of direct current offset that is used for the analog signal of detection filter;
Be used for detected direct current offset is converted to the device (323) of digital DC shifted signal; With
Be used for deducting the digital DC shifted signal and being used for that periodically the signal of sampling is removed direct-flow shifted signal being added to digital input signals being converted to device (326) on the device of analog signal from the signal of sampling.
8. according to the dual-mode wireless phone of claim 7, it is characterized in that the device that is used for compensating periodically also comprises:
Be used for the device (460) of digital DC shifted signal calibration for the digital DC shifted signal of calibration;
Be used to carry out the device of the device of subtraction, from the signal of sampling, to deduct the digital DC shifted signal of calibration in response to calibration.
9. according to the dual-mode wireless phone of claim 7, it is characterized in that the device that is used for compensating periodically also comprises:
Be used for latching off and on the digital DC shifted signal and the digital DC shifted signal that latchs is added to device (325) on the substracting unit, thereby the digital DC shifted signal that latchs is deducted from the signal of sampling.
10. according to the dual-mode wireless phone of claim 9, the device of direct-flow shifted signal that it is characterized in that being used for detected direct current offset is converted to numeral with first clock frequency by clock, the device that is used for latching off and on than the lower second clock frequency of first clock frequency by clock.
11., it is characterized in that the device that is used for compensating periodically also comprises according to the dual-mode wireless phone of claim 9:
Be used for the device (460) of digital DC shifted signal calibration for the digital DC shifted signal of calibration;
The device that is used for latching off and on (325) in response to the device of calibration, latching the digital DC shifted signal of calibration periodically, thereby deducts the digital DC shifted signal of the calibration of latching from the signal of sampling.
12., it is characterized in that the device that is used to detect comprises the device of low-pass filtering according to the dual-mode wireless phone of claim 7.
13., it is characterized in that being used for the device that detected direct current offset is converted to the direct-flow shifted signal of numeral is comprised one ∑ δ analog to digital converter according to the dual-mode wireless phone of claim 7.
14. according to the dual-mode wireless phone of claim 7, it is characterized in that being used for periodically, compensation arrangement also comprises:
Be used for periodically the polarity paraphase of detected direct current offset and the detected direct current offset of polarity paraphase be applied to detected direct current offset is converted to the device (81) of the device of digital DC shifted signal.
15. double mode modulation method that is used for first digital input signals (350) and second digital input signals (340) with narrow bandwidth different with first digital input signals, wherein at least one is a nonbinary signal of representing the variable time waveform in first and second digital input signals, and the method comprising the steps of:
Second digital input signals is carried out over-sampling (330);
Second digital input signals of first digital input signals and over-sampling is converted to analog signal (314);
Analog signal is carried out low-pass filtering and produced filtered analog signal (312);
The analog signal of low-pass filtering is modulated to (310) on the carrier wave.
16. the double mode modulation method according to claim 15 is characterized in that:
At least one step is introduced direct current offset in the analog signal of filtering in conversion and the low-pass filtering step;
This method also comprise the analog signal that is used for compensating periodically (322) filtering by the step that is used to change in its operating period and be used for the step of the direct current offset that at least one step of the step of low-pass filtering introduces.
17., it is characterized in that the step that compensates periodically comprises the step of the digital value that deducts the direct current offset that at least one step by in the conversion and the step of low-pass filtering in the analog signal of representing filtering introduces from the digital input signals of first and second over-samplings periodically according to the double mode modulation method of claim 16.
18., it is characterized in that the step that compensates periodically comprises step according to the double mode modulation method of claim 16:
Direct current offset in the analog signal of detection filter (321);
Detected direct current offset is converted to digital DC shifted signal (323); With
From the digital input signals of first and second over-samplings, deduct digital DC shifted signal (326).
19., it is characterized in that the step that compensates periodically also comprises step according to the double mode modulation method of claim 18:
The digital DC shifted signal (460) of digital DC shifted signal calibration for calibration.
20., it is characterized in that the step that compensates periodically also comprises step according to the double mode modulation method of claim 18:
Latch digital DC shifted signal (325) off and on.
21. double mode modulation method according to claim 20, the step of direct-flow shifted signal that it is characterized in that detected direct current offset is converted to numeral with first clock frequency by clock, the step that latchs off and on than the lower second clock frequency of first clock frequency by clock.
22., it is characterized in that the step that compensates periodically also comprises step according to the double mode modulation method of claim 21:
The digital DC shifted signal (460) of digital DC shifted signal calibration for calibration.
23. the double mode modulation method according to claim 18 is characterized in that detecting the step that step comprises the filtered analog signal of low-pass filtering.
24., it is characterized in that the step that detected direct current offset is converted to the direct-flow shifted signal of numeral comprises the step of detected direct current offset ∑ δ analog-to-digital conversion for the direct-flow shifted signal of numeral according to the double mode modulation method of claim 18.
25., it is characterized in that the step that compensates periodically also comprises step according to the double mode modulation method of claim 18:
Periodically the polarity paraphase (81) of detected direct current offset.
26. according to the double mode modulation method of claim 15, it is characterized in that first digital input signals is the CDMA signal, second digital input signals is the FM signal.
27. according to the double mode modulation method of claim 20, it is characterized in that the CDMA signal is the direct sequence spread spectrum signal, the FM signal is the analog mobile telephone signal.
28., it is characterized in that modulation step comprises the step that the analog signal of the filtering of homophase and quadrature is modulated to the IQ modulation on the carrier wave according to the double mode modulation method of claim 15.
29. double mode modulation method according to claim 15, it is characterized in that the low-pass filtering step comprises the step of the fixed low-pass filters of using the passband with second digital input signals that comprises first digital input signals and over-sampling, thereby fixed low-pass filters is used to the filtering to second digital input signals of first digital input signals and over-sampling.
30. a modulating system that is used for digital input signals comprises:
Digital input signals is converted to the digital to analog converter (314) of analog signal;
Analog signal is carried out filtering and produced the low pass filter (312) of filtered analog signal, and at least one direct current offset is introduced in the analog signal of filtering in digital to analog converter and the low pass filter;
The analog signal of filtering is modulated to modulator (310) on the carrier wave, and
Periodically in the analog signal of compensation filter by at its digital to analog converter and the cycle DC-offset compensation device (322) of the direct current offset of at least one introducing of low pass filter operating period, it is characterized in that described cycle DC-offset compensation device comprises:
The detector of the direct current offset in the analog signal of detection filter (321);
Detected direct current offset is converted to the analog to digital converter (323) of digital DC shifted signal in response to " detector "; With
From digital input signals, deduct the digital DC shifted signal and the digital input signals that removes direct-flow shifted signal is added in subtracter (326) on the digital to analog converter in response to analog to digital converter.
31., it is characterized in that cycle DC-offset compensation device comes the direct current offset by at least one introducing in digital to analog converter and the low pass filter in the analog signal of compensation filter periodically by deduct the digital value by the direct current offset of at least one introducing of digital to analog converter and low pass filter in the analog signal of representing filtering from digital input signals according to the modulating system of claim 30.
32., it is characterized in that the DC-offset compensation device also comprises according to the modulating system of claim 30:
In response to analog to digital converter is the calibration of digital DC shifted signal the scaler (460) of the digital DC shifted signal of calibration periodically;
From digital input signals, deduct the subtracter of the digital DC shifted signal of calibration in response to scaler.
33., it is characterized in that cycle DC-offset compensation device also comprises according to the modulating system of claim 30:
Latch the digital DC shifted signal off and on and the digital DC shifted signal that latchs is added to the latch (325) of subtracter in response to analog to digital converter, thereby the digital DC shifted signal that latchs is deducted from digital input signals.
34. according to the modulating system of claim 33, it is characterized in that analog to digital converter with first clock frequency by clock, latch with than the lower second clock frequency of first clock frequency by clock.
35., it is characterized in that cycle DC-offset compensation device also comprises according to the modulating system of claim 33:
In response to analog to digital converter is the calibration of digital DC shifted signal the scaler (460) of the digital DC shifted signal of calibration;
Thereby from digital input signals, deduct the latch of the digital DC shifted signal of the calibration of latching in response to the digital DC skew that scaler latchs calibration periodically.
36., it is characterized in that detector comprises low pass filter according to the modulating system of claim 30.
37., it is characterized in that analog to digital converter is one a ∑ δ analog to digital converter according to the modulating system of claim 30.
38., it is characterized in that the DC-offset compensation device also comprises according to the modulating system of claim 30:
Come periodically to be added to the polarity phase inverter (81) of analog to digital converter the polarity paraphase of detected direct current offset and the detected direct current offset of polarity paraphase in response to transducer, analog to digital converter is being converted to the digimigration signal by the detected direct-flow shifted signal of polarity paraphase periodically.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/971,502 | 1997-11-17 | ||
| US08/971,502US6137826A (en) | 1997-11-17 | 1997-11-17 | Dual-mode modulation systems and methods including oversampling of narrow bandwidth signals |
| US09/151,996US6535561B2 (en) | 1997-11-17 | 1998-09-11 | Dual-mode modulation systems and methods including oversampling of narrow bandwidth signals and DC offset compensation |
| US09/151,996 | 1998-09-11 | ||
| US09/151,622 | 1998-09-11 | ||
| US09/151,622US6100827A (en) | 1998-09-11 | 1998-09-11 | Modulation systems and methods that compensate for DC offset introduced by the digital-to-analog converter and/or the low pass filter thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1286834A CN1286834A (en) | 2001-03-07 |
| CN1150694Ctrue CN1150694C (en) | 2004-05-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB988131668AExpired - Fee RelatedCN1150694C (en) | 1997-11-17 | 1998-11-05 | Modulation system and method including oversampling and DC offset compensation of narrow bandwidth signals |
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| Country | Link |
|---|---|
| JP (1) | JP2002542633A (en) |
| CN (1) | CN1150694C (en) |
| AU (1) | AU1382199A (en) |
| BR (1) | BR9814200A (en) |
| CA (1) | CA2310220A1 (en) |
| FI (1) | FI20001178A7 (en) |
| WO (1) | WO1999026361A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444517C (en)* | 2004-10-19 | 2008-12-17 | 联发科技股份有限公司 | DC offset correction device |
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| KR20020051301A (en)* | 2000-12-22 | 2002-06-28 | 오길록 | A digital orthogonal demodulator with controlled DC offset |
| DE10136741A1 (en)* | 2001-07-27 | 2002-10-31 | Infineon Technologies Ag | Circuit arrangement for regulating a DC signal component and mobile radio transmitter |
| US7349680B2 (en)* | 2002-04-29 | 2008-03-25 | Broadcom Corporation | Method and system for using PSK sync word for fine tuning frequency adjustment |
| US7231193B2 (en)* | 2004-04-13 | 2007-06-12 | Skyworks Solutions, Inc. | Direct current offset correction systems and methods |
| JP4628881B2 (en)* | 2005-06-15 | 2011-02-09 | ルネサスエレクトロニクス株式会社 | Variable gain amplifier circuit, DC offset correction method thereof, and wireless receiver |
| US7391196B2 (en)* | 2005-09-30 | 2008-06-24 | Silicon Laboratories Inc. | In system analysis and compensation for a digital PWM controller |
| US8279180B2 (en) | 2006-05-02 | 2012-10-02 | Apple Inc. | Multipoint touch surface controller |
| WO2008026760A1 (en)* | 2006-09-01 | 2008-03-06 | Panasonic Corporation | Radio communication method and radio communication device |
| JP5190233B2 (en) | 2006-09-01 | 2013-04-24 | パナソニック株式会社 | Wireless communication device |
| JP4875767B2 (en)* | 2008-04-28 | 2012-02-15 | パナソニック株式会社 | Integrator, resonator and oversampling A / D converter |
| CN101286961B (en)* | 2008-05-26 | 2012-04-18 | 华为技术有限公司 | Apparatus and method for calibrating DC offset of device output |
| JP5275196B2 (en)* | 2009-09-29 | 2013-08-28 | パナソニック株式会社 | Integrator and oversampling A / D converter having the same |
| CN103941069A (en)* | 2013-12-30 | 2014-07-23 | 上海大郡动力控制技术有限公司 | Method for removing DC bias voltage in AC current sampling process |
| CN114754926B (en)* | 2022-04-19 | 2025-07-25 | 辽宁机电职业技术学院 | Balance wheel unbalance parameter measurement system and method |
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| FR2636183B1 (en)* | 1988-08-12 | 1990-10-12 | Thiriet Jean Yves | VARIABLE FLOW DIGITAL FILTER FOR PHASE MODULATOR |
| US5248970A (en)* | 1991-11-08 | 1993-09-28 | Crystal Semiconductor Corp. | Offset calibration of a dac using a calibrated adc |
| FI96811C (en)* | 1993-11-30 | 1996-08-26 | Nokia Mobile Phones Ltd | Method and circuitry for compensating the DC offset voltage in a D / A converter |
| TW294867B (en)* | 1994-12-23 | 1997-01-01 | Qualcomm Inc |
- 1998
- 1998-11-05JPJP2000521604Apatent/JP2002542633A/enactivePending
- 1998-11-05AUAU13821/99Apatent/AU1382199A/ennot_activeAbandoned
- 1998-11-05CNCNB988131668Apatent/CN1150694C/ennot_activeExpired - Fee Related
- 1998-11-05CACA002310220Apatent/CA2310220A1/ennot_activeAbandoned
- 1998-11-05BRBR9814200-3Apatent/BR9814200A/ennot_activeIP Right Cessation
- 1998-11-05WOPCT/US1998/023566patent/WO1999026361A1/enactiveIP Right Grant
- 2000
- 2000-05-16FIFI20001178Apatent/FI20001178A7/ennot_activeApplication Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444517C (en)* | 2004-10-19 | 2008-12-17 | 联发科技股份有限公司 | DC offset correction device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002542633A (en) | 2002-12-10 |
| BR9814200A (en) | 2000-09-26 |
| FI20001178A7 (en) | 2000-05-16 |
| AU1382199A (en) | 1999-06-07 |
| WO1999026361A1 (en) | 1999-05-27 |
| HK1035454A1 (en) | 2001-11-23 |
| CN1286834A (en) | 2001-03-07 |
| CA2310220A1 (en) | 1999-05-27 |
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