Detailed Description
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Referring to fig. 1, the semiconductor device 10A includes a substrate 100, a metal oxide semiconductor layer OS, a first gate dielectric layer 120, a gate electrode G, an interlayer dielectric layer 140, a first conductive oxide layer T1, a first electrode S, and a second electrode D. In this embodiment, the semiconductor device 10A further includes a buffer layer 110, a second conductive oxide layer T2, and a second gate dielectric layer 130.
The substrate 100 may be made of glass, quartz, organic polymer, or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic, or other suitable material), or other suitable material. If a conductive material or metal is used, an insulating layer (not shown) is coated on the substrate 100 to avoid short circuit. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene naphthalate (polyethylene naphthalate, PEN), polyester (PES), polymethyl methacrylate (PMMA), polycarbonate (polycarbonate, PC), polyimide (PI), or Metal Foil (Metal Foil), or other flexible materials. The buffer layer 110 is disposed on the substrate 100, the buffer layer 110 has a single-layer or multi-layer structure, and the material of the buffer layer 110 may include silicon oxide, silicon oxynitride, or other suitable material or a stacked layer of the above materials. In this embodiment, the buffer layer 110 includes a stack of a silicon nitride layer 112 and a silicon oxide layer 114.
The metal oxide semiconductor layer OS is located over the substrate 100. In this embodiment, the metal oxide semiconductor layer OS is directly formed on the buffer layer 110. The material of the metal oxide semiconductor layer OS includes a quaternary metal compound such as Indium Gallium Tin Zinc Oxide (IGTZO) or Indium Gallium Zinc Oxide (IGZO), indium Tin Zinc Oxide (ITZO), aluminum Zinc Tin Oxide (AZTO), indium tungsten zinc oxide (IWZO), or an oxide of a ternary metal including any one of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W), or a lanthanide rare earth doped metal oxide (for example, ln-IZO).
The first gate dielectric layer 120 is located on the metal oxide semiconductor layer OS. In the present embodiment, the first gate dielectric layer 120 is directly formed on the metal oxide semiconductor layer OS. The first gate dielectric layer 120 has a first opening O1 and a second opening O2 overlapping the metal oxide semiconductor layer OS. In some embodiments, the material of the first gate dielectric layer 120 includes silicon oxide, silicon oxynitride, hafnium oxide, or other suitable material or a stack of the above materials.
The first conductive oxide layer T1 and the second conductive oxide layer T2 are located on the first gate dielectric layer 120 and are connected to the metal oxide semiconductor layer OS. The first conductive oxide layer T1 and the second conductive oxide layer T2 are filled in the first opening O1 and the second opening O2, respectively, and contact the upper surface of the metal oxide semiconductor layer OS. In some embodiments, the materials of the first conductive oxide layer T1 and the second conductive oxide layer T2 include transparent conductive oxides, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide, or a stacked layer of at least two of the foregoing.
In some embodiments, the work functions of the first conductive oxide layer T1 and the second conductive oxide layer T2 are close to the work function of the metal oxide semiconductor layer OS. For example, the energy barrier (barrier) between the first conductive oxide layer T1 and the metal oxide semiconductor layer OS and between the second conductive oxide layer T2 and the metal oxide semiconductor layer OS is lower than the energy barrier between the metal electrode (e.g., copper electrode) and the metal oxide semiconductor layer OS. In some embodiments, there is ohmic contact between the first conductive oxide layer T1 and the metal oxide semiconductor layer OS and between the second conductive oxide layer T2 and the metal oxide semiconductor layer OS.
The second gate dielectric layer 130 is disposed on the first gate dielectric layer 120 and covers the first conductive oxide layer T1 and the second conductive oxide layer T2. The first conductive oxide layer T1 and the second conductive oxide layer T2 are located between the second gate dielectric layer 130 and the first gate dielectric layer 110. In some embodiments, the material of the second gate dielectric layer 130 includes silicon oxide, silicon oxynitride, hafnium oxide, or other suitable material or a stack of the above materials.
The gate G is located over the first gate dielectric layer 120. In this embodiment, the gate G is located on the second gate dielectric layer 130. The gate electrode G is overlapped with the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100. In some embodiments, the material of the gate electrode G may include a metal, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or an alloy of any combination of the above metals, or a stack of the above metals and/or alloys, but the present invention is not limited thereto. Other conductive materials such as metal nitrides, metal oxides, metal oxynitrides, metal stacks with other conductive materials, or other materials with conductive properties may also be used for the gate G.
The interlayer dielectric 140 is disposed on the gate G and the second gate dielectric 130. In some embodiments, the material of the interlayer dielectric layer 140 includes silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, or other suitable material or a stack of the above materials.
The interlayer dielectric layer 140 has a first contact hole V1 and a second contact hole V2. In the present embodiment, the first contact hole V1 and the second contact hole V2 penetrate through the interlayer dielectric layer 140 and the second gate dielectric layer 130. The first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS. In other words, the first contact hole V1 and the second contact hole V2 do not overlap the metal oxide semiconductor layer OS in the normal direction ND. The first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located under the first contact hole V1 and the second contact hole V2. The first conductive oxide layer T1 extends from the first contact hole V1 to the first opening O1, and the second conductive oxide layer T2 extends from the second contact hole V2 to the second opening O2.
The first electrode S and the second electrode D are respectively filled in the first contact hole V1 and the second contact hole V2. The first electrode S is electrically connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1. The second electrode D is electrically connected to the metal oxide semiconductor layer OS through the second conductive oxide layer T2. One of the first electrode S and the second electrode D is a drain electrode, and the other is a source electrode.
In some embodiments, a first portion T1a of the first conductive oxide layer T1 extends from the first opening O1 to the gate G, and a second portion T2a of the second conductive oxide layer T2 extends from the second opening O2 to the gate G. The first portion T1a and the second portion T2a overlap the metal oxide semiconductor layer OS in the normal direction ND, thereby shielding a lateral electric field between the gate electrode G and the first electrode S or between the gate electrode G and the second electrode D, and further reducing a hot carrier effect of the semiconductor device 10A. In some embodiments, a horizontal distance H1a between the first conductive oxide layer T1 and the gate G is smaller than a horizontal distance H1b between the first opening O1 and the gate G. In some embodiments, a horizontal distance H2b between the second conductive oxide layer T1 and the gate G is smaller than a horizontal distance H2b between the second opening O2 and the gate G.
In some embodiments, the material of the first electrode S and the second electrode D may comprise a metal, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or an alloy of any combination of the foregoing metals, or a stack of the foregoing metals and/or alloys. In the present embodiment, compared to the metal oxide semiconductor layer OS, the first conductive oxide layer T1 and the second conductive oxide layer T2 are less likely to react with the first electrode S and the second electrode D, so that the problem of poor electrical connection between the first electrode S and the metal oxide semiconductor layer OS and between the second electrode D and the metal oxide semiconductor layer OS is avoided. For example, if the first electrode S and the second electrode D directly contact the metal oxide semiconductor layer OS, oxygen in the metal oxide semiconductor layer OS may diffuse into the first electrode S and the second electrode D, resulting in oxidation of the first electrode S and the second electrode D, or metal in the first electrode S and the second electrode D may diffuse into the metal oxide semiconductor layer OS, such that voids may occur at the interface between the first electrode S and the metal oxide semiconductor layer OS and the interface between the second electrode D and the metal oxide semiconductor layer OS.
Based on the above, the first conductive oxide layer T1 and the second conductive oxide layer T2 can avoid the problem of poor electrical connection between the first electrode S and the metal oxide semiconductor layer OS and between the second electrode D and the metal oxide semiconductor layer OS.
Fig. 2A to 2E are schematic cross-sectional views of a method of manufacturing the semiconductor device of fig. 1.
Referring to fig. 2A to 2C, a metal oxide semiconductor layer OS, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on a substrate 100.
Referring to fig. 2A, a metal oxide semiconductor (mos) layer OS is formed on a substrate 100. In this embodiment, the metal oxide semiconductor layer OS is formed on the buffer layer 110.
Referring to fig. 2B, a first gate dielectric layer 120 is formed on the mos layer OS. The first gate dielectric layer 120 has a first opening O1 and a second opening O2 overlapping and exposing the metal oxide semiconductor layer OS. In some embodiments, the method of forming the first gate dielectric layer 120 includes a photolithographic etching process.
Referring to fig. 2C, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on the first gate dielectric layer 120, and the first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located in the first opening O1 and the second opening O2 to connect to the upper surface of the metal oxide semiconductor layer OS. Part of the first conductive oxide layer T1 and part of the second conductive oxide layer T2 overlap the metal oxide semiconductor layer OS, and the other part of the first conductive oxide layer T1 and the other part of the second conductive oxide layer T2 do not overlap the metal oxide semiconductor layer OS.
In some examples, the method of forming the first conductive oxide layer T1 and the second conductive oxide layer T2 includes forming a conductive oxide layer (not depicted) blanket on the first gate dielectric layer 120, forming a patterned photoresist (not depicted) on the conductive oxide layer, etching the conductive oxide layer with the patterned photoresist as a mask to form the first conductive oxide layer T1 and the second conductive oxide layer T2 separated from each other, and finally removing the patterned photoresist. In other words, in some embodiments, the first conductive oxide layer T1 and the second conductive oxide layer T2 are the same patterned film layer, and the first conductive oxide layer T1 and the second conductive oxide layer T2 are formed simultaneously.
Referring to fig. 2D, a second gate dielectric layer 130 is formed on the first conductive oxide layer T1 and the second conductive oxide layer T2. A gate G is formed over the first gate dielectric layer 120. In the present embodiment, the gate electrode G is directly formed on the second gate dielectric layer 130, and the gate electrode G is overlapped with the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100.
In some embodiments, the metal oxide semiconductor layer OS is doped with the gate G as a mask to form a source region, a drain region and a channel region between the source region and the drain region in the metal oxide semiconductor layer OS, wherein the channel region overlaps the gate G, and the source region and the drain region are doped to have a lower resistivity than the channel region. In some embodiments, the doping fabrication process includes, for example, a hydrogen plasma fabrication process.
Referring to fig. 2E, an interlayer dielectric layer 140 is formed on the gate G and the second gate dielectric layer 130. A first contact hole V1 and a second contact hole V2 are formed in the interlayer dielectric layer 140. In the present embodiment, the first contact hole V1 and the second contact hole V2 extend through the interlayer dielectric layer 140 and the second gate dielectric layer 130, and expose the upper surface of the first conductive oxide layer T1 and the upper surface of the second conductive oxide layer T2, respectively. In other words, the first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located under the first contact hole V1 and the second contact hole V2. In some embodiments, the method of forming the first contact hole V1 and the second contact hole V2 includes forming a patterned photoresist (not shown) on the interlayer dielectric layer 140, etching the interlayer dielectric layer 140 and the second gate dielectric layer 130 using the patterned photoresist as a mask, and finally removing the patterned photoresist. Since the first contact hole V1 and the second contact hole V2 are laterally separated from the mos layer OS, the mos layer OS is not damaged by the etching process during etching the interlayer dielectric layer 140 and the second gate dielectric layer 130, thereby improving the yield of the semiconductor device.
Finally, referring back to fig. 1, a first electrode S is formed in the first contact hole V1, and the first electrode S is electrically connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1. A second electrode D is formed in the second contact hole V2, and the second electrode D is electrically connected to the metal oxide semiconductor layer OS through the second conductive oxide layer T2. Thus, the semiconductor device 10A is substantially completed.
In some examples, the method of forming the first electrode S and the second electrode D includes forming a conductive layer (not shown) blanket-coated on the interlayer dielectric layer 140, forming a patterned photoresist (not shown) on the conductive layer, etching the conductive layer using the patterned photoresist as a mask to form the first electrode S and the second electrode D separated from each other, and finally removing the patterned photoresist. In other words, in some embodiments, the first electrode S and the second electrode D are the same patterned film layer, and the first electrode S and the second electrode D are formed simultaneously.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It should be noted that the embodiment of fig. 3 uses the element numbers and part of the content of the embodiment of fig. 1, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
The main difference between the semiconductor device 10B of fig. 3 and the semiconductor device 10A of fig. 1 is that the semiconductor device 10B further comprises an auxiliary conductive oxide layer T3.
Referring to fig. 3, the auxiliary conductive oxide layer T3 is located between the metal oxide semiconductor layer OS and the substrate 100. The resistivity of the auxiliary conductive oxide layer T3 is lower than that of the metal oxide semiconductor layer OS, and the current level of the semiconductor device 10B can be increased by providing the auxiliary conductive oxide layer T3.
In some embodiments, the material of the auxiliary conductive oxide layer T3 includes a transparent conductive oxide, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide, or a stacked layer of at least two of the foregoing.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It should be noted that the embodiment of fig. 4 uses the element numbers and part of the content of the embodiment of fig. 1, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
The main difference between the semiconductor device 10C of fig. 4 and the semiconductor device 10A of fig. 1 is that the metal oxide semiconductor layer OS of the semiconductor device 10C contacts the upper surface of the first conductive oxide layer T1 and the upper surface of the second conductive oxide layer T2.
Referring to fig. 4, a first conductive oxide layer T1 and a second conductive oxide layer T2 are disposed on the buffer layer 110. The metal oxide semiconductor layer OS is located on the first conductive oxide layer T1 and the second conductive oxide layer T2. In some embodiments, the first conductive oxide layer T1 and the second conductive oxide layer T2 extend below the gate G. In other words, in the normal direction ND, a part of the first conductive oxide layer T1 and a part of the second conductive oxide layer T2 are located between the substrate 100 and the gate electrode G.
The metal oxide semiconductor layer OS extends to the upper surface of the first conductive oxide layer T1 along the side of the first conductive oxide layer T1, and the metal oxide semiconductor layer OS has a step GP1 at the side of the first conductive oxide layer T1. The gate electrode G overlaps the offset GP1 of the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100, thereby reducing an influence of a lateral electric field between the gate electrode G and the first electrode S on the metal oxide semiconductor layer OS.
The metal oxide semiconductor layer OS extends to the upper surface of the second conductive oxide layer T2 along the side of the second conductive oxide layer T2, and the metal oxide semiconductor layer OS has a step GP2 at the side of the second conductive oxide layer T2. The gate electrode G overlaps the offset GP2 of the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100, thereby reducing an influence of a lateral electric field between the gate electrode G and the second electrode D on the metal oxide semiconductor layer OS.
In the present embodiment, the gate G is formed on the first gate dielectric layer 120, and the first contact hole V1 and the second contact hole V2 penetrate through the interlayer dielectric layer 140 and the first gate dielectric layer 120. The first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS. In other words, the first contact hole V1 and the second contact hole V2 do not overlap the metal oxide semiconductor layer OS in the normal direction ND.
Fig. 5A to 5D are schematic cross-sectional views of a method of manufacturing the semiconductor device of fig. 4.
Referring to fig. 5A and 5B, a metal oxide semiconductor layer OS, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on a substrate 100.
Referring to fig. 5A, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on a substrate 100. In this embodiment, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on the buffer layer 110.
In some examples, the method of forming the first conductive oxide layer T1 and the second conductive oxide layer T2 includes forming a conductive oxide layer (not shown) blanket on the buffer layer 110, forming a patterned photoresist (not shown) on the conductive oxide layer, etching the conductive oxide layer using the patterned photoresist as a mask to form the first conductive oxide layer T1 and the second conductive oxide layer T2 separated from each other, and finally removing the patterned photoresist. In other words, in some embodiments, the first conductive oxide layer T1 and the second conductive oxide layer T2 are the same patterned film layer, and the first conductive oxide layer T1 and the second conductive oxide layer T2 are formed simultaneously.
Referring to fig. 5B, a metal oxide semiconductor layer OS is formed on the buffer layer 110, the first conductive oxide layer T1 and the second conductive oxide layer T2. In the present embodiment, the metal oxide semiconductor layer OS fills in the gap between the first conductive oxide layer T1 and the second conductive oxide layer T2. The metal oxide semiconductor layer OS contacts the upper surface of the first conductive oxide layer T1 and the upper surface of the second conductive oxide layer T2. Part of the first conductive oxide layer T1 and part of the second conductive oxide layer T2 overlap the metal oxide semiconductor layer OS, and the other part of the first conductive oxide layer T1 and the other part of the second conductive oxide layer T2 do not overlap the metal oxide semiconductor layer OS.
Referring to fig. 5C, a first gate dielectric layer 120 is formed on the mos layer OS. The gate electrode G is formed on the first gate dielectric layer 120, and the gate electrode G is overlapped with the metal oxide semiconductor layer OS in a normal direction ND of the upper surface of the substrate 100.
In some embodiments, the metal oxide semiconductor layer OS is doped with the gate G as a mask to form a source region, a drain region and a channel region between the source region and the drain region in the metal oxide semiconductor layer OS, wherein the channel region overlaps the gate G, and the source region and the drain region are doped to have a lower resistivity than the channel region. In some embodiments, the doping fabrication process includes, for example, a hydrogen plasma fabrication process.
Referring to fig. 5D, an interlayer dielectric layer 140 is formed on the gate G. A first contact hole V1 and a second contact hole V2 are formed in the interlayer dielectric layer 140. In the present embodiment, the first contact hole V1 and the second contact hole V2 extend through the interlayer dielectric layer 140 and the first gate dielectric layer 120, and expose the upper surface of the first conductive oxide layer T1 and the upper surface of the second conductive oxide layer T2, respectively. In other words, the first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located under the first contact hole V1 and the second contact hole V2. In some embodiments, the method of forming the first contact hole V1 and the second contact hole V2 includes forming a patterned photoresist (not shown) on the interlayer dielectric layer 140, etching the interlayer dielectric layer 140 and the first gate dielectric layer 120 using the patterned photoresist as a mask, and finally removing the patterned photoresist. Since the first contact hole V1 and the second contact hole V2 are laterally separated from the mos layer OS, the mos layer OS is not damaged by the etching process during etching the interlayer dielectric layer 140 and the first gate dielectric layer 120, thereby improving the yield of the semiconductor device.
Finally, referring back to fig. 4, a first electrode S is formed in the first contact hole V1, and the first electrode S is electrically connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1. A second electrode D is formed in the second contact hole V2, and the second electrode D is electrically connected to the metal oxide semiconductor layer OS through the second conductive oxide layer T2. Thus, the semiconductor device 10C is substantially completed.
In some examples, the method of forming the first electrode S and the second electrode D includes forming a conductive layer (not shown) blanket-coated on the interlayer dielectric layer 140, forming a patterned photoresist (not shown) on the conductive layer, etching the conductive layer using the patterned photoresist as a mask to form the first electrode S and the second electrode D separated from each other, and finally removing the patterned photoresist. In other words, in some embodiments, the first electrode S and the second electrode D are the same patterned film layer, and the first electrode S and the second electrode D are formed simultaneously.
Fig. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It should be noted that the embodiment of fig. 6 uses the element numbers and part of the content of the embodiment of fig. 4, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
The main difference between the semiconductor device 10D of fig. 6 and the semiconductor device 10C of fig. 4 is that the semiconductor device 10D further comprises an auxiliary conductive oxide layer T3.
Referring to fig. 6, the auxiliary conductive oxide layer T3 is located between the gate G and the mos layer OS. The resistivity of the auxiliary conductive oxide layer T3 is lower than that of the metal oxide semiconductor layer OS, and the current level of the semiconductor device 10D can be increased by providing the auxiliary conductive oxide layer T3.
In some embodiments, the material of the auxiliary conductive oxide layer T3 includes a transparent conductive oxide, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide, or a stacked layer of at least two of the foregoing.
Fig. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It should be noted that the embodiment of fig. 7 uses the element numbers and part of the content of the embodiment of fig. 1, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
The main difference between the semiconductor device 10E of fig. 7 and the semiconductor device 10A of fig. 1 is that the metal oxide semiconductor layer OS of the semiconductor device 10E contacts the upper surface of the second conductive oxide layer T2.
Referring to fig. 7, the first conductive oxide layer T1 and the second conductive oxide layer T2 belong to different layers, wherein the first conductive oxide layer T1 is located between the first gate dielectric layer 120 and the second gate dielectric layer 130, and the second conductive oxide layer T2 is located between the buffer layer 110 and the first gate dielectric layer 120. The first contact hole V1 penetrates the interlayer dielectric layer 140 and the second gate dielectric layer 130, and the second contact hole V2 penetrates the interlayer dielectric layer 140, the second gate dielectric layer 130 and the first gate dielectric layer 120.
The metal oxide semiconductor layer OS extends to the upper surface of the second conductive oxide layer T2 along the side of the second conductive oxide layer T2, and the metal oxide semiconductor layer OS has a step GP2 at the side of the second conductive oxide layer T2. The gate electrode G overlaps the offset GP2 of the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100, thereby reducing an influence of a lateral electric field between the gate electrode G and the second electrode D on the metal oxide semiconductor layer OS.
Fig. 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It should be noted that the embodiment of fig. 8 uses the element numbers and part of the content of the embodiment of fig. 1, where the same or similar numbers are used to denote the same or similar elements, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
The main difference between the semiconductor device 10F of fig. 8 and the semiconductor device 10A of fig. 1 is that the second electrode D of the semiconductor device 10F directly contacts the upper surface of the metal oxide semiconductor layer OS.
Referring to fig. 8, in the present embodiment, the first electrode S is connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1, and the second electrode D is directly connected to the metal oxide semiconductor layer OS.